4 * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
22 #include "qemu/module.h"
23 #include "qapi/error.h"
26 #include "exec/gdbstub.h"
27 #include "hw/qdev-properties.h"
29 static void nios2_cpu_set_pc(CPUState
*cs
, vaddr value
)
31 Nios2CPU
*cpu
= NIOS2_CPU(cs
);
32 CPUNios2State
*env
= &cpu
->env
;
34 env
->regs
[R_PC
] = value
;
37 static bool nios2_cpu_has_work(CPUState
*cs
)
39 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_NMI
);
42 static void nios2_cpu_reset(DeviceState
*dev
)
44 CPUState
*cs
= CPU(dev
);
45 Nios2CPU
*cpu
= NIOS2_CPU(cs
);
46 Nios2CPUClass
*ncc
= NIOS2_CPU_GET_CLASS(cpu
);
47 CPUNios2State
*env
= &cpu
->env
;
49 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
50 qemu_log("CPU Reset (CPU %d)\n", cs
->cpu_index
);
54 ncc
->parent_reset(dev
);
56 memset(env
->regs
, 0, sizeof(uint32_t) * NUM_CORE_REGS
);
57 env
->regs
[R_PC
] = cpu
->reset_addr
;
59 #if defined(CONFIG_USER_ONLY)
60 /* Start in user mode with interrupts enabled. */
61 env
->regs
[CR_STATUS
] = CR_STATUS_U
| CR_STATUS_PIE
;
63 env
->regs
[CR_STATUS
] = 0;
67 #ifndef CONFIG_USER_ONLY
68 static void nios2_cpu_set_irq(void *opaque
, int irq
, int level
)
70 Nios2CPU
*cpu
= opaque
;
71 CPUNios2State
*env
= &cpu
->env
;
72 CPUState
*cs
= CPU(cpu
);
74 env
->regs
[CR_IPENDING
] = deposit32(env
->regs
[CR_IPENDING
], irq
, 1, !!level
);
76 if (env
->regs
[CR_IPENDING
]) {
77 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
79 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
84 static void nios2_cpu_initfn(Object
*obj
)
86 Nios2CPU
*cpu
= NIOS2_CPU(obj
);
88 cpu_set_cpustate_pointers(cpu
);
90 #if !defined(CONFIG_USER_ONLY)
94 * These interrupt lines model the IIC (internal interrupt
95 * controller). QEMU does not currently support the EIC
96 * (external interrupt controller) -- if we did it would be
97 * a separate device in hw/intc with a custom interface to
98 * the CPU, and boards using it would not wire up these IRQ lines.
100 qdev_init_gpio_in_named(DEVICE(cpu
), nios2_cpu_set_irq
, "IRQ", 32);
104 static ObjectClass
*nios2_cpu_class_by_name(const char *cpu_model
)
106 return object_class_by_name(TYPE_NIOS2_CPU
);
109 static void nios2_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
111 CPUState
*cs
= CPU(dev
);
112 Nios2CPUClass
*ncc
= NIOS2_CPU_GET_CLASS(dev
);
113 Error
*local_err
= NULL
;
115 cpu_exec_realizefn(cs
, &local_err
);
116 if (local_err
!= NULL
) {
117 error_propagate(errp
, local_err
);
124 ncc
->parent_realize(dev
, errp
);
127 #ifndef CONFIG_USER_ONLY
128 static bool nios2_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
130 Nios2CPU
*cpu
= NIOS2_CPU(cs
);
131 CPUNios2State
*env
= &cpu
->env
;
133 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
134 (env
->regs
[CR_STATUS
] & CR_STATUS_PIE
) &&
135 (env
->regs
[CR_IPENDING
] & env
->regs
[CR_IENABLE
])) {
136 cs
->exception_index
= EXCP_IRQ
;
137 nios2_cpu_do_interrupt(cs
);
142 #endif /* !CONFIG_USER_ONLY */
144 static void nios2_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
146 /* NOTE: NiosII R2 is not supported yet. */
147 info
->mach
= bfd_arch_nios2
;
148 info
->print_insn
= print_insn_nios2
;
151 static int nios2_cpu_gdb_read_register(CPUState
*cs
, GByteArray
*mem_buf
, int n
)
153 Nios2CPU
*cpu
= NIOS2_CPU(cs
);
154 CPUClass
*cc
= CPU_GET_CLASS(cs
);
155 CPUNios2State
*env
= &cpu
->env
;
157 if (n
> cc
->gdb_num_core_regs
) {
161 if (n
< 32) { /* GP regs */
162 return gdb_get_reg32(mem_buf
, env
->regs
[n
]);
163 } else if (n
== 32) { /* PC */
164 return gdb_get_reg32(mem_buf
, env
->regs
[R_PC
]);
165 } else if (n
< 49) { /* Status regs */
166 return gdb_get_reg32(mem_buf
, env
->regs
[n
- 1]);
173 static int nios2_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
175 Nios2CPU
*cpu
= NIOS2_CPU(cs
);
176 CPUClass
*cc
= CPU_GET_CLASS(cs
);
177 CPUNios2State
*env
= &cpu
->env
;
179 if (n
> cc
->gdb_num_core_regs
) {
183 if (n
< 32) { /* GP regs */
184 env
->regs
[n
] = ldl_p(mem_buf
);
185 } else if (n
== 32) { /* PC */
186 env
->regs
[R_PC
] = ldl_p(mem_buf
);
187 } else if (n
< 49) { /* Status regs */
188 env
->regs
[n
- 1] = ldl_p(mem_buf
);
194 static Property nios2_properties
[] = {
195 DEFINE_PROP_BOOL("mmu_present", Nios2CPU
, mmu_present
, true),
196 /* ALTR,pid-num-bits */
197 DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU
, pid_num_bits
, 8),
198 /* ALTR,tlb-num-ways */
199 DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU
, tlb_num_ways
, 16),
200 /* ALTR,tlb-num-entries */
201 DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU
, tlb_num_entries
, 256),
202 DEFINE_PROP_END_OF_LIST(),
205 #ifndef CONFIG_USER_ONLY
206 #include "hw/core/sysemu-cpu-ops.h"
208 static const struct SysemuCPUOps nios2_sysemu_ops
= {
209 .get_phys_page_debug
= nios2_cpu_get_phys_page_debug
,
213 #include "hw/core/tcg-cpu-ops.h"
215 static const struct TCGCPUOps nios2_tcg_ops
= {
216 .initialize
= nios2_tcg_init
,
218 #ifdef CONFIG_USER_ONLY
219 .record_sigsegv
= nios2_cpu_record_sigsegv
,
221 .tlb_fill
= nios2_cpu_tlb_fill
,
222 .cpu_exec_interrupt
= nios2_cpu_exec_interrupt
,
223 .do_interrupt
= nios2_cpu_do_interrupt
,
224 .do_unaligned_access
= nios2_cpu_do_unaligned_access
,
225 #endif /* !CONFIG_USER_ONLY */
228 static void nios2_cpu_class_init(ObjectClass
*oc
, void *data
)
230 DeviceClass
*dc
= DEVICE_CLASS(oc
);
231 CPUClass
*cc
= CPU_CLASS(oc
);
232 Nios2CPUClass
*ncc
= NIOS2_CPU_CLASS(oc
);
234 device_class_set_parent_realize(dc
, nios2_cpu_realizefn
,
235 &ncc
->parent_realize
);
236 device_class_set_props(dc
, nios2_properties
);
237 device_class_set_parent_reset(dc
, nios2_cpu_reset
, &ncc
->parent_reset
);
239 cc
->class_by_name
= nios2_cpu_class_by_name
;
240 cc
->has_work
= nios2_cpu_has_work
;
241 cc
->dump_state
= nios2_cpu_dump_state
;
242 cc
->set_pc
= nios2_cpu_set_pc
;
243 cc
->disas_set_info
= nios2_cpu_disas_set_info
;
244 #ifndef CONFIG_USER_ONLY
245 cc
->sysemu_ops
= &nios2_sysemu_ops
;
247 cc
->gdb_read_register
= nios2_cpu_gdb_read_register
;
248 cc
->gdb_write_register
= nios2_cpu_gdb_write_register
;
249 cc
->gdb_num_core_regs
= 49;
250 cc
->tcg_ops
= &nios2_tcg_ops
;
253 static const TypeInfo nios2_cpu_type_info
= {
254 .name
= TYPE_NIOS2_CPU
,
256 .instance_size
= sizeof(Nios2CPU
),
257 .instance_init
= nios2_cpu_initfn
,
258 .class_size
= sizeof(Nios2CPUClass
),
259 .class_init
= nios2_cpu_class_init
,
262 static void nios2_cpu_register_types(void)
264 type_register_static(&nios2_cpu_type_info
);
267 type_init(nios2_cpu_register_types
)