target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42     }
  43     cs->exception_index = exception;
  44     env->error_code = error_code;
  45
  46     if (pc) {
  47         /* now we have a real cpu fault */
  48         cpu_restore_state(cs, pc);
  49     }
  50
  51     cpu_loop_exit(cs);
  52 }
  53
  54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  55                                                     uint32_t exception,
  56                                                     uintptr_t pc)
  57 {
  58     do_raise_exception_err(env, exception, 0, pc);
  59 }
  60
  61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  62                                 int error_code)
  63 {
  64     do_raise_exception_err(env, exception, error_code, 0);
  65 }
  66
  67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  68 {
  69     do_raise_exception(env, exception, 0);
  70 }
  71
  72 #if defined(CONFIG_USER_ONLY)
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     return (type) cpu_##insn##_data(env, addr);                         \
  78 }
  79 #else
  80 #define HELPER_LD(name, insn, type)                                     \
  81 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  82                              int mem_idx)                               \
  83 {                                                                       \
  84     switch (mem_idx)                                                    \
  85     {                                                                   \
  86     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  87     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  88     default:                                                            \
  89     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  90     }                                                                   \
  91 }
  92 #endif
  93 HELPER_LD(lw, ldl, int32_t)
  94 #if defined(TARGET_MIPS64)
  95 HELPER_LD(ld, ldq, int64_t)
  96 #endif
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     cpu_##insn##_data(env, addr, val);                                  \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sw, stl, uint32_t)
 122 #if defined(TARGET_MIPS64)
 123 HELPER_ST(sd, stq, uint64_t)
 124 #endif
 125 #undef HELPER_ST
 126
 127 target_ulong helper_clo (target_ulong arg1)
 128 {
 129     return clo32(arg1);
 130 }
 131
 132 target_ulong helper_clz (target_ulong arg1)
 133 {
 134     return clz32(arg1);
 135 }
 136
 137 #if defined(TARGET_MIPS64)
 138 target_ulong helper_dclo (target_ulong arg1)
 139 {
 140     return clo64(arg1);
 141 }
 142
 143 target_ulong helper_dclz (target_ulong arg1)
 144 {
 145     return clz64(arg1);
 146 }
 147 #endif /* TARGET_MIPS64 */
 148
 149 /* 64 bits arithmetic for 32 bits hosts */
 150 static inline uint64_t get_HILO(CPUMIPSState *env)
 151 {
 152     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 153 }
 154
 155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 156 {
 157     target_ulong tmp;
 158     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 159     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 160     return tmp;
 161 }
 162
 163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 164 {
 165     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 166     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 167     return tmp;
 168 }
 169
 170 /* Multiplication variants of the vr54xx. */
 171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 172                          target_ulong arg2)
 173 {
 174     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 175                                  (int64_t)(int32_t)arg2));
 176 }
 177
 178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 179                           target_ulong arg2)
 180 {
 181     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 182                        (uint64_t)(uint32_t)arg2);
 183 }
 184
 185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 186                          target_ulong arg2)
 187 {
 188     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 189                        (int64_t)(int32_t)arg2);
 190 }
 191
 192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 193                            target_ulong arg2)
 194 {
 195     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 196                        (int64_t)(int32_t)arg2);
 197 }
 198
 199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 200                           target_ulong arg2)
 201 {
 202     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 203                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 204 }
 205
 206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 207                             target_ulong arg2)
 208 {
 209     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 210                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 211 }
 212
 213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 214                          target_ulong arg2)
 215 {
 216     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 217                        (int64_t)(int32_t)arg2);
 218 }
 219
 220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 221                            target_ulong arg2)
 222 {
 223     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 224                        (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 228                           target_ulong arg2)
 229 {
 230     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 231                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 235                             target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 238                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 242                           target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 245 }
 246
 247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 248                            target_ulong arg2)
 249 {
 250     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 251                        (uint64_t)(uint32_t)arg2);
 252 }
 253
 254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 255                            target_ulong arg2)
 256 {
 257     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 258                        (int64_t)(int32_t)arg2);
 259 }
 260
 261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 262                             target_ulong arg2)
 263 {
 264     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 265                        (uint64_t)(uint32_t)arg2);
 266 }
 267
 268 static inline target_ulong bitswap(target_ulong v)
 269 {
 270     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 271               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 272     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 273               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 274     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 275               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 276     return v;
 277 }
 278
 279 #ifdef TARGET_MIPS64
 280 target_ulong helper_dbitswap(target_ulong rt)
 281 {
 282     return bitswap(rt);
 283 }
 284 #endif
 285
 286 target_ulong helper_bitswap(target_ulong rt)
 287 {
 288     return (int32_t)bitswap(rt);
 289 }
 290
 291 #ifndef CONFIG_USER_ONLY
 292
 293 static inline hwaddr do_translate_address(CPUMIPSState *env,
 294                                                       target_ulong address,
 295                                                       int rw)
 296 {
 297     hwaddr lladdr;
 298
 299     lladdr = cpu_mips_translate_address(env, address, rw);
 300
 301     if (lladdr == -1LL) {
 302         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 303     } else {
 304         return lladdr;
 305     }
 306 }
 307
 308 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 310 {                                                                             \
 311     if (arg & almask) {                                                       \
 312         env->CP0_BadVAddr = arg;                                              \
 313         helper_raise_exception(env, EXCP_AdEL);                               \
 314     }                                                                         \
 315     env->lladdr = do_translate_address(env, arg, 0);                          \
 316     env->llval = do_##insn(env, arg, mem_idx);                                \
 317     return env->llval;                                                        \
 318 }
 319 HELPER_LD_ATOMIC(ll, lw, 0x3)
 320 #ifdef TARGET_MIPS64
 321 HELPER_LD_ATOMIC(lld, ld, 0x7)
 322 #endif
 323 #undef HELPER_LD_ATOMIC
 324
 325 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 326 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 327                            target_ulong arg2, int mem_idx)                    \
 328 {                                                                             \
 329     target_long tmp;                                                          \
 330                                                                               \
 331     if (arg2 & almask) {                                                      \
 332         env->CP0_BadVAddr = arg2;                                             \
 333         helper_raise_exception(env, EXCP_AdES);                               \
 334     }                                                                         \
 335     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 336         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 337         if (tmp == env->llval) {                                              \
 338             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 339             return 1;                                                         \
 340         }                                                                     \
 341     }                                                                         \
 342     return 0;                                                                 \
 343 }
 344 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 345 #ifdef TARGET_MIPS64
 346 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 347 #endif
 348 #undef HELPER_ST_ATOMIC
 349 #endif
 350
 351 #ifdef TARGET_WORDS_BIGENDIAN
 352 #define GET_LMASK(v) ((v) & 3)
 353 #define GET_OFFSET(addr, offset) (addr + (offset))
 354 #else
 355 #define GET_LMASK(v) (((v) & 3) ^ 3)
 356 #define GET_OFFSET(addr, offset) (addr - (offset))
 357 #endif
 358
 359 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 360                 int mem_idx)
 361 {
 362     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 363
 364     if (GET_LMASK(arg2) <= 2)
 365         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 366
 367     if (GET_LMASK(arg2) <= 1)
 368         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 369
 370     if (GET_LMASK(arg2) == 0)
 371         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 372 }
 373
 374 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 375                 int mem_idx)
 376 {
 377     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 378
 379     if (GET_LMASK(arg2) >= 1)
 380         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 381
 382     if (GET_LMASK(arg2) >= 2)
 383         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 384
 385     if (GET_LMASK(arg2) == 3)
 386         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 387 }
 388
 389 #if defined(TARGET_MIPS64)
 390 /* "half" load and stores.  We must do the memory access inline,
 391    or fault handling won't work.  */
 392
 393 #ifdef TARGET_WORDS_BIGENDIAN
 394 #define GET_LMASK64(v) ((v) & 7)
 395 #else
 396 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 397 #endif
 398
 399 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 400                 int mem_idx)
 401 {
 402     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 403
 404     if (GET_LMASK64(arg2) <= 6)
 405         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 406
 407     if (GET_LMASK64(arg2) <= 5)
 408         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 409
 410     if (GET_LMASK64(arg2) <= 4)
 411         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 412
 413     if (GET_LMASK64(arg2) <= 3)
 414         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 415
 416     if (GET_LMASK64(arg2) <= 2)
 417         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 418
 419     if (GET_LMASK64(arg2) <= 1)
 420         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 421
 422     if (GET_LMASK64(arg2) <= 0)
 423         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 424 }
 425
 426 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 427                 int mem_idx)
 428 {
 429     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 430
 431     if (GET_LMASK64(arg2) >= 1)
 432         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 433
 434     if (GET_LMASK64(arg2) >= 2)
 435         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 436
 437     if (GET_LMASK64(arg2) >= 3)
 438         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 439
 440     if (GET_LMASK64(arg2) >= 4)
 441         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 442
 443     if (GET_LMASK64(arg2) >= 5)
 444         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 445
 446     if (GET_LMASK64(arg2) >= 6)
 447         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 448
 449     if (GET_LMASK64(arg2) == 7)
 450         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 451 }
 452 #endif /* TARGET_MIPS64 */
 453
 454 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 455
 456 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 457                 uint32_t mem_idx)
 458 {
 459     target_ulong base_reglist = reglist & 0xf;
 460     target_ulong do_r31 = reglist & 0x10;
 461
 462     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 463         target_ulong i;
 464
 465         for (i = 0; i < base_reglist; i++) {
 466             env->active_tc.gpr[multiple_regs[i]] =
 467                 (target_long)do_lw(env, addr, mem_idx);
 468             addr += 4;
 469         }
 470     }
 471
 472     if (do_r31) {
 473         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 474     }
 475 }
 476
 477 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 478                 uint32_t mem_idx)
 479 {
 480     target_ulong base_reglist = reglist & 0xf;
 481     target_ulong do_r31 = reglist & 0x10;
 482
 483     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 484         target_ulong i;
 485
 486         for (i = 0; i < base_reglist; i++) {
 487             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 488             addr += 4;
 489         }
 490     }
 491
 492     if (do_r31) {
 493         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 494     }
 495 }
 496
 497 #if defined(TARGET_MIPS64)
 498 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 499                 uint32_t mem_idx)
 500 {
 501     target_ulong base_reglist = reglist & 0xf;
 502     target_ulong do_r31 = reglist & 0x10;
 503
 504     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 505         target_ulong i;
 506
 507         for (i = 0; i < base_reglist; i++) {
 508             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 509             addr += 8;
 510         }
 511     }
 512
 513     if (do_r31) {
 514         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 515     }
 516 }
 517
 518 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 519                 uint32_t mem_idx)
 520 {
 521     target_ulong base_reglist = reglist & 0xf;
 522     target_ulong do_r31 = reglist & 0x10;
 523
 524     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 525         target_ulong i;
 526
 527         for (i = 0; i < base_reglist; i++) {
 528             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 529             addr += 8;
 530         }
 531     }
 532
 533     if (do_r31) {
 534         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 535     }
 536 }
 537 #endif
 538
 539 #ifndef CONFIG_USER_ONLY
 540 /* SMP helpers.  */
 541 static bool mips_vpe_is_wfi(MIPSCPU *c)
 542 {
 543     CPUState *cpu = CPU(c);
 544     CPUMIPSState *env = &c->env;
 545
 546     /* If the VPE is halted but otherwise active, it means it's waiting for
 547        an interrupt.  */
 548     return cpu->halted && mips_vpe_active(env);
 549 }
 550
 551 static inline void mips_vpe_wake(MIPSCPU *c)
 552 {
 553     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 554        because there might be other conditions that state that c should
 555        be sleeping.  */
 556     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 557 }
 558
 559 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 560 {
 561     CPUState *cs = CPU(cpu);
 562
 563     /* The VPE was shut off, really go to bed.
 564        Reset any old _WAKE requests.  */
 565     cs->halted = 1;
 566     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 567 }
 568
 569 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 570 {
 571     CPUMIPSState *c = &cpu->env;
 572
 573     /* FIXME: TC reschedule.  */
 574     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 575         mips_vpe_wake(cpu);
 576     }
 577 }
 578
 579 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 580 {
 581     CPUMIPSState *c = &cpu->env;
 582
 583     /* FIXME: TC reschedule.  */
 584     if (!mips_vpe_active(c)) {
 585         mips_vpe_sleep(cpu);
 586     }
 587 }
 588
 589 /**
 590  * mips_cpu_map_tc:
 591  * @env: CPU from which mapping is performed.
 592  * @tc: Should point to an int with the value of the global TC index.
 593  *
 594  * This function will transform @tc into a local index within the
 595  * returned #CPUMIPSState.
 596  */
 597 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 598           which depends on runtime setup. Can probably be fixed by
 599           walking the list of CPUMIPSStates.  */
 600 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 601 {
 602     MIPSCPU *cpu;
 603     CPUState *cs;
 604     CPUState *other_cs;
 605     int vpe_idx;
 606     int tc_idx = *tc;
 607
 608     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 609         /* Not allowed to address other CPUs.  */
 610         *tc = env->current_tc;
 611         return env;
 612     }
 613
 614     cs = CPU(mips_env_get_cpu(env));
 615     vpe_idx = tc_idx / cs->nr_threads;
 616     *tc = tc_idx % cs->nr_threads;
 617     other_cs = qemu_get_cpu(vpe_idx);
 618     if (other_cs == NULL) {
 619         return env;
 620     }
 621     cpu = MIPS_CPU(other_cs);
 622     return &cpu->env;
 623 }
 624
 625 /* The per VPE CP0_Status register shares some fields with the per TC
 626    CP0_TCStatus registers. These fields are wired to the same registers,
 627    so changes to either of them should be reflected on both registers.
 628
 629    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 630
 631    These helper call synchronizes the regs for a given cpu.  */
 632
 633 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 634 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 635                                      int tc);  */
 636
 637 /* Called for updates to CP0_TCStatus.  */
 638 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 639                              target_ulong v)
 640 {
 641     uint32_t status;
 642     uint32_t tcu, tmx, tasid, tksu;
 643     uint32_t mask = ((1U << CP0St_CU3)
 644                        | (1 << CP0St_CU2)
 645                        | (1 << CP0St_CU1)
 646                        | (1 << CP0St_CU0)
 647                        | (1 << CP0St_MX)
 648                        | (3 << CP0St_KSU));
 649
 650     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 651     tmx = (v >> CP0TCSt_TMX) & 0x1;
 652     tasid = v & 0xff;
 653     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 654
 655     status = tcu << CP0St_CU0;
 656     status |= tmx << CP0St_MX;
 657     status |= tksu << CP0St_KSU;
 658
 659     cpu->CP0_Status &= ~mask;
 660     cpu->CP0_Status |= status;
 661
 662     /* Sync the TASID with EntryHi.  */
 663     cpu->CP0_EntryHi &= ~0xff;
 664     cpu->CP0_EntryHi |= tasid;
 665
 666     compute_hflags(cpu);
 667 }
 668
 669 /* Called for updates to CP0_EntryHi.  */
 670 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 671 {
 672     int32_t *tcst;
 673     uint32_t asid, v = cpu->CP0_EntryHi;
 674
 675     asid = v & 0xff;
 676
 677     if (tc == cpu->current_tc) {
 678         tcst = &cpu->active_tc.CP0_TCStatus;
 679     } else {
 680         tcst = &cpu->tcs[tc].CP0_TCStatus;
 681     }
 682
 683     *tcst &= ~0xff;
 684     *tcst |= asid;
 685 }
 686
 687 /* CP0 helpers */
 688 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 689 {
 690     return env->mvp->CP0_MVPControl;
 691 }
 692
 693 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 694 {
 695     return env->mvp->CP0_MVPConf0;
 696 }
 697
 698 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 699 {
 700     return env->mvp->CP0_MVPConf1;
 701 }
 702
 703 target_ulong helper_mfc0_random(CPUMIPSState *env)
 704 {
 705     return (int32_t)cpu_mips_get_random(env);
 706 }
 707
 708 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 709 {
 710     return env->active_tc.CP0_TCStatus;
 711 }
 712
 713 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 714 {
 715     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 716     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 717
 718     if (other_tc == other->current_tc)
 719         return other->active_tc.CP0_TCStatus;
 720     else
 721         return other->tcs[other_tc].CP0_TCStatus;
 722 }
 723
 724 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 725 {
 726     return env->active_tc.CP0_TCBind;
 727 }
 728
 729 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 730 {
 731     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 732     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 733
 734     if (other_tc == other->current_tc)
 735         return other->active_tc.CP0_TCBind;
 736     else
 737         return other->tcs[other_tc].CP0_TCBind;
 738 }
 739
 740 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 741 {
 742     return env->active_tc.PC;
 743 }
 744
 745 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 746 {
 747     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 748     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 749
 750     if (other_tc == other->current_tc)
 751         return other->active_tc.PC;
 752     else
 753         return other->tcs[other_tc].PC;
 754 }
 755
 756 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 757 {
 758     return env->active_tc.CP0_TCHalt;
 759 }
 760
 761 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 762 {
 763     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 764     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 765
 766     if (other_tc == other->current_tc)
 767         return other->active_tc.CP0_TCHalt;
 768     else
 769         return other->tcs[other_tc].CP0_TCHalt;
 770 }
 771
 772 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 773 {
 774     return env->active_tc.CP0_TCContext;
 775 }
 776
 777 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 778 {
 779     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 780     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 781
 782     if (other_tc == other->current_tc)
 783         return other->active_tc.CP0_TCContext;
 784     else
 785         return other->tcs[other_tc].CP0_TCContext;
 786 }
 787
 788 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 789 {
 790     return env->active_tc.CP0_TCSchedule;
 791 }
 792
 793 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 794 {
 795     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 796     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 797
 798     if (other_tc == other->current_tc)
 799         return other->active_tc.CP0_TCSchedule;
 800     else
 801         return other->tcs[other_tc].CP0_TCSchedule;
 802 }
 803
 804 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 805 {
 806     return env->active_tc.CP0_TCScheFBack;
 807 }
 808
 809 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 810 {
 811     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 812     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 813
 814     if (other_tc == other->current_tc)
 815         return other->active_tc.CP0_TCScheFBack;
 816     else
 817         return other->tcs[other_tc].CP0_TCScheFBack;
 818 }
 819
 820 target_ulong helper_mfc0_count(CPUMIPSState *env)
 821 {
 822     return (int32_t)cpu_mips_get_count(env);
 823 }
 824
 825 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 826 {
 827     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 828     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 829
 830     return other->CP0_EntryHi;
 831 }
 832
 833 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 834 {
 835     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 836     int32_t tccause;
 837     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 838
 839     if (other_tc == other->current_tc) {
 840         tccause = other->CP0_Cause;
 841     } else {
 842         tccause = other->CP0_Cause;
 843     }
 844
 845     return tccause;
 846 }
 847
 848 target_ulong helper_mftc0_status(CPUMIPSState *env)
 849 {
 850     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 851     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 852
 853     return other->CP0_Status;
 854 }
 855
 856 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 857 {
 858     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 859 }
 860
 861 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 862 {
 863     return (int32_t)env->CP0_WatchLo[sel];
 864 }
 865
 866 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 867 {
 868     return env->CP0_WatchHi[sel];
 869 }
 870
 871 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 872 {
 873     target_ulong t0 = env->CP0_Debug;
 874     if (env->hflags & MIPS_HFLAG_DM)
 875         t0 |= 1 << CP0DB_DM;
 876
 877     return t0;
 878 }
 879
 880 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 881 {
 882     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 883     int32_t tcstatus;
 884     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 885
 886     if (other_tc == other->current_tc)
 887         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 888     else
 889         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 890
 891     /* XXX: Might be wrong, check with EJTAG spec. */
 892     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 893             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 894 }
 895
 896 #if defined(TARGET_MIPS64)
 897 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 898 {
 899     return env->active_tc.PC;
 900 }
 901
 902 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 903 {
 904     return env->active_tc.CP0_TCHalt;
 905 }
 906
 907 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 908 {
 909     return env->active_tc.CP0_TCContext;
 910 }
 911
 912 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 913 {
 914     return env->active_tc.CP0_TCSchedule;
 915 }
 916
 917 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 918 {
 919     return env->active_tc.CP0_TCScheFBack;
 920 }
 921
 922 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 923 {
 924     return env->lladdr >> env->CP0_LLAddr_shift;
 925 }
 926
 927 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 928 {
 929     return env->CP0_WatchLo[sel];
 930 }
 931 #endif /* TARGET_MIPS64 */
 932
 933 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 934 {
 935     uint32_t index_p = env->CP0_Index & 0x80000000;
 936     uint32_t tlb_index = arg1 & 0x7fffffff;
 937     if (tlb_index < env->tlb->nb_tlb) {
 938         if (env->insn_flags & ISA_MIPS32R6) {
 939             index_p |= arg1 & 0x80000000;
 940         }
 941         env->CP0_Index = index_p | tlb_index;
 942     }
 943 }
 944
 945 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 946 {
 947     uint32_t mask = 0;
 948     uint32_t newval;
 949
 950     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 951         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 952                 (1 << CP0MVPCo_EVP);
 953     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 954         mask |= (1 << CP0MVPCo_STLB);
 955     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 956
 957     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 958
 959     env->mvp->CP0_MVPControl = newval;
 960 }
 961
 962 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 963 {
 964     uint32_t mask;
 965     uint32_t newval;
 966
 967     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 968            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 969     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 970
 971     /* Yield scheduler intercept not implemented. */
 972     /* Gating storage scheduler intercept not implemented. */
 973
 974     // TODO: Enable/disable TCs.
 975
 976     env->CP0_VPEControl = newval;
 977 }
 978
 979 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 980 {
 981     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 982     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 983     uint32_t mask;
 984     uint32_t newval;
 985
 986     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 987            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 988     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 989
 990     /* TODO: Enable/disable TCs.  */
 991
 992     other->CP0_VPEControl = newval;
 993 }
 994
 995 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
 996 {
 997     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 998     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 999     /* FIXME: Mask away return zero on read bits.  */
1000     return other->CP0_VPEControl;
1001 }
1002
1003 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1004 {
1005     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1006     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1007
1008     return other->CP0_VPEConf0;
1009 }
1010
1011 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1012 {
1013     uint32_t mask = 0;
1014     uint32_t newval;
1015
1016     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1017         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1018             mask |= (0xff << CP0VPEC0_XTC);
1019         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1020     }
1021     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1022
1023     // TODO: TC exclusive handling due to ERL/EXL.
1024
1025     env->CP0_VPEConf0 = newval;
1026 }
1027
1028 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1029 {
1030     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1031     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1032     uint32_t mask = 0;
1033     uint32_t newval;
1034
1035     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1036     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1037
1038     /* TODO: TC exclusive handling due to ERL/EXL.  */
1039     other->CP0_VPEConf0 = newval;
1040 }
1041
1042 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1043 {
1044     uint32_t mask = 0;
1045     uint32_t newval;
1046
1047     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1048         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1049                 (0xff << CP0VPEC1_NCP1);
1050     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1051
1052     /* UDI not implemented. */
1053     /* CP2 not implemented. */
1054
1055     // TODO: Handle FPU (CP1) binding.
1056
1057     env->CP0_VPEConf1 = newval;
1058 }
1059
1060 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1061 {
1062     /* Yield qualifier inputs not implemented. */
1063     env->CP0_YQMask = 0x00000000;
1064 }
1065
1066 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1067 {
1068     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1069 }
1070
1071 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1072
1073 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1074 {
1075     /* 1k pages not implemented */
1076     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1077     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1078                         | (rxi << (CP0EnLo_XI - 30));
1079 }
1080
1081 #if defined(TARGET_MIPS64)
1082 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1083
1084 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1085 {
1086     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1087     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1088 }
1089 #endif
1090
1091 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1092 {
1093     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1094     uint32_t newval;
1095
1096     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1097
1098     env->active_tc.CP0_TCStatus = newval;
1099     sync_c0_tcstatus(env, env->current_tc, newval);
1100 }
1101
1102 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1103 {
1104     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1105     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1106
1107     if (other_tc == other->current_tc)
1108         other->active_tc.CP0_TCStatus = arg1;
1109     else
1110         other->tcs[other_tc].CP0_TCStatus = arg1;
1111     sync_c0_tcstatus(other, other_tc, arg1);
1112 }
1113
1114 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1115 {
1116     uint32_t mask = (1 << CP0TCBd_TBE);
1117     uint32_t newval;
1118
1119     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1120         mask |= (1 << CP0TCBd_CurVPE);
1121     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1122     env->active_tc.CP0_TCBind = newval;
1123 }
1124
1125 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1126 {
1127     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1128     uint32_t mask = (1 << CP0TCBd_TBE);
1129     uint32_t newval;
1130     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1131
1132     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1133         mask |= (1 << CP0TCBd_CurVPE);
1134     if (other_tc == other->current_tc) {
1135         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1136         other->active_tc.CP0_TCBind = newval;
1137     } else {
1138         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1139         other->tcs[other_tc].CP0_TCBind = newval;
1140     }
1141 }
1142
1143 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1144 {
1145     env->active_tc.PC = arg1;
1146     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1147     env->lladdr = 0ULL;
1148     /* MIPS16 not implemented. */
1149 }
1150
1151 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1152 {
1153     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1154     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1155
1156     if (other_tc == other->current_tc) {
1157         other->active_tc.PC = arg1;
1158         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159         other->lladdr = 0ULL;
1160         /* MIPS16 not implemented. */
1161     } else {
1162         other->tcs[other_tc].PC = arg1;
1163         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1164         other->lladdr = 0ULL;
1165         /* MIPS16 not implemented. */
1166     }
1167 }
1168
1169 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1170 {
1171     MIPSCPU *cpu = mips_env_get_cpu(env);
1172
1173     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1174
1175     // TODO: Halt TC / Restart (if allocated+active) TC.
1176     if (env->active_tc.CP0_TCHalt & 1) {
1177         mips_tc_sleep(cpu, env->current_tc);
1178     } else {
1179         mips_tc_wake(cpu, env->current_tc);
1180     }
1181 }
1182
1183 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1184 {
1185     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1186     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1187     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1188
1189     // TODO: Halt TC / Restart (if allocated+active) TC.
1190
1191     if (other_tc == other->current_tc)
1192         other->active_tc.CP0_TCHalt = arg1;
1193     else
1194         other->tcs[other_tc].CP0_TCHalt = arg1;
1195
1196     if (arg1 & 1) {
1197         mips_tc_sleep(other_cpu, other_tc);
1198     } else {
1199         mips_tc_wake(other_cpu, other_tc);
1200     }
1201 }
1202
1203 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1204 {
1205     env->active_tc.CP0_TCContext = arg1;
1206 }
1207
1208 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1209 {
1210     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1211     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1212
1213     if (other_tc == other->current_tc)
1214         other->active_tc.CP0_TCContext = arg1;
1215     else
1216         other->tcs[other_tc].CP0_TCContext = arg1;
1217 }
1218
1219 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1220 {
1221     env->active_tc.CP0_TCSchedule = arg1;
1222 }
1223
1224 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1225 {
1226     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1227     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1228
1229     if (other_tc == other->current_tc)
1230         other->active_tc.CP0_TCSchedule = arg1;
1231     else
1232         other->tcs[other_tc].CP0_TCSchedule = arg1;
1233 }
1234
1235 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1236 {
1237     env->active_tc.CP0_TCScheFBack = arg1;
1238 }
1239
1240 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1241 {
1242     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1243     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1244
1245     if (other_tc == other->current_tc)
1246         other->active_tc.CP0_TCScheFBack = arg1;
1247     else
1248         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1249 }
1250
1251 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1252 {
1253     /* 1k pages not implemented */
1254     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1255     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1256                         | (rxi << (CP0EnLo_XI - 30));
1257 }
1258
1259 #if defined(TARGET_MIPS64)
1260 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1261 {
1262     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1263     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1264 }
1265 #endif
1266
1267 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1268 {
1269     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1270 }
1271
1272 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1273 {
1274     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1275     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1276         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1277          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1278          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1279         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1280     }
1281 }
1282
1283 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1284 {
1285     /* SmartMIPS not implemented */
1286     /* 1k pages not implemented */
1287     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1288                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1289     compute_hflags(env);
1290     restore_pamask(env);
1291 }
1292
1293 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1294 {
1295     if (env->insn_flags & ISA_MIPS32R6) {
1296         if (arg1 < env->tlb->nb_tlb) {
1297             env->CP0_Wired = arg1;
1298         }
1299     } else {
1300         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1301     }
1302 }
1303
1304 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1305 {
1306     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1307 }
1308
1309 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1310 {
1311     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1312 }
1313
1314 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1315 {
1316     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1317 }
1318
1319 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1320 {
1321     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1322 }
1323
1324 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1325 {
1326     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1327 }
1328
1329 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1330 {
1331     uint32_t mask = 0x0000000F;
1332
1333     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1334         mask |= (1 << 29);
1335
1336         if (arg1 & (1 << 29)) {
1337             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1338         } else {
1339             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1340         }
1341     }
1342
1343     env->CP0_HWREna = arg1 & mask;
1344 }
1345
1346 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1347 {
1348     cpu_mips_store_count(env, arg1);
1349 }
1350
1351 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1352 {
1353     target_ulong old, val, mask;
1354     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1355     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1356         mask |= 1 << CP0EnHi_EHINV;
1357     }
1358
1359     /* 1k pages not implemented */
1360 #if defined(TARGET_MIPS64)
1361     if (env->insn_flags & ISA_MIPS32R6) {
1362         int entryhi_r = extract64(arg1, 62, 2);
1363         int config0_at = extract32(env->CP0_Config0, 13, 2);
1364         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1365         if ((entryhi_r == 2) ||
1366             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1367             /* skip EntryHi.R field if new value is reserved */
1368             mask &= ~(0x3ull << 62);
1369         }
1370     }
1371     mask &= env->SEGMask;
1372 #endif
1373     old = env->CP0_EntryHi;
1374     val = (arg1 & mask) | (old & ~mask);
1375     env->CP0_EntryHi = val;
1376     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1377         sync_c0_entryhi(env, env->current_tc);
1378     }
1379     /* If the ASID changes, flush qemu's TLB.  */
1380     if ((old & 0xFF) != (val & 0xFF))
1381         cpu_mips_tlb_flush(env, 1);
1382 }
1383
1384 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1385 {
1386     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1387     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1388
1389     other->CP0_EntryHi = arg1;
1390     sync_c0_entryhi(other, other_tc);
1391 }
1392
1393 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1394 {
1395     cpu_mips_store_compare(env, arg1);
1396 }
1397
1398 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1399 {
1400     MIPSCPU *cpu = mips_env_get_cpu(env);
1401     uint32_t val, old;
1402
1403     old = env->CP0_Status;
1404     cpu_mips_store_status(env, arg1);
1405     val = env->CP0_Status;
1406
1407     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1408         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1409                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1410                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1411                 env->CP0_Cause);
1412         switch (env->hflags & MIPS_HFLAG_KSU) {
1413         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1414         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1415         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1416         default:
1417             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1418             break;
1419         }
1420     }
1421 }
1422
1423 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1424 {
1425     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1426     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1427     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1428
1429     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1430     sync_c0_status(env, other, other_tc);
1431 }
1432
1433 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1434 {
1435     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1436 }
1437
1438 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1439 {
1440     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1441     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1442 }
1443
1444 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1445 {
1446     cpu_mips_store_cause(env, arg1);
1447 }
1448
1449 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1450 {
1451     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1452     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1453
1454     cpu_mips_store_cause(other, arg1);
1455 }
1456
1457 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1458 {
1459     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1460     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1461
1462     return other->CP0_EPC;
1463 }
1464
1465 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1466 {
1467     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1468     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1469
1470     return other->CP0_EBase;
1471 }
1472
1473 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1474 {
1475     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1476 }
1477
1478 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1479 {
1480     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1481     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1482     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1483 }
1484
1485 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1486 {
1487     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1488     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1489
1490     switch (idx) {
1491     case 0: return other->CP0_Config0;
1492     case 1: return other->CP0_Config1;
1493     case 2: return other->CP0_Config2;
1494     case 3: return other->CP0_Config3;
1495     /* 4 and 5 are reserved.  */
1496     case 6: return other->CP0_Config6;
1497     case 7: return other->CP0_Config7;
1498     default:
1499         break;
1500     }
1501     return 0;
1502 }
1503
1504 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1505 {
1506     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1507 }
1508
1509 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1510 {
1511     /* tertiary/secondary caches not implemented */
1512     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1513 }
1514
1515 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1516 {
1517     if (env->insn_flags & ASE_MICROMIPS) {
1518         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1519                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1520     }
1521 }
1522
1523 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1524 {
1525     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1526                        (arg1 & env->CP0_Config4_rw_bitmask);
1527 }
1528
1529 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1530 {
1531     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1532                        (arg1 & env->CP0_Config5_rw_bitmask);
1533     compute_hflags(env);
1534 }
1535
1536 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1537 {
1538     target_long mask = env->CP0_LLAddr_rw_bitmask;
1539     arg1 = arg1 << env->CP0_LLAddr_shift;
1540     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1541 }
1542
1543 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1544 {
1545     /* Watch exceptions for instructions, data loads, data stores
1546        not implemented. */
1547     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1548 }
1549
1550 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1551 {
1552     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1553     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1554 }
1555
1556 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1557 {
1558     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1559     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1560 }
1561
1562 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1563 {
1564     env->CP0_Framemask = arg1; /* XXX */
1565 }
1566
1567 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1568 {
1569     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1570     if (arg1 & (1 << CP0DB_DM))
1571         env->hflags |= MIPS_HFLAG_DM;
1572     else
1573         env->hflags &= ~MIPS_HFLAG_DM;
1574 }
1575
1576 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1577 {
1578     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1579     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1580     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1581
1582     /* XXX: Might be wrong, check with EJTAG spec. */
1583     if (other_tc == other->current_tc)
1584         other->active_tc.CP0_Debug_tcstatus = val;
1585     else
1586         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1587     other->CP0_Debug = (other->CP0_Debug &
1588                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1589                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1590 }
1591
1592 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1593 {
1594     env->CP0_Performance0 = arg1 & 0x000007ff;
1595 }
1596
1597 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1598 {
1599     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1600 }
1601
1602 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1603 {
1604     env->CP0_DataLo = arg1; /* XXX */
1605 }
1606
1607 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1608 {
1609     env->CP0_TagHi = arg1; /* XXX */
1610 }
1611
1612 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1613 {
1614     env->CP0_DataHi = arg1; /* XXX */
1615 }
1616
1617 /* MIPS MT functions */
1618 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1619 {
1620     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1621     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1622
1623     if (other_tc == other->current_tc)
1624         return other->active_tc.gpr[sel];
1625     else
1626         return other->tcs[other_tc].gpr[sel];
1627 }
1628
1629 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1630 {
1631     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1632     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1633
1634     if (other_tc == other->current_tc)
1635         return other->active_tc.LO[sel];
1636     else
1637         return other->tcs[other_tc].LO[sel];
1638 }
1639
1640 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1641 {
1642     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1643     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1644
1645     if (other_tc == other->current_tc)
1646         return other->active_tc.HI[sel];
1647     else
1648         return other->tcs[other_tc].HI[sel];
1649 }
1650
1651 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1652 {
1653     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1654     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1655
1656     if (other_tc == other->current_tc)
1657         return other->active_tc.ACX[sel];
1658     else
1659         return other->tcs[other_tc].ACX[sel];
1660 }
1661
1662 target_ulong helper_mftdsp(CPUMIPSState *env)
1663 {
1664     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1665     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1666
1667     if (other_tc == other->current_tc)
1668         return other->active_tc.DSPControl;
1669     else
1670         return other->tcs[other_tc].DSPControl;
1671 }
1672
1673 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1674 {
1675     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1676     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1677
1678     if (other_tc == other->current_tc)
1679         other->active_tc.gpr[sel] = arg1;
1680     else
1681         other->tcs[other_tc].gpr[sel] = arg1;
1682 }
1683
1684 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1685 {
1686     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1687     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1688
1689     if (other_tc == other->current_tc)
1690         other->active_tc.LO[sel] = arg1;
1691     else
1692         other->tcs[other_tc].LO[sel] = arg1;
1693 }
1694
1695 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1696 {
1697     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1698     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1699
1700     if (other_tc == other->current_tc)
1701         other->active_tc.HI[sel] = arg1;
1702     else
1703         other->tcs[other_tc].HI[sel] = arg1;
1704 }
1705
1706 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1707 {
1708     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1709     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1710
1711     if (other_tc == other->current_tc)
1712         other->active_tc.ACX[sel] = arg1;
1713     else
1714         other->tcs[other_tc].ACX[sel] = arg1;
1715 }
1716
1717 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1718 {
1719     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1720     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1721
1722     if (other_tc == other->current_tc)
1723         other->active_tc.DSPControl = arg1;
1724     else
1725         other->tcs[other_tc].DSPControl = arg1;
1726 }
1727
1728 /* MIPS MT functions */
1729 target_ulong helper_dmt(void)
1730 {
1731     // TODO
1732      return 0;
1733 }
1734
1735 target_ulong helper_emt(void)
1736 {
1737     // TODO
1738     return 0;
1739 }
1740
1741 target_ulong helper_dvpe(CPUMIPSState *env)
1742 {
1743     CPUState *other_cs = first_cpu;
1744     target_ulong prev = env->mvp->CP0_MVPControl;
1745
1746     CPU_FOREACH(other_cs) {
1747         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1748         /* Turn off all VPEs except the one executing the dvpe.  */
1749         if (&other_cpu->env != env) {
1750             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1751             mips_vpe_sleep(other_cpu);
1752         }
1753     }
1754     return prev;
1755 }
1756
1757 target_ulong helper_evpe(CPUMIPSState *env)
1758 {
1759     CPUState *other_cs = first_cpu;
1760     target_ulong prev = env->mvp->CP0_MVPControl;
1761
1762     CPU_FOREACH(other_cs) {
1763         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1764
1765         if (&other_cpu->env != env
1766             /* If the VPE is WFI, don't disturb its sleep.  */
1767             && !mips_vpe_is_wfi(other_cpu)) {
1768             /* Enable the VPE.  */
1769             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1770             mips_vpe_wake(other_cpu); /* And wake it up.  */
1771         }
1772     }
1773     return prev;
1774 }
1775 #endif /* !CONFIG_USER_ONLY */
1776
1777 void helper_fork(target_ulong arg1, target_ulong arg2)
1778 {
1779     // arg1 = rt, arg2 = rs
1780     // TODO: store to TC register
1781 }
1782
1783 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1784 {
1785     target_long arg1 = arg;
1786
1787     if (arg1 < 0) {
1788         /* No scheduling policy implemented. */
1789         if (arg1 != -2) {
1790             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1791                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1792                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1793                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1794                 helper_raise_exception(env, EXCP_THREAD);
1795             }
1796         }
1797     } else if (arg1 == 0) {
1798         if (0 /* TODO: TC underflow */) {
1799             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1800             helper_raise_exception(env, EXCP_THREAD);
1801         } else {
1802             // TODO: Deallocate TC
1803         }
1804     } else if (arg1 > 0) {
1805         /* Yield qualifier inputs not implemented. */
1806         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1807         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1808         helper_raise_exception(env, EXCP_THREAD);
1809     }
1810     return env->CP0_YQMask;
1811 }
1812
1813 #ifndef CONFIG_USER_ONLY
1814 /* TLB management */
1815 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1816 {
1817     MIPSCPU *cpu = mips_env_get_cpu(env);
1818
1819     /* Flush qemu's TLB and discard all shadowed entries.  */
1820     tlb_flush(CPU(cpu), flush_global);
1821     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1822 }
1823
1824 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1825 {
1826     /* Discard entries from env->tlb[first] onwards.  */
1827     while (env->tlb->tlb_in_use > first) {
1828         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1829     }
1830 }
1831
1832 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1833 {
1834 #if defined(TARGET_MIPS64)
1835     return extract64(entrylo, 6, 54);
1836 #else
1837     return extract64(entrylo, 6, 24) | /* PFN */
1838            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1839 #endif
1840 }
1841
1842 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1843 {
1844     r4k_tlb_t *tlb;
1845
1846     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1847     tlb = &env->tlb->mmu.r4k.tlb[idx];
1848     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1849         tlb->EHINV = 1;
1850         return;
1851     }
1852     tlb->EHINV = 0;
1853     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1854 #if defined(TARGET_MIPS64)
1855     tlb->VPN &= env->SEGMask;
1856 #endif
1857     tlb->ASID = env->CP0_EntryHi & 0xFF;
1858     tlb->PageMask = env->CP0_PageMask;
1859     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1860     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1861     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1862     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1863     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1864     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1865     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1866     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1867     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1868     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1869     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1870     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1871     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1872 }
1873
1874 void r4k_helper_tlbinv(CPUMIPSState *env)
1875 {
1876     int idx;
1877     r4k_tlb_t *tlb;
1878     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1879
1880     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1881         tlb = &env->tlb->mmu.r4k.tlb[idx];
1882         if (!tlb->G && tlb->ASID == ASID) {
1883             tlb->EHINV = 1;
1884         }
1885     }
1886     cpu_mips_tlb_flush(env, 1);
1887 }
1888
1889 void r4k_helper_tlbinvf(CPUMIPSState *env)
1890 {
1891     int idx;
1892
1893     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1894         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1895     }
1896     cpu_mips_tlb_flush(env, 1);
1897 }
1898
1899 void r4k_helper_tlbwi(CPUMIPSState *env)
1900 {
1901     r4k_tlb_t *tlb;
1902     int idx;
1903     target_ulong VPN;
1904     uint8_t ASID;
1905     bool G, V0, D0, V1, D1;
1906
1907     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1908     tlb = &env->tlb->mmu.r4k.tlb[idx];
1909     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1910 #if defined(TARGET_MIPS64)
1911     VPN &= env->SEGMask;
1912 #endif
1913     ASID = env->CP0_EntryHi & 0xff;
1914     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1915     V0 = (env->CP0_EntryLo0 & 2) != 0;
1916     D0 = (env->CP0_EntryLo0 & 4) != 0;
1917     V1 = (env->CP0_EntryLo1 & 2) != 0;
1918     D1 = (env->CP0_EntryLo1 & 4) != 0;
1919
1920     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1921        permissions on the current entry. */
1922     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1923         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1924         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1925         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1926     }
1927
1928     r4k_invalidate_tlb(env, idx, 0);
1929     r4k_fill_tlb(env, idx);
1930 }
1931
1932 void r4k_helper_tlbwr(CPUMIPSState *env)
1933 {
1934     int r = cpu_mips_get_random(env);
1935
1936     r4k_invalidate_tlb(env, r, 1);
1937     r4k_fill_tlb(env, r);
1938 }
1939
1940 void r4k_helper_tlbp(CPUMIPSState *env)
1941 {
1942     r4k_tlb_t *tlb;
1943     target_ulong mask;
1944     target_ulong tag;
1945     target_ulong VPN;
1946     uint8_t ASID;
1947     int i;
1948
1949     ASID = env->CP0_EntryHi & 0xFF;
1950     for (i = 0; i < env->tlb->nb_tlb; i++) {
1951         tlb = &env->tlb->mmu.r4k.tlb[i];
1952         /* 1k pages are not supported. */
1953         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1954         tag = env->CP0_EntryHi & ~mask;
1955         VPN = tlb->VPN & ~mask;
1956 #if defined(TARGET_MIPS64)
1957         tag &= env->SEGMask;
1958 #endif
1959         /* Check ASID, virtual page number & size */
1960         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1961             /* TLB match */
1962             env->CP0_Index = i;
1963             break;
1964         }
1965     }
1966     if (i == env->tlb->nb_tlb) {
1967         /* No match.  Discard any shadow entries, if any of them match.  */
1968         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1969             tlb = &env->tlb->mmu.r4k.tlb[i];
1970             /* 1k pages are not supported. */
1971             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1972             tag = env->CP0_EntryHi & ~mask;
1973             VPN = tlb->VPN & ~mask;
1974 #if defined(TARGET_MIPS64)
1975             tag &= env->SEGMask;
1976 #endif
1977             /* Check ASID, virtual page number & size */
1978             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1979                 r4k_mips_tlb_flush_extra (env, i);
1980                 break;
1981             }
1982         }
1983
1984         env->CP0_Index |= 0x80000000;
1985     }
1986 }
1987
1988 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
1989 {
1990 #if defined(TARGET_MIPS64)
1991     return tlb_pfn << 6;
1992 #else
1993     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
1994            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
1995 #endif
1996 }
1997
1998 void r4k_helper_tlbr(CPUMIPSState *env)
1999 {
2000     r4k_tlb_t *tlb;
2001     uint8_t ASID;
2002     int idx;
2003
2004     ASID = env->CP0_EntryHi & 0xFF;
2005     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2006     tlb = &env->tlb->mmu.r4k.tlb[idx];
2007
2008     /* If this will change the current ASID, flush qemu's TLB.  */
2009     if (ASID != tlb->ASID)
2010         cpu_mips_tlb_flush (env, 1);
2011
2012     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2013
2014     if (tlb->EHINV) {
2015         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2016         env->CP0_PageMask = 0;
2017         env->CP0_EntryLo0 = 0;
2018         env->CP0_EntryLo1 = 0;
2019     } else {
2020         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2021         env->CP0_PageMask = tlb->PageMask;
2022         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2023                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2024                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2025                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2026         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2027                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2028                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2029                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2030     }
2031 }
2032
2033 void helper_tlbwi(CPUMIPSState *env)
2034 {
2035     env->tlb->helper_tlbwi(env);
2036 }
2037
2038 void helper_tlbwr(CPUMIPSState *env)
2039 {
2040     env->tlb->helper_tlbwr(env);
2041 }
2042
2043 void helper_tlbp(CPUMIPSState *env)
2044 {
2045     env->tlb->helper_tlbp(env);
2046 }
2047
2048 void helper_tlbr(CPUMIPSState *env)
2049 {
2050     env->tlb->helper_tlbr(env);
2051 }
2052
2053 void helper_tlbinv(CPUMIPSState *env)
2054 {
2055     env->tlb->helper_tlbinv(env);
2056 }
2057
2058 void helper_tlbinvf(CPUMIPSState *env)
2059 {
2060     env->tlb->helper_tlbinvf(env);
2061 }
2062
2063 /* Specials */
2064 target_ulong helper_di(CPUMIPSState *env)
2065 {
2066     target_ulong t0 = env->CP0_Status;
2067
2068     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2069     return t0;
2070 }
2071
2072 target_ulong helper_ei(CPUMIPSState *env)
2073 {
2074     target_ulong t0 = env->CP0_Status;
2075
2076     env->CP0_Status = t0 | (1 << CP0St_IE);
2077     return t0;
2078 }
2079
2080 static void debug_pre_eret(CPUMIPSState *env)
2081 {
2082     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2083         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2084                 env->active_tc.PC, env->CP0_EPC);
2085         if (env->CP0_Status & (1 << CP0St_ERL))
2086             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2087         if (env->hflags & MIPS_HFLAG_DM)
2088             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2089         qemu_log("\n");
2090     }
2091 }
2092
2093 static void debug_post_eret(CPUMIPSState *env)
2094 {
2095     MIPSCPU *cpu = mips_env_get_cpu(env);
2096
2097     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2098         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2099                 env->active_tc.PC, env->CP0_EPC);
2100         if (env->CP0_Status & (1 << CP0St_ERL))
2101             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2102         if (env->hflags & MIPS_HFLAG_DM)
2103             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2104         switch (env->hflags & MIPS_HFLAG_KSU) {
2105         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2106         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2107         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2108         default:
2109             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2110             break;
2111         }
2112     }
2113 }
2114
2115 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2116 {
2117     env->active_tc.PC = error_pc & ~(target_ulong)1;
2118     if (error_pc & 1) {
2119         env->hflags |= MIPS_HFLAG_M16;
2120     } else {
2121         env->hflags &= ~(MIPS_HFLAG_M16);
2122     }
2123 }
2124
2125 static inline void exception_return(CPUMIPSState *env)
2126 {
2127     debug_pre_eret(env);
2128     if (env->CP0_Status & (1 << CP0St_ERL)) {
2129         set_pc(env, env->CP0_ErrorEPC);
2130         env->CP0_Status &= ~(1 << CP0St_ERL);
2131     } else {
2132         set_pc(env, env->CP0_EPC);
2133         env->CP0_Status &= ~(1 << CP0St_EXL);
2134     }
2135     compute_hflags(env);
2136     debug_post_eret(env);
2137 }
2138
2139 void helper_eret(CPUMIPSState *env)
2140 {
2141     exception_return(env);
2142     env->lladdr = 1;
2143 }
2144
2145 void helper_eretnc(CPUMIPSState *env)
2146 {
2147     exception_return(env);
2148 }
2149
2150 void helper_deret(CPUMIPSState *env)
2151 {
2152     debug_pre_eret(env);
2153     set_pc(env, env->CP0_DEPC);
2154
2155     env->hflags &= ~MIPS_HFLAG_DM;
2156     compute_hflags(env);
2157     debug_post_eret(env);
2158 }
2159 #endif /* !CONFIG_USER_ONLY */
2160
2161 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2162 {
2163     if ((env->hflags & MIPS_HFLAG_CP0) ||
2164         (env->CP0_HWREna & (1 << 0)))
2165         return env->CP0_EBase & 0x3ff;
2166     else
2167         helper_raise_exception(env, EXCP_RI);
2168
2169     return 0;
2170 }
2171
2172 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2173 {
2174     if ((env->hflags & MIPS_HFLAG_CP0) ||
2175         (env->CP0_HWREna & (1 << 1)))
2176         return env->SYNCI_Step;
2177     else
2178         helper_raise_exception(env, EXCP_RI);
2179
2180     return 0;
2181 }
2182
2183 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2184 {
2185     if ((env->hflags & MIPS_HFLAG_CP0) ||
2186         (env->CP0_HWREna & (1 << 2)))
2187         return env->CP0_Count;
2188     else
2189         helper_raise_exception(env, EXCP_RI);
2190
2191     return 0;
2192 }
2193
2194 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2195 {
2196     if ((env->hflags & MIPS_HFLAG_CP0) ||
2197         (env->CP0_HWREna & (1 << 3)))
2198         return env->CCRes;
2199     else
2200         helper_raise_exception(env, EXCP_RI);
2201
2202     return 0;
2203 }
2204
2205 void helper_pmon(CPUMIPSState *env, int function)
2206 {
2207     function /= 2;
2208     switch (function) {
2209     case 2: /* TODO: char inbyte(int waitflag); */
2210         if (env->active_tc.gpr[4] == 0)
2211             env->active_tc.gpr[2] = -1;
2212         /* Fall through */
2213     case 11: /* TODO: char inbyte (void); */
2214         env->active_tc.gpr[2] = -1;
2215         break;
2216     case 3:
2217     case 12:
2218         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2219         break;
2220     case 17:
2221         break;
2222     case 158:
2223         {
2224             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2225             printf("%s", fmt);
2226         }
2227         break;
2228     }
2229 }
2230
2231 void helper_wait(CPUMIPSState *env)
2232 {
2233     CPUState *cs = CPU(mips_env_get_cpu(env));
2234
2235     cs->halted = 1;
2236     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2237     helper_raise_exception(env, EXCP_HLT);
2238 }
2239
2240 #if !defined(CONFIG_USER_ONLY)
2241
2242 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2243                                   int access_type, int is_user,
2244                                   uintptr_t retaddr)
2245 {
2246     MIPSCPU *cpu = MIPS_CPU(cs);
2247     CPUMIPSState *env = &cpu->env;
2248     int error_code = 0;
2249     int excp;
2250
2251     env->CP0_BadVAddr = addr;
2252
2253     if (access_type == MMU_DATA_STORE) {
2254         excp = EXCP_AdES;
2255     } else {
2256         excp = EXCP_AdEL;
2257         if (access_type == MMU_INST_FETCH) {
2258             error_code |= EXCP_INST_NOTAVAIL;
2259         }
2260     }
2261
2262     do_raise_exception_err(env, excp, error_code, retaddr);
2263 }
2264
2265 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2266               uintptr_t retaddr)
2267 {
2268     int ret;
2269
2270     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2271     if (ret) {
2272         MIPSCPU *cpu = MIPS_CPU(cs);
2273         CPUMIPSState *env = &cpu->env;
2274
2275         do_raise_exception_err(env, cs->exception_index,
2276                                env->error_code, retaddr);
2277     }
2278 }
2279
2280 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2281                                 bool is_write, bool is_exec, int unused,
2282                                 unsigned size)
2283 {
2284     MIPSCPU *cpu = MIPS_CPU(cs);
2285     CPUMIPSState *env = &cpu->env;
2286
2287     /*
2288      * Raising an exception with KVM enabled will crash because it won't be from
2289      * the main execution loop so the longjmp won't have a matching setjmp.
2290      * Until we can trigger a bus error exception through KVM lets just ignore
2291      * the access.
2292      */
2293     if (kvm_enabled()) {
2294         return;
2295     }
2296
2297     if (is_exec) {
2298         helper_raise_exception(env, EXCP_IBE);
2299     } else {
2300         helper_raise_exception(env, EXCP_DBE);
2301     }
2302 }
2303 #endif /* !CONFIG_USER_ONLY */
2304
2305 /* Complex FPU operations which may need stack space. */
2306
2307 #define FLOAT_TWO32 make_float32(1 << 30)
2308 #define FLOAT_TWO64 make_float64(1ULL << 62)
2309 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2310 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2311
2312 /* convert MIPS rounding mode in FCR31 to IEEE library */
2313 unsigned int ieee_rm[] = {
2314     float_round_nearest_even,
2315     float_round_to_zero,
2316     float_round_up,
2317     float_round_down
2318 };
2319
2320 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2321 {
2322     target_ulong arg1 = 0;
2323
2324     switch (reg) {
2325     case 0:
2326         arg1 = (int32_t)env->active_fpu.fcr0;
2327         break;
2328     case 1:
2329         /* UFR Support - Read Status FR */
2330         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2331             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2332                 arg1 = (int32_t)
2333                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2334             } else {
2335                 helper_raise_exception(env, EXCP_RI);
2336             }
2337         }
2338         break;
2339     case 5:
2340         /* FRE Support - read Config5.FRE bit */
2341         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2342             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2343                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2344             } else {
2345                 helper_raise_exception(env, EXCP_RI);
2346             }
2347         }
2348         break;
2349     case 25:
2350         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2351         break;
2352     case 26:
2353         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2354         break;
2355     case 28:
2356         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2357         break;
2358     default:
2359         arg1 = (int32_t)env->active_fpu.fcr31;
2360         break;
2361     }
2362
2363     return arg1;
2364 }
2365
2366 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2367 {
2368     switch (fs) {
2369     case 1:
2370         /* UFR Alias - Reset Status FR */
2371         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2372             return;
2373         }
2374         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2375             env->CP0_Status &= ~(1 << CP0St_FR);
2376             compute_hflags(env);
2377         } else {
2378             helper_raise_exception(env, EXCP_RI);
2379         }
2380         break;
2381     case 4:
2382         /* UNFR Alias - Set Status FR */
2383         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2384             return;
2385         }
2386         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2387             env->CP0_Status |= (1 << CP0St_FR);
2388             compute_hflags(env);
2389         } else {
2390             helper_raise_exception(env, EXCP_RI);
2391         }
2392         break;
2393     case 5:
2394         /* FRE Support - clear Config5.FRE bit */
2395         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2396             return;
2397         }
2398         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2399             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2400             compute_hflags(env);
2401         } else {
2402             helper_raise_exception(env, EXCP_RI);
2403         }
2404         break;
2405     case 6:
2406         /* FRE Support - set Config5.FRE bit */
2407         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2408             return;
2409         }
2410         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2411             env->CP0_Config5 |= (1 << CP0C5_FRE);
2412             compute_hflags(env);
2413         } else {
2414             helper_raise_exception(env, EXCP_RI);
2415         }
2416         break;
2417     case 25:
2418         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2419             return;
2420         }
2421         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2422                      ((arg1 & 0x1) << 23);
2423         break;
2424     case 26:
2425         if (arg1 & 0x007c0000)
2426             return;
2427         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2428         break;
2429     case 28:
2430         if (arg1 & 0x007c0000)
2431             return;
2432         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2433                      ((arg1 & 0x4) << 22);
2434         break;
2435     case 31:
2436         if (env->insn_flags & ISA_MIPS32R6) {
2437             uint32_t mask = 0xfefc0000;
2438             env->active_fpu.fcr31 = (arg1 & ~mask) |
2439                 (env->active_fpu.fcr31 & mask);
2440         } else if (!(arg1 & 0x007c0000)) {
2441             env->active_fpu.fcr31 = arg1;
2442         }
2443         break;
2444     default:
2445         return;
2446     }
2447     /* set rounding mode */
2448     restore_rounding_mode(env);
2449     /* set flush-to-zero mode */
2450     restore_flush_mode(env);
2451     set_float_exception_flags(0, &env->active_fpu.fp_status);
2452     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2453         do_raise_exception(env, EXCP_FPE, GETPC());
2454 }
2455
2456 int ieee_ex_to_mips(int xcpt)
2457 {
2458     int ret = 0;
2459     if (xcpt) {
2460         if (xcpt & float_flag_invalid) {
2461             ret |= FP_INVALID;
2462         }
2463         if (xcpt & float_flag_overflow) {
2464             ret |= FP_OVERFLOW;
2465         }
2466         if (xcpt & float_flag_underflow) {
2467             ret |= FP_UNDERFLOW;
2468         }
2469         if (xcpt & float_flag_divbyzero) {
2470             ret |= FP_DIV0;
2471         }
2472         if (xcpt & float_flag_inexact) {
2473             ret |= FP_INEXACT;
2474         }
2475     }
2476     return ret;
2477 }
2478
2479 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2480 {
2481     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2482
2483     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2484
2485     if (tmp) {
2486         set_float_exception_flags(0, &env->active_fpu.fp_status);
2487
2488         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2489             do_raise_exception(env, EXCP_FPE, pc);
2490         } else {
2491             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2492         }
2493     }
2494 }
2495
2496 /* Float support.
2497    Single precition routines have a "s" suffix, double precision a
2498    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2499    paired single lower "pl", paired single upper "pu".  */
2500
2501 /* unary operations, modifying fp status  */
2502 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2503 {
2504     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2505     update_fcr31(env, GETPC());
2506     return fdt0;
2507 }
2508
2509 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2510 {
2511     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2512     update_fcr31(env, GETPC());
2513     return fst0;
2514 }
2515
2516 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2517 {
2518     uint64_t fdt2;
2519
2520     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2521     update_fcr31(env, GETPC());
2522     return fdt2;
2523 }
2524
2525 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2526 {
2527     uint64_t fdt2;
2528
2529     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2530     update_fcr31(env, GETPC());
2531     return fdt2;
2532 }
2533
2534 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2535 {
2536     uint64_t fdt2;
2537
2538     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2539     update_fcr31(env, GETPC());
2540     return fdt2;
2541 }
2542
2543 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2544 {
2545     uint64_t dt2;
2546
2547     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2548     if (get_float_exception_flags(&env->active_fpu.fp_status)
2549         & (float_flag_invalid | float_flag_overflow)) {
2550         dt2 = FP_TO_INT64_OVERFLOW;
2551     }
2552     update_fcr31(env, GETPC());
2553     return dt2;
2554 }
2555
2556 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2557 {
2558     uint64_t dt2;
2559
2560     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2561     if (get_float_exception_flags(&env->active_fpu.fp_status)
2562         & (float_flag_invalid | float_flag_overflow)) {
2563         dt2 = FP_TO_INT64_OVERFLOW;
2564     }
2565     update_fcr31(env, GETPC());
2566     return dt2;
2567 }
2568
2569 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2570 {
2571     uint32_t fst2;
2572     uint32_t fsth2;
2573
2574     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2575     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2576     update_fcr31(env, GETPC());
2577     return ((uint64_t)fsth2 << 32) | fst2;
2578 }
2579
2580 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2581 {
2582     uint32_t wt2;
2583     uint32_t wth2;
2584     int excp, excph;
2585
2586     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2587     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2588     if (excp & (float_flag_overflow | float_flag_invalid)) {
2589         wt2 = FP_TO_INT32_OVERFLOW;
2590     }
2591
2592     set_float_exception_flags(0, &env->active_fpu.fp_status);
2593     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2594     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2595     if (excph & (float_flag_overflow | float_flag_invalid)) {
2596         wth2 = FP_TO_INT32_OVERFLOW;
2597     }
2598
2599     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2600     update_fcr31(env, GETPC());
2601
2602     return ((uint64_t)wth2 << 32) | wt2;
2603 }
2604
2605 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2606 {
2607     uint32_t fst2;
2608
2609     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2610     update_fcr31(env, GETPC());
2611     return fst2;
2612 }
2613
2614 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2615 {
2616     uint32_t fst2;
2617
2618     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2619     update_fcr31(env, GETPC());
2620     return fst2;
2621 }
2622
2623 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2624 {
2625     uint32_t fst2;
2626
2627     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2628     update_fcr31(env, GETPC());
2629     return fst2;
2630 }
2631
2632 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2633 {
2634     uint32_t wt2;
2635
2636     wt2 = wt0;
2637     update_fcr31(env, GETPC());
2638     return wt2;
2639 }
2640
2641 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2642 {
2643     uint32_t wt2;
2644
2645     wt2 = wth0;
2646     update_fcr31(env, GETPC());
2647     return wt2;
2648 }
2649
2650 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2651 {
2652     uint32_t wt2;
2653
2654     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2655     if (get_float_exception_flags(&env->active_fpu.fp_status)
2656         & (float_flag_invalid | float_flag_overflow)) {
2657         wt2 = FP_TO_INT32_OVERFLOW;
2658     }
2659     update_fcr31(env, GETPC());
2660     return wt2;
2661 }
2662
2663 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2664 {
2665     uint32_t wt2;
2666
2667     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2668     if (get_float_exception_flags(&env->active_fpu.fp_status)
2669         & (float_flag_invalid | float_flag_overflow)) {
2670         wt2 = FP_TO_INT32_OVERFLOW;
2671     }
2672     update_fcr31(env, GETPC());
2673     return wt2;
2674 }
2675
2676 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2677 {
2678     uint64_t dt2;
2679
2680     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2681     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2682     restore_rounding_mode(env);
2683     if (get_float_exception_flags(&env->active_fpu.fp_status)
2684         & (float_flag_invalid | float_flag_overflow)) {
2685         dt2 = FP_TO_INT64_OVERFLOW;
2686     }
2687     update_fcr31(env, GETPC());
2688     return dt2;
2689 }
2690
2691 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2692 {
2693     uint64_t dt2;
2694
2695     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2696     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2697     restore_rounding_mode(env);
2698     if (get_float_exception_flags(&env->active_fpu.fp_status)
2699         & (float_flag_invalid | float_flag_overflow)) {
2700         dt2 = FP_TO_INT64_OVERFLOW;
2701     }
2702     update_fcr31(env, GETPC());
2703     return dt2;
2704 }
2705
2706 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2707 {
2708     uint32_t wt2;
2709
2710     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2711     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2712     restore_rounding_mode(env);
2713     if (get_float_exception_flags(&env->active_fpu.fp_status)
2714         & (float_flag_invalid | float_flag_overflow)) {
2715         wt2 = FP_TO_INT32_OVERFLOW;
2716     }
2717     update_fcr31(env, GETPC());
2718     return wt2;
2719 }
2720
2721 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2722 {
2723     uint32_t wt2;
2724
2725     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2726     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2727     restore_rounding_mode(env);
2728     if (get_float_exception_flags(&env->active_fpu.fp_status)
2729         & (float_flag_invalid | float_flag_overflow)) {
2730         wt2 = FP_TO_INT32_OVERFLOW;
2731     }
2732     update_fcr31(env, GETPC());
2733     return wt2;
2734 }
2735
2736 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2737 {
2738     uint64_t dt2;
2739
2740     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2741     if (get_float_exception_flags(&env->active_fpu.fp_status)
2742         & (float_flag_invalid | float_flag_overflow)) {
2743         dt2 = FP_TO_INT64_OVERFLOW;
2744     }
2745     update_fcr31(env, GETPC());
2746     return dt2;
2747 }
2748
2749 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2750 {
2751     uint64_t dt2;
2752
2753     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2754     if (get_float_exception_flags(&env->active_fpu.fp_status)
2755         & (float_flag_invalid | float_flag_overflow)) {
2756         dt2 = FP_TO_INT64_OVERFLOW;
2757     }
2758     update_fcr31(env, GETPC());
2759     return dt2;
2760 }
2761
2762 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2763 {
2764     uint32_t wt2;
2765
2766     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2767     if (get_float_exception_flags(&env->active_fpu.fp_status)
2768         & (float_flag_invalid | float_flag_overflow)) {
2769         wt2 = FP_TO_INT32_OVERFLOW;
2770     }
2771     update_fcr31(env, GETPC());
2772     return wt2;
2773 }
2774
2775 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2776 {
2777     uint32_t wt2;
2778
2779     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2780     if (get_float_exception_flags(&env->active_fpu.fp_status)
2781         & (float_flag_invalid | float_flag_overflow)) {
2782         wt2 = FP_TO_INT32_OVERFLOW;
2783     }
2784     update_fcr31(env, GETPC());
2785     return wt2;
2786 }
2787
2788 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2789 {
2790     uint64_t dt2;
2791
2792     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2793     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2794     restore_rounding_mode(env);
2795     if (get_float_exception_flags(&env->active_fpu.fp_status)
2796         & (float_flag_invalid | float_flag_overflow)) {
2797         dt2 = FP_TO_INT64_OVERFLOW;
2798     }
2799     update_fcr31(env, GETPC());
2800     return dt2;
2801 }
2802
2803 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2804 {
2805     uint64_t dt2;
2806
2807     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2808     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2809     restore_rounding_mode(env);
2810     if (get_float_exception_flags(&env->active_fpu.fp_status)
2811         & (float_flag_invalid | float_flag_overflow)) {
2812         dt2 = FP_TO_INT64_OVERFLOW;
2813     }
2814     update_fcr31(env, GETPC());
2815     return dt2;
2816 }
2817
2818 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2819 {
2820     uint32_t wt2;
2821
2822     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2823     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2824     restore_rounding_mode(env);
2825     if (get_float_exception_flags(&env->active_fpu.fp_status)
2826         & (float_flag_invalid | float_flag_overflow)) {
2827         wt2 = FP_TO_INT32_OVERFLOW;
2828     }
2829     update_fcr31(env, GETPC());
2830     return wt2;
2831 }
2832
2833 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2834 {
2835     uint32_t wt2;
2836
2837     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2838     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2839     restore_rounding_mode(env);
2840     if (get_float_exception_flags(&env->active_fpu.fp_status)
2841         & (float_flag_invalid | float_flag_overflow)) {
2842         wt2 = FP_TO_INT32_OVERFLOW;
2843     }
2844     update_fcr31(env, GETPC());
2845     return wt2;
2846 }
2847
2848 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2849 {
2850     uint64_t dt2;
2851
2852     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2853     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2854     restore_rounding_mode(env);
2855     if (get_float_exception_flags(&env->active_fpu.fp_status)
2856         & (float_flag_invalid | float_flag_overflow)) {
2857         dt2 = FP_TO_INT64_OVERFLOW;
2858     }
2859     update_fcr31(env, GETPC());
2860     return dt2;
2861 }
2862
2863 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2864 {
2865     uint64_t dt2;
2866
2867     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2868     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2869     restore_rounding_mode(env);
2870     if (get_float_exception_flags(&env->active_fpu.fp_status)
2871         & (float_flag_invalid | float_flag_overflow)) {
2872         dt2 = FP_TO_INT64_OVERFLOW;
2873     }
2874     update_fcr31(env, GETPC());
2875     return dt2;
2876 }
2877
2878 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2879 {
2880     uint32_t wt2;
2881
2882     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2883     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2884     restore_rounding_mode(env);
2885     if (get_float_exception_flags(&env->active_fpu.fp_status)
2886         & (float_flag_invalid | float_flag_overflow)) {
2887         wt2 = FP_TO_INT32_OVERFLOW;
2888     }
2889     update_fcr31(env, GETPC());
2890     return wt2;
2891 }
2892
2893 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2894 {
2895     uint32_t wt2;
2896
2897     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2898     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2899     restore_rounding_mode(env);
2900     if (get_float_exception_flags(&env->active_fpu.fp_status)
2901         & (float_flag_invalid | float_flag_overflow)) {
2902         wt2 = FP_TO_INT32_OVERFLOW;
2903     }
2904     update_fcr31(env, GETPC());
2905     return wt2;
2906 }
2907
2908 /* unary operations, not modifying fp status  */
2909 #define FLOAT_UNOP(name)                                       \
2910 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2911 {                                                              \
2912     return float64_ ## name(fdt0);                             \
2913 }                                                              \
2914 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2915 {                                                              \
2916     return float32_ ## name(fst0);                             \
2917 }                                                              \
2918 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2919 {                                                              \
2920     uint32_t wt0;                                              \
2921     uint32_t wth0;                                             \
2922                                                                \
2923     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2924     wth0 = float32_ ## name(fdt0 >> 32);                       \
2925     return ((uint64_t)wth0 << 32) | wt0;                       \
2926 }
2927 FLOAT_UNOP(abs)
2928 FLOAT_UNOP(chs)
2929 #undef FLOAT_UNOP
2930
2931 /* MIPS specific unary operations */
2932 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2933 {
2934     uint64_t fdt2;
2935
2936     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2937     update_fcr31(env, GETPC());
2938     return fdt2;
2939 }
2940
2941 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2942 {
2943     uint32_t fst2;
2944
2945     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2946     update_fcr31(env, GETPC());
2947     return fst2;
2948 }
2949
2950 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2951 {
2952     uint64_t fdt2;
2953
2954     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2955     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2956     update_fcr31(env, GETPC());
2957     return fdt2;
2958 }
2959
2960 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2961 {
2962     uint32_t fst2;
2963
2964     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2965     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2966     update_fcr31(env, GETPC());
2967     return fst2;
2968 }
2969
2970 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2971 {
2972     uint64_t fdt2;
2973
2974     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2975     update_fcr31(env, GETPC());
2976     return fdt2;
2977 }
2978
2979 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2980 {
2981     uint32_t fst2;
2982
2983     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2984     update_fcr31(env, GETPC());
2985     return fst2;
2986 }
2987
2988 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2989 {
2990     uint32_t fst2;
2991     uint32_t fsth2;
2992
2993     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2994     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2995     update_fcr31(env, GETPC());
2996     return ((uint64_t)fsth2 << 32) | fst2;
2997 }
2998
2999 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3000 {
3001     uint64_t fdt2;
3002
3003     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3004     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3005     update_fcr31(env, GETPC());
3006     return fdt2;
3007 }
3008
3009 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3010 {
3011     uint32_t fst2;
3012
3013     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3014     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3015     update_fcr31(env, GETPC());
3016     return fst2;
3017 }
3018
3019 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3020 {
3021     uint32_t fst2;
3022     uint32_t fsth2;
3023
3024     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3025     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3026     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3027     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3028     update_fcr31(env, GETPC());
3029     return ((uint64_t)fsth2 << 32) | fst2;
3030 }
3031
3032 #define FLOAT_RINT(name, bits)                                              \
3033 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3034                                           uint ## bits ## _t fs)            \
3035 {                                                                           \
3036     uint ## bits ## _t fdret;                                               \
3037                                                                             \
3038     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3039     update_fcr31(env, GETPC());                                             \
3040     return fdret;                                                           \
3041 }
3042
3043 FLOAT_RINT(rint_s, 32)
3044 FLOAT_RINT(rint_d, 64)
3045 #undef FLOAT_RINT
3046
3047 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3048 #define FLOAT_CLASS_QUIET_NAN          0x002
3049 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3050 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3051 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3052 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3053 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3054 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3055 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3056 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3057
3058 #define FLOAT_CLASS(name, bits)                                      \
3059 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3060 {                                                                    \
3061     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3062         return FLOAT_CLASS_SIGNALING_NAN;                            \
3063     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3064         return FLOAT_CLASS_QUIET_NAN;                                \
3065     } else if (float ## bits ## _is_neg(arg)) {                      \
3066         if (float ## bits ## _is_infinity(arg)) {                    \
3067             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3068         } else if (float ## bits ## _is_zero(arg)) {                 \
3069             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3070         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3071             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3072         } else {                                                     \
3073             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3074         }                                                            \
3075     } else {                                                         \
3076         if (float ## bits ## _is_infinity(arg)) {                    \
3077             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3078         } else if (float ## bits ## _is_zero(arg)) {                 \
3079             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3080         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3081             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3082         } else {                                                     \
3083             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3084         }                                                            \
3085     }                                                                \
3086 }
3087
3088 FLOAT_CLASS(class_s, 32)
3089 FLOAT_CLASS(class_d, 64)
3090 #undef FLOAT_CLASS
3091
3092 /* binary operations */
3093 #define FLOAT_BINOP(name)                                          \
3094 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3095                                      uint64_t fdt0, uint64_t fdt1) \
3096 {                                                                  \
3097     uint64_t dt2;                                                  \
3098                                                                    \
3099     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3100     update_fcr31(env, GETPC());                                    \
3101     return dt2;                                                    \
3102 }                                                                  \
3103                                                                    \
3104 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3105                                      uint32_t fst0, uint32_t fst1) \
3106 {                                                                  \
3107     uint32_t wt2;                                                  \
3108                                                                    \
3109     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3110     update_fcr31(env, GETPC());                                    \
3111     return wt2;                                                    \
3112 }                                                                  \
3113                                                                    \
3114 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3115                                       uint64_t fdt0,               \
3116                                       uint64_t fdt1)               \
3117 {                                                                  \
3118     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3119     uint32_t fsth0 = fdt0 >> 32;                                   \
3120     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3121     uint32_t fsth1 = fdt1 >> 32;                                   \
3122     uint32_t wt2;                                                  \
3123     uint32_t wth2;                                                 \
3124                                                                    \
3125     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3126     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3127     update_fcr31(env, GETPC());                                    \
3128     return ((uint64_t)wth2 << 32) | wt2;                           \
3129 }
3130
3131 FLOAT_BINOP(add)
3132 FLOAT_BINOP(sub)
3133 FLOAT_BINOP(mul)
3134 FLOAT_BINOP(div)
3135 #undef FLOAT_BINOP
3136
3137 /* MIPS specific binary operations */
3138 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3139 {
3140     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3141     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3142     update_fcr31(env, GETPC());
3143     return fdt2;
3144 }
3145
3146 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3147 {
3148     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3149     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3150     update_fcr31(env, GETPC());
3151     return fst2;
3152 }
3153
3154 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3155 {
3156     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3157     uint32_t fsth0 = fdt0 >> 32;
3158     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3159     uint32_t fsth2 = fdt2 >> 32;
3160
3161     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3162     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3163     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3164     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3165     update_fcr31(env, GETPC());
3166     return ((uint64_t)fsth2 << 32) | fst2;
3167 }
3168
3169 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3170 {
3171     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3172     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3173     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3174     update_fcr31(env, GETPC());
3175     return fdt2;
3176 }
3177
3178 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3179 {
3180     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3181     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3182     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3183     update_fcr31(env, GETPC());
3184     return fst2;
3185 }
3186
3187 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3188 {
3189     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3190     uint32_t fsth0 = fdt0 >> 32;
3191     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3192     uint32_t fsth2 = fdt2 >> 32;
3193
3194     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3195     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3196     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3197     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3198     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3199     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3200     update_fcr31(env, GETPC());
3201     return ((uint64_t)fsth2 << 32) | fst2;
3202 }
3203
3204 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3205 {
3206     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3207     uint32_t fsth0 = fdt0 >> 32;
3208     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3209     uint32_t fsth1 = fdt1 >> 32;
3210     uint32_t fst2;
3211     uint32_t fsth2;
3212
3213     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3214     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3215     update_fcr31(env, GETPC());
3216     return ((uint64_t)fsth2 << 32) | fst2;
3217 }
3218
3219 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3220 {
3221     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3222     uint32_t fsth0 = fdt0 >> 32;
3223     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3224     uint32_t fsth1 = fdt1 >> 32;
3225     uint32_t fst2;
3226     uint32_t fsth2;
3227
3228     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3229     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3230     update_fcr31(env, GETPC());
3231     return ((uint64_t)fsth2 << 32) | fst2;
3232 }
3233
3234 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3235 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3236                                           uint ## bits ## _t fs,        \
3237                                           uint ## bits ## _t ft)        \
3238 {                                                                       \
3239     uint ## bits ## _t fdret;                                           \
3240                                                                         \
3241     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3242                                            &env->active_fpu.fp_status); \
3243     update_fcr31(env, GETPC());                                         \
3244     return fdret;                                                       \
3245 }
3246
3247 FLOAT_MINMAX(max_s, 32, maxnum)
3248 FLOAT_MINMAX(max_d, 64, maxnum)
3249 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3250 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3251
3252 FLOAT_MINMAX(min_s, 32, minnum)
3253 FLOAT_MINMAX(min_d, 64, minnum)
3254 FLOAT_MINMAX(mina_s, 32, minnummag)
3255 FLOAT_MINMAX(mina_d, 64, minnummag)
3256 #undef FLOAT_MINMAX
3257
3258 /* ternary operations */
3259 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3260 {                                                                    \
3261     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3262     if ((flags) & float_muladd_negate_c) {                           \
3263         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3264     } else {                                                         \
3265         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3266     }                                                                \
3267     if ((flags) & float_muladd_negate_result) {                      \
3268         a = prefix##_chs(a);                                         \
3269     }                                                                \
3270 }
3271
3272 /* FMA based operations */
3273 #define FLOAT_FMA(name, type)                                        \
3274 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3275                                      uint64_t fdt0, uint64_t fdt1,   \
3276                                      uint64_t fdt2)                  \
3277 {                                                                    \
3278     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3279     update_fcr31(env, GETPC());                                      \
3280     return fdt0;                                                     \
3281 }                                                                    \
3282                                                                      \
3283 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3284                                      uint32_t fst0, uint32_t fst1,   \
3285                                      uint32_t fst2)                  \
3286 {                                                                    \
3287     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3288     update_fcr31(env, GETPC());                                      \
3289     return fst0;                                                     \
3290 }                                                                    \
3291                                                                      \
3292 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3293                                       uint64_t fdt0, uint64_t fdt1,  \
3294                                       uint64_t fdt2)                 \
3295 {                                                                    \
3296     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3297     uint32_t fsth0 = fdt0 >> 32;                                     \
3298     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3299     uint32_t fsth1 = fdt1 >> 32;                                     \
3300     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3301     uint32_t fsth2 = fdt2 >> 32;                                     \
3302                                                                      \
3303     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3304     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3305     update_fcr31(env, GETPC());                                      \
3306     return ((uint64_t)fsth0 << 32) | fst0;                           \
3307 }
3308 FLOAT_FMA(madd, 0)
3309 FLOAT_FMA(msub, float_muladd_negate_c)
3310 FLOAT_FMA(nmadd, float_muladd_negate_result)
3311 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3312 #undef FLOAT_FMA
3313
3314 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3315 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3316                                           uint ## bits ## _t fs,        \
3317                                           uint ## bits ## _t ft,        \
3318                                           uint ## bits ## _t fd)        \
3319 {                                                                       \
3320     uint ## bits ## _t fdret;                                           \
3321                                                                         \
3322     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3323                                      &env->active_fpu.fp_status);       \
3324     update_fcr31(env, GETPC());                                         \
3325     return fdret;                                                       \
3326 }
3327
3328 FLOAT_FMADDSUB(maddf_s, 32, 0)
3329 FLOAT_FMADDSUB(maddf_d, 64, 0)
3330 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3331 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3332 #undef FLOAT_FMADDSUB
3333
3334 /* compare operations */
3335 #define FOP_COND_D(op, cond)                                   \
3336 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3337                          uint64_t fdt1, int cc)                \
3338 {                                                              \
3339     int c;                                                     \
3340     c = cond;                                                  \
3341     update_fcr31(env, GETPC());                                \
3342     if (c)                                                     \
3343         SET_FP_COND(cc, env->active_fpu);                      \
3344     else                                                       \
3345         CLEAR_FP_COND(cc, env->active_fpu);                    \
3346 }                                                              \
3347 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3348                             uint64_t fdt1, int cc)             \
3349 {                                                              \
3350     int c;                                                     \
3351     fdt0 = float64_abs(fdt0);                                  \
3352     fdt1 = float64_abs(fdt1);                                  \
3353     c = cond;                                                  \
3354     update_fcr31(env, GETPC());                                \
3355     if (c)                                                     \
3356         SET_FP_COND(cc, env->active_fpu);                      \
3357     else                                                       \
3358         CLEAR_FP_COND(cc, env->active_fpu);                    \
3359 }
3360
3361 /* NOTE: the comma operator will make "cond" to eval to false,
3362  * but float64_unordered_quiet() is still called. */
3363 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3364 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3365 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3366 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3367 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3368 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3369 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3370 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3371 /* NOTE: the comma operator will make "cond" to eval to false,
3372  * but float64_unordered() is still called. */
3373 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3374 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3375 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3376 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3377 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3378 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3379 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3380 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3381
3382 #define FOP_COND_S(op, cond)                                   \
3383 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3384                          uint32_t fst1, int cc)                \
3385 {                                                              \
3386     int c;                                                     \
3387     c = cond;                                                  \
3388     update_fcr31(env, GETPC());                                \
3389     if (c)                                                     \
3390         SET_FP_COND(cc, env->active_fpu);                      \
3391     else                                                       \
3392         CLEAR_FP_COND(cc, env->active_fpu);                    \
3393 }                                                              \
3394 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3395                             uint32_t fst1, int cc)             \
3396 {                                                              \
3397     int c;                                                     \
3398     fst0 = float32_abs(fst0);                                  \
3399     fst1 = float32_abs(fst1);                                  \
3400     c = cond;                                                  \
3401     update_fcr31(env, GETPC());                                \
3402     if (c)                                                     \
3403         SET_FP_COND(cc, env->active_fpu);                      \
3404     else                                                       \
3405         CLEAR_FP_COND(cc, env->active_fpu);                    \
3406 }
3407
3408 /* NOTE: the comma operator will make "cond" to eval to false,
3409  * but float32_unordered_quiet() is still called. */
3410 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3411 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3412 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3413 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3414 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3415 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3416 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3417 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3418 /* NOTE: the comma operator will make "cond" to eval to false,
3419  * but float32_unordered() is still called. */
3420 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3421 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3422 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3423 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3424 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3425 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3426 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3427 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3428
3429 #define FOP_COND_PS(op, condl, condh)                           \
3430 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3431                           uint64_t fdt1, int cc)                \
3432 {                                                               \
3433     uint32_t fst0, fsth0, fst1, fsth1;                          \
3434     int ch, cl;                                                 \
3435     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3436     fsth0 = fdt0 >> 32;                                         \
3437     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3438     fsth1 = fdt1 >> 32;                                         \
3439     cl = condl;                                                 \
3440     ch = condh;                                                 \
3441     update_fcr31(env, GETPC());                                 \
3442     if (cl)                                                     \
3443         SET_FP_COND(cc, env->active_fpu);                       \
3444     else                                                        \
3445         CLEAR_FP_COND(cc, env->active_fpu);                     \
3446     if (ch)                                                     \
3447         SET_FP_COND(cc + 1, env->active_fpu);                   \
3448     else                                                        \
3449         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3450 }                                                               \
3451 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3452                              uint64_t fdt1, int cc)             \
3453 {                                                               \
3454     uint32_t fst0, fsth0, fst1, fsth1;                          \
3455     int ch, cl;                                                 \
3456     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3457     fsth0 = float32_abs(fdt0 >> 32);                            \
3458     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3459     fsth1 = float32_abs(fdt1 >> 32);                            \
3460     cl = condl;                                                 \
3461     ch = condh;                                                 \
3462     update_fcr31(env, GETPC());                                 \
3463     if (cl)                                                     \
3464         SET_FP_COND(cc, env->active_fpu);                       \
3465     else                                                        \
3466         CLEAR_FP_COND(cc, env->active_fpu);                     \
3467     if (ch)                                                     \
3468         SET_FP_COND(cc + 1, env->active_fpu);                   \
3469     else                                                        \
3470         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3471 }
3472
3473 /* NOTE: the comma operator will make "cond" to eval to false,
3474  * but float32_unordered_quiet() is still called. */
3475 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3476                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3477 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3478                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3479 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3480                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3481 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3482                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3483 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3484                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3485 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3486                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3487 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3488                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3489 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3490                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3491 /* NOTE: the comma operator will make "cond" to eval to false,
3492  * but float32_unordered() is still called. */
3493 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3494                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3495 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3496                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3497 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3498                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3499 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3500                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3501 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3502                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3503 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3504                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3505 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3506                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3507 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3508                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3509
3510 /* R6 compare operations */
3511 #define FOP_CONDN_D(op, cond)                                       \
3512 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3513                          uint64_t fdt1)                             \
3514 {                                                                   \
3515     uint64_t c;                                                     \
3516     c = cond;                                                       \
3517     update_fcr31(env, GETPC());                                     \
3518     if (c) {                                                        \
3519         return -1;                                                  \
3520     } else {                                                        \
3521         return 0;                                                   \
3522     }                                                               \
3523 }
3524
3525 /* NOTE: the comma operator will make "cond" to eval to false,
3526  * but float64_unordered_quiet() is still called. */
3527 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3528 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3529 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3530 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3531                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3532 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3533 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3534                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3535 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3536 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3537                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3538 /* NOTE: the comma operator will make "cond" to eval to false,
3539  * but float64_unordered() is still called. */
3540 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3541 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3542 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3543 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3544                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3545 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3546 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3547                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3548 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3549 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3550                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3551 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3552                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3553 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3554                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3555                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3556 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3557                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3558 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3559                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3560 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3561                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3562                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3563 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3564                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3565
3566 #define FOP_CONDN_S(op, cond)                                       \
3567 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3568                          uint32_t fst1)                             \
3569 {                                                                   \
3570     uint64_t c;                                                     \
3571     c = cond;                                                       \
3572     update_fcr31(env, GETPC());                                     \
3573     if (c) {                                                        \
3574         return -1;                                                  \
3575     } else {                                                        \
3576         return 0;                                                   \
3577     }                                                               \
3578 }
3579
3580 /* NOTE: the comma operator will make "cond" to eval to false,
3581  * but float32_unordered_quiet() is still called. */
3582 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3583 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3584 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3585 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3586                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3587 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3588 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3589                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3590 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3591 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3592                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3593 /* NOTE: the comma operator will make "cond" to eval to false,
3594  * but float32_unordered() is still called. */
3595 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3596 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3597 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3598 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3599                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3600 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3601 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3602                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3603 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3604 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3605                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3606 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3607                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3608 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3609                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3610                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3611 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3612                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3613 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3614                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3615 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3616                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3617                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3618 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3619                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3620
3621 /* MSA */
3622 /* Data format min and max values */
3623 #define DF_BITS(df) (1 << ((df) + 3))
3624
3625 /* Element-by-element access macros */
3626 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3627
3628 #if !defined(CONFIG_USER_ONLY)
3629 #define MEMOP_IDX(DF)                                           \
3630         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
3631                                         cpu_mmu_index(env));
3632 #else
3633 #define MEMOP_IDX(DF)
3634 #endif
3635
3636 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
3637 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3638                             target_ulong addr)                          \
3639 {                                                                       \
3640     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3641     wr_t wx;                                                            \
3642     int i;                                                              \
3643     MEMOP_IDX(DF)                                                       \
3644     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3645         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
3646     }                                                                   \
3647     memcpy(pwd, &wx, sizeof(wr_t));                                     \
3648 }
3649
3650 #if !defined(CONFIG_USER_ONLY)
3651 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
3652 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
3653 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
3654 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
3655 #else
3656 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
3657 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
3658 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
3659 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3660 #endif
3661
3662 #define MSA_PAGESPAN(x) \
3663         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3664
3665 static inline void ensure_writable_pages(CPUMIPSState *env,
3666                                          target_ulong addr,
3667                                          int mmu_idx,
3668                                          uintptr_t retaddr)
3669 {
3670 #if !defined(CONFIG_USER_ONLY)
3671     target_ulong page_addr;
3672     if (unlikely(MSA_PAGESPAN(addr))) {
3673         /* first page */
3674         probe_write(env, addr, mmu_idx, retaddr);
3675         /* second page */
3676         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3677         probe_write(env, page_addr, mmu_idx, retaddr);
3678     }
3679 #endif
3680 }
3681
3682 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
3683 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3684                             target_ulong addr)                          \
3685 {                                                                       \
3686     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3687     int mmu_idx = cpu_mmu_index(env);                                   \
3688     int i;                                                              \
3689     MEMOP_IDX(DF)                                                       \
3690     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
3691     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3692         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
3693     }                                                                   \
3694 }
3695
3696 #if !defined(CONFIG_USER_ONLY)
3697 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
3698 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
3699 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
3700 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3701 #else
3702 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
3703 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
3704 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
3705 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3706 #endif