hw/isa/piix3.c

   1 /*
   2  * QEMU PIIX PCI ISA Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/range.h"
  27 #include "qapi/error.h"
  28 #include "hw/dma/i8257.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/irq.h"
  31 #include "hw/qdev-properties.h"
  32 #include "hw/ide/piix.h"
  33 #include "hw/isa/isa.h"
  34 #include "sysemu/runstate.h"
  35 #include "migration/vmstate.h"
  36 #include "hw/acpi/acpi_aml_interface.h"
  37
  38 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
  39 {
  40     qemu_set_irq(piix3->isa_irqs_in[pic_irq],
  41                  !!(piix3->pic_levels &
  42                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
  43                      (pic_irq * PIIX_NUM_PIRQS))));
  44 }
  45
  46 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
  47 {
  48     int pic_irq;
  49     uint64_t mask;
  50
  51     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  52     if (pic_irq >= ISA_NUM_IRQS) {
  53         return;
  54     }
  55
  56     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
  57     piix3->pic_levels &= ~mask;
  58     piix3->pic_levels |= mask * !!level;
  59 }
  60
  61 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
  62 {
  63     int pic_irq;
  64
  65     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  66     if (pic_irq >= ISA_NUM_IRQS) {
  67         return;
  68     }
  69
  70     piix3_set_irq_level_internal(piix3, pirq, level);
  71
  72     piix3_set_irq_pic(piix3, pic_irq);
  73 }
  74
  75 static void piix3_set_irq(void *opaque, int pirq, int level)
  76 {
  77     PIIX3State *piix3 = opaque;
  78     piix3_set_irq_level(piix3, pirq, level);
  79 }
  80
  81 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
  82 {
  83     PIIX3State *piix3 = opaque;
  84     int irq = piix3->dev.config[PIIX_PIRQCA + pin];
  85     PCIINTxRoute route;
  86
  87     if (irq < ISA_NUM_IRQS) {
  88         route.mode = PCI_INTX_ENABLED;
  89         route.irq = irq;
  90     } else {
  91         route.mode = PCI_INTX_DISABLED;
  92         route.irq = -1;
  93     }
  94     return route;
  95 }
  96
  97 /* irq routing is changed. so rebuild bitmap */
  98 static void piix3_update_irq_levels(PIIX3State *piix3)
  99 {
 100     PCIBus *bus = pci_get_bus(&piix3->dev);
 101     int pirq;
 102
 103     piix3->pic_levels = 0;
 104     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 105         piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
 106     }
 107 }
 108
 109 static void piix3_write_config(PCIDevice *dev,
 110                                uint32_t address, uint32_t val, int len)
 111 {
 112     pci_default_write_config(dev, address, val, len);
 113     if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
 114         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 115         int pic_irq;
 116
 117         pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
 118         piix3_update_irq_levels(piix3);
 119         for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
 120             piix3_set_irq_pic(piix3, pic_irq);
 121         }
 122     }
 123 }
 124
 125 static void piix3_reset(DeviceState *dev)
 126 {
 127     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 128     uint8_t *pci_conf = d->dev.config;
 129
 130     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 131     pci_conf[0x05] = 0x00;
 132     pci_conf[0x06] = 0x00;
 133     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 134     pci_conf[0x4c] = 0x4d;
 135     pci_conf[0x4e] = 0x03;
 136     pci_conf[0x4f] = 0x00;
 137     pci_conf[0x60] = 0x80;
 138     pci_conf[0x61] = 0x80;
 139     pci_conf[0x62] = 0x80;
 140     pci_conf[0x63] = 0x80;
 141     pci_conf[0x69] = 0x02;
 142     pci_conf[0x70] = 0x80;
 143     pci_conf[0x76] = 0x0c;
 144     pci_conf[0x77] = 0x0c;
 145     pci_conf[0x78] = 0x02;
 146     pci_conf[0x79] = 0x00;
 147     pci_conf[0x80] = 0x00;
 148     pci_conf[0x82] = 0x00;
 149     pci_conf[0xa0] = 0x08;
 150     pci_conf[0xa2] = 0x00;
 151     pci_conf[0xa3] = 0x00;
 152     pci_conf[0xa4] = 0x00;
 153     pci_conf[0xa5] = 0x00;
 154     pci_conf[0xa6] = 0x00;
 155     pci_conf[0xa7] = 0x00;
 156     pci_conf[0xa8] = 0x0f;
 157     pci_conf[0xaa] = 0x00;
 158     pci_conf[0xab] = 0x00;
 159     pci_conf[0xac] = 0x00;
 160     pci_conf[0xae] = 0x00;
 161
 162     d->pic_levels = 0;
 163     d->rcr = 0;
 164 }
 165
 166 static int piix3_post_load(void *opaque, int version_id)
 167 {
 168     PIIX3State *piix3 = opaque;
 169     int pirq;
 170
 171     /*
 172      * Because the i8259 has not been deserialized yet, qemu_irq_raise
 173      * might bring the system to a different state than the saved one;
 174      * for example, the interrupt could be masked but the i8259 would
 175      * not know that yet and would trigger an interrupt in the CPU.
 176      *
 177      * Here, we update irq levels without raising the interrupt.
 178      * Interrupt state will be deserialized separately through the i8259.
 179      */
 180     piix3->pic_levels = 0;
 181     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 182         piix3_set_irq_level_internal(piix3, pirq,
 183             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
 184     }
 185     return 0;
 186 }
 187
 188 static int piix3_pre_save(void *opaque)
 189 {
 190     int i;
 191     PIIX3State *piix3 = opaque;
 192
 193     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 194         piix3->pci_irq_levels_vmstate[i] =
 195             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
 196     }
 197
 198     return 0;
 199 }
 200
 201 static bool piix3_rcr_needed(void *opaque)
 202 {
 203     PIIX3State *piix3 = opaque;
 204
 205     return (piix3->rcr != 0);
 206 }
 207
 208 static const VMStateDescription vmstate_piix3_rcr = {
 209     .name = "PIIX3/rcr",
 210     .version_id = 1,
 211     .minimum_version_id = 1,
 212     .needed = piix3_rcr_needed,
 213     .fields = (VMStateField[]) {
 214         VMSTATE_UINT8(rcr, PIIX3State),
 215         VMSTATE_END_OF_LIST()
 216     }
 217 };
 218
 219 static const VMStateDescription vmstate_piix3 = {
 220     .name = "PIIX3",
 221     .version_id = 3,
 222     .minimum_version_id = 2,
 223     .post_load = piix3_post_load,
 224     .pre_save = piix3_pre_save,
 225     .fields = (VMStateField[]) {
 226         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 227         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 228                               PIIX_NUM_PIRQS, 3),
 229         VMSTATE_END_OF_LIST()
 230     },
 231     .subsections = (const VMStateDescription*[]) {
 232         &vmstate_piix3_rcr,
 233         NULL
 234     }
 235 };
 236
 237
 238 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 239 {
 240     PIIX3State *d = opaque;
 241
 242     if (val & 4) {
 243         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 244         return;
 245     }
 246     d->rcr = val & 2; /* keep System Reset type only */
 247 }
 248
 249 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 250 {
 251     PIIX3State *d = opaque;
 252
 253     return d->rcr;
 254 }
 255
 256 static const MemoryRegionOps rcr_ops = {
 257     .read = rcr_read,
 258     .write = rcr_write,
 259     .endianness = DEVICE_LITTLE_ENDIAN,
 260     .impl = {
 261         .min_access_size = 1,
 262         .max_access_size = 1,
 263     },
 264 };
 265
 266 static void pci_piix3_realize(PCIDevice *dev, Error **errp)
 267 {
 268     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 269     PCIBus *pci_bus = pci_get_bus(dev);
 270     ISABus *isa_bus;
 271     uint32_t irq;
 272
 273     isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
 274                           pci_address_space_io(dev), errp);
 275     if (!isa_bus) {
 276         return;
 277     }
 278
 279     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 280                           "piix3-reset-control", 1);
 281     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 282                                         PIIX_RCR_IOPORT, &d->rcr_mem, 1);
 283
 284     isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in);
 285
 286     i8257_dma_init(isa_bus, 0);
 287
 288     /* RTC */
 289     qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
 290     if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
 291         return;
 292     }
 293     irq = object_property_get_uint(OBJECT(&d->rtc), "irq", &error_fatal);
 294     isa_connect_gpio_out(ISA_DEVICE(&d->rtc), 0, irq);
 295
 296     /* IDE */
 297     qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1);
 298     if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
 299         return;
 300     }
 301
 302     /* USB */
 303     if (d->has_usb) {
 304         object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
 305                                 TYPE_PIIX3_USB_UHCI);
 306         qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
 307         if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
 308             return;
 309         }
 310     }
 311 }
 312
 313 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
 314 {
 315     Aml *field;
 316     Aml *sb_scope = aml_scope("\\_SB");
 317     BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
 318
 319     /* PIIX PCI to ISA irq remapping */
 320     aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
 321                                            aml_int(0x60), 0x04));
 322     /* Fields declarion has to happen *after* operation region */
 323     field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
 324     aml_append(field, aml_named_field("PRQ0", 8));
 325     aml_append(field, aml_named_field("PRQ1", 8));
 326     aml_append(field, aml_named_field("PRQ2", 8));
 327     aml_append(field, aml_named_field("PRQ3", 8));
 328     aml_append(sb_scope, field);
 329     aml_append(scope, sb_scope);
 330
 331     qbus_build_aml(bus, scope);
 332 }
 333
 334 static void pci_piix3_init(Object *obj)
 335 {
 336     PIIX3State *d = PIIX3_PCI_DEVICE(obj);
 337
 338     qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs",
 339                              ISA_NUM_IRQS);
 340
 341     object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
 342     object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
 343 }
 344
 345 static Property pci_piix3_props[] = {
 346     DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
 347     DEFINE_PROP_END_OF_LIST(),
 348 };
 349
 350 static void pci_piix3_class_init(ObjectClass *klass, void *data)
 351 {
 352     DeviceClass *dc = DEVICE_CLASS(klass);
 353     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 354     AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 355
 356     k->config_write = piix3_write_config;
 357     dc->reset       = piix3_reset;
 358     dc->desc        = "ISA bridge";
 359     dc->vmsd        = &vmstate_piix3;
 360     dc->hotpluggable   = false;
 361     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 362     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 363     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 364     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 365     /*
 366      * Reason: part of PIIX3 southbridge, needs to be wired up by
 367      * pc_piix.c's pc_init1()
 368      */
 369     dc->user_creatable = false;
 370     device_class_set_props(dc, pci_piix3_props);
 371     adevc->build_dev_aml = build_pci_isa_aml;
 372 }
 373
 374 static const TypeInfo piix3_pci_type_info = {
 375     .name = TYPE_PIIX3_PCI_DEVICE,
 376     .parent = TYPE_PCI_DEVICE,
 377     .instance_size = sizeof(PIIX3State),
 378     .instance_init = pci_piix3_init,
 379     .abstract = true,
 380     .class_init = pci_piix3_class_init,
 381     .interfaces = (InterfaceInfo[]) {
 382         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 383         { TYPE_ACPI_DEV_AML_IF },
 384         { },
 385     },
 386 };
 387
 388 static void piix3_realize(PCIDevice *dev, Error **errp)
 389 {
 390     ERRP_GUARD();
 391     PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 392     PCIBus *pci_bus = pci_get_bus(dev);
 393
 394     pci_piix3_realize(dev, errp);
 395     if (*errp) {
 396         return;
 397     }
 398
 399     pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS);
 400     pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
 401 }
 402
 403 static void piix3_class_init(ObjectClass *klass, void *data)
 404 {
 405     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 406
 407     k->realize = piix3_realize;
 408 }
 409
 410 static const TypeInfo piix3_info = {
 411     .name          = TYPE_PIIX3_DEVICE,
 412     .parent        = TYPE_PIIX3_PCI_DEVICE,
 413     .class_init    = piix3_class_init,
 414 };
 415
 416 static void piix3_register_types(void)
 417 {
 418     type_register_static(&piix3_pci_type_info);
 419     type_register_static(&piix3_info);
 420 }
 421
 422 type_init(piix3_register_types)