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xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob95e0c657a7b3417d1d9c774fe5ced73b87e17d4e
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
45
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
53
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61
62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
64 * a little bit, there should be plenty of free space since the DSDT
65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
66 */
67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
68 #define ACPI_BUILD_ALIGN_SIZE 0x1000
69
70 #define ACPI_BUILD_TABLE_SIZE 0x20000
71
72 /* #define DEBUG_ACPI_BUILD */
73 #ifdef DEBUG_ACPI_BUILD
74 #define ACPI_BUILD_DPRINTF(fmt, ...) \
75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
76 #else
77 #define ACPI_BUILD_DPRINTF(fmt, ...)
78 #endif
79
80 typedef struct AcpiCpuInfo {
81 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
82 } AcpiCpuInfo;
83
84 typedef struct AcpiMcfgInfo {
85 uint64_t mcfg_base;
86 uint32_t mcfg_size;
87 } AcpiMcfgInfo;
88
89 typedef struct AcpiPmInfo {
90 bool s3_disabled;
91 bool s4_disabled;
92 bool pcihp_bridge_en;
93 uint8_t s4_val;
94 uint16_t sci_int;
95 uint8_t acpi_enable_cmd;
96 uint8_t acpi_disable_cmd;
97 uint32_t gpe0_blk;
98 uint32_t gpe0_blk_len;
99 uint32_t io_base;
100 uint16_t cpu_hp_io_base;
101 uint16_t cpu_hp_io_len;
102 uint16_t mem_hp_io_base;
103 uint16_t mem_hp_io_len;
104 uint16_t pcihp_io_base;
105 uint16_t pcihp_io_len;
106 } AcpiPmInfo;
107
108 typedef struct AcpiMiscInfo {
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 static void acpi_get_dsdt(AcpiMiscInfo *info)
125 {
126 Object *piix = piix4_pm_find();
127 Object *lpc = ich9_lpc_find();
128 assert(!!piix != !!lpc);
129
130 if (piix) {
131 info->dsdt_code = AcpiDsdtAmlCode;
132 info->dsdt_size = sizeof AcpiDsdtAmlCode;
133 }
134 if (lpc) {
135 info->dsdt_code = Q35AcpiDsdtAmlCode;
136 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
137 }
138 }
139
140 static
141 int acpi_add_cpu_info(Object *o, void *opaque)
142 {
143 AcpiCpuInfo *cpu = opaque;
144 uint64_t apic_id;
145
146 if (object_dynamic_cast(o, TYPE_CPU)) {
147 apic_id = object_property_get_int(o, "apic-id", NULL);
148 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
149
150 set_bit(apic_id, cpu->found_cpus);
151 }
152
153 object_child_foreach(o, acpi_add_cpu_info, opaque);
154 return 0;
155 }
156
157 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
158 {
159 Object *root = object_get_root();
160
161 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
162 object_child_foreach(root, acpi_add_cpu_info, cpu);
163 }
164
165 static void acpi_get_pm_info(AcpiPmInfo *pm)
166 {
167 Object *piix = piix4_pm_find();
168 Object *lpc = ich9_lpc_find();
169 Object *obj = NULL;
170 QObject *o;
171
172 pm->cpu_hp_io_base = 0;
173 pm->pcihp_io_base = 0;
174 pm->pcihp_io_len = 0;
175 if (piix) {
176 obj = piix;
177 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
178 pm->pcihp_io_base =
179 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
180 pm->pcihp_io_len =
181 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
182 }
183 if (lpc) {
184 obj = lpc;
185 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
186 }
187 assert(obj);
188
189 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
190 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
191 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
192
193 /* Fill in optional s3/s4 related properties */
194 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
195 if (o) {
196 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
197 } else {
198 pm->s3_disabled = false;
199 }
200 qobject_decref(o);
201 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
202 if (o) {
203 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
204 } else {
205 pm->s4_disabled = false;
206 }
207 qobject_decref(o);
208 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
209 if (o) {
210 pm->s4_val = qint_get_int(qobject_to_qint(o));
211 } else {
212 pm->s4_val = false;
213 }
214 qobject_decref(o);
215
216 /* Fill in mandatory properties */
217 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
218
219 pm->acpi_enable_cmd = object_property_get_int(obj,
220 ACPI_PM_PROP_ACPI_ENABLE_CMD,
221 NULL);
222 pm->acpi_disable_cmd = object_property_get_int(obj,
223 ACPI_PM_PROP_ACPI_DISABLE_CMD,
224 NULL);
225 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
226 NULL);
227 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
228 NULL);
229 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
230 NULL);
231 pm->pcihp_bridge_en =
232 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
233 NULL);
234 }
235
236 static void acpi_get_misc_info(AcpiMiscInfo *info)
237 {
238 info->has_hpet = hpet_find();
239 info->tpm_version = tpm_get_version();
240 info->pvpanic_port = pvpanic_port();
241 info->applesmc_io_base = applesmc_port();
242 }
243
244 /*
245 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
246 * On i386 arch we only have two pci hosts, so we can look only for them.
247 */
248 static Object *acpi_get_i386_pci_host(void)
249 {
250 PCIHostState *host;
251
252 host = OBJECT_CHECK(PCIHostState,
253 object_resolve_path("/machine/i440fx", NULL),
254 TYPE_PCI_HOST_BRIDGE);
255 if (!host) {
256 host = OBJECT_CHECK(PCIHostState,
257 object_resolve_path("/machine/q35", NULL),
258 TYPE_PCI_HOST_BRIDGE);
259 }
260
261 return OBJECT(host);
262 }
263
264 static void acpi_get_pci_info(PcPciInfo *info)
265 {
266 Object *pci_host;
267
268
269 pci_host = acpi_get_i386_pci_host();
270 g_assert(pci_host);
271
272 info->w32.begin = object_property_get_int(pci_host,
273 PCI_HOST_PROP_PCI_HOLE_START,
274 NULL);
275 info->w32.end = object_property_get_int(pci_host,
276 PCI_HOST_PROP_PCI_HOLE_END,
277 NULL);
278 info->w64.begin = object_property_get_int(pci_host,
279 PCI_HOST_PROP_PCI_HOLE64_START,
280 NULL);
281 info->w64.end = object_property_get_int(pci_host,
282 PCI_HOST_PROP_PCI_HOLE64_END,
283 NULL);
284 }
285
286 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
287
288 static void acpi_align_size(GArray *blob, unsigned align)
289 {
290 /* Align size to multiple of given size. This reduces the chance
291 * we need to change size in the future (breaking cross version migration).
292 */
293 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
294 }
295
296 /* FACS */
297 static void
298 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
299 {
300 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
301 memcpy(&facs->signature, "FACS", 4);
302 facs->length = cpu_to_le32(sizeof(*facs));
303 }
304
305 /* Load chipset information in FADT */
306 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
307 {
308 fadt->model = 1;
309 fadt->reserved1 = 0;
310 fadt->sci_int = cpu_to_le16(pm->sci_int);
311 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
312 fadt->acpi_enable = pm->acpi_enable_cmd;
313 fadt->acpi_disable = pm->acpi_disable_cmd;
314 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
315 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
316 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
317 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
318 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
319 /* EVT, CNT, TMR length matches hw/acpi/core.c */
320 fadt->pm1_evt_len = 4;
321 fadt->pm1_cnt_len = 2;
322 fadt->pm_tmr_len = 4;
323 fadt->gpe0_blk_len = pm->gpe0_blk_len;
324 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
325 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
326 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
327 (1 << ACPI_FADT_F_PROC_C1) |
328 (1 << ACPI_FADT_F_SLP_BUTTON) |
329 (1 << ACPI_FADT_F_RTC_S4));
330 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
331 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
332 * For more than 8 CPUs, "Clustered Logical" mode has to be used
333 */
334 if (max_cpus > 8) {
335 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
336 }
337 }
338
339
340 /* FADT */
341 static void
342 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
343 unsigned facs, unsigned dsdt)
344 {
345 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
346
347 fadt->firmware_ctrl = cpu_to_le32(facs);
348 /* FACS address to be filled by Guest linker */
349 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
350 ACPI_BUILD_TABLE_FILE,
351 table_data, &fadt->firmware_ctrl,
352 sizeof fadt->firmware_ctrl);
353
354 fadt->dsdt = cpu_to_le32(dsdt);
355 /* DSDT address to be filled by Guest linker */
356 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
357 ACPI_BUILD_TABLE_FILE,
358 table_data, &fadt->dsdt,
359 sizeof fadt->dsdt);
360
361 fadt_setup(fadt, pm);
362
363 build_header(linker, table_data,
364 (void *)fadt, "FACP", sizeof(*fadt), 1);
365 }
366
367 static void
368 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
369 PcGuestInfo *guest_info)
370 {
371 int madt_start = table_data->len;
372
373 AcpiMultipleApicTable *madt;
374 AcpiMadtIoApic *io_apic;
375 AcpiMadtIntsrcovr *intsrcovr;
376 AcpiMadtLocalNmi *local_nmi;
377 int i;
378
379 madt = acpi_data_push(table_data, sizeof *madt);
380 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
381 madt->flags = cpu_to_le32(1);
382
383 for (i = 0; i < guest_info->apic_id_limit; i++) {
384 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
385 apic->type = ACPI_APIC_PROCESSOR;
386 apic->length = sizeof(*apic);
387 apic->processor_id = i;
388 apic->local_apic_id = i;
389 if (test_bit(i, cpu->found_cpus)) {
390 apic->flags = cpu_to_le32(1);
391 } else {
392 apic->flags = cpu_to_le32(0);
393 }
394 }
395 io_apic = acpi_data_push(table_data, sizeof *io_apic);
396 io_apic->type = ACPI_APIC_IO;
397 io_apic->length = sizeof(*io_apic);
398 #define ACPI_BUILD_IOAPIC_ID 0x0
399 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
400 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
401 io_apic->interrupt = cpu_to_le32(0);
402
403 if (guest_info->apic_xrupt_override) {
404 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
405 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
406 intsrcovr->length = sizeof(*intsrcovr);
407 intsrcovr->source = 0;
408 intsrcovr->gsi = cpu_to_le32(2);
409 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
410 }
411 for (i = 1; i < 16; i++) {
412 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
413 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
414 /* No need for a INT source override structure. */
415 continue;
416 }
417 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
418 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
419 intsrcovr->length = sizeof(*intsrcovr);
420 intsrcovr->source = i;
421 intsrcovr->gsi = cpu_to_le32(i);
422 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
423 }
424
425 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
426 local_nmi->type = ACPI_APIC_LOCAL_NMI;
427 local_nmi->length = sizeof(*local_nmi);
428 local_nmi->processor_id = 0xff; /* all processors */
429 local_nmi->flags = cpu_to_le16(0);
430 local_nmi->lint = 1; /* ACPI_LINT1 */
431
432 build_header(linker, table_data,
433 (void *)(table_data->data + madt_start), "APIC",
434 table_data->len - madt_start, 1);
435 }
436
437 /* Assign BSEL property to all buses. In the future, this can be changed
438 * to only assign to buses that support hotplug.
439 */
440 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
441 {
442 unsigned *bsel_alloc = opaque;
443 unsigned *bus_bsel;
444
445 if (qbus_is_hotpluggable(BUS(bus))) {
446 bus_bsel = g_malloc(sizeof *bus_bsel);
447
448 *bus_bsel = (*bsel_alloc)++;
449 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
450 bus_bsel, NULL);
451 }
452
453 return bsel_alloc;
454 }
455
456 static void acpi_set_pci_info(void)
457 {
458 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
459 unsigned bsel_alloc = 0;
460
461 if (bus) {
462 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
463 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
464 }
465 }
466
467 static void build_append_pcihp_notify_entry(Aml *method, int slot)
468 {
469 Aml *if_ctx;
470 int32_t devfn = PCI_DEVFN(slot, 0);
471
472 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot)));
473 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
474 aml_append(method, if_ctx);
475 }
476
477 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
478 bool pcihp_bridge_en)
479 {
480 Aml *dev, *notify_method, *method;
481 QObject *bsel;
482 PCIBus *sec;
483 int i;
484
485 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
486 if (bsel) {
487 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
488
489 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
490 notify_method = aml_method("DVNT", 2);
491 }
492
493 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
494 DeviceClass *dc;
495 PCIDeviceClass *pc;
496 PCIDevice *pdev = bus->devices[i];
497 int slot = PCI_SLOT(i);
498 bool hotplug_enabled_dev;
499 bool bridge_in_acpi;
500
501 if (!pdev) {
502 if (bsel) { /* add hotplug slots for non present devices */
503 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
504 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
505 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
506 method = aml_method("_EJ0", 1);
507 aml_append(method,
508 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
509 );
510 aml_append(dev, method);
511 aml_append(parent_scope, dev);
512
513 build_append_pcihp_notify_entry(notify_method, slot);
514 }
515 continue;
516 }
517
518 pc = PCI_DEVICE_GET_CLASS(pdev);
519 dc = DEVICE_GET_CLASS(pdev);
520
521 /* When hotplug for bridges is enabled, bridges are
522 * described in ACPI separately (see build_pci_bus_end).
523 * In this case they aren't themselves hot-pluggable.
524 * Hotplugged bridges *are* hot-pluggable.
525 */
526 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
527 !DEVICE(pdev)->hotplugged;
528
529 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
530
531 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
532 continue;
533 }
534
535 /* start to compose PCI slot descriptor */
536 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
537 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
538
539 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
540 /* add VGA specific AML methods */
541 int s3d;
542
543 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
544 s3d = 3;
545 } else {
546 s3d = 0;
547 }
548
549 method = aml_method("_S1D", 0);
550 aml_append(method, aml_return(aml_int(0)));
551 aml_append(dev, method);
552
553 method = aml_method("_S2D", 0);
554 aml_append(method, aml_return(aml_int(0)));
555 aml_append(dev, method);
556
557 method = aml_method("_S3D", 0);
558 aml_append(method, aml_return(aml_int(s3d)));
559 aml_append(dev, method);
560 } else if (hotplug_enabled_dev) {
561 /* add _SUN/_EJ0 to make slot hotpluggable */
562 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
563
564 method = aml_method("_EJ0", 1);
565 aml_append(method,
566 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
567 );
568 aml_append(dev, method);
569
570 if (bsel) {
571 build_append_pcihp_notify_entry(notify_method, slot);
572 }
573 } else if (bridge_in_acpi) {
574 /*
575 * device is coldplugged bridge,
576 * add child device descriptions into its scope
577 */
578 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
579
580 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
581 }
582 /* slot descriptor has been composed, add it into parent context */
583 aml_append(parent_scope, dev);
584 }
585
586 if (bsel) {
587 aml_append(parent_scope, notify_method);
588 }
589
590 /* Append PCNT method to notify about events on local and child buses.
591 * Add unconditionally for root since DSDT expects it.
592 */
593 method = aml_method("PCNT", 0);
594
595 /* If bus supports hotplug select it and notify about local events */
596 if (bsel) {
597 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
598 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
599 aml_append(method,
600 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
601 );
602 aml_append(method,
603 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
604 );
605 }
606
607 /* Notify about child bus events in any case */
608 if (pcihp_bridge_en) {
609 QLIST_FOREACH(sec, &bus->child, sibling) {
610 int32_t devfn = sec->parent_dev->devfn;
611
612 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
613 }
614 }
615 aml_append(parent_scope, method);
616 qobject_decref(bsel);
617 }
618
619 /*
620 * initialize_route - Initialize the interrupt routing rule
621 * through a specific LINK:
622 * if (lnk_idx == idx)
623 * route using link 'link_name'
624 */
625 static Aml *initialize_route(Aml *route, const char *link_name,
626 Aml *lnk_idx, int idx)
627 {
628 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
629 Aml *pkg = aml_package(4);
630
631 aml_append(pkg, aml_int(0));
632 aml_append(pkg, aml_int(0));
633 aml_append(pkg, aml_name("%s", link_name));
634 aml_append(pkg, aml_int(0));
635 aml_append(if_ctx, aml_store(pkg, route));
636
637 return if_ctx;
638 }
639
640 /*
641 * build_prt - Define interrupt rounting rules
642 *
643 * Returns an array of 128 routes, one for each device,
644 * based on device location.
645 * The main goal is to equaly distribute the interrupts
646 * over the 4 existing ACPI links (works only for i440fx).
647 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
648 *
649 */
650 static Aml *build_prt(void)
651 {
652 Aml *method, *while_ctx, *pin, *res;
653
654 method = aml_method("_PRT", 0);
655 res = aml_local(0);
656 pin = aml_local(1);
657 aml_append(method, aml_store(aml_package(128), res));
658 aml_append(method, aml_store(aml_int(0), pin));
659
660 /* while (pin < 128) */
661 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
662 {
663 Aml *slot = aml_local(2);
664 Aml *lnk_idx = aml_local(3);
665 Aml *route = aml_local(4);
666
667 /* slot = pin >> 2 */
668 aml_append(while_ctx,
669 aml_store(aml_shiftright(pin, aml_int(2)), slot));
670 /* lnk_idx = (slot + pin) & 3 */
671 aml_append(while_ctx,
672 aml_store(aml_and(aml_add(pin, slot), aml_int(3)), lnk_idx));
673
674 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
675 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
676 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
677 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
678 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
679
680 /* route[0] = 0x[slot]FFFF */
681 aml_append(while_ctx,
682 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF)),
683 aml_index(route, aml_int(0))));
684 /* route[1] = pin & 3 */
685 aml_append(while_ctx,
686 aml_store(aml_and(pin, aml_int(3)), aml_index(route, aml_int(1))));
687 /* res[pin] = route */
688 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
689 /* pin++ */
690 aml_append(while_ctx, aml_increment(pin));
691 }
692 aml_append(method, while_ctx);
693 /* return res*/
694 aml_append(method, aml_return(res));
695
696 return method;
697 }
698
699 typedef struct CrsRangeEntry {
700 uint64_t base;
701 uint64_t limit;
702 } CrsRangeEntry;
703
704 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
705 {
706 CrsRangeEntry *entry;
707
708 entry = g_malloc(sizeof(*entry));
709 entry->base = base;
710 entry->limit = limit;
711
712 g_ptr_array_add(ranges, entry);
713 }
714
715 static void crs_range_free(gpointer data)
716 {
717 CrsRangeEntry *entry = (CrsRangeEntry *)data;
718 g_free(entry);
719 }
720
721 static gint crs_range_compare(gconstpointer a, gconstpointer b)
722 {
723 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
724 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
725
726 return (int64_t)entry_a->base - (int64_t)entry_b->base;
727 }
728
729 /*
730 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
731 * interval, computes the 'free' ranges from the same interval.
732 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
733 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
734 */
735 static void crs_replace_with_free_ranges(GPtrArray *ranges,
736 uint64_t start, uint64_t end)
737 {
738 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
739 uint64_t free_base = start;
740 int i;
741
742 g_ptr_array_sort(ranges, crs_range_compare);
743 for (i = 0; i < ranges->len; i++) {
744 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
745
746 if (free_base < used->base) {
747 crs_range_insert(free_ranges, free_base, used->base - 1);
748 }
749
750 free_base = used->limit + 1;
751 }
752
753 if (free_base < end) {
754 crs_range_insert(free_ranges, free_base, end);
755 }
756
757 g_ptr_array_set_size(ranges, 0);
758 for (i = 0; i < free_ranges->len; i++) {
759 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
760 }
761
762 g_ptr_array_free(free_ranges, false);
763 }
764
765 static Aml *build_crs(PCIHostState *host,
766 GPtrArray *io_ranges, GPtrArray *mem_ranges)
767 {
768 Aml *crs = aml_resource_template();
769 uint8_t max_bus = pci_bus_num(host->bus);
770 uint8_t type;
771 int devfn;
772
773 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
774 int i;
775 uint64_t range_base, range_limit;
776 PCIDevice *dev = host->bus->devices[devfn];
777
778 if (!dev) {
779 continue;
780 }
781
782 for (i = 0; i < PCI_NUM_REGIONS; i++) {
783 PCIIORegion *r = &dev->io_regions[i];
784
785 range_base = r->addr;
786 range_limit = r->addr + r->size - 1;
787
788 /*
789 * Work-around for old bioses
790 * that do not support multiple root buses
791 */
792 if (!range_base || range_base > range_limit) {
793 continue;
794 }
795
796 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
797 aml_append(crs,
798 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
799 AML_POS_DECODE, AML_ENTIRE_RANGE,
800 0,
801 range_base,
802 range_limit,
803 0,
804 range_limit - range_base + 1));
805 crs_range_insert(io_ranges, range_base, range_limit);
806 } else { /* "memory" */
807 aml_append(crs,
808 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
809 AML_MAX_FIXED, AML_NON_CACHEABLE,
810 AML_READ_WRITE,
811 0,
812 range_base,
813 range_limit,
814 0,
815 range_limit - range_base + 1));
816 crs_range_insert(mem_ranges, range_base, range_limit);
817 }
818 }
819
820 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
821 if (type == PCI_HEADER_TYPE_BRIDGE) {
822 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
823 if (subordinate > max_bus) {
824 max_bus = subordinate;
825 }
826
827 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
828 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
829
830 /*
831 * Work-around for old bioses
832 * that do not support multiple root buses
833 */
834 if (range_base && range_base <= range_limit) {
835 aml_append(crs,
836 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
837 AML_POS_DECODE, AML_ENTIRE_RANGE,
838 0,
839 range_base,
840 range_limit,
841 0,
842 range_limit - range_base + 1));
843 crs_range_insert(io_ranges, range_base, range_limit);
844 }
845
846 range_base =
847 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
848 range_limit =
849 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
850
851 /*
852 * Work-around for old bioses
853 * that do not support multiple root buses
854 */
855 if (range_base && range_base <= range_limit) {
856 aml_append(crs,
857 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
858 AML_MAX_FIXED, AML_NON_CACHEABLE,
859 AML_READ_WRITE,
860 0,
861 range_base,
862 range_limit,
863 0,
864 range_limit - range_base + 1));
865 crs_range_insert(mem_ranges, range_base, range_limit);
866 }
867
868 range_base =
869 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
870 range_limit =
871 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
872
873 /*
874 * Work-around for old bioses
875 * that do not support multiple root buses
876 */
877 if (range_base && range_base <= range_limit) {
878 aml_append(crs,
879 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
880 AML_MAX_FIXED, AML_NON_CACHEABLE,
881 AML_READ_WRITE,
882 0,
883 range_base,
884 range_limit,
885 0,
886 range_limit - range_base + 1));
887 crs_range_insert(mem_ranges, range_base, range_limit);
888 }
889 }
890 }
891
892 aml_append(crs,
893 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
894 0,
895 pci_bus_num(host->bus),
896 max_bus,
897 0,
898 max_bus - pci_bus_num(host->bus) + 1));
899
900 return crs;
901 }
902
903 static void
904 build_ssdt(GArray *table_data, GArray *linker,
905 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
906 PcPciInfo *pci, PcGuestInfo *guest_info)
907 {
908 MachineState *machine = MACHINE(qdev_get_machine());
909 uint32_t nr_mem = machine->ram_slots;
910 unsigned acpi_cpus = guest_info->apic_id_limit;
911 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
912 PCIBus *bus = NULL;
913 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
914 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
915 CrsRangeEntry *entry;
916 int root_bus_limit = 0xFF;
917 int i;
918
919 ssdt = init_aml_allocator();
920 /* The current AML generator can cover the APIC ID range [0..255],
921 * inclusive, for VCPU hotplug. */
922 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
923 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
924
925 /* Reserve space for header */
926 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
927
928 /* Extra PCI root buses are implemented only for i440fx */
929 bus = find_i440fx();
930 if (bus) {
931 QLIST_FOREACH(bus, &bus->child, sibling) {
932 uint8_t bus_num = pci_bus_num(bus);
933 uint8_t numa_node = pci_bus_numa_node(bus);
934
935 /* look only for expander root buses */
936 if (!pci_bus_is_root(bus)) {
937 continue;
938 }
939
940 if (bus_num < root_bus_limit) {
941 root_bus_limit = bus_num - 1;
942 }
943
944 scope = aml_scope("\\_SB");
945 dev = aml_device("PC%.02X", bus_num);
946 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
947 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
948 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
949
950 if (numa_node != NUMA_NODE_UNASSIGNED) {
951 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
952 }
953
954 aml_append(dev, build_prt());
955 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
956 io_ranges, mem_ranges);
957 aml_append(dev, aml_name_decl("_CRS", crs));
958 aml_append(scope, dev);
959 aml_append(ssdt, scope);
960 }
961 }
962
963 scope = aml_scope("\\_SB.PCI0");
964 /* build PCI0._CRS */
965 crs = aml_resource_template();
966 aml_append(crs,
967 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
968 0x0000, 0x0, root_bus_limit,
969 0x0000, root_bus_limit + 1));
970 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
971
972 aml_append(crs,
973 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
974 AML_POS_DECODE, AML_ENTIRE_RANGE,
975 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
976
977 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
978 for (i = 0; i < io_ranges->len; i++) {
979 entry = g_ptr_array_index(io_ranges, i);
980 aml_append(crs,
981 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
982 AML_POS_DECODE, AML_ENTIRE_RANGE,
983 0x0000, entry->base, entry->limit,
984 0x0000, entry->limit - entry->base + 1));
985 }
986
987 aml_append(crs,
988 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
989 AML_CACHEABLE, AML_READ_WRITE,
990 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
991
992 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
993 for (i = 0; i < mem_ranges->len; i++) {
994 entry = g_ptr_array_index(mem_ranges, i);
995 aml_append(crs,
996 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
997 AML_NON_CACHEABLE, AML_READ_WRITE,
998 0, entry->base, entry->limit,
999 0, entry->limit - entry->base + 1));
1000 }
1001
1002 if (pci->w64.begin) {
1003 aml_append(crs,
1004 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1005 AML_CACHEABLE, AML_READ_WRITE,
1006 0, pci->w64.begin, pci->w64.end - 1, 0,
1007 pci->w64.end - pci->w64.begin));
1008 }
1009 aml_append(scope, aml_name_decl("_CRS", crs));
1010
1011 /* reserve GPE0 block resources */
1012 dev = aml_device("GPE0");
1013 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1014 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1015 /* device present, functioning, decoding, not shown in UI */
1016 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1017 crs = aml_resource_template();
1018 aml_append(crs,
1019 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1020 );
1021 aml_append(dev, aml_name_decl("_CRS", crs));
1022 aml_append(scope, dev);
1023
1024 g_ptr_array_free(io_ranges, true);
1025 g_ptr_array_free(mem_ranges, true);
1026
1027 /* reserve PCIHP resources */
1028 if (pm->pcihp_io_len) {
1029 dev = aml_device("PHPR");
1030 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1031 aml_append(dev,
1032 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1033 /* device present, functioning, decoding, not shown in UI */
1034 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1035 crs = aml_resource_template();
1036 aml_append(crs,
1037 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1038 pm->pcihp_io_len)
1039 );
1040 aml_append(dev, aml_name_decl("_CRS", crs));
1041 aml_append(scope, dev);
1042 }
1043 aml_append(ssdt, scope);
1044
1045 /* create S3_ / S4_ / S5_ packages if necessary */
1046 scope = aml_scope("\\");
1047 if (!pm->s3_disabled) {
1048 pkg = aml_package(4);
1049 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1050 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1051 aml_append(pkg, aml_int(0)); /* reserved */
1052 aml_append(pkg, aml_int(0)); /* reserved */
1053 aml_append(scope, aml_name_decl("_S3", pkg));
1054 }
1055
1056 if (!pm->s4_disabled) {
1057 pkg = aml_package(4);
1058 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1059 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1060 aml_append(pkg, aml_int(pm->s4_val));
1061 aml_append(pkg, aml_int(0)); /* reserved */
1062 aml_append(pkg, aml_int(0)); /* reserved */
1063 aml_append(scope, aml_name_decl("_S4", pkg));
1064 }
1065
1066 pkg = aml_package(4);
1067 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1068 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1069 aml_append(pkg, aml_int(0)); /* reserved */
1070 aml_append(pkg, aml_int(0)); /* reserved */
1071 aml_append(scope, aml_name_decl("_S5", pkg));
1072 aml_append(ssdt, scope);
1073
1074 if (misc->applesmc_io_base) {
1075 scope = aml_scope("\\_SB.PCI0.ISA");
1076 dev = aml_device("SMC");
1077
1078 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1079 /* device present, functioning, decoding, not shown in UI */
1080 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1081
1082 crs = aml_resource_template();
1083 aml_append(crs,
1084 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1085 0x01, APPLESMC_MAX_DATA_LENGTH)
1086 );
1087 aml_append(crs, aml_irq_no_flags(6));
1088 aml_append(dev, aml_name_decl("_CRS", crs));
1089
1090 aml_append(scope, dev);
1091 aml_append(ssdt, scope);
1092 }
1093
1094 if (misc->pvpanic_port) {
1095 scope = aml_scope("\\_SB.PCI0.ISA");
1096
1097 dev = aml_device("PEVT");
1098 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1099
1100 crs = aml_resource_template();
1101 aml_append(crs,
1102 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1103 );
1104 aml_append(dev, aml_name_decl("_CRS", crs));
1105
1106 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1107 misc->pvpanic_port, 1));
1108 field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE);
1109 aml_append(field, aml_named_field("PEPT", 8));
1110 aml_append(dev, field);
1111
1112 /* device present, functioning, decoding, shown in UI */
1113 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1114
1115 method = aml_method("RDPT", 0);
1116 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1117 aml_append(method, aml_return(aml_local(0)));
1118 aml_append(dev, method);
1119
1120 method = aml_method("WRPT", 1);
1121 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1122 aml_append(dev, method);
1123
1124 aml_append(scope, dev);
1125 aml_append(ssdt, scope);
1126 }
1127
1128 sb_scope = aml_scope("\\_SB");
1129 {
1130 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
1131 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
1132 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1133 aml_append(dev,
1134 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
1135 );
1136 /* device present, functioning, decoding, not shown in UI */
1137 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1138 crs = aml_resource_template();
1139 aml_append(crs,
1140 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
1141 pm->cpu_hp_io_len)
1142 );
1143 aml_append(dev, aml_name_decl("_CRS", crs));
1144 aml_append(sb_scope, dev);
1145 /* declare CPU hotplug MMIO region and PRS field to access it */
1146 aml_append(sb_scope, aml_operation_region(
1147 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1148 field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE);
1149 aml_append(field, aml_named_field("PRS", 256));
1150 aml_append(sb_scope, field);
1151
1152 /* build Processor object for each processor */
1153 for (i = 0; i < acpi_cpus; i++) {
1154 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1155
1156 method = aml_method("_MAT", 0);
1157 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
1158 aml_append(dev, method);
1159
1160 method = aml_method("_STA", 0);
1161 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
1162 aml_append(dev, method);
1163
1164 method = aml_method("_EJ0", 1);
1165 aml_append(method,
1166 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
1167 );
1168 aml_append(dev, method);
1169
1170 aml_append(sb_scope, dev);
1171 }
1172
1173 /* build this code:
1174 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1175 */
1176 /* Arg0 = Processor ID = APIC ID */
1177 method = aml_method("NTFY", 2);
1178 for (i = 0; i < acpi_cpus; i++) {
1179 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1180 aml_append(ifctx,
1181 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1182 );
1183 aml_append(method, ifctx);
1184 }
1185 aml_append(sb_scope, method);
1186
1187 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1188 *
1189 * Note: The ability to create variable-sized packages was first
1190 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1191 * ith up to 255 elements. Windows guests up to win2k8 fail when
1192 * VarPackageOp is used.
1193 */
1194 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1195 aml_varpackage(acpi_cpus);
1196
1197 for (i = 0; i < acpi_cpus; i++) {
1198 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1199 aml_append(pkg, aml_int(b));
1200 }
1201 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1202
1203 /* build memory devices */
1204 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1205 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
1206 aml_append(scope,
1207 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
1208 );
1209
1210 crs = aml_resource_template();
1211 aml_append(crs,
1212 aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
1213 pm->mem_hp_io_len)
1214 );
1215 aml_append(scope, aml_name_decl("_CRS", crs));
1216
1217 aml_append(scope, aml_operation_region(
1218 stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO,
1219 pm->mem_hp_io_base, pm->mem_hp_io_len)
1220 );
1221
1222 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
1223 AML_PRESERVE);
1224 aml_append(field, /* read only */
1225 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
1226 aml_append(field, /* read only */
1227 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
1228 aml_append(field, /* read only */
1229 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
1230 aml_append(field, /* read only */
1231 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
1232 aml_append(field, /* read only */
1233 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
1234 aml_append(scope, field);
1235
1236 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC,
1237 AML_WRITE_AS_ZEROS);
1238 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1239 aml_append(field, /* 1 if enabled, read only */
1240 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
1241 aml_append(field,
1242 /*(read) 1 if has a insert event. (write) 1 to clear event */
1243 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
1244 aml_append(field,
1245 /* (read) 1 if has a remove event. (write) 1 to clear event */
1246 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1));
1247 aml_append(field,
1248 /* initiates device eject, write only */
1249 aml_named_field(stringify(MEMORY_SLOT_EJECT), 1));
1250 aml_append(scope, field);
1251
1252 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
1253 AML_PRESERVE);
1254 aml_append(field, /* DIMM selector, write only */
1255 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
1256 aml_append(field, /* _OST event code, write only */
1257 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
1258 aml_append(field, /* _OST status code, write only */
1259 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
1260 aml_append(scope, field);
1261
1262 aml_append(sb_scope, scope);
1263
1264 for (i = 0; i < nr_mem; i++) {
1265 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1266 const char *s;
1267
1268 dev = aml_device("MP%02X", i);
1269 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1270 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1271
1272 method = aml_method("_CRS", 0);
1273 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1274 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1275 aml_append(dev, method);
1276
1277 method = aml_method("_STA", 0);
1278 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1279 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1280 aml_append(dev, method);
1281
1282 method = aml_method("_PXM", 0);
1283 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1284 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1285 aml_append(dev, method);
1286
1287 method = aml_method("_OST", 3);
1288 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1289 aml_append(method, aml_return(aml_call4(
1290 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1291 )));
1292 aml_append(dev, method);
1293
1294 method = aml_method("_EJ0", 1);
1295 s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD);
1296 aml_append(method, aml_return(aml_call2(
1297 s, aml_name("_UID"), aml_arg(0))));
1298 aml_append(dev, method);
1299
1300 aml_append(sb_scope, dev);
1301 }
1302
1303 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1304 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1305 */
1306 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2);
1307 for (i = 0; i < nr_mem; i++) {
1308 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1309 aml_append(ifctx,
1310 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1311 );
1312 aml_append(method, ifctx);
1313 }
1314 aml_append(sb_scope, method);
1315
1316 {
1317 Object *pci_host;
1318 PCIBus *bus = NULL;
1319
1320 pci_host = acpi_get_i386_pci_host();
1321 if (pci_host) {
1322 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1323 }
1324
1325 if (bus) {
1326 Aml *scope = aml_scope("PCI0");
1327 /* Scan all PCI buses. Generate tables to support hotplug. */
1328 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1329
1330 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
1331 dev = aml_device("ISA.TPM");
1332 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
1333 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1334 crs = aml_resource_template();
1335 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1336 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1337 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
1338 aml_append(dev, aml_name_decl("_CRS", crs));
1339 aml_append(scope, dev);
1340 }
1341
1342 aml_append(sb_scope, scope);
1343 }
1344 }
1345 aml_append(ssdt, sb_scope);
1346 }
1347
1348 /* copy AML table into ACPI tables blob and patch header there */
1349 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1350 build_header(linker, table_data,
1351 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1352 "SSDT", ssdt->buf->len, 1);
1353 free_aml_allocator();
1354 }
1355
1356 static void
1357 build_hpet(GArray *table_data, GArray *linker)
1358 {
1359 Acpi20Hpet *hpet;
1360
1361 hpet = acpi_data_push(table_data, sizeof(*hpet));
1362 /* Note timer_block_id value must be kept in sync with value advertised by
1363 * emulated hpet
1364 */
1365 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1366 hpet->addr.address = cpu_to_le64(HPET_BASE);
1367 build_header(linker, table_data,
1368 (void *)hpet, "HPET", sizeof(*hpet), 1);
1369 }
1370
1371 static void
1372 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1373 {
1374 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1375 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1376
1377 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1378 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1379 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1380
1381 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1382 false /* high memory */);
1383
1384 /* log area start address to be filled by Guest linker */
1385 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1386 ACPI_BUILD_TPMLOG_FILE,
1387 table_data, &tcpa->log_area_start_address,
1388 sizeof(tcpa->log_area_start_address));
1389
1390 build_header(linker, table_data,
1391 (void *)tcpa, "TCPA", sizeof(*tcpa), 2);
1392
1393 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1394 }
1395
1396 static void
1397 build_tpm2(GArray *table_data, GArray *linker)
1398 {
1399 Acpi20TPM2 *tpm2_ptr;
1400
1401 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
1402
1403 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
1404 tpm2_ptr->control_area_address = cpu_to_le64(0);
1405 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
1406
1407 build_header(linker, table_data,
1408 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4);
1409 }
1410
1411 typedef enum {
1412 MEM_AFFINITY_NOFLAGS = 0,
1413 MEM_AFFINITY_ENABLED = (1 << 0),
1414 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1415 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1416 } MemoryAffinityFlags;
1417
1418 static void
1419 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1420 uint64_t len, int node, MemoryAffinityFlags flags)
1421 {
1422 numamem->type = ACPI_SRAT_MEMORY;
1423 numamem->length = sizeof(*numamem);
1424 memset(numamem->proximity, 0, 4);
1425 numamem->proximity[0] = node;
1426 numamem->flags = cpu_to_le32(flags);
1427 numamem->base_addr = cpu_to_le64(base);
1428 numamem->range_length = cpu_to_le64(len);
1429 }
1430
1431 static void
1432 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1433 {
1434 AcpiSystemResourceAffinityTable *srat;
1435 AcpiSratProcessorAffinity *core;
1436 AcpiSratMemoryAffinity *numamem;
1437
1438 int i;
1439 uint64_t curnode;
1440 int srat_start, numa_start, slots;
1441 uint64_t mem_len, mem_base, next_base;
1442 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1443 ram_addr_t hotplugabble_address_space_size =
1444 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1445 NULL);
1446
1447 srat_start = table_data->len;
1448
1449 srat = acpi_data_push(table_data, sizeof *srat);
1450 srat->reserved1 = cpu_to_le32(1);
1451 core = (void *)(srat + 1);
1452
1453 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1454 core = acpi_data_push(table_data, sizeof *core);
1455 core->type = ACPI_SRAT_PROCESSOR;
1456 core->length = sizeof(*core);
1457 core->local_apic_id = i;
1458 curnode = guest_info->node_cpu[i];
1459 core->proximity_lo = curnode;
1460 memset(core->proximity_hi, 0, 3);
1461 core->local_sapic_eid = 0;
1462 core->flags = cpu_to_le32(1);
1463 }
1464
1465
1466 /* the memory map is a bit tricky, it contains at least one hole
1467 * from 640k-1M and possibly another one from 3.5G-4G.
1468 */
1469 next_base = 0;
1470 numa_start = table_data->len;
1471
1472 numamem = acpi_data_push(table_data, sizeof *numamem);
1473 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1474 next_base = 1024 * 1024;
1475 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1476 mem_base = next_base;
1477 mem_len = guest_info->node_mem[i - 1];
1478 if (i == 1) {
1479 mem_len -= 1024 * 1024;
1480 }
1481 next_base = mem_base + mem_len;
1482
1483 /* Cut out the ACPI_PCI hole */
1484 if (mem_base <= guest_info->ram_size_below_4g &&
1485 next_base > guest_info->ram_size_below_4g) {
1486 mem_len -= next_base - guest_info->ram_size_below_4g;
1487 if (mem_len > 0) {
1488 numamem = acpi_data_push(table_data, sizeof *numamem);
1489 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1490 MEM_AFFINITY_ENABLED);
1491 }
1492 mem_base = 1ULL << 32;
1493 mem_len = next_base - guest_info->ram_size_below_4g;
1494 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1495 }
1496 numamem = acpi_data_push(table_data, sizeof *numamem);
1497 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1498 MEM_AFFINITY_ENABLED);
1499 }
1500 slots = (table_data->len - numa_start) / sizeof *numamem;
1501 for (; slots < guest_info->numa_nodes + 2; slots++) {
1502 numamem = acpi_data_push(table_data, sizeof *numamem);
1503 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1504 }
1505
1506 /*
1507 * Entry is required for Windows to enable memory hotplug in OS.
1508 * Memory devices may override proximity set by this entry,
1509 * providing _PXM method if necessary.
1510 */
1511 if (hotplugabble_address_space_size) {
1512 numamem = acpi_data_push(table_data, sizeof *numamem);
1513 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
1514 hotplugabble_address_space_size, 0,
1515 MEM_AFFINITY_HOTPLUGGABLE |
1516 MEM_AFFINITY_ENABLED);
1517 }
1518
1519 build_header(linker, table_data,
1520 (void *)(table_data->data + srat_start),
1521 "SRAT",
1522 table_data->len - srat_start, 1);
1523 }
1524
1525 static void
1526 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1527 {
1528 AcpiTableMcfg *mcfg;
1529 const char *sig;
1530 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1531
1532 mcfg = acpi_data_push(table_data, len);
1533 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1534 /* Only a single allocation so no need to play with segments */
1535 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1536 mcfg->allocation[0].start_bus_number = 0;
1537 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1538
1539 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1540 * To avoid table size changes (which create migration issues),
1541 * always create the table even if there are no allocations,
1542 * but set the signature to a reserved value in this case.
1543 * ACPI spec requires OSPMs to ignore such tables.
1544 */
1545 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1546 /* Reserved signature: ignored by OSPM */
1547 sig = "QEMU";
1548 } else {
1549 sig = "MCFG";
1550 }
1551 build_header(linker, table_data, (void *)mcfg, sig, len, 1);
1552 }
1553
1554 static void
1555 build_dmar_q35(GArray *table_data, GArray *linker)
1556 {
1557 int dmar_start = table_data->len;
1558
1559 AcpiTableDmar *dmar;
1560 AcpiDmarHardwareUnit *drhd;
1561
1562 dmar = acpi_data_push(table_data, sizeof(*dmar));
1563 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1564 dmar->flags = 0; /* No intr_remap for now */
1565
1566 /* DMAR Remapping Hardware Unit Definition structure */
1567 drhd = acpi_data_push(table_data, sizeof(*drhd));
1568 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1569 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1570 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1571 drhd->pci_segment = cpu_to_le16(0);
1572 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1573
1574 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1575 "DMAR", table_data->len - dmar_start, 1);
1576 }
1577
1578 static void
1579 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1580 {
1581 AcpiTableHeader *dsdt;
1582
1583 assert(misc->dsdt_code && misc->dsdt_size);
1584
1585 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1586 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1587
1588 memset(dsdt, 0, sizeof *dsdt);
1589 build_header(linker, table_data, dsdt, "DSDT",
1590 misc->dsdt_size, 1);
1591 }
1592
1593 static GArray *
1594 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1595 {
1596 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1597
1598 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1599 true /* fseg memory */);
1600
1601 memcpy(&rsdp->signature, "RSD PTR ", 8);
1602 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1603 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1604 /* Address to be filled by Guest linker */
1605 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1606 ACPI_BUILD_TABLE_FILE,
1607 rsdp_table, &rsdp->rsdt_physical_address,
1608 sizeof rsdp->rsdt_physical_address);
1609 rsdp->checksum = 0;
1610 /* Checksum to be filled by Guest linker */
1611 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1612 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1613
1614 return rsdp_table;
1615 }
1616
1617 typedef
1618 struct AcpiBuildState {
1619 /* Copy of table in RAM (for patching). */
1620 MemoryRegion *table_mr;
1621 /* Is table patched? */
1622 uint8_t patched;
1623 PcGuestInfo *guest_info;
1624 void *rsdp;
1625 MemoryRegion *rsdp_mr;
1626 MemoryRegion *linker_mr;
1627 } AcpiBuildState;
1628
1629 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1630 {
1631 Object *pci_host;
1632 QObject *o;
1633
1634 pci_host = acpi_get_i386_pci_host();
1635 g_assert(pci_host);
1636
1637 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1638 if (!o) {
1639 return false;
1640 }
1641 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1642 qobject_decref(o);
1643
1644 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1645 assert(o);
1646 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1647 qobject_decref(o);
1648 return true;
1649 }
1650
1651 static bool acpi_has_iommu(void)
1652 {
1653 bool ambiguous;
1654 Object *intel_iommu;
1655
1656 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1657 &ambiguous);
1658 return intel_iommu && !ambiguous;
1659 }
1660
1661 static
1662 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1663 {
1664 GArray *table_offsets;
1665 unsigned facs, ssdt, dsdt, rsdt;
1666 AcpiCpuInfo cpu;
1667 AcpiPmInfo pm;
1668 AcpiMiscInfo misc;
1669 AcpiMcfgInfo mcfg;
1670 PcPciInfo pci;
1671 uint8_t *u;
1672 size_t aml_len = 0;
1673 GArray *tables_blob = tables->table_data;
1674
1675 acpi_get_cpu_info(&cpu);
1676 acpi_get_pm_info(&pm);
1677 acpi_get_dsdt(&misc);
1678 acpi_get_misc_info(&misc);
1679 acpi_get_pci_info(&pci);
1680
1681 table_offsets = g_array_new(false, true /* clear */,
1682 sizeof(uint32_t));
1683 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1684
1685 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1686 64 /* Ensure FACS is aligned */,
1687 false /* high memory */);
1688
1689 /*
1690 * FACS is pointed to by FADT.
1691 * We place it first since it's the only table that has alignment
1692 * requirements.
1693 */
1694 facs = tables_blob->len;
1695 build_facs(tables_blob, tables->linker, guest_info);
1696
1697 /* DSDT is pointed to by FADT */
1698 dsdt = tables_blob->len;
1699 build_dsdt(tables_blob, tables->linker, &misc);
1700
1701 /* Count the size of the DSDT and SSDT, we will need it for legacy
1702 * sizing of ACPI tables.
1703 */
1704 aml_len += tables_blob->len - dsdt;
1705
1706 /* ACPI tables pointed to by RSDT */
1707 acpi_add_table(table_offsets, tables_blob);
1708 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1709
1710 ssdt = tables_blob->len;
1711 acpi_add_table(table_offsets, tables_blob);
1712 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1713 guest_info);
1714 aml_len += tables_blob->len - ssdt;
1715
1716 acpi_add_table(table_offsets, tables_blob);
1717 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1718
1719 if (misc.has_hpet) {
1720 acpi_add_table(table_offsets, tables_blob);
1721 build_hpet(tables_blob, tables->linker);
1722 }
1723 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
1724 acpi_add_table(table_offsets, tables_blob);
1725 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1726
1727 if (misc.tpm_version == TPM_VERSION_2_0) {
1728 acpi_add_table(table_offsets, tables_blob);
1729 build_tpm2(tables_blob, tables->linker);
1730 }
1731 }
1732 if (guest_info->numa_nodes) {
1733 acpi_add_table(table_offsets, tables_blob);
1734 build_srat(tables_blob, tables->linker, guest_info);
1735 }
1736 if (acpi_get_mcfg(&mcfg)) {
1737 acpi_add_table(table_offsets, tables_blob);
1738 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1739 }
1740 if (acpi_has_iommu()) {
1741 acpi_add_table(table_offsets, tables_blob);
1742 build_dmar_q35(tables_blob, tables->linker);
1743 }
1744
1745 /* Add tables supplied by user (if any) */
1746 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1747 unsigned len = acpi_table_len(u);
1748
1749 acpi_add_table(table_offsets, tables_blob);
1750 g_array_append_vals(tables_blob, u, len);
1751 }
1752
1753 /* RSDT is pointed to by RSDP */
1754 rsdt = tables_blob->len;
1755 build_rsdt(tables_blob, tables->linker, table_offsets);
1756
1757 /* RSDP is in FSEG memory, so allocate it separately */
1758 build_rsdp(tables->rsdp, tables->linker, rsdt);
1759
1760 /* We'll expose it all to Guest so we want to reduce
1761 * chance of size changes.
1762 *
1763 * We used to align the tables to 4k, but of course this would
1764 * too simple to be enough. 4k turned out to be too small an
1765 * alignment very soon, and in fact it is almost impossible to
1766 * keep the table size stable for all (max_cpus, max_memory_slots)
1767 * combinations. So the table size is always 64k for pc-i440fx-2.1
1768 * and we give an error if the table grows beyond that limit.
1769 *
1770 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1771 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1772 * than 2.0 and we can always pad the smaller tables with zeros. We can
1773 * then use the exact size of the 2.0 tables.
1774 *
1775 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1776 */
1777 if (guest_info->legacy_acpi_table_size) {
1778 /* Subtracting aml_len gives the size of fixed tables. Then add the
1779 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1780 */
1781 int legacy_aml_len =
1782 guest_info->legacy_acpi_table_size +
1783 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1784 int legacy_table_size =
1785 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1786 ACPI_BUILD_ALIGN_SIZE);
1787 if (tables_blob->len > legacy_table_size) {
1788 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1789 error_report("Warning: migration may not work.");
1790 }
1791 g_array_set_size(tables_blob, legacy_table_size);
1792 } else {
1793 /* Make sure we have a buffer in case we need to resize the tables. */
1794 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1795 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1796 error_report("Warning: ACPI tables are larger than 64k.");
1797 error_report("Warning: migration may not work.");
1798 error_report("Warning: please remove CPUs, NUMA nodes, "
1799 "memory slots or PCI bridges.");
1800 }
1801 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1802 }
1803
1804 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1805
1806 /* Cleanup memory that's no longer used. */
1807 g_array_free(table_offsets, true);
1808 }
1809
1810 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1811 {
1812 uint32_t size = acpi_data_len(data);
1813
1814 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1815 memory_region_ram_resize(mr, size, &error_abort);
1816
1817 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1818 memory_region_set_dirty(mr, 0, size);
1819 }
1820
1821 static void acpi_build_update(void *build_opaque, uint32_t offset)
1822 {
1823 AcpiBuildState *build_state = build_opaque;
1824 AcpiBuildTables tables;
1825
1826 /* No state to update or already patched? Nothing to do. */
1827 if (!build_state || build_state->patched) {
1828 return;
1829 }
1830 build_state->patched = 1;
1831
1832 acpi_build_tables_init(&tables);
1833
1834 acpi_build(build_state->guest_info, &tables);
1835
1836 acpi_ram_update(build_state->table_mr, tables.table_data);
1837
1838 if (build_state->rsdp) {
1839 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1840 } else {
1841 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1842 }
1843
1844 acpi_ram_update(build_state->linker_mr, tables.linker);
1845 acpi_build_tables_cleanup(&tables, true);
1846 }
1847
1848 static void acpi_build_reset(void *build_opaque)
1849 {
1850 AcpiBuildState *build_state = build_opaque;
1851 build_state->patched = 0;
1852 }
1853
1854 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
1855 GArray *blob, const char *name,
1856 uint64_t max_size)
1857 {
1858 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1859 name, acpi_build_update, build_state);
1860 }
1861
1862 static const VMStateDescription vmstate_acpi_build = {
1863 .name = "acpi_build",
1864 .version_id = 1,
1865 .minimum_version_id = 1,
1866 .fields = (VMStateField[]) {
1867 VMSTATE_UINT8(patched, AcpiBuildState),
1868 VMSTATE_END_OF_LIST()
1869 },
1870 };
1871
1872 void acpi_setup(PcGuestInfo *guest_info)
1873 {
1874 AcpiBuildTables tables;
1875 AcpiBuildState *build_state;
1876
1877 if (!guest_info->fw_cfg) {
1878 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1879 return;
1880 }
1881
1882 if (!guest_info->has_acpi_build) {
1883 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1884 return;
1885 }
1886
1887 if (!acpi_enabled) {
1888 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1889 return;
1890 }
1891
1892 build_state = g_malloc0(sizeof *build_state);
1893
1894 build_state->guest_info = guest_info;
1895
1896 acpi_set_pci_info();
1897
1898 acpi_build_tables_init(&tables);
1899 acpi_build(build_state->guest_info, &tables);
1900
1901 /* Now expose it all to Guest */
1902 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
1903 ACPI_BUILD_TABLE_FILE,
1904 ACPI_BUILD_TABLE_MAX_SIZE);
1905 assert(build_state->table_mr != NULL);
1906
1907 build_state->linker_mr =
1908 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1909
1910 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1911 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1912
1913 if (!guest_info->rsdp_in_ram) {
1914 /*
1915 * Keep for compatibility with old machine types.
1916 * Though RSDP is small, its contents isn't immutable, so
1917 * we'll update it along with the rest of tables on guest access.
1918 */
1919 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1920
1921 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1922 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1923 acpi_build_update, build_state,
1924 build_state->rsdp, rsdp_size);
1925 build_state->rsdp_mr = NULL;
1926 } else {
1927 build_state->rsdp = NULL;
1928 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
1929 ACPI_BUILD_RSDP_FILE, 0);
1930 }
1931
1932 qemu_register_reset(acpi_build_reset, build_state);
1933 acpi_build_reset(build_state);
1934 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1935
1936 /* Cleanup tables but don't free the memory: we track it
1937 * in build_state.
1938 */
1939 acpi_build_tables_cleanup(&tables, false);
1940 }
AR7 emulation for QEMU