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sm501: Shorten long variable names in sm501_2d_operation
[qemu/ar7.git] / hw / i386 / pc.c
blob2128f3d6fe8baa81a2f5be0030c84fa273db7bc0
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
36 #include "hw/ide.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "migration/vmstate.h"
45 #include "multiboot.h"
46 #include "hw/rtc/mc146818rtc.h"
47 #include "hw/intc/i8259.h"
48 #include "hw/dma/i8257.h"
49 #include "hw/timer/i8254.h"
50 #include "hw/input/i8042.h"
51 #include "hw/irq.h"
52 #include "hw/audio/pcspk.h"
53 #include "hw/pci/msi.h"
54 #include "hw/sysbus.h"
55 #include "sysemu/sysemu.h"
56 #include "sysemu/tcg.h"
57 #include "sysemu/numa.h"
58 #include "sysemu/kvm.h"
59 #include "sysemu/qtest.h"
60 #include "sysemu/reset.h"
61 #include "sysemu/runstate.h"
62 #include "kvm_i386.h"
63 #include "hw/xen/xen.h"
64 #include "hw/xen/start_info.h"
65 #include "ui/qemu-spice.h"
66 #include "exec/memory.h"
67 #include "exec/address-spaces.h"
68 #include "sysemu/arch_init.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "hw/boards.h"
77 #include "acpi-build.h"
78 #include "hw/mem/pc-dimm.h"
79 #include "hw/mem/nvdimm.h"
80 #include "qapi/error.h"
81 #include "qapi/qapi-visit-common.h"
82 #include "qapi/visitor.h"
83 #include "hw/core/cpu.h"
84 #include "hw/usb.h"
85 #include "hw/i386/intel_iommu.h"
86 #include "hw/net/ne2000-isa.h"
87 #include "standard-headers/asm-x86/bootparam.h"
88 #include "hw/virtio/virtio-pmem-pci.h"
89 #include "hw/mem/memory-device.h"
90 #include "sysemu/replay.h"
91 #include "qapi/qmp/qerror.h"
92 #include "config-devices.h"
93 #include "e820_memory_layout.h"
94 #include "vmport.h"
95 #include "fw_cfg.h"
96 #include "trace.h"
97
98 GlobalProperty pc_compat_5_0[] = {};
99 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
100
101 GlobalProperty pc_compat_4_2[] = {
102 { "mch", "smbase-smram", "off" },
103 };
104 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
105
106 GlobalProperty pc_compat_4_1[] = {};
107 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
108
109 GlobalProperty pc_compat_4_0[] = {};
110 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
111
112 GlobalProperty pc_compat_3_1[] = {
113 { "intel-iommu", "dma-drain", "off" },
114 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
115 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
116 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
117 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
118 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
119 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
120 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
121 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
122 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
123 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
124 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
125 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
126 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
128 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
129 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
130 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
131 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
133 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
134 };
135 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
136
137 GlobalProperty pc_compat_3_0[] = {
138 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
139 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
140 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
141 };
142 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
143
144 GlobalProperty pc_compat_2_12[] = {
145 { TYPE_X86_CPU, "legacy-cache", "on" },
146 { TYPE_X86_CPU, "topoext", "off" },
147 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
148 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
149 };
150 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
151
152 GlobalProperty pc_compat_2_11[] = {
153 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
154 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
155 };
156 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
157
158 GlobalProperty pc_compat_2_10[] = {
159 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
160 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
161 { "q35-pcihost", "x-pci-hole64-fix", "off" },
162 };
163 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
164
165 GlobalProperty pc_compat_2_9[] = {
166 { "mch", "extended-tseg-mbytes", "0" },
167 };
168 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
169
170 GlobalProperty pc_compat_2_8[] = {
171 { TYPE_X86_CPU, "tcg-cpuid", "off" },
172 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
173 { "ICH9-LPC", "x-smi-broadcast", "off" },
174 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
175 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
176 };
177 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
178
179 GlobalProperty pc_compat_2_7[] = {
180 { TYPE_X86_CPU, "l3-cache", "off" },
181 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
182 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
183 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
184 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
185 { "isa-pcspk", "migrate", "off" },
186 };
187 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
188
189 GlobalProperty pc_compat_2_6[] = {
190 { TYPE_X86_CPU, "cpuid-0xb", "off" },
191 { "vmxnet3", "romfile", "" },
192 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
193 { "apic-common", "legacy-instance-id", "on", }
194 };
195 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
196
197 GlobalProperty pc_compat_2_5[] = {};
198 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
199
200 GlobalProperty pc_compat_2_4[] = {
201 PC_CPU_MODEL_IDS("2.4.0")
202 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
203 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
204 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
205 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
206 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
207 { TYPE_X86_CPU, "check", "off" },
208 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
209 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
210 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
211 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
212 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
213 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
214 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
215 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
216 };
217 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
218
219 GlobalProperty pc_compat_2_3[] = {
220 PC_CPU_MODEL_IDS("2.3.0")
221 { TYPE_X86_CPU, "arat", "off" },
222 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
223 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
224 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
225 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
226 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
227 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
228 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
229 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
230 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
241 };
242 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
243
244 GlobalProperty pc_compat_2_2[] = {
245 PC_CPU_MODEL_IDS("2.2.0")
246 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
247 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
248 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
252 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
253 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
261 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
262 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
264 };
265 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
266
267 GlobalProperty pc_compat_2_1[] = {
268 PC_CPU_MODEL_IDS("2.1.0")
269 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
270 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
271 };
272 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
273
274 GlobalProperty pc_compat_2_0[] = {
275 PC_CPU_MODEL_IDS("2.0.0")
276 { "virtio-scsi-pci", "any_layout", "off" },
277 { "PIIX4_PM", "memory-hotplug-support", "off" },
278 { "apic", "version", "0x11" },
279 { "nec-usb-xhci", "superspeed-ports-first", "off" },
280 { "nec-usb-xhci", "force-pcie-endcap", "on" },
281 { "pci-serial", "prog_if", "0" },
282 { "pci-serial-2x", "prog_if", "0" },
283 { "pci-serial-4x", "prog_if", "0" },
284 { "virtio-net-pci", "guest_announce", "off" },
285 { "ICH9-LPC", "memory-hotplug-support", "off" },
286 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
287 { "ioh3420", COMPAT_PROP_PCP, "off" },
288 };
289 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
290
291 GlobalProperty pc_compat_1_7[] = {
292 PC_CPU_MODEL_IDS("1.7.0")
293 { TYPE_USB_DEVICE, "msos-desc", "no" },
294 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
295 { "hpet", HPET_INTCAP, "4" },
296 };
297 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
298
299 GlobalProperty pc_compat_1_6[] = {
300 PC_CPU_MODEL_IDS("1.6.0")
301 { "e1000", "mitigation", "off" },
302 { "qemu64-" TYPE_X86_CPU, "model", "2" },
303 { "qemu32-" TYPE_X86_CPU, "model", "3" },
304 { "i440FX-pcihost", "short_root_bus", "1" },
305 { "q35-pcihost", "short_root_bus", "1" },
306 };
307 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
308
309 GlobalProperty pc_compat_1_5[] = {
310 PC_CPU_MODEL_IDS("1.5.0")
311 { "Conroe-" TYPE_X86_CPU, "model", "2" },
312 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
313 { "Penryn-" TYPE_X86_CPU, "model", "2" },
314 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
315 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
316 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
317 { "virtio-net-pci", "any_layout", "off" },
318 { TYPE_X86_CPU, "pmu", "on" },
319 { "i440FX-pcihost", "short_root_bus", "0" },
320 { "q35-pcihost", "short_root_bus", "0" },
321 };
322 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
323
324 GlobalProperty pc_compat_1_4[] = {
325 PC_CPU_MODEL_IDS("1.4.0")
326 { "scsi-hd", "discard_granularity", "0" },
327 { "scsi-cd", "discard_granularity", "0" },
328 { "scsi-disk", "discard_granularity", "0" },
329 { "ide-hd", "discard_granularity", "0" },
330 { "ide-cd", "discard_granularity", "0" },
331 { "ide-drive", "discard_granularity", "0" },
332 { "virtio-blk-pci", "discard_granularity", "0" },
333 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
334 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
335 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
336 { "e1000", "romfile", "pxe-e1000.rom" },
337 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
338 { "pcnet", "romfile", "pxe-pcnet.rom" },
339 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
340 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
341 { "486-" TYPE_X86_CPU, "model", "0" },
342 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
343 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
344 };
345 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
346
347 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
348 {
349 GSIState *s;
350
351 s = g_new0(GSIState, 1);
352 if (kvm_ioapic_in_kernel()) {
353 kvm_pc_setup_irq_routing(pci_enabled);
354 }
355 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
356
357 return s;
358 }
359
360 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
361 unsigned size)
362 {
363 }
364
365 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
366 {
367 return 0xffffffffffffffffULL;
368 }
369
370 /* MSDOS compatibility mode FPU exception support */
371 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
372 unsigned size)
373 {
374 if (tcg_enabled()) {
375 cpu_set_ignne();
376 }
377 }
378
379 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
380 {
381 return 0xffffffffffffffffULL;
382 }
383
384 /* PC cmos mappings */
385
386 #define REG_EQUIPMENT_BYTE 0x14
387
388 int cmos_get_fd_drive_type(FloppyDriveType fd0)
389 {
390 int val;
391
392 switch (fd0) {
393 case FLOPPY_DRIVE_TYPE_144:
394 /* 1.44 Mb 3"5 drive */
395 val = 4;
396 break;
397 case FLOPPY_DRIVE_TYPE_288:
398 /* 2.88 Mb 3"5 drive */
399 val = 5;
400 break;
401 case FLOPPY_DRIVE_TYPE_120:
402 /* 1.2 Mb 5"5 drive */
403 val = 2;
404 break;
405 case FLOPPY_DRIVE_TYPE_NONE:
406 default:
407 val = 0;
408 break;
409 }
410 return val;
411 }
412
413 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
414 int16_t cylinders, int8_t heads, int8_t sectors)
415 {
416 rtc_set_memory(s, type_ofs, 47);
417 rtc_set_memory(s, info_ofs, cylinders);
418 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
419 rtc_set_memory(s, info_ofs + 2, heads);
420 rtc_set_memory(s, info_ofs + 3, 0xff);
421 rtc_set_memory(s, info_ofs + 4, 0xff);
422 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
423 rtc_set_memory(s, info_ofs + 6, cylinders);
424 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
425 rtc_set_memory(s, info_ofs + 8, sectors);
426 }
427
428 /* convert boot_device letter to something recognizable by the bios */
429 static int boot_device2nibble(char boot_device)
430 {
431 switch(boot_device) {
432 case 'a':
433 case 'b':
434 return 0x01; /* floppy boot */
435 case 'c':
436 return 0x02; /* hard drive boot */
437 case 'd':
438 return 0x03; /* CD-ROM boot */
439 case 'n':
440 return 0x04; /* Network boot */
441 }
442 return 0;
443 }
444
445 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
446 {
447 #define PC_MAX_BOOT_DEVICES 3
448 int nbds, bds[3] = { 0, };
449 int i;
450
451 nbds = strlen(boot_device);
452 if (nbds > PC_MAX_BOOT_DEVICES) {
453 error_setg(errp, "Too many boot devices for PC");
454 return;
455 }
456 for (i = 0; i < nbds; i++) {
457 bds[i] = boot_device2nibble(boot_device[i]);
458 if (bds[i] == 0) {
459 error_setg(errp, "Invalid boot device for PC: '%c'",
460 boot_device[i]);
461 return;
462 }
463 }
464 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
465 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
466 }
467
468 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
469 {
470 set_boot_dev(opaque, boot_device, errp);
471 }
472
473 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
474 {
475 int val, nb, i;
476 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
477 FLOPPY_DRIVE_TYPE_NONE };
478
479 /* floppy type */
480 if (floppy) {
481 for (i = 0; i < 2; i++) {
482 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
483 }
484 }
485 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
486 cmos_get_fd_drive_type(fd_type[1]);
487 rtc_set_memory(rtc_state, 0x10, val);
488
489 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
490 nb = 0;
491 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
492 nb++;
493 }
494 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
495 nb++;
496 }
497 switch (nb) {
498 case 0:
499 break;
500 case 1:
501 val |= 0x01; /* 1 drive, ready for boot */
502 break;
503 case 2:
504 val |= 0x41; /* 2 drives, ready for boot */
505 break;
506 }
507 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
508 }
509
510 typedef struct pc_cmos_init_late_arg {
511 ISADevice *rtc_state;
512 BusState *idebus[2];
513 } pc_cmos_init_late_arg;
514
515 typedef struct check_fdc_state {
516 ISADevice *floppy;
517 bool multiple;
518 } CheckFdcState;
519
520 static int check_fdc(Object *obj, void *opaque)
521 {
522 CheckFdcState *state = opaque;
523 Object *fdc;
524 uint32_t iobase;
525 Error *local_err = NULL;
526
527 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
528 if (!fdc) {
529 return 0;
530 }
531
532 iobase = object_property_get_uint(obj, "iobase", &local_err);
533 if (local_err || iobase != 0x3f0) {
534 error_free(local_err);
535 return 0;
536 }
537
538 if (state->floppy) {
539 state->multiple = true;
540 } else {
541 state->floppy = ISA_DEVICE(obj);
542 }
543 return 0;
544 }
545
546 static const char * const fdc_container_path[] = {
547 "/unattached", "/peripheral", "/peripheral-anon"
548 };
549
550 /*
551 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
552 * and ACPI objects.
553 */
554 ISADevice *pc_find_fdc0(void)
555 {
556 int i;
557 Object *container;
558 CheckFdcState state = { 0 };
559
560 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
561 container = container_get(qdev_get_machine(), fdc_container_path[i]);
562 object_child_foreach(container, check_fdc, &state);
563 }
564
565 if (state.multiple) {
566 warn_report("multiple floppy disk controllers with "
567 "iobase=0x3f0 have been found");
568 error_printf("the one being picked for CMOS setup might not reflect "
569 "your intent");
570 }
571
572 return state.floppy;
573 }
574
575 static void pc_cmos_init_late(void *opaque)
576 {
577 pc_cmos_init_late_arg *arg = opaque;
578 ISADevice *s = arg->rtc_state;
579 int16_t cylinders;
580 int8_t heads, sectors;
581 int val;
582 int i, trans;
583
584 val = 0;
585 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
586 &cylinders, &heads, &sectors) >= 0) {
587 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
588 val |= 0xf0;
589 }
590 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
591 &cylinders, &heads, &sectors) >= 0) {
592 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
593 val |= 0x0f;
594 }
595 rtc_set_memory(s, 0x12, val);
596
597 val = 0;
598 for (i = 0; i < 4; i++) {
599 /* NOTE: ide_get_geometry() returns the physical
600 geometry. It is always such that: 1 <= sects <= 63, 1
601 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
602 geometry can be different if a translation is done. */
603 if (arg->idebus[i / 2] &&
604 ide_get_geometry(arg->idebus[i / 2], i % 2,
605 &cylinders, &heads, &sectors) >= 0) {
606 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
607 assert((trans & ~3) == 0);
608 val |= trans << (i * 2);
609 }
610 }
611 rtc_set_memory(s, 0x39, val);
612
613 pc_cmos_init_floppy(s, pc_find_fdc0());
614
615 qemu_unregister_reset(pc_cmos_init_late, opaque);
616 }
617
618 void pc_cmos_init(PCMachineState *pcms,
619 BusState *idebus0, BusState *idebus1,
620 ISADevice *s)
621 {
622 int val;
623 static pc_cmos_init_late_arg arg;
624 X86MachineState *x86ms = X86_MACHINE(pcms);
625
626 /* various important CMOS locations needed by PC/Bochs bios */
627
628 /* memory size */
629 /* base memory (first MiB) */
630 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
631 rtc_set_memory(s, 0x15, val);
632 rtc_set_memory(s, 0x16, val >> 8);
633 /* extended memory (next 64MiB) */
634 if (x86ms->below_4g_mem_size > 1 * MiB) {
635 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
636 } else {
637 val = 0;
638 }
639 if (val > 65535)
640 val = 65535;
641 rtc_set_memory(s, 0x17, val);
642 rtc_set_memory(s, 0x18, val >> 8);
643 rtc_set_memory(s, 0x30, val);
644 rtc_set_memory(s, 0x31, val >> 8);
645 /* memory between 16MiB and 4GiB */
646 if (x86ms->below_4g_mem_size > 16 * MiB) {
647 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
648 } else {
649 val = 0;
650 }
651 if (val > 65535)
652 val = 65535;
653 rtc_set_memory(s, 0x34, val);
654 rtc_set_memory(s, 0x35, val >> 8);
655 /* memory above 4GiB */
656 val = x86ms->above_4g_mem_size / 65536;
657 rtc_set_memory(s, 0x5b, val);
658 rtc_set_memory(s, 0x5c, val >> 8);
659 rtc_set_memory(s, 0x5d, val >> 16);
660
661 object_property_add_link(OBJECT(pcms), "rtc_state",
662 TYPE_ISA_DEVICE,
663 (Object **)&x86ms->rtc,
664 object_property_allow_set_link,
665 OBJ_PROP_LINK_STRONG);
666 object_property_set_link(OBJECT(pcms), OBJECT(s),
667 "rtc_state", &error_abort);
668
669 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
670
671 val = 0;
672 val |= 0x02; /* FPU is there */
673 val |= 0x04; /* PS/2 mouse installed */
674 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
675
676 /* hard drives and FDC */
677 arg.rtc_state = s;
678 arg.idebus[0] = idebus0;
679 arg.idebus[1] = idebus1;
680 qemu_register_reset(pc_cmos_init_late, &arg);
681 }
682
683 static void handle_a20_line_change(void *opaque, int irq, int level)
684 {
685 X86CPU *cpu = opaque;
686
687 /* XXX: send to all CPUs ? */
688 /* XXX: add logic to handle multiple A20 line sources */
689 x86_cpu_set_a20(cpu, level);
690 }
691
692 #define NE2000_NB_MAX 6
693
694 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
695 0x280, 0x380 };
696 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
697
698 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
699 {
700 static int nb_ne2k = 0;
701
702 if (nb_ne2k == NE2000_NB_MAX)
703 return;
704 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
705 ne2000_irq[nb_ne2k], nd);
706 nb_ne2k++;
707 }
708
709 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
710 {
711 X86CPU *cpu = opaque;
712
713 if (level) {
714 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
715 }
716 }
717
718 /*
719 * This function is very similar to smp_parse()
720 * in hw/core/machine.c but includes CPU die support.
721 */
722 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
723 {
724 X86MachineState *x86ms = X86_MACHINE(ms);
725
726 if (opts) {
727 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
728 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
729 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
730 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
731 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
732
733 /* compute missing values, prefer sockets over cores over threads */
734 if (cpus == 0 || sockets == 0) {
735 cores = cores > 0 ? cores : 1;
736 threads = threads > 0 ? threads : 1;
737 if (cpus == 0) {
738 sockets = sockets > 0 ? sockets : 1;
739 cpus = cores * threads * dies * sockets;
740 } else {
741 ms->smp.max_cpus =
742 qemu_opt_get_number(opts, "maxcpus", cpus);
743 sockets = ms->smp.max_cpus / (cores * threads * dies);
744 }
745 } else if (cores == 0) {
746 threads = threads > 0 ? threads : 1;
747 cores = cpus / (sockets * dies * threads);
748 cores = cores > 0 ? cores : 1;
749 } else if (threads == 0) {
750 threads = cpus / (cores * dies * sockets);
751 threads = threads > 0 ? threads : 1;
752 } else if (sockets * dies * cores * threads < cpus) {
753 error_report("cpu topology: "
754 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
755 "smp_cpus (%u)",
756 sockets, dies, cores, threads, cpus);
757 exit(1);
758 }
759
760 ms->smp.max_cpus =
761 qemu_opt_get_number(opts, "maxcpus", cpus);
762
763 if (ms->smp.max_cpus < cpus) {
764 error_report("maxcpus must be equal to or greater than smp");
765 exit(1);
766 }
767
768 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
769 error_report("cpu topology: "
770 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
771 "maxcpus (%u)",
772 sockets, dies, cores, threads,
773 ms->smp.max_cpus);
774 exit(1);
775 }
776
777 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
778 warn_report("Invalid CPU topology deprecated: "
779 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
780 "!= maxcpus (%u)",
781 sockets, dies, cores, threads,
782 ms->smp.max_cpus);
783 }
784
785 ms->smp.cpus = cpus;
786 ms->smp.cores = cores;
787 ms->smp.threads = threads;
788 ms->smp.sockets = sockets;
789 x86ms->smp_dies = dies;
790 }
791
792 if (ms->smp.cpus > 1) {
793 Error *blocker = NULL;
794 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
795 replay_add_blocker(blocker);
796 }
797 }
798
799 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
800 {
801 X86MachineState *x86ms = X86_MACHINE(ms);
802 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
803 Error *local_err = NULL;
804
805 if (id < 0) {
806 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
807 return;
808 }
809
810 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
811 error_setg(errp, "Unable to add CPU: %" PRIi64
812 ", resulting APIC ID (%" PRIi64 ") is too large",
813 id, apic_id);
814 return;
815 }
816
817
818 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
819 if (local_err) {
820 error_propagate(errp, local_err);
821 return;
822 }
823 }
824
825 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
826 {
827 if (cpus_count > 0xff) {
828 /* If the number of CPUs can't be represented in 8 bits, the
829 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
830 * to make old BIOSes fail more predictably.
831 */
832 rtc_set_memory(rtc, 0x5f, 0);
833 } else {
834 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
835 }
836 }
837
838 static
839 void pc_machine_done(Notifier *notifier, void *data)
840 {
841 PCMachineState *pcms = container_of(notifier,
842 PCMachineState, machine_done);
843 X86MachineState *x86ms = X86_MACHINE(pcms);
844 PCIBus *bus = pcms->bus;
845
846 /* set the number of CPUs */
847 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
848
849 if (bus) {
850 int extra_hosts = 0;
851
852 QLIST_FOREACH(bus, &bus->child, sibling) {
853 /* look for expander root buses */
854 if (pci_bus_is_root(bus)) {
855 extra_hosts++;
856 }
857 }
858 if (extra_hosts && x86ms->fw_cfg) {
859 uint64_t *val = g_malloc(sizeof(*val));
860 *val = cpu_to_le64(extra_hosts);
861 fw_cfg_add_file(x86ms->fw_cfg,
862 "etc/extra-pci-roots", val, sizeof(*val));
863 }
864 }
865
866 acpi_setup();
867 if (x86ms->fw_cfg) {
868 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
869 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
870 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
871 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
872 }
873
874 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
875 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
876
877 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
878 iommu->intr_eim != ON_OFF_AUTO_ON) {
879 error_report("current -smp configuration requires "
880 "Extended Interrupt Mode enabled. "
881 "You can add an IOMMU using: "
882 "-device intel-iommu,intremap=on,eim=on");
883 exit(EXIT_FAILURE);
884 }
885 }
886 }
887
888 void pc_guest_info_init(PCMachineState *pcms)
889 {
890 int i;
891 MachineState *ms = MACHINE(pcms);
892 X86MachineState *x86ms = X86_MACHINE(pcms);
893
894 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
895 pcms->numa_nodes = ms->numa_state->num_nodes;
896 pcms->node_mem = g_malloc0(pcms->numa_nodes *
897 sizeof *pcms->node_mem);
898 for (i = 0; i < ms->numa_state->num_nodes; i++) {
899 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
900 }
901
902 pcms->machine_done.notify = pc_machine_done;
903 qemu_add_machine_init_done_notifier(&pcms->machine_done);
904 }
905
906 /* setup pci memory address space mapping into system address space */
907 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
908 MemoryRegion *pci_address_space)
909 {
910 /* Set to lower priority than RAM */
911 memory_region_add_subregion_overlap(system_memory, 0x0,
912 pci_address_space, -1);
913 }
914
915 void xen_load_linux(PCMachineState *pcms)
916 {
917 int i;
918 FWCfgState *fw_cfg;
919 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
920 X86MachineState *x86ms = X86_MACHINE(pcms);
921
922 assert(MACHINE(pcms)->kernel_filename != NULL);
923
924 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
925 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
926 rom_set_fw(fw_cfg);
927
928 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
929 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
930 for (i = 0; i < nb_option_roms; i++) {
931 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
932 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
933 !strcmp(option_rom[i].name, "pvh.bin") ||
934 !strcmp(option_rom[i].name, "multiboot.bin"));
935 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
936 }
937 x86ms->fw_cfg = fw_cfg;
938 }
939
940 void pc_memory_init(PCMachineState *pcms,
941 MemoryRegion *system_memory,
942 MemoryRegion *rom_memory,
943 MemoryRegion **ram_memory)
944 {
945 int linux_boot, i;
946 MemoryRegion *option_rom_mr;
947 MemoryRegion *ram_below_4g, *ram_above_4g;
948 FWCfgState *fw_cfg;
949 MachineState *machine = MACHINE(pcms);
950 MachineClass *mc = MACHINE_GET_CLASS(machine);
951 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
952 X86MachineState *x86ms = X86_MACHINE(pcms);
953
954 assert(machine->ram_size == x86ms->below_4g_mem_size +
955 x86ms->above_4g_mem_size);
956
957 linux_boot = (machine->kernel_filename != NULL);
958
959 /*
960 * Split single memory region and use aliases to address portions of it,
961 * done for backwards compatibility with older qemus.
962 */
963 *ram_memory = machine->ram;
964 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
965 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
966 0, x86ms->below_4g_mem_size);
967 memory_region_add_subregion(system_memory, 0, ram_below_4g);
968 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
969 if (x86ms->above_4g_mem_size > 0) {
970 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
971 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
972 machine->ram,
973 x86ms->below_4g_mem_size,
974 x86ms->above_4g_mem_size);
975 memory_region_add_subregion(system_memory, 0x100000000ULL,
976 ram_above_4g);
977 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
978 }
979
980 if (!pcmc->has_reserved_memory &&
981 (machine->ram_slots ||
982 (machine->maxram_size > machine->ram_size))) {
983
984 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
985 mc->name);
986 exit(EXIT_FAILURE);
987 }
988
989 /* always allocate the device memory information */
990 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
991
992 /* initialize device memory address space */
993 if (pcmc->has_reserved_memory &&
994 (machine->ram_size < machine->maxram_size)) {
995 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
996
997 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
998 error_report("unsupported amount of memory slots: %"PRIu64,
999 machine->ram_slots);
1000 exit(EXIT_FAILURE);
1001 }
1002
1003 if (QEMU_ALIGN_UP(machine->maxram_size,
1004 TARGET_PAGE_SIZE) != machine->maxram_size) {
1005 error_report("maximum memory size must by aligned to multiple of "
1006 "%d bytes", TARGET_PAGE_SIZE);
1007 exit(EXIT_FAILURE);
1008 }
1009
1010 machine->device_memory->base =
1011 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1012
1013 if (pcmc->enforce_aligned_dimm) {
1014 /* size device region assuming 1G page max alignment per slot */
1015 device_mem_size += (1 * GiB) * machine->ram_slots;
1016 }
1017
1018 if ((machine->device_memory->base + device_mem_size) <
1019 device_mem_size) {
1020 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1021 machine->maxram_size);
1022 exit(EXIT_FAILURE);
1023 }
1024
1025 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1026 "device-memory", device_mem_size);
1027 memory_region_add_subregion(system_memory, machine->device_memory->base,
1028 &machine->device_memory->mr);
1029 }
1030
1031 /* Initialize PC system firmware */
1032 pc_system_firmware_init(pcms, rom_memory);
1033
1034 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1035 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1036 &error_fatal);
1037 if (pcmc->pci_enabled) {
1038 memory_region_set_readonly(option_rom_mr, true);
1039 }
1040 memory_region_add_subregion_overlap(rom_memory,
1041 PC_ROM_MIN_VGA,
1042 option_rom_mr,
1043 1);
1044
1045 fw_cfg = fw_cfg_arch_create(machine,
1046 x86ms->boot_cpus, x86ms->apic_id_limit);
1047
1048 rom_set_fw(fw_cfg);
1049
1050 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1051 uint64_t *val = g_malloc(sizeof(*val));
1052 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1053 uint64_t res_mem_end = machine->device_memory->base;
1054
1055 if (!pcmc->broken_reserved_end) {
1056 res_mem_end += memory_region_size(&machine->device_memory->mr);
1057 }
1058 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1059 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1060 }
1061
1062 if (linux_boot) {
1063 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1064 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1065 }
1066
1067 for (i = 0; i < nb_option_roms; i++) {
1068 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1069 }
1070 x86ms->fw_cfg = fw_cfg;
1071
1072 /* Init default IOAPIC address space */
1073 x86ms->ioapic_as = &address_space_memory;
1074
1075 /* Init ACPI memory hotplug IO base address */
1076 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1077 }
1078
1079 /*
1080 * The 64bit pci hole starts after "above 4G RAM" and
1081 * potentially the space reserved for memory hotplug.
1082 */
1083 uint64_t pc_pci_hole64_start(void)
1084 {
1085 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1086 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1087 MachineState *ms = MACHINE(pcms);
1088 X86MachineState *x86ms = X86_MACHINE(pcms);
1089 uint64_t hole64_start = 0;
1090
1091 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1092 hole64_start = ms->device_memory->base;
1093 if (!pcmc->broken_reserved_end) {
1094 hole64_start += memory_region_size(&ms->device_memory->mr);
1095 }
1096 } else {
1097 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1098 }
1099
1100 return ROUND_UP(hole64_start, 1 * GiB);
1101 }
1102
1103 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1104 {
1105 DeviceState *dev = NULL;
1106
1107 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1108 if (pci_bus) {
1109 PCIDevice *pcidev = pci_vga_init(pci_bus);
1110 dev = pcidev ? &pcidev->qdev : NULL;
1111 } else if (isa_bus) {
1112 ISADevice *isadev = isa_vga_init(isa_bus);
1113 dev = isadev ? DEVICE(isadev) : NULL;
1114 }
1115 rom_reset_order_override();
1116 return dev;
1117 }
1118
1119 static const MemoryRegionOps ioport80_io_ops = {
1120 .write = ioport80_write,
1121 .read = ioport80_read,
1122 .endianness = DEVICE_NATIVE_ENDIAN,
1123 .impl = {
1124 .min_access_size = 1,
1125 .max_access_size = 1,
1126 },
1127 };
1128
1129 static const MemoryRegionOps ioportF0_io_ops = {
1130 .write = ioportF0_write,
1131 .read = ioportF0_read,
1132 .endianness = DEVICE_NATIVE_ENDIAN,
1133 .impl = {
1134 .min_access_size = 1,
1135 .max_access_size = 1,
1136 },
1137 };
1138
1139 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1140 {
1141 int i;
1142 DriveInfo *fd[MAX_FD];
1143 qemu_irq *a20_line;
1144 ISADevice *i8042, *port92, *vmmouse;
1145
1146 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1147 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1148
1149 for (i = 0; i < MAX_FD; i++) {
1150 fd[i] = drive_get(IF_FLOPPY, 0, i);
1151 create_fdctrl |= !!fd[i];
1152 }
1153 if (create_fdctrl) {
1154 fdctrl_init_isa(isa_bus, fd);
1155 }
1156
1157 i8042 = isa_create_simple(isa_bus, "i8042");
1158 if (!no_vmport) {
1159 isa_create_simple(isa_bus, TYPE_VMPORT);
1160 vmmouse = isa_try_create(isa_bus, "vmmouse");
1161 } else {
1162 vmmouse = NULL;
1163 }
1164 if (vmmouse) {
1165 object_property_set_link(OBJECT(vmmouse), OBJECT(i8042),
1166 "i8042", &error_abort);
1167 qdev_init_nofail(DEVICE(vmmouse));
1168 }
1169 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1170
1171 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1172 i8042_setup_a20_line(i8042, a20_line[0]);
1173 qdev_connect_gpio_out_named(DEVICE(port92),
1174 PORT92_A20_LINE, 0, a20_line[1]);
1175 g_free(a20_line);
1176 }
1177
1178 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1179 ISADevice **rtc_state,
1180 bool create_fdctrl,
1181 bool no_vmport,
1182 bool has_pit,
1183 uint32_t hpet_irqs)
1184 {
1185 int i;
1186 DeviceState *hpet = NULL;
1187 int pit_isa_irq = 0;
1188 qemu_irq pit_alt_irq = NULL;
1189 qemu_irq rtc_irq = NULL;
1190 ISADevice *pit = NULL;
1191 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1192 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1193
1194 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1195 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1196
1197 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1198 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1199
1200 /*
1201 * Check if an HPET shall be created.
1202 *
1203 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1204 * when the HPET wants to take over. Thus we have to disable the latter.
1205 */
1206 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1207 hpet = qdev_try_create(NULL, TYPE_HPET);
1208 if (hpet) {
1209 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1210 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1211 * IRQ8 and IRQ2.
1212 */
1213 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1214 HPET_INTCAP, NULL);
1215 if (!compat) {
1216 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1217 }
1218 qdev_init_nofail(hpet);
1219 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1220
1221 for (i = 0; i < GSI_NUM_PINS; i++) {
1222 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1223 }
1224 pit_isa_irq = -1;
1225 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1226 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1227 }
1228 }
1229 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1230
1231 qemu_register_boot_set(pc_boot_set, *rtc_state);
1232
1233 if (!xen_enabled() && has_pit) {
1234 if (kvm_pit_in_kernel()) {
1235 pit = kvm_pit_init(isa_bus, 0x40);
1236 } else {
1237 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1238 }
1239 if (hpet) {
1240 /* connect PIT to output control line of the HPET */
1241 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1242 }
1243 pcspk_init(isa_bus, pit);
1244 }
1245
1246 i8257_dma_init(isa_bus, 0);
1247
1248 /* Super I/O */
1249 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1250 }
1251
1252 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1253 {
1254 int i;
1255
1256 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1257 for (i = 0; i < nb_nics; i++) {
1258 NICInfo *nd = &nd_table[i];
1259 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1260
1261 if (g_str_equal(model, "ne2k_isa")) {
1262 pc_init_ne2k_isa(isa_bus, nd);
1263 } else {
1264 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1265 }
1266 }
1267 rom_reset_order_override();
1268 }
1269
1270 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1271 {
1272 qemu_irq *i8259;
1273
1274 if (kvm_pic_in_kernel()) {
1275 i8259 = kvm_i8259_init(isa_bus);
1276 } else if (xen_enabled()) {
1277 i8259 = xen_interrupt_controller_init();
1278 } else {
1279 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1280 }
1281
1282 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1283 i8259_irqs[i] = i8259[i];
1284 }
1285
1286 g_free(i8259);
1287 }
1288
1289 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1290 Error **errp)
1291 {
1292 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1293 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1294 const MachineState *ms = MACHINE(hotplug_dev);
1295 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1296 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1297 Error *local_err = NULL;
1298
1299 /*
1300 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1301 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1302 * addition to cover this case.
1303 */
1304 if (!pcms->acpi_dev || !x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
1305 error_setg(errp,
1306 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1307 return;
1308 }
1309
1310 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1311 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1312 return;
1313 }
1314
1315 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1316 if (local_err) {
1317 error_propagate(errp, local_err);
1318 return;
1319 }
1320
1321 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1322 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1323 }
1324
1325 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1326 DeviceState *dev, Error **errp)
1327 {
1328 Error *local_err = NULL;
1329 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1330 MachineState *ms = MACHINE(hotplug_dev);
1331 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1332
1333 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1334 if (local_err) {
1335 goto out;
1336 }
1337
1338 if (is_nvdimm) {
1339 nvdimm_plug(ms->nvdimms_state);
1340 }
1341
1342 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1343 out:
1344 error_propagate(errp, local_err);
1345 }
1346
1347 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1348 DeviceState *dev, Error **errp)
1349 {
1350 Error *local_err = NULL;
1351 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1352
1353 /*
1354 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1355 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1356 * addition to cover this case.
1357 */
1358 if (!pcms->acpi_dev || !x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
1359 error_setg(&local_err,
1360 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1361 goto out;
1362 }
1363
1364 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1365 error_setg(&local_err,
1366 "nvdimm device hot unplug is not supported yet.");
1367 goto out;
1368 }
1369
1370 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1371 &local_err);
1372 out:
1373 error_propagate(errp, local_err);
1374 }
1375
1376 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1377 DeviceState *dev, Error **errp)
1378 {
1379 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1380 Error *local_err = NULL;
1381
1382 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1383 if (local_err) {
1384 goto out;
1385 }
1386
1387 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1388 object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
1389 out:
1390 error_propagate(errp, local_err);
1391 }
1392
1393 static int pc_apic_cmp(const void *a, const void *b)
1394 {
1395 CPUArchId *apic_a = (CPUArchId *)a;
1396 CPUArchId *apic_b = (CPUArchId *)b;
1397
1398 return apic_a->arch_id - apic_b->arch_id;
1399 }
1400
1401 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1402 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1403 * entry corresponding to CPU's apic_id returns NULL.
1404 */
1405 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1406 {
1407 CPUArchId apic_id, *found_cpu;
1408
1409 apic_id.arch_id = id;
1410 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1411 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1412 pc_apic_cmp);
1413 if (found_cpu && idx) {
1414 *idx = found_cpu - ms->possible_cpus->cpus;
1415 }
1416 return found_cpu;
1417 }
1418
1419 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1420 DeviceState *dev, Error **errp)
1421 {
1422 CPUArchId *found_cpu;
1423 Error *local_err = NULL;
1424 X86CPU *cpu = X86_CPU(dev);
1425 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1426 X86MachineState *x86ms = X86_MACHINE(pcms);
1427
1428 if (pcms->acpi_dev) {
1429 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1430 if (local_err) {
1431 goto out;
1432 }
1433 }
1434
1435 /* increment the number of CPUs */
1436 x86ms->boot_cpus++;
1437 if (x86ms->rtc) {
1438 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1439 }
1440 if (x86ms->fw_cfg) {
1441 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1442 }
1443
1444 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1445 found_cpu->cpu = OBJECT(dev);
1446 out:
1447 error_propagate(errp, local_err);
1448 }
1449 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1450 DeviceState *dev, Error **errp)
1451 {
1452 int idx = -1;
1453 Error *local_err = NULL;
1454 X86CPU *cpu = X86_CPU(dev);
1455 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1456
1457 if (!pcms->acpi_dev) {
1458 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1459 goto out;
1460 }
1461
1462 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1463 assert(idx != -1);
1464 if (idx == 0) {
1465 error_setg(&local_err, "Boot CPU is unpluggable");
1466 goto out;
1467 }
1468
1469 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1470 &local_err);
1471 if (local_err) {
1472 goto out;
1473 }
1474
1475 out:
1476 error_propagate(errp, local_err);
1477
1478 }
1479
1480 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1481 DeviceState *dev, Error **errp)
1482 {
1483 CPUArchId *found_cpu;
1484 Error *local_err = NULL;
1485 X86CPU *cpu = X86_CPU(dev);
1486 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1487 X86MachineState *x86ms = X86_MACHINE(pcms);
1488
1489 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1490 if (local_err) {
1491 goto out;
1492 }
1493
1494 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1495 found_cpu->cpu = NULL;
1496 object_property_set_bool(OBJECT(dev), false, "realized", &error_abort);
1497
1498 /* decrement the number of CPUs */
1499 x86ms->boot_cpus--;
1500 /* Update the number of CPUs in CMOS */
1501 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1502 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1503 out:
1504 error_propagate(errp, local_err);
1505 }
1506
1507 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1508 DeviceState *dev, Error **errp)
1509 {
1510 int idx;
1511 CPUState *cs;
1512 CPUArchId *cpu_slot;
1513 X86CPUTopoIDs topo_ids;
1514 X86CPU *cpu = X86_CPU(dev);
1515 CPUX86State *env = &cpu->env;
1516 MachineState *ms = MACHINE(hotplug_dev);
1517 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1518 X86MachineState *x86ms = X86_MACHINE(pcms);
1519 unsigned int smp_cores = ms->smp.cores;
1520 unsigned int smp_threads = ms->smp.threads;
1521 X86CPUTopoInfo topo_info;
1522
1523 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1524 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1525 ms->cpu_type);
1526 return;
1527 }
1528
1529 init_topo_info(&topo_info, x86ms);
1530
1531 env->nr_dies = x86ms->smp_dies;
1532 env->nr_nodes = topo_info.nodes_per_pkg;
1533 env->pkg_offset = x86ms->apicid_pkg_offset(&topo_info);
1534
1535 /*
1536 * If APIC ID is not set,
1537 * set it based on socket/die/core/thread properties.
1538 */
1539 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1540 int max_socket = (ms->smp.max_cpus - 1) /
1541 smp_threads / smp_cores / x86ms->smp_dies;
1542
1543 /*
1544 * die-id was optional in QEMU 4.0 and older, so keep it optional
1545 * if there's only one die per socket.
1546 */
1547 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1548 cpu->die_id = 0;
1549 }
1550
1551 if (cpu->socket_id < 0) {
1552 error_setg(errp, "CPU socket-id is not set");
1553 return;
1554 } else if (cpu->socket_id > max_socket) {
1555 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1556 cpu->socket_id, max_socket);
1557 return;
1558 }
1559 if (cpu->die_id < 0) {
1560 error_setg(errp, "CPU die-id is not set");
1561 return;
1562 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1563 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1564 cpu->die_id, x86ms->smp_dies - 1);
1565 return;
1566 }
1567 if (cpu->core_id < 0) {
1568 error_setg(errp, "CPU core-id is not set");
1569 return;
1570 } else if (cpu->core_id > (smp_cores - 1)) {
1571 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1572 cpu->core_id, smp_cores - 1);
1573 return;
1574 }
1575 if (cpu->thread_id < 0) {
1576 error_setg(errp, "CPU thread-id is not set");
1577 return;
1578 } else if (cpu->thread_id > (smp_threads - 1)) {
1579 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1580 cpu->thread_id, smp_threads - 1);
1581 return;
1582 }
1583
1584 topo_ids.pkg_id = cpu->socket_id;
1585 topo_ids.die_id = cpu->die_id;
1586 topo_ids.core_id = cpu->core_id;
1587 topo_ids.smt_id = cpu->thread_id;
1588 cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids);
1589 }
1590
1591 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1592 if (!cpu_slot) {
1593 MachineState *ms = MACHINE(pcms);
1594
1595 x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
1596 error_setg(errp,
1597 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1598 " APIC ID %" PRIu32 ", valid index range 0:%d",
1599 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id,
1600 cpu->apic_id, ms->possible_cpus->len - 1);
1601 return;
1602 }
1603
1604 if (cpu_slot->cpu) {
1605 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1606 idx, cpu->apic_id);
1607 return;
1608 }
1609
1610 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1611 * so that machine_query_hotpluggable_cpus would show correct values
1612 */
1613 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1614 * once -smp refactoring is complete and there will be CPU private
1615 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1616 x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
1617 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
1618 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1619 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
1620 topo_ids.pkg_id);
1621 return;
1622 }
1623 cpu->socket_id = topo_ids.pkg_id;
1624
1625 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
1626 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1627 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
1628 return;
1629 }
1630 cpu->die_id = topo_ids.die_id;
1631
1632 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
1633 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1634 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
1635 topo_ids.core_id);
1636 return;
1637 }
1638 cpu->core_id = topo_ids.core_id;
1639
1640 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
1641 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1642 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
1643 topo_ids.smt_id);
1644 return;
1645 }
1646 cpu->thread_id = topo_ids.smt_id;
1647
1648 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1649 !kvm_hv_vpindex_settable()) {
1650 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1651 return;
1652 }
1653
1654 cs = CPU(cpu);
1655 cs->cpu_index = idx;
1656
1657 numa_cpu_pre_plug(cpu_slot, dev, errp);
1658 }
1659
1660 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1661 DeviceState *dev, Error **errp)
1662 {
1663 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1664 Error *local_err = NULL;
1665
1666 if (!hotplug_dev2) {
1667 /*
1668 * Without a bus hotplug handler, we cannot control the plug/unplug
1669 * order. This should never be the case on x86, however better add
1670 * a safety net.
1671 */
1672 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1673 return;
1674 }
1675 /*
1676 * First, see if we can plug this memory device at all. If that
1677 * succeeds, branch of to the actual hotplug handler.
1678 */
1679 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1680 &local_err);
1681 if (!local_err) {
1682 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1683 }
1684 error_propagate(errp, local_err);
1685 }
1686
1687 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1688 DeviceState *dev, Error **errp)
1689 {
1690 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1691 Error *local_err = NULL;
1692
1693 /*
1694 * Plug the memory device first and then branch off to the actual
1695 * hotplug handler. If that one fails, we can easily undo the memory
1696 * device bits.
1697 */
1698 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1699 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1700 if (local_err) {
1701 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1702 }
1703 error_propagate(errp, local_err);
1704 }
1705
1706 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1707 DeviceState *dev, Error **errp)
1708 {
1709 /* We don't support virtio pmem hot unplug */
1710 error_setg(errp, "virtio pmem device unplug not supported.");
1711 }
1712
1713 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1714 DeviceState *dev, Error **errp)
1715 {
1716 /* We don't support virtio pmem hot unplug */
1717 }
1718
1719 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1720 DeviceState *dev, Error **errp)
1721 {
1722 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1723 pc_memory_pre_plug(hotplug_dev, dev, errp);
1724 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1725 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1726 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1727 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1728 }
1729 }
1730
1731 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1732 DeviceState *dev, Error **errp)
1733 {
1734 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1735 pc_memory_plug(hotplug_dev, dev, errp);
1736 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1737 pc_cpu_plug(hotplug_dev, dev, errp);
1738 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1739 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1740 }
1741 }
1742
1743 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1744 DeviceState *dev, Error **errp)
1745 {
1746 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1747 pc_memory_unplug_request(hotplug_dev, dev, errp);
1748 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1749 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1750 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1751 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1752 } else {
1753 error_setg(errp, "acpi: device unplug request for not supported device"
1754 " type: %s", object_get_typename(OBJECT(dev)));
1755 }
1756 }
1757
1758 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1759 DeviceState *dev, Error **errp)
1760 {
1761 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1762 pc_memory_unplug(hotplug_dev, dev, errp);
1763 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1764 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1765 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1766 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1767 } else {
1768 error_setg(errp, "acpi: device unplug for not supported device"
1769 " type: %s", object_get_typename(OBJECT(dev)));
1770 }
1771 }
1772
1773 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1774 DeviceState *dev)
1775 {
1776 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1777 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1778 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1779 return HOTPLUG_HANDLER(machine);
1780 }
1781
1782 return NULL;
1783 }
1784
1785 static void
1786 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1787 const char *name, void *opaque,
1788 Error **errp)
1789 {
1790 MachineState *ms = MACHINE(obj);
1791 int64_t value = 0;
1792
1793 if (ms->device_memory) {
1794 value = memory_region_size(&ms->device_memory->mr);
1795 }
1796
1797 visit_type_int(v, name, &value, errp);
1798 }
1799
1800 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1801 void *opaque, Error **errp)
1802 {
1803 PCMachineState *pcms = PC_MACHINE(obj);
1804 OnOffAuto vmport = pcms->vmport;
1805
1806 visit_type_OnOffAuto(v, name, &vmport, errp);
1807 }
1808
1809 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1810 void *opaque, Error **errp)
1811 {
1812 PCMachineState *pcms = PC_MACHINE(obj);
1813
1814 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1815 }
1816
1817 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1818 {
1819 PCMachineState *pcms = PC_MACHINE(obj);
1820
1821 return pcms->smbus_enabled;
1822 }
1823
1824 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1825 {
1826 PCMachineState *pcms = PC_MACHINE(obj);
1827
1828 pcms->smbus_enabled = value;
1829 }
1830
1831 static bool pc_machine_get_sata(Object *obj, Error **errp)
1832 {
1833 PCMachineState *pcms = PC_MACHINE(obj);
1834
1835 return pcms->sata_enabled;
1836 }
1837
1838 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1839 {
1840 PCMachineState *pcms = PC_MACHINE(obj);
1841
1842 pcms->sata_enabled = value;
1843 }
1844
1845 static bool pc_machine_get_pit(Object *obj, Error **errp)
1846 {
1847 PCMachineState *pcms = PC_MACHINE(obj);
1848
1849 return pcms->pit_enabled;
1850 }
1851
1852 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1853 {
1854 PCMachineState *pcms = PC_MACHINE(obj);
1855
1856 pcms->pit_enabled = value;
1857 }
1858
1859 static void pc_machine_initfn(Object *obj)
1860 {
1861 PCMachineState *pcms = PC_MACHINE(obj);
1862
1863 #ifdef CONFIG_VMPORT
1864 pcms->vmport = ON_OFF_AUTO_AUTO;
1865 #else
1866 pcms->vmport = ON_OFF_AUTO_OFF;
1867 #endif /* CONFIG_VMPORT */
1868 /* acpi build is enabled by default if machine supports it */
1869 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1870 pcms->smbus_enabled = true;
1871 pcms->sata_enabled = true;
1872 pcms->pit_enabled = true;
1873
1874 pc_system_flash_create(pcms);
1875 }
1876
1877 static void pc_machine_reset(MachineState *machine)
1878 {
1879 CPUState *cs;
1880 X86CPU *cpu;
1881
1882 qemu_devices_reset();
1883
1884 /* Reset APIC after devices have been reset to cancel
1885 * any changes that qemu_devices_reset() might have done.
1886 */
1887 CPU_FOREACH(cs) {
1888 cpu = X86_CPU(cs);
1889
1890 if (cpu->apic_state) {
1891 device_legacy_reset(cpu->apic_state);
1892 }
1893 }
1894 }
1895
1896 static void pc_machine_wakeup(MachineState *machine)
1897 {
1898 cpu_synchronize_all_states();
1899 pc_machine_reset(machine);
1900 cpu_synchronize_all_post_reset();
1901 }
1902
1903 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1904 {
1905 X86IOMMUState *iommu = x86_iommu_get_default();
1906 IntelIOMMUState *intel_iommu;
1907
1908 if (iommu &&
1909 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1910 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1911 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1912 if (!intel_iommu->caching_mode) {
1913 error_setg(errp, "Device assignment is not allowed without "
1914 "enabling caching-mode=on for Intel IOMMU.");
1915 return false;
1916 }
1917 }
1918
1919 return true;
1920 }
1921
1922 static void pc_machine_class_init(ObjectClass *oc, void *data)
1923 {
1924 MachineClass *mc = MACHINE_CLASS(oc);
1925 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1926 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1927
1928 pcmc->pci_enabled = true;
1929 pcmc->has_acpi_build = true;
1930 pcmc->rsdp_in_ram = true;
1931 pcmc->smbios_defaults = true;
1932 pcmc->smbios_uuid_encoded = true;
1933 pcmc->gigabyte_align = true;
1934 pcmc->has_reserved_memory = true;
1935 pcmc->kvmclock_enabled = true;
1936 pcmc->enforce_aligned_dimm = true;
1937 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1938 * to be used at the moment, 32K should be enough for a while. */
1939 pcmc->acpi_data_size = 0x20000 + 0x8000;
1940 pcmc->linuxboot_dma_enabled = true;
1941 pcmc->pvh_enabled = true;
1942 assert(!mc->get_hotplug_handler);
1943 mc->get_hotplug_handler = pc_get_hotplug_handler;
1944 mc->hotplug_allowed = pc_hotplug_allowed;
1945 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1946 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1947 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1948 mc->auto_enable_numa_with_memhp = true;
1949 mc->has_hotpluggable_cpus = true;
1950 mc->default_boot_order = "cad";
1951 mc->hot_add_cpu = pc_hot_add_cpu;
1952 mc->smp_parse = pc_smp_parse;
1953 mc->block_default_type = IF_IDE;
1954 mc->max_cpus = 255;
1955 mc->reset = pc_machine_reset;
1956 mc->wakeup = pc_machine_wakeup;
1957 hc->pre_plug = pc_machine_device_pre_plug_cb;
1958 hc->plug = pc_machine_device_plug_cb;
1959 hc->unplug_request = pc_machine_device_unplug_request_cb;
1960 hc->unplug = pc_machine_device_unplug_cb;
1961 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1962 mc->nvdimm_supported = true;
1963 mc->numa_mem_supported = true;
1964 mc->default_ram_id = "pc.ram";
1965
1966 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1967 pc_machine_get_device_memory_region_size, NULL,
1968 NULL, NULL);
1969
1970 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1971 pc_machine_get_vmport, pc_machine_set_vmport,
1972 NULL, NULL);
1973 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1974 "Enable vmport (pc & q35)");
1975
1976 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1977 pc_machine_get_smbus, pc_machine_set_smbus);
1978
1979 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1980 pc_machine_get_sata, pc_machine_set_sata);
1981
1982 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1983 pc_machine_get_pit, pc_machine_set_pit);
1984 }
1985
1986 static const TypeInfo pc_machine_info = {
1987 .name = TYPE_PC_MACHINE,
1988 .parent = TYPE_X86_MACHINE,
1989 .abstract = true,
1990 .instance_size = sizeof(PCMachineState),
1991 .instance_init = pc_machine_initfn,
1992 .class_size = sizeof(PCMachineClass),
1993 .class_init = pc_machine_class_init,
1994 .interfaces = (InterfaceInfo[]) {
1995 { TYPE_HOTPLUG_HANDLER },
1996 { }
1997 },
1998 };
1999
2000 static void pc_machine_register_types(void)
2001 {
2002 type_register_static(&pc_machine_info);
2003 }
2004
2005 type_init(pc_machine_register_types)
AR7 emulation for QEMU