target/arm/cpu_tcg.c

   1 /*
   2  * QEMU ARM TCG CPUs.
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This code is licensed under the GNU GPL v2 or later.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0-or-later
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "cpu.h"
  13 #ifdef CONFIG_TCG
  14 #include "hw/core/tcg-cpu-ops.h"
  15 #endif /* CONFIG_TCG */
  16 #include "internals.h"
  17 #include "target/arm/idau.h"
  18
  19 /* CPU models. These are not needed for the AArch64 linux-user build. */
  20 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
  21
  22 #ifdef CONFIG_TCG
  23 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  24 {
  25     CPUClass *cc = CPU_GET_CLASS(cs);
  26     ARMCPU *cpu = ARM_CPU(cs);
  27     CPUARMState *env = &cpu->env;
  28     bool ret = false;
  29
  30     /*
  31      * ARMv7-M interrupt masking works differently than -A or -R.
  32      * There is no FIQ/IRQ distinction. Instead of I and F bits
  33      * masking FIQ and IRQ interrupts, an exception is taken only
  34      * if it is higher priority than the current execution priority
  35      * (which depends on state like BASEPRI, FAULTMASK and the
  36      * currently active exception).
  37      */
  38     if (interrupt_request & CPU_INTERRUPT_HARD
  39         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
  40         cs->exception_index = EXCP_IRQ;
  41         cc->tcg_ops->do_interrupt(cs);
  42         ret = true;
  43     }
  44     return ret;
  45 }
  46 #endif /* CONFIG_TCG */
  47
  48 static void arm926_initfn(Object *obj)
  49 {
  50     ARMCPU *cpu = ARM_CPU(obj);
  51
  52     cpu->dtb_compatible = "arm,arm926";
  53     set_feature(&cpu->env, ARM_FEATURE_V5);
  54     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  55     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
  56     cpu->midr = 0x41069265;
  57     cpu->reset_fpsid = 0x41011090;
  58     cpu->ctr = 0x1dd20d2;
  59     cpu->reset_sctlr = 0x00090078;
  60
  61     /*
  62      * ARMv5 does not have the ID_ISAR registers, but we can still
  63      * set the field to indicate Jazelle support within QEMU.
  64      */
  65     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
  66     /*
  67      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
  68      * support even though ARMv5 doesn't have this register.
  69      */
  70     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
  71     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
  72     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
  73 }
  74
  75 static void arm946_initfn(Object *obj)
  76 {
  77     ARMCPU *cpu = ARM_CPU(obj);
  78
  79     cpu->dtb_compatible = "arm,arm946";
  80     set_feature(&cpu->env, ARM_FEATURE_V5);
  81     set_feature(&cpu->env, ARM_FEATURE_PMSA);
  82     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  83     cpu->midr = 0x41059461;
  84     cpu->ctr = 0x0f004006;
  85     cpu->reset_sctlr = 0x00000078;
  86 }
  87
  88 static void arm1026_initfn(Object *obj)
  89 {
  90     ARMCPU *cpu = ARM_CPU(obj);
  91
  92     cpu->dtb_compatible = "arm,arm1026";
  93     set_feature(&cpu->env, ARM_FEATURE_V5);
  94     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
  95     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
  96     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
  97     cpu->midr = 0x4106a262;
  98     cpu->reset_fpsid = 0x410110a0;
  99     cpu->ctr = 0x1dd20d2;
 100     cpu->reset_sctlr = 0x00090078;
 101     cpu->reset_auxcr = 1;
 102
 103     /*
 104      * ARMv5 does not have the ID_ISAR registers, but we can still
 105      * set the field to indicate Jazelle support within QEMU.
 106      */
 107     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
 108     /*
 109      * Similarly, we need to set MVFR0 fields to enable vfp and short vector
 110      * support even though ARMv5 doesn't have this register.
 111      */
 112     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 113     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
 114     cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
 115
 116     {
 117         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 118         ARMCPRegInfo ifar = {
 119             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 120             .access = PL1_RW,
 121             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 122             .resetvalue = 0
 123         };
 124         define_one_arm_cp_reg(cpu, &ifar);
 125     }
 126 }
 127
 128 static void arm1136_r2_initfn(Object *obj)
 129 {
 130     ARMCPU *cpu = ARM_CPU(obj);
 131     /*
 132      * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 133      * older core than plain "arm1136". In particular this does not
 134      * have the v6K features.
 135      * These ID register values are correct for 1136 but may be wrong
 136      * for 1136_r2 (in particular r0p2 does not actually implement most
 137      * of the ID registers).
 138      */
 139
 140     cpu->dtb_compatible = "arm,arm1136";
 141     set_feature(&cpu->env, ARM_FEATURE_V6);
 142     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 143     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 144     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 145     cpu->midr = 0x4107b362;
 146     cpu->reset_fpsid = 0x410120b4;
 147     cpu->isar.mvfr0 = 0x11111111;
 148     cpu->isar.mvfr1 = 0x00000000;
 149     cpu->ctr = 0x1dd20d2;
 150     cpu->reset_sctlr = 0x00050078;
 151     cpu->isar.id_pfr0 = 0x111;
 152     cpu->isar.id_pfr1 = 0x1;
 153     cpu->isar.id_dfr0 = 0x2;
 154     cpu->id_afr0 = 0x3;
 155     cpu->isar.id_mmfr0 = 0x01130003;
 156     cpu->isar.id_mmfr1 = 0x10030302;
 157     cpu->isar.id_mmfr2 = 0x01222110;
 158     cpu->isar.id_isar0 = 0x00140011;
 159     cpu->isar.id_isar1 = 0x12002111;
 160     cpu->isar.id_isar2 = 0x11231111;
 161     cpu->isar.id_isar3 = 0x01102131;
 162     cpu->isar.id_isar4 = 0x141;
 163     cpu->reset_auxcr = 7;
 164 }
 165
 166 static void arm1136_initfn(Object *obj)
 167 {
 168     ARMCPU *cpu = ARM_CPU(obj);
 169
 170     cpu->dtb_compatible = "arm,arm1136";
 171     set_feature(&cpu->env, ARM_FEATURE_V6K);
 172     set_feature(&cpu->env, ARM_FEATURE_V6);
 173     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 174     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 175     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 176     cpu->midr = 0x4117b363;
 177     cpu->reset_fpsid = 0x410120b4;
 178     cpu->isar.mvfr0 = 0x11111111;
 179     cpu->isar.mvfr1 = 0x00000000;
 180     cpu->ctr = 0x1dd20d2;
 181     cpu->reset_sctlr = 0x00050078;
 182     cpu->isar.id_pfr0 = 0x111;
 183     cpu->isar.id_pfr1 = 0x1;
 184     cpu->isar.id_dfr0 = 0x2;
 185     cpu->id_afr0 = 0x3;
 186     cpu->isar.id_mmfr0 = 0x01130003;
 187     cpu->isar.id_mmfr1 = 0x10030302;
 188     cpu->isar.id_mmfr2 = 0x01222110;
 189     cpu->isar.id_isar0 = 0x00140011;
 190     cpu->isar.id_isar1 = 0x12002111;
 191     cpu->isar.id_isar2 = 0x11231111;
 192     cpu->isar.id_isar3 = 0x01102131;
 193     cpu->isar.id_isar4 = 0x141;
 194     cpu->reset_auxcr = 7;
 195 }
 196
 197 static void arm1176_initfn(Object *obj)
 198 {
 199     ARMCPU *cpu = ARM_CPU(obj);
 200
 201     cpu->dtb_compatible = "arm,arm1176";
 202     set_feature(&cpu->env, ARM_FEATURE_V6K);
 203     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 204     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 205     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 206     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 207     set_feature(&cpu->env, ARM_FEATURE_EL3);
 208     cpu->midr = 0x410fb767;
 209     cpu->reset_fpsid = 0x410120b5;
 210     cpu->isar.mvfr0 = 0x11111111;
 211     cpu->isar.mvfr1 = 0x00000000;
 212     cpu->ctr = 0x1dd20d2;
 213     cpu->reset_sctlr = 0x00050078;
 214     cpu->isar.id_pfr0 = 0x111;
 215     cpu->isar.id_pfr1 = 0x11;
 216     cpu->isar.id_dfr0 = 0x33;
 217     cpu->id_afr0 = 0;
 218     cpu->isar.id_mmfr0 = 0x01130003;
 219     cpu->isar.id_mmfr1 = 0x10030302;
 220     cpu->isar.id_mmfr2 = 0x01222100;
 221     cpu->isar.id_isar0 = 0x0140011;
 222     cpu->isar.id_isar1 = 0x12002111;
 223     cpu->isar.id_isar2 = 0x11231121;
 224     cpu->isar.id_isar3 = 0x01102131;
 225     cpu->isar.id_isar4 = 0x01141;
 226     cpu->reset_auxcr = 7;
 227 }
 228
 229 static void arm11mpcore_initfn(Object *obj)
 230 {
 231     ARMCPU *cpu = ARM_CPU(obj);
 232
 233     cpu->dtb_compatible = "arm,arm11mpcore";
 234     set_feature(&cpu->env, ARM_FEATURE_V6K);
 235     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 236     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 237     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 238     cpu->midr = 0x410fb022;
 239     cpu->reset_fpsid = 0x410120b4;
 240     cpu->isar.mvfr0 = 0x11111111;
 241     cpu->isar.mvfr1 = 0x00000000;
 242     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 243     cpu->isar.id_pfr0 = 0x111;
 244     cpu->isar.id_pfr1 = 0x1;
 245     cpu->isar.id_dfr0 = 0;
 246     cpu->id_afr0 = 0x2;
 247     cpu->isar.id_mmfr0 = 0x01100103;
 248     cpu->isar.id_mmfr1 = 0x10020302;
 249     cpu->isar.id_mmfr2 = 0x01222000;
 250     cpu->isar.id_isar0 = 0x00100011;
 251     cpu->isar.id_isar1 = 0x12002111;
 252     cpu->isar.id_isar2 = 0x11221011;
 253     cpu->isar.id_isar3 = 0x01102131;
 254     cpu->isar.id_isar4 = 0x141;
 255     cpu->reset_auxcr = 1;
 256 }
 257
 258 static void cortex_m0_initfn(Object *obj)
 259 {
 260     ARMCPU *cpu = ARM_CPU(obj);
 261     set_feature(&cpu->env, ARM_FEATURE_V6);
 262     set_feature(&cpu->env, ARM_FEATURE_M);
 263
 264     cpu->midr = 0x410cc200;
 265
 266     /*
 267      * These ID register values are not guest visible, because
 268      * we do not implement the Main Extension. They must be set
 269      * to values corresponding to the Cortex-M0's implemented
 270      * features, because QEMU generally controls its emulation
 271      * by looking at ID register fields. We use the same values as
 272      * for the M3.
 273      */
 274     cpu->isar.id_pfr0 = 0x00000030;
 275     cpu->isar.id_pfr1 = 0x00000200;
 276     cpu->isar.id_dfr0 = 0x00100000;
 277     cpu->id_afr0 = 0x00000000;
 278     cpu->isar.id_mmfr0 = 0x00000030;
 279     cpu->isar.id_mmfr1 = 0x00000000;
 280     cpu->isar.id_mmfr2 = 0x00000000;
 281     cpu->isar.id_mmfr3 = 0x00000000;
 282     cpu->isar.id_isar0 = 0x01141110;
 283     cpu->isar.id_isar1 = 0x02111000;
 284     cpu->isar.id_isar2 = 0x21112231;
 285     cpu->isar.id_isar3 = 0x01111110;
 286     cpu->isar.id_isar4 = 0x01310102;
 287     cpu->isar.id_isar5 = 0x00000000;
 288     cpu->isar.id_isar6 = 0x00000000;
 289 }
 290
 291 static void cortex_m3_initfn(Object *obj)
 292 {
 293     ARMCPU *cpu = ARM_CPU(obj);
 294     set_feature(&cpu->env, ARM_FEATURE_V7);
 295     set_feature(&cpu->env, ARM_FEATURE_M);
 296     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 297     cpu->midr = 0x410fc231;
 298     cpu->pmsav7_dregion = 8;
 299     cpu->isar.id_pfr0 = 0x00000030;
 300     cpu->isar.id_pfr1 = 0x00000200;
 301     cpu->isar.id_dfr0 = 0x00100000;
 302     cpu->id_afr0 = 0x00000000;
 303     cpu->isar.id_mmfr0 = 0x00000030;
 304     cpu->isar.id_mmfr1 = 0x00000000;
 305     cpu->isar.id_mmfr2 = 0x00000000;
 306     cpu->isar.id_mmfr3 = 0x00000000;
 307     cpu->isar.id_isar0 = 0x01141110;
 308     cpu->isar.id_isar1 = 0x02111000;
 309     cpu->isar.id_isar2 = 0x21112231;
 310     cpu->isar.id_isar3 = 0x01111110;
 311     cpu->isar.id_isar4 = 0x01310102;
 312     cpu->isar.id_isar5 = 0x00000000;
 313     cpu->isar.id_isar6 = 0x00000000;
 314 }
 315
 316 static void cortex_m4_initfn(Object *obj)
 317 {
 318     ARMCPU *cpu = ARM_CPU(obj);
 319
 320     set_feature(&cpu->env, ARM_FEATURE_V7);
 321     set_feature(&cpu->env, ARM_FEATURE_M);
 322     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 323     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 324     cpu->midr = 0x410fc240; /* r0p0 */
 325     cpu->pmsav7_dregion = 8;
 326     cpu->isar.mvfr0 = 0x10110021;
 327     cpu->isar.mvfr1 = 0x11000011;
 328     cpu->isar.mvfr2 = 0x00000000;
 329     cpu->isar.id_pfr0 = 0x00000030;
 330     cpu->isar.id_pfr1 = 0x00000200;
 331     cpu->isar.id_dfr0 = 0x00100000;
 332     cpu->id_afr0 = 0x00000000;
 333     cpu->isar.id_mmfr0 = 0x00000030;
 334     cpu->isar.id_mmfr1 = 0x00000000;
 335     cpu->isar.id_mmfr2 = 0x00000000;
 336     cpu->isar.id_mmfr3 = 0x00000000;
 337     cpu->isar.id_isar0 = 0x01141110;
 338     cpu->isar.id_isar1 = 0x02111000;
 339     cpu->isar.id_isar2 = 0x21112231;
 340     cpu->isar.id_isar3 = 0x01111110;
 341     cpu->isar.id_isar4 = 0x01310102;
 342     cpu->isar.id_isar5 = 0x00000000;
 343     cpu->isar.id_isar6 = 0x00000000;
 344 }
 345
 346 static void cortex_m7_initfn(Object *obj)
 347 {
 348     ARMCPU *cpu = ARM_CPU(obj);
 349
 350     set_feature(&cpu->env, ARM_FEATURE_V7);
 351     set_feature(&cpu->env, ARM_FEATURE_M);
 352     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 353     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 354     cpu->midr = 0x411fc272; /* r1p2 */
 355     cpu->pmsav7_dregion = 8;
 356     cpu->isar.mvfr0 = 0x10110221;
 357     cpu->isar.mvfr1 = 0x12000011;
 358     cpu->isar.mvfr2 = 0x00000040;
 359     cpu->isar.id_pfr0 = 0x00000030;
 360     cpu->isar.id_pfr1 = 0x00000200;
 361     cpu->isar.id_dfr0 = 0x00100000;
 362     cpu->id_afr0 = 0x00000000;
 363     cpu->isar.id_mmfr0 = 0x00100030;
 364     cpu->isar.id_mmfr1 = 0x00000000;
 365     cpu->isar.id_mmfr2 = 0x01000000;
 366     cpu->isar.id_mmfr3 = 0x00000000;
 367     cpu->isar.id_isar0 = 0x01101110;
 368     cpu->isar.id_isar1 = 0x02112000;
 369     cpu->isar.id_isar2 = 0x20232231;
 370     cpu->isar.id_isar3 = 0x01111131;
 371     cpu->isar.id_isar4 = 0x01310132;
 372     cpu->isar.id_isar5 = 0x00000000;
 373     cpu->isar.id_isar6 = 0x00000000;
 374 }
 375
 376 static void cortex_m33_initfn(Object *obj)
 377 {
 378     ARMCPU *cpu = ARM_CPU(obj);
 379
 380     set_feature(&cpu->env, ARM_FEATURE_V8);
 381     set_feature(&cpu->env, ARM_FEATURE_M);
 382     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 383     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 384     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 385     cpu->midr = 0x410fd213; /* r0p3 */
 386     cpu->pmsav7_dregion = 16;
 387     cpu->sau_sregion = 8;
 388     cpu->isar.mvfr0 = 0x10110021;
 389     cpu->isar.mvfr1 = 0x11000011;
 390     cpu->isar.mvfr2 = 0x00000040;
 391     cpu->isar.id_pfr0 = 0x00000030;
 392     cpu->isar.id_pfr1 = 0x00000210;
 393     cpu->isar.id_dfr0 = 0x00200000;
 394     cpu->id_afr0 = 0x00000000;
 395     cpu->isar.id_mmfr0 = 0x00101F40;
 396     cpu->isar.id_mmfr1 = 0x00000000;
 397     cpu->isar.id_mmfr2 = 0x01000000;
 398     cpu->isar.id_mmfr3 = 0x00000000;
 399     cpu->isar.id_isar0 = 0x01101110;
 400     cpu->isar.id_isar1 = 0x02212000;
 401     cpu->isar.id_isar2 = 0x20232232;
 402     cpu->isar.id_isar3 = 0x01111131;
 403     cpu->isar.id_isar4 = 0x01310132;
 404     cpu->isar.id_isar5 = 0x00000000;
 405     cpu->isar.id_isar6 = 0x00000000;
 406     cpu->clidr = 0x00000000;
 407     cpu->ctr = 0x8000c000;
 408 }
 409
 410 static void cortex_m55_initfn(Object *obj)
 411 {
 412     ARMCPU *cpu = ARM_CPU(obj);
 413
 414     set_feature(&cpu->env, ARM_FEATURE_V8);
 415     set_feature(&cpu->env, ARM_FEATURE_V8_1M);
 416     set_feature(&cpu->env, ARM_FEATURE_M);
 417     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
 418     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
 419     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 420     cpu->midr = 0x410fd221; /* r0p1 */
 421     cpu->revidr = 0;
 422     cpu->pmsav7_dregion = 16;
 423     cpu->sau_sregion = 8;
 424     /*
 425      * These are the MVFR* values for the FPU, no MVE configuration;
 426      * we will update them later when we implement MVE
 427      */
 428     cpu->isar.mvfr0 = 0x10110221;
 429     cpu->isar.mvfr1 = 0x12100011;
 430     cpu->isar.mvfr2 = 0x00000040;
 431     cpu->isar.id_pfr0 = 0x20000030;
 432     cpu->isar.id_pfr1 = 0x00000230;
 433     cpu->isar.id_dfr0 = 0x10200000;
 434     cpu->id_afr0 = 0x00000000;
 435     cpu->isar.id_mmfr0 = 0x00111040;
 436     cpu->isar.id_mmfr1 = 0x00000000;
 437     cpu->isar.id_mmfr2 = 0x01000000;
 438     cpu->isar.id_mmfr3 = 0x00000011;
 439     cpu->isar.id_isar0 = 0x01103110;
 440     cpu->isar.id_isar1 = 0x02212000;
 441     cpu->isar.id_isar2 = 0x20232232;
 442     cpu->isar.id_isar3 = 0x01111131;
 443     cpu->isar.id_isar4 = 0x01310132;
 444     cpu->isar.id_isar5 = 0x00000000;
 445     cpu->isar.id_isar6 = 0x00000000;
 446     cpu->clidr = 0x00000000; /* caches not implemented */
 447     cpu->ctr = 0x8303c003;
 448 }
 449
 450 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 451     /* Dummy the TCM region regs for the moment */
 452     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 453       .access = PL1_RW, .type = ARM_CP_CONST },
 454     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 455       .access = PL1_RW, .type = ARM_CP_CONST },
 456     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
 457       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
 458     REGINFO_SENTINEL
 459 };
 460
 461 static void cortex_r5_initfn(Object *obj)
 462 {
 463     ARMCPU *cpu = ARM_CPU(obj);
 464
 465     set_feature(&cpu->env, ARM_FEATURE_V7);
 466     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 467     set_feature(&cpu->env, ARM_FEATURE_PMSA);
 468     set_feature(&cpu->env, ARM_FEATURE_PMU);
 469     cpu->midr = 0x411fc153; /* r1p3 */
 470     cpu->isar.id_pfr0 = 0x0131;
 471     cpu->isar.id_pfr1 = 0x001;
 472     cpu->isar.id_dfr0 = 0x010400;
 473     cpu->id_afr0 = 0x0;
 474     cpu->isar.id_mmfr0 = 0x0210030;
 475     cpu->isar.id_mmfr1 = 0x00000000;
 476     cpu->isar.id_mmfr2 = 0x01200000;
 477     cpu->isar.id_mmfr3 = 0x0211;
 478     cpu->isar.id_isar0 = 0x02101111;
 479     cpu->isar.id_isar1 = 0x13112111;
 480     cpu->isar.id_isar2 = 0x21232141;
 481     cpu->isar.id_isar3 = 0x01112131;
 482     cpu->isar.id_isar4 = 0x0010142;
 483     cpu->isar.id_isar5 = 0x0;
 484     cpu->isar.id_isar6 = 0x0;
 485     cpu->mp_is_up = true;
 486     cpu->pmsav7_dregion = 16;
 487     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 488 }
 489
 490 static void cortex_r5f_initfn(Object *obj)
 491 {
 492     ARMCPU *cpu = ARM_CPU(obj);
 493
 494     cortex_r5_initfn(obj);
 495     cpu->isar.mvfr0 = 0x10110221;
 496     cpu->isar.mvfr1 = 0x00000011;
 497 }
 498
 499 static void ti925t_initfn(Object *obj)
 500 {
 501     ARMCPU *cpu = ARM_CPU(obj);
 502     set_feature(&cpu->env, ARM_FEATURE_V4T);
 503     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 504     cpu->midr = ARM_CPUID_TI925T;
 505     cpu->ctr = 0x5109149;
 506     cpu->reset_sctlr = 0x00000070;
 507 }
 508
 509 static void sa1100_initfn(Object *obj)
 510 {
 511     ARMCPU *cpu = ARM_CPU(obj);
 512
 513     cpu->dtb_compatible = "intel,sa1100";
 514     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 515     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 516     cpu->midr = 0x4401A11B;
 517     cpu->reset_sctlr = 0x00000070;
 518 }
 519
 520 static void sa1110_initfn(Object *obj)
 521 {
 522     ARMCPU *cpu = ARM_CPU(obj);
 523     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 524     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 525     cpu->midr = 0x6901B119;
 526     cpu->reset_sctlr = 0x00000070;
 527 }
 528
 529 static void pxa250_initfn(Object *obj)
 530 {
 531     ARMCPU *cpu = ARM_CPU(obj);
 532
 533     cpu->dtb_compatible = "marvell,xscale";
 534     set_feature(&cpu->env, ARM_FEATURE_V5);
 535     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 536     cpu->midr = 0x69052100;
 537     cpu->ctr = 0xd172172;
 538     cpu->reset_sctlr = 0x00000078;
 539 }
 540
 541 static void pxa255_initfn(Object *obj)
 542 {
 543     ARMCPU *cpu = ARM_CPU(obj);
 544
 545     cpu->dtb_compatible = "marvell,xscale";
 546     set_feature(&cpu->env, ARM_FEATURE_V5);
 547     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 548     cpu->midr = 0x69052d00;
 549     cpu->ctr = 0xd172172;
 550     cpu->reset_sctlr = 0x00000078;
 551 }
 552
 553 static void pxa260_initfn(Object *obj)
 554 {
 555     ARMCPU *cpu = ARM_CPU(obj);
 556
 557     cpu->dtb_compatible = "marvell,xscale";
 558     set_feature(&cpu->env, ARM_FEATURE_V5);
 559     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 560     cpu->midr = 0x69052903;
 561     cpu->ctr = 0xd172172;
 562     cpu->reset_sctlr = 0x00000078;
 563 }
 564
 565 static void pxa261_initfn(Object *obj)
 566 {
 567     ARMCPU *cpu = ARM_CPU(obj);
 568
 569     cpu->dtb_compatible = "marvell,xscale";
 570     set_feature(&cpu->env, ARM_FEATURE_V5);
 571     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 572     cpu->midr = 0x69052d05;
 573     cpu->ctr = 0xd172172;
 574     cpu->reset_sctlr = 0x00000078;
 575 }
 576
 577 static void pxa262_initfn(Object *obj)
 578 {
 579     ARMCPU *cpu = ARM_CPU(obj);
 580
 581     cpu->dtb_compatible = "marvell,xscale";
 582     set_feature(&cpu->env, ARM_FEATURE_V5);
 583     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 584     cpu->midr = 0x69052d06;
 585     cpu->ctr = 0xd172172;
 586     cpu->reset_sctlr = 0x00000078;
 587 }
 588
 589 static void pxa270a0_initfn(Object *obj)
 590 {
 591     ARMCPU *cpu = ARM_CPU(obj);
 592
 593     cpu->dtb_compatible = "marvell,xscale";
 594     set_feature(&cpu->env, ARM_FEATURE_V5);
 595     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 596     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 597     cpu->midr = 0x69054110;
 598     cpu->ctr = 0xd172172;
 599     cpu->reset_sctlr = 0x00000078;
 600 }
 601
 602 static void pxa270a1_initfn(Object *obj)
 603 {
 604     ARMCPU *cpu = ARM_CPU(obj);
 605
 606     cpu->dtb_compatible = "marvell,xscale";
 607     set_feature(&cpu->env, ARM_FEATURE_V5);
 608     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 609     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 610     cpu->midr = 0x69054111;
 611     cpu->ctr = 0xd172172;
 612     cpu->reset_sctlr = 0x00000078;
 613 }
 614
 615 static void pxa270b0_initfn(Object *obj)
 616 {
 617     ARMCPU *cpu = ARM_CPU(obj);
 618
 619     cpu->dtb_compatible = "marvell,xscale";
 620     set_feature(&cpu->env, ARM_FEATURE_V5);
 621     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 622     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 623     cpu->midr = 0x69054112;
 624     cpu->ctr = 0xd172172;
 625     cpu->reset_sctlr = 0x00000078;
 626 }
 627
 628 static void pxa270b1_initfn(Object *obj)
 629 {
 630     ARMCPU *cpu = ARM_CPU(obj);
 631
 632     cpu->dtb_compatible = "marvell,xscale";
 633     set_feature(&cpu->env, ARM_FEATURE_V5);
 634     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 635     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 636     cpu->midr = 0x69054113;
 637     cpu->ctr = 0xd172172;
 638     cpu->reset_sctlr = 0x00000078;
 639 }
 640
 641 static void pxa270c0_initfn(Object *obj)
 642 {
 643     ARMCPU *cpu = ARM_CPU(obj);
 644
 645     cpu->dtb_compatible = "marvell,xscale";
 646     set_feature(&cpu->env, ARM_FEATURE_V5);
 647     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 648     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 649     cpu->midr = 0x69054114;
 650     cpu->ctr = 0xd172172;
 651     cpu->reset_sctlr = 0x00000078;
 652 }
 653
 654 static void pxa270c5_initfn(Object *obj)
 655 {
 656     ARMCPU *cpu = ARM_CPU(obj);
 657
 658     cpu->dtb_compatible = "marvell,xscale";
 659     set_feature(&cpu->env, ARM_FEATURE_V5);
 660     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 661     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 662     cpu->midr = 0x69054117;
 663     cpu->ctr = 0xd172172;
 664     cpu->reset_sctlr = 0x00000078;
 665 }
 666
 667 #ifdef CONFIG_TCG
 668 static struct TCGCPUOps arm_v7m_tcg_ops = {
 669     .initialize = arm_translate_init,
 670     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
 671     .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
 672     .tlb_fill = arm_cpu_tlb_fill,
 673     .debug_excp_handler = arm_debug_excp_handler,
 674
 675 #if !defined(CONFIG_USER_ONLY)
 676     .do_interrupt = arm_v7m_cpu_do_interrupt,
 677     .do_transaction_failed = arm_cpu_do_transaction_failed,
 678     .do_unaligned_access = arm_cpu_do_unaligned_access,
 679     .adjust_watchpoint_address = arm_adjust_watchpoint_address,
 680     .debug_check_watchpoint = arm_debug_check_watchpoint,
 681 #endif /* !CONFIG_USER_ONLY */
 682 };
 683 #endif /* CONFIG_TCG */
 684
 685 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 686 {
 687     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 688     CPUClass *cc = CPU_CLASS(oc);
 689
 690     acc->info = data;
 691 #ifdef CONFIG_TCG
 692     cc->tcg_ops = &arm_v7m_tcg_ops;
 693 #endif /* CONFIG_TCG */
 694
 695     cc->gdb_core_xml_file = "arm-m-profile.xml";
 696 }
 697
 698 static const ARMCPUInfo arm_tcg_cpus[] = {
 699     { .name = "arm926",      .initfn = arm926_initfn },
 700     { .name = "arm946",      .initfn = arm946_initfn },
 701     { .name = "arm1026",     .initfn = arm1026_initfn },
 702     /*
 703      * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 704      * older core than plain "arm1136". In particular this does not
 705      * have the v6K features.
 706      */
 707     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 708     { .name = "arm1136",     .initfn = arm1136_initfn },
 709     { .name = "arm1176",     .initfn = arm1176_initfn },
 710     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 711     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
 712                              .class_init = arm_v7m_class_init },
 713     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 714                              .class_init = arm_v7m_class_init },
 715     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
 716                              .class_init = arm_v7m_class_init },
 717     { .name = "cortex-m7",   .initfn = cortex_m7_initfn,
 718                              .class_init = arm_v7m_class_init },
 719     { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
 720                              .class_init = arm_v7m_class_init },
 721     { .name = "cortex-m55",  .initfn = cortex_m55_initfn,
 722                              .class_init = arm_v7m_class_init },
 723     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
 724     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
 725     { .name = "ti925t",      .initfn = ti925t_initfn },
 726     { .name = "sa1100",      .initfn = sa1100_initfn },
 727     { .name = "sa1110",      .initfn = sa1110_initfn },
 728     { .name = "pxa250",      .initfn = pxa250_initfn },
 729     { .name = "pxa255",      .initfn = pxa255_initfn },
 730     { .name = "pxa260",      .initfn = pxa260_initfn },
 731     { .name = "pxa261",      .initfn = pxa261_initfn },
 732     { .name = "pxa262",      .initfn = pxa262_initfn },
 733     /* "pxa270" is an alias for "pxa270-a0" */
 734     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 735     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 736     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 737     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 738     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 739     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 740     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 741 };
 742
 743 static const TypeInfo idau_interface_type_info = {
 744     .name = TYPE_IDAU_INTERFACE,
 745     .parent = TYPE_INTERFACE,
 746     .class_size = sizeof(IDAUInterfaceClass),
 747 };
 748
 749 static void arm_tcg_cpu_register_types(void)
 750 {
 751     size_t i;
 752
 753     type_register_static(&idau_interface_type_info);
 754     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
 755         arm_cpu_register(&arm_tcg_cpus[i]);
 756     }
 757 }
 758
 759 type_init(arm_tcg_cpu_register_types)
 760
 761 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */