target/arm: Provide and use H8 and H1_8 macros
[qemu/ar7.git] / target / arm / vec_internal.h
blob613f3421b9c030b4a7b3fc5bdbf08caa741e7cd9
1 /*
2 * ARM AdvSIMD / SVE Vector Helpers
4 * Copyright (c) 2020 Linaro
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef TARGET_ARM_VEC_INTERNALS_H
21 #define TARGET_ARM_VEC_INTERNALS_H
24 * Note that vector data is stored in host-endian 64-bit chunks,
25 * so addressing units smaller than that needs a host-endian fixup.
27 * The H<N> macros are used when indexing an array of elements of size N.
29 * The H1_<N> macros are used when performing byte arithmetic and then
30 * casting the final pointer to a type of size N.
32 #ifdef HOST_WORDS_BIGENDIAN
33 #define H1(x) ((x) ^ 7)
34 #define H1_2(x) ((x) ^ 6)
35 #define H1_4(x) ((x) ^ 4)
36 #define H2(x) ((x) ^ 3)
37 #define H4(x) ((x) ^ 1)
38 #else
39 #define H1(x) (x)
40 #define H1_2(x) (x)
41 #define H1_4(x) (x)
42 #define H2(x) (x)
43 #define H4(x) (x)
44 #endif
46 * Access to 64-bit elements isn't host-endian dependent; we provide H8
47 * and H1_8 so that when a function is being generated from a macro we
48 * can pass these rather than an empty macro argument, for clarity.
50 #define H8(x) (x)
51 #define H1_8(x) (x)
53 static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
55 uint64_t *d = vd + opr_sz;
56 uintptr_t i;
58 for (i = opr_sz; i < max_sz; i += 8) {
59 *d++ = 0;
63 static inline int32_t do_sqrshl_bhs(int32_t src, int32_t shift, int bits,
64 bool round, uint32_t *sat)
66 if (shift <= -bits) {
67 /* Rounding the sign bit always produces 0. */
68 if (round) {
69 return 0;
71 return src >> 31;
72 } else if (shift < 0) {
73 if (round) {
74 src >>= -shift - 1;
75 return (src >> 1) + (src & 1);
77 return src >> -shift;
78 } else if (shift < bits) {
79 int32_t val = src << shift;
80 if (bits == 32) {
81 if (!sat || val >> shift == src) {
82 return val;
84 } else {
85 int32_t extval = sextract32(val, 0, bits);
86 if (!sat || val == extval) {
87 return extval;
90 } else if (!sat || src == 0) {
91 return 0;
94 *sat = 1;
95 return (1u << (bits - 1)) - (src >= 0);
98 static inline uint32_t do_uqrshl_bhs(uint32_t src, int32_t shift, int bits,
99 bool round, uint32_t *sat)
101 if (shift <= -(bits + round)) {
102 return 0;
103 } else if (shift < 0) {
104 if (round) {
105 src >>= -shift - 1;
106 return (src >> 1) + (src & 1);
108 return src >> -shift;
109 } else if (shift < bits) {
110 uint32_t val = src << shift;
111 if (bits == 32) {
112 if (!sat || val >> shift == src) {
113 return val;
115 } else {
116 uint32_t extval = extract32(val, 0, bits);
117 if (!sat || val == extval) {
118 return extval;
121 } else if (!sat || src == 0) {
122 return 0;
125 *sat = 1;
126 return MAKE_64BIT_MASK(0, bits);
129 static inline int32_t do_suqrshl_bhs(int32_t src, int32_t shift, int bits,
130 bool round, uint32_t *sat)
132 if (sat && src < 0) {
133 *sat = 1;
134 return 0;
136 return do_uqrshl_bhs(src, shift, bits, round, sat);
139 static inline int64_t do_sqrshl_d(int64_t src, int64_t shift,
140 bool round, uint32_t *sat)
142 if (shift <= -64) {
143 /* Rounding the sign bit always produces 0. */
144 if (round) {
145 return 0;
147 return src >> 63;
148 } else if (shift < 0) {
149 if (round) {
150 src >>= -shift - 1;
151 return (src >> 1) + (src & 1);
153 return src >> -shift;
154 } else if (shift < 64) {
155 int64_t val = src << shift;
156 if (!sat || val >> shift == src) {
157 return val;
159 } else if (!sat || src == 0) {
160 return 0;
163 *sat = 1;
164 return src < 0 ? INT64_MIN : INT64_MAX;
167 static inline uint64_t do_uqrshl_d(uint64_t src, int64_t shift,
168 bool round, uint32_t *sat)
170 if (shift <= -(64 + round)) {
171 return 0;
172 } else if (shift < 0) {
173 if (round) {
174 src >>= -shift - 1;
175 return (src >> 1) + (src & 1);
177 return src >> -shift;
178 } else if (shift < 64) {
179 uint64_t val = src << shift;
180 if (!sat || val >> shift == src) {
181 return val;
183 } else if (!sat || src == 0) {
184 return 0;
187 *sat = 1;
188 return UINT64_MAX;
191 static inline int64_t do_suqrshl_d(int64_t src, int64_t shift,
192 bool round, uint32_t *sat)
194 if (sat && src < 0) {
195 *sat = 1;
196 return 0;
198 return do_uqrshl_d(src, shift, round, sat);
201 int8_t do_sqrdmlah_b(int8_t, int8_t, int8_t, bool, bool);
202 int16_t do_sqrdmlah_h(int16_t, int16_t, int16_t, bool, bool, uint32_t *);
203 int32_t do_sqrdmlah_s(int32_t, int32_t, int32_t, bool, bool, uint32_t *);
204 int64_t do_sqrdmlah_d(int64_t, int64_t, int64_t, bool, bool);
206 #endif /* TARGET_ARM_VEC_INTERNALS_H */