target-arm/cpu-qom.h

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_ARM_CPU_QOM_H
  21 #define QEMU_ARM_CPU_QOM_H
  22
  23 #include "qom/cpu.h"
  24
  25 #define TYPE_ARM_CPU "arm-cpu"
  26
  27 #define ARM_CPU_CLASS(klass) \
  28     OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
  29 #define ARM_CPU(obj) \
  30     OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
  31 #define ARM_CPU_GET_CLASS(obj) \
  32     OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
  33
  34 /**
  35  * ARMCPUClass:
  36  * @parent_realize: The parent class' realize handler.
  37  * @parent_reset: The parent class' reset handler.
  38  *
  39  * An ARM CPU model.
  40  */
  41 typedef struct ARMCPUClass {
  42     /*< private >*/
  43     CPUClass parent_class;
  44     /*< public >*/
  45
  46     DeviceRealize parent_realize;
  47     void (*parent_reset)(CPUState *cpu);
  48 } ARMCPUClass;
  49
  50 /**
  51  * ARMCPU:
  52  * @env: #CPUARMState
  53  *
  54  * An ARM CPU core.
  55  */
  56 typedef struct ARMCPU {
  57     /*< private >*/
  58     CPUState parent_obj;
  59     /*< public >*/
  60
  61     CPUARMState env;
  62
  63     /* Coprocessor information */
  64     GHashTable *cp_regs;
  65     /* For marshalling (mostly coprocessor) register state between the
  66      * kernel and QEMU (for KVM) and between two QEMUs (for migration),
  67      * we use these arrays.
  68      */
  69     /* List of register indexes managed via these arrays; (full KVM style
  70      * 64 bit indexes, not CPRegInfo 32 bit indexes)
  71      */
  72     uint64_t *cpreg_indexes;
  73     /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
  74     uint64_t *cpreg_values;
  75     /* When using KVM, keeps a copy of the initial state of the VCPU,
  76      * so that on reset we can feed the reset values back into the kernel.
  77      */
  78     uint64_t *cpreg_reset_values;
  79     /* Length of the indexes, values, reset_values arrays */
  80     int32_t cpreg_array_len;
  81     /* These are used only for migration: incoming data arrives in
  82      * these fields and is sanity checked in post_load before copying
  83      * to the working data structures above.
  84      */
  85     uint64_t *cpreg_vmstate_indexes;
  86     uint64_t *cpreg_vmstate_values;
  87     int32_t cpreg_vmstate_array_len;
  88
  89     /* The instance init functions for implementation-specific subclasses
  90      * set these fields to specify the implementation-dependent values of
  91      * various constant registers and reset values of non-constant
  92      * registers.
  93      * Some of these might become QOM properties eventually.
  94      * Field names match the official register names as defined in the
  95      * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
  96      * is used for reset values of non-constant registers; no reset_
  97      * prefix means a constant register.
  98      */
  99     uint32_t midr;
 100     uint32_t reset_fpsid;
 101     uint32_t mvfr0;
 102     uint32_t mvfr1;
 103     uint32_t ctr;
 104     uint32_t reset_sctlr;
 105     uint32_t id_pfr0;
 106     uint32_t id_pfr1;
 107     uint32_t id_dfr0;
 108     uint32_t id_afr0;
 109     uint32_t id_mmfr0;
 110     uint32_t id_mmfr1;
 111     uint32_t id_mmfr2;
 112     uint32_t id_mmfr3;
 113     uint32_t id_isar0;
 114     uint32_t id_isar1;
 115     uint32_t id_isar2;
 116     uint32_t id_isar3;
 117     uint32_t id_isar4;
 118     uint32_t id_isar5;
 119     uint32_t clidr;
 120     /* The elements of this array are the CCSIDR values for each cache,
 121      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
 122      */
 123     uint32_t ccsidr[16];
 124     uint32_t reset_cbar;
 125     uint32_t reset_auxcr;
 126 } ARMCPU;
 127
 128 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
 129 {
 130     return container_of(env, ARMCPU, env);
 131 }
 132
 133 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
 134
 135 #define ENV_OFFSET offsetof(ARMCPU, env)
 136
 137 #ifndef CONFIG_USER_ONLY
 138 extern const struct VMStateDescription vmstate_arm_cpu;
 139 #endif
 140
 141 void register_cp_regs_for_features(ARMCPU *cpu);
 142 void init_cpreg_list(ARMCPU *cpu);
 143
 144 void arm_cpu_do_interrupt(CPUState *cpu);
 145 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
 146
 147 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
 148                         int flags);
 149
 150 #endif