2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/error-report.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "monitor/monitor.h"
17 #include "hw/ppc/fdt.h"
18 #include "hw/ppc/spapr.h"
19 #include "hw/ppc/spapr_xive.h"
20 #include "hw/ppc/xive.h"
21 #include "hw/ppc/xive_regs.h"
24 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
25 * use for the ESB pages and the TIMA pages
27 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
28 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
31 * The allocation of VP blocks is a complex operation in OPAL and the
32 * VP identifiers have a relation with the number of HW chips, the
33 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
34 * controller model does not have the same constraints and can use a
35 * simple mapping scheme of the CPU vcpu_id
37 * These identifiers are never returned to the OS.
40 #define SPAPR_XIVE_NVT_BASE 0x400
43 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value
44 * to the controller block id value. It can nevertheless be changed
45 * for testing purpose.
47 #define SPAPR_XIVE_BLOCK_ID 0x0
50 * sPAPR NVT and END indexing helpers
52 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
54 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
57 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
58 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
63 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
67 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
71 static int spapr_xive_target_to_nvt(uint32_t target
,
72 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
74 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
80 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
85 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
88 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
89 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
94 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
98 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
102 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
105 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
111 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
116 * On sPAPR machines, use a simplified output for the XIVE END
117 * structure dumping only the information related to the OS EQ.
119 static void spapr_xive_end_pic_print_info(sPAPRXive
*xive
, XiveEND
*end
,
122 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
123 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
124 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
125 uint32_t qentries
= 1 << (qsize
+ 10);
126 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
127 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
129 monitor_printf(mon
, "%3d/%d % 6d/%5d ^%d",
130 spapr_xive_nvt_to_target(0, nvt
),
131 priority
, qindex
, qentries
, qgen
);
133 xive_end_queue_pic_print_info(end
, 6, mon
);
134 monitor_printf(mon
, "]");
137 void spapr_xive_pic_print_info(sPAPRXive
*xive
, Monitor
*mon
)
139 XiveSource
*xsrc
= &xive
->source
;
142 monitor_printf(mon
, " LSIN PQ EISN CPU/PRIO EQ\n");
144 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
145 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
146 XiveEAS
*eas
= &xive
->eat
[i
];
148 if (!xive_eas_is_valid(eas
)) {
152 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
153 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
154 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
155 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
156 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
157 xive_eas_is_masked(eas
) ? "M" : " ",
158 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
160 if (!xive_eas_is_masked(eas
)) {
161 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
164 assert(end_idx
< xive
->nr_ends
);
165 end
= &xive
->endt
[end_idx
];
167 if (xive_end_is_valid(end
)) {
168 spapr_xive_end_pic_print_info(xive
, end
, mon
);
171 monitor_printf(mon
, "\n");
175 static void spapr_xive_map_mmio(sPAPRXive
*xive
)
177 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
178 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
179 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
182 static void spapr_xive_end_reset(XiveEND
*end
)
184 memset(end
, 0, sizeof(*end
));
186 /* switch off the escalation and notification ESBs */
187 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
190 static void spapr_xive_reset(void *dev
)
192 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
196 * The XiveSource has its own reset handler, which mask off all
200 /* Mask all valid EASs in the IRQ number space. */
201 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
202 XiveEAS
*eas
= &xive
->eat
[i
];
203 if (xive_eas_is_valid(eas
)) {
204 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
211 for (i
= 0; i
< xive
->nr_ends
; i
++) {
212 spapr_xive_end_reset(&xive
->endt
[i
]);
216 static void spapr_xive_instance_init(Object
*obj
)
218 sPAPRXive
*xive
= SPAPR_XIVE(obj
);
220 object_initialize(&xive
->source
, sizeof(xive
->source
), TYPE_XIVE_SOURCE
);
221 object_property_add_child(obj
, "source", OBJECT(&xive
->source
), NULL
);
223 object_initialize(&xive
->end_source
, sizeof(xive
->end_source
),
224 TYPE_XIVE_END_SOURCE
);
225 object_property_add_child(obj
, "end_source", OBJECT(&xive
->end_source
),
229 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
231 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
232 XiveSource
*xsrc
= &xive
->source
;
233 XiveENDSource
*end_xsrc
= &xive
->end_source
;
234 Error
*local_err
= NULL
;
236 if (!xive
->nr_irqs
) {
237 error_setg(errp
, "Number of interrupt needs to be greater 0");
241 if (!xive
->nr_ends
) {
242 error_setg(errp
, "Number of interrupt needs to be greater 0");
247 * Initialize the internal sources, for IPIs and virtual devices.
249 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
251 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
253 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
255 error_propagate(errp
, local_err
);
260 * Initialize the END ESB source
262 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
264 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
266 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
268 error_propagate(errp
, local_err
);
272 /* Set the mapping address of the END ESB pages after the source ESBs */
273 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
276 * Allocate the routing tables
278 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
279 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
281 /* TIMA initialization */
282 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
283 "xive.tima", 4ull << TM_SHIFT
);
285 /* Define all XIVE MMIO regions on SysBus */
286 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
287 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
288 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
290 /* Map all regions */
291 spapr_xive_map_mmio(xive
);
293 qemu_register_reset(spapr_xive_reset
, dev
);
296 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
297 uint32_t eas_idx
, XiveEAS
*eas
)
299 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
301 if (eas_idx
>= xive
->nr_irqs
) {
305 *eas
= xive
->eat
[eas_idx
];
309 static int spapr_xive_get_end(XiveRouter
*xrtr
,
310 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
312 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
314 if (end_idx
>= xive
->nr_ends
) {
318 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
322 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
323 uint32_t end_idx
, XiveEND
*end
,
326 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
328 if (end_idx
>= xive
->nr_ends
) {
332 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
336 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
337 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
339 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
340 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
343 /* TODO: should we assert() if we can find a NVT ? */
348 * sPAPR does not maintain a NVT table. Return that the NVT is
349 * valid if we have found a matching CPU
351 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
355 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
356 uint32_t nvt_idx
, XiveNVT
*nvt
,
360 * We don't need to write back to the NVTs because the sPAPR
361 * machine should never hit a non-scheduled NVT. It should never
364 g_assert_not_reached();
367 static const VMStateDescription vmstate_spapr_xive_end
= {
368 .name
= TYPE_SPAPR_XIVE
"/end",
370 .minimum_version_id
= 1,
371 .fields
= (VMStateField
[]) {
372 VMSTATE_UINT32(w0
, XiveEND
),
373 VMSTATE_UINT32(w1
, XiveEND
),
374 VMSTATE_UINT32(w2
, XiveEND
),
375 VMSTATE_UINT32(w3
, XiveEND
),
376 VMSTATE_UINT32(w4
, XiveEND
),
377 VMSTATE_UINT32(w5
, XiveEND
),
378 VMSTATE_UINT32(w6
, XiveEND
),
379 VMSTATE_UINT32(w7
, XiveEND
),
380 VMSTATE_END_OF_LIST()
384 static const VMStateDescription vmstate_spapr_xive_eas
= {
385 .name
= TYPE_SPAPR_XIVE
"/eas",
387 .minimum_version_id
= 1,
388 .fields
= (VMStateField
[]) {
389 VMSTATE_UINT64(w
, XiveEAS
),
390 VMSTATE_END_OF_LIST()
394 static const VMStateDescription vmstate_spapr_xive
= {
395 .name
= TYPE_SPAPR_XIVE
,
397 .minimum_version_id
= 1,
398 .fields
= (VMStateField
[]) {
399 VMSTATE_UINT32_EQUAL(nr_irqs
, sPAPRXive
, NULL
),
400 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, sPAPRXive
, nr_irqs
,
401 vmstate_spapr_xive_eas
, XiveEAS
),
402 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, sPAPRXive
, nr_ends
,
403 vmstate_spapr_xive_end
, XiveEND
),
404 VMSTATE_END_OF_LIST()
408 static Property spapr_xive_properties
[] = {
409 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive
, nr_irqs
, 0),
410 DEFINE_PROP_UINT32("nr-ends", sPAPRXive
, nr_ends
, 0),
411 DEFINE_PROP_UINT64("vc-base", sPAPRXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
412 DEFINE_PROP_UINT64("tm-base", sPAPRXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
413 DEFINE_PROP_END_OF_LIST(),
416 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
418 DeviceClass
*dc
= DEVICE_CLASS(klass
);
419 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
421 dc
->desc
= "sPAPR XIVE Interrupt Controller";
422 dc
->props
= spapr_xive_properties
;
423 dc
->realize
= spapr_xive_realize
;
424 dc
->vmsd
= &vmstate_spapr_xive
;
426 xrc
->get_eas
= spapr_xive_get_eas
;
427 xrc
->get_end
= spapr_xive_get_end
;
428 xrc
->write_end
= spapr_xive_write_end
;
429 xrc
->get_nvt
= spapr_xive_get_nvt
;
430 xrc
->write_nvt
= spapr_xive_write_nvt
;
433 static const TypeInfo spapr_xive_info
= {
434 .name
= TYPE_SPAPR_XIVE
,
435 .parent
= TYPE_XIVE_ROUTER
,
436 .instance_init
= spapr_xive_instance_init
,
437 .instance_size
= sizeof(sPAPRXive
),
438 .class_init
= spapr_xive_class_init
,
441 static void spapr_xive_register_types(void)
443 type_register_static(&spapr_xive_info
);
446 type_init(spapr_xive_register_types
)
448 bool spapr_xive_irq_claim(sPAPRXive
*xive
, uint32_t lisn
, bool lsi
)
450 XiveSource
*xsrc
= &xive
->source
;
452 if (lisn
>= xive
->nr_irqs
) {
456 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
457 xive_source_irq_set(xsrc
, lisn
, lsi
);
461 bool spapr_xive_irq_free(sPAPRXive
*xive
, uint32_t lisn
)
463 XiveSource
*xsrc
= &xive
->source
;
465 if (lisn
>= xive
->nr_irqs
) {
469 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
470 xive_source_irq_set(xsrc
, lisn
, false);
474 qemu_irq
spapr_xive_qirq(sPAPRXive
*xive
, uint32_t lisn
)
476 XiveSource
*xsrc
= &xive
->source
;
478 if (lisn
>= xive
->nr_irqs
) {
482 /* The sPAPR machine/device should have claimed the IRQ before */
483 assert(xive_eas_is_valid(&xive
->eat
[lisn
]));
485 return xive_source_qirq(xsrc
, lisn
);
491 * The terminology used by the XIVE hcalls is the following :
494 * EQ Event Queue assigned by OS to receive event data
495 * ESB page for source interrupt management
496 * LISN Logical Interrupt Source Number identifying a source in the
498 * EISN Effective Interrupt Source Number used by guest OS to
499 * identify source in the guest
501 * The EAS, END, NVT structures are not exposed.
505 * Linux hosts under OPAL reserve priority 7 for their own escalation
506 * interrupts (DD2.X POWER9). So we only allow the guest to use
509 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
514 case 7: /* OPAL escalation queue */
521 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
522 * real address of the MMIO page through which the Event State Buffer
523 * entry associated with the value of the "lisn" parameter is managed.
529 * - R5: "lisn" is per "interrupts", "interrupt-map", or
530 * "ibm,xive-lisn-ranges" properties, or as returned by the
531 * ibm,query-interrupt-source-number RTAS call, or as returned
532 * by the H_ALLOCATE_VAS_WINDOW hcall
536 * Bits 0-59: Reserved
537 * Bit 60: H_INT_ESB must be used for Event State Buffer
539 * Bit 61: 1 == LSI 0 == MSI
540 * Bit 62: the full function page supports trigger
541 * Bit 63: Store EOI Supported
542 * - R5: Logical Real address of full function Event State Buffer
543 * management page, -1 if H_INT_ESB hcall flag is set to 1.
544 * - R6: Logical Real Address of trigger only Event State Buffer
545 * management page or -1.
546 * - R7: Power of 2 page size for the ESB management pages returned in
550 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
551 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
552 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
554 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
556 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
557 sPAPRMachineState
*spapr
,
561 sPAPRXive
*xive
= spapr
->xive
;
562 XiveSource
*xsrc
= &xive
->source
;
563 target_ulong flags
= args
[0];
564 target_ulong lisn
= args
[1];
566 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
574 if (lisn
>= xive
->nr_irqs
) {
575 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
580 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
581 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
587 * All sources are emulated under the main XIVE object and share
588 * the same characteristics.
591 if (!xive_source_esb_has_2page(xsrc
)) {
592 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
594 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
595 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
599 * Force the use of the H_INT_ESB hcall in case of an LSI
600 * interrupt. This is necessary under KVM to re-trigger the
601 * interrupt if the level is still asserted
603 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
604 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
607 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
608 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
613 if (xive_source_esb_has_2page(xsrc
) &&
614 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
615 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
620 if (xive_source_esb_has_2page(xsrc
)) {
621 args
[3] = xsrc
->esb_shift
- 1;
623 args
[3] = xsrc
->esb_shift
;
630 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
631 * Interrupt Source to a target. The Logical Interrupt Source is
632 * designated with the "lisn" parameter and the target is designated
633 * with the "target" and "priority" parameters. Upon return from the
634 * hcall(), no additional interrupts will be directed to the old EQ.
639 * Bits 0-61: Reserved
640 * Bit 62: set the "eisn" in the EAS
641 * Bit 63: masks the interrupt source in the hardware interrupt
642 * control structure. An interrupt masked by this mechanism will
643 * be dropped, but it's source state bits will still be
644 * set. There is no race-free way of unmasking and restoring the
645 * source. Thus this should only be used in interrupts that are
646 * also masked at the source, and only in cases where the
647 * interrupt is not meant to be used for a large amount of time
648 * because no valid target exists for it for example
649 * - R5: "lisn" is per "interrupts", "interrupt-map", or
650 * "ibm,xive-lisn-ranges" properties, or as returned by the
651 * ibm,query-interrupt-source-number RTAS call, or as returned by
652 * the H_ALLOCATE_VAS_WINDOW hcall
653 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
654 * "ibm,ppc-interrupt-gserver#s"
655 * - R7: "priority" is a valid priority not in
656 * "ibm,plat-res-int-priorities"
657 * - R8: "eisn" is the guest EISN associated with the "lisn"
663 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
664 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
666 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
667 sPAPRMachineState
*spapr
,
671 sPAPRXive
*xive
= spapr
->xive
;
672 XiveEAS eas
, new_eas
;
673 target_ulong flags
= args
[0];
674 target_ulong lisn
= args
[1];
675 target_ulong target
= args
[2];
676 target_ulong priority
= args
[3];
677 target_ulong eisn
= args
[4];
681 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
685 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
689 if (lisn
>= xive
->nr_irqs
) {
690 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
695 eas
= xive
->eat
[lisn
];
696 if (!xive_eas_is_valid(&eas
)) {
697 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
702 /* priority 0xff is used to reset the EAS */
703 if (priority
== 0xff) {
704 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
708 if (flags
& SPAPR_XIVE_SRC_MASK
) {
709 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
711 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
714 if (spapr_xive_priority_is_reserved(priority
)) {
715 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
716 " is reserved\n", priority
);
721 * Validate that "target" is part of the list of threads allocated
722 * to the partition. For that, find the END corresponding to the
725 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
729 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
730 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
732 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
733 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
737 xive
->eat
[lisn
] = new_eas
;
742 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
743 * target/priority pair is assigned to the specified Logical Interrupt
750 * - R5: "lisn" is per "interrupts", "interrupt-map", or
751 * "ibm,xive-lisn-ranges" properties, or as returned by the
752 * ibm,query-interrupt-source-number RTAS call, or as
753 * returned by the H_ALLOCATE_VAS_WINDOW hcall
756 * - R4: Target to which the specified Logical Interrupt Source is
758 * - R5: Priority to which the specified Logical Interrupt Source is
760 * - R6: EISN for the specified Logical Interrupt Source (this will be
761 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
763 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
764 sPAPRMachineState
*spapr
,
768 sPAPRXive
*xive
= spapr
->xive
;
769 target_ulong flags
= args
[0];
770 target_ulong lisn
= args
[1];
774 uint32_t end_idx
, nvt_idx
;
776 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
784 if (lisn
>= xive
->nr_irqs
) {
785 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
790 eas
= xive
->eat
[lisn
];
791 if (!xive_eas_is_valid(&eas
)) {
792 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
797 /* EAS_END_BLOCK is unused on sPAPR */
798 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
800 assert(end_idx
< xive
->nr_ends
);
801 end
= &xive
->endt
[end_idx
];
803 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
804 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
805 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
807 if (xive_eas_is_masked(&eas
)) {
810 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
813 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
819 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
820 * address of the notification management page associated with the
821 * specified target and priority.
827 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
828 * "ibm,ppc-interrupt-gserver#s"
829 * - R6: "priority" is a valid priority not in
830 * "ibm,plat-res-int-priorities"
833 * - R4: Logical real address of notification page
834 * - R5: Power of 2 page size of the notification page
836 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
837 sPAPRMachineState
*spapr
,
841 sPAPRXive
*xive
= spapr
->xive
;
842 XiveENDSource
*end_xsrc
= &xive
->end_source
;
843 target_ulong flags
= args
[0];
844 target_ulong target
= args
[1];
845 target_ulong priority
= args
[2];
850 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
859 * H_STATE should be returned if a H_INT_RESET is in progress.
860 * This is not needed when running the emulation under QEMU
863 if (spapr_xive_priority_is_reserved(priority
)) {
864 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
865 " is reserved\n", priority
);
870 * Validate that "target" is part of the list of threads allocated
871 * to the partition. For that, find the END corresponding to the
874 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
878 assert(end_idx
< xive
->nr_ends
);
879 end
= &xive
->endt
[end_idx
];
881 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
882 if (xive_end_is_enqueue(end
)) {
883 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
892 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
893 * a given "target" and "priority". It is also used to set the
894 * notification config associated with the EQ. An EQ size of 0 is
895 * used to reset the EQ config for a given target and priority. If
896 * resetting the EQ config, the END associated with the given "target"
897 * and "priority" will be changed to disable queueing.
899 * Upon return from the hcall(), no additional interrupts will be
900 * directed to the old EQ (if one was set). The old EQ (if one was
901 * set) should be investigated for interrupts that occurred prior to
902 * or during the hcall().
907 * Bits 0-62: Reserved
908 * Bit 63: Unconditional Notify (n) per the XIVE spec
909 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
910 * "ibm,ppc-interrupt-gserver#s"
911 * - R6: "priority" is a valid priority not in
912 * "ibm,plat-res-int-priorities"
913 * - R7: "eventQueue": The logical real address of the start of the EQ
914 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
920 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
922 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
923 sPAPRMachineState
*spapr
,
927 sPAPRXive
*xive
= spapr
->xive
;
928 target_ulong flags
= args
[0];
929 target_ulong target
= args
[1];
930 target_ulong priority
= args
[2];
931 target_ulong qpage
= args
[3];
932 target_ulong qsize
= args
[4];
934 uint8_t end_blk
, nvt_blk
;
935 uint32_t end_idx
, nvt_idx
;
937 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
941 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
946 * H_STATE should be returned if a H_INT_RESET is in progress.
947 * This is not needed when running the emulation under QEMU
950 if (spapr_xive_priority_is_reserved(priority
)) {
951 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
952 " is reserved\n", priority
);
957 * Validate that "target" is part of the list of threads allocated
958 * to the partition. For that, find the END corresponding to the
962 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
966 assert(end_idx
< xive
->nr_ends
);
967 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
974 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
975 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
976 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
977 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
980 /* reset queue and disable queueing */
981 spapr_xive_end_reset(&end
);
985 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
991 hwaddr plen
= 1 << qsize
;
995 * Validate the guest EQ. We should also check that the queue
996 * has been zeroed by the OS.
998 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
999 MEMTXATTRS_UNSPECIFIED
);
1000 if (plen
!= 1 << qsize
) {
1001 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1002 HWADDR_PRIx
"\n", qpage
);
1005 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1008 /* "target" should have been validated above */
1009 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1010 g_assert_not_reached();
1014 * Ensure the priority and target are correctly set (they will not
1015 * be right after allocation)
1017 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1018 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1019 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1021 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1022 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1024 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1028 * The generation bit for the END starts at 1 and The END page
1029 * offset counter starts at 0.
1031 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1032 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1033 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1036 * TODO: issue syncs required to ensure all in-flight interrupts
1037 * are complete on the old END
1042 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1047 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1048 * target and priority.
1053 * Bits 0-62: Reserved
1054 * Bit 63: Debug: Return debug data
1055 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1056 * "ibm,ppc-interrupt-gserver#s"
1057 * - R6: "priority" is a valid priority not in
1058 * "ibm,plat-res-int-priorities"
1062 * Bits 0-61: Reserved
1063 * Bit 62: The value of Event Queue Generation Number (g) per
1064 * the XIVE spec if "Debug" = 1
1065 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1066 * - R5: The logical real address of the start of the EQ
1067 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1068 * - R7: The value of Event Queue Offset Counter per XIVE spec
1069 * if "Debug" = 1, else 0
1073 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1075 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1076 sPAPRMachineState
*spapr
,
1077 target_ulong opcode
,
1080 sPAPRXive
*xive
= spapr
->xive
;
1081 target_ulong flags
= args
[0];
1082 target_ulong target
= args
[1];
1083 target_ulong priority
= args
[2];
1088 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1092 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1097 * H_STATE should be returned if a H_INT_RESET is in progress.
1098 * This is not needed when running the emulation under QEMU
1101 if (spapr_xive_priority_is_reserved(priority
)) {
1102 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1103 " is reserved\n", priority
);
1108 * Validate that "target" is part of the list of threads allocated
1109 * to the partition. For that, find the END corresponding to the
1112 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1116 assert(end_idx
< xive
->nr_ends
);
1117 end
= &xive
->endt
[end_idx
];
1120 if (xive_end_is_notify(end
)) {
1121 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1124 if (xive_end_is_enqueue(end
)) {
1125 args
[1] = (uint64_t) be32_to_cpu(end
->w2
& 0x0fffffff) << 32
1126 | be32_to_cpu(end
->w3
);
1127 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1133 /* TODO: do we need any locking on the END ? */
1134 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1135 /* Load the event queue generation number into the return flags */
1136 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1138 /* Load R7 with the event queue offset counter */
1139 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1148 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1149 * reporting cache line pair for the calling thread. The reporting
1150 * cache lines will contain the OS interrupt context when the OS
1151 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1152 * interrupt. The reporting cache lines can be reset by inputting -1
1153 * in "reportingLine". Issuing the CI store byte without reporting
1154 * cache lines registered will result in the data not being accessible
1160 * Bits 0-63: Reserved
1161 * - R5: "reportingLine": The logical real address of the reporting cache
1167 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1168 sPAPRMachineState
*spapr
,
1169 target_ulong opcode
,
1172 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1177 * H_STATE should be returned if a H_INT_RESET is in progress.
1178 * This is not needed when running the emulation under QEMU
1181 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1186 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1187 * real address of the reporting cache line pair set for the input
1188 * "target". If no reporting cache line pair has been set, -1 is
1194 * Bits 0-63: Reserved
1195 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1196 * "ibm,ppc-interrupt-gserver#s"
1197 * - R6: "reportingLine": The logical real address of the reporting
1201 * - R4: The logical real address of the reporting line if set, else -1
1203 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1204 sPAPRMachineState
*spapr
,
1205 target_ulong opcode
,
1208 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1213 * H_STATE should be returned if a H_INT_RESET is in progress.
1214 * This is not needed when running the emulation under QEMU
1217 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1222 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1223 * page for the input "lisn". This hcall is only supported for LISNs
1224 * that have the ESB hcall flag set to 1 when returned from hcall()
1225 * H_INT_GET_SOURCE_INFO.
1230 * Bits 0-62: Reserved
1231 * bit 63: Store: Store=1, store operation, else load operation
1232 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1233 * "ibm,xive-lisn-ranges" properties, or as returned by the
1234 * ibm,query-interrupt-source-number RTAS call, or as
1235 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1236 * - R6: "esbOffset" is the offset into the ESB page for the load or
1238 * - R7: "storeData" is the data to write for a store operation
1241 * - R4: The value of the load if load operation, else -1
1244 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1246 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1247 sPAPRMachineState
*spapr
,
1248 target_ulong opcode
,
1251 sPAPRXive
*xive
= spapr
->xive
;
1253 target_ulong flags
= args
[0];
1254 target_ulong lisn
= args
[1];
1255 target_ulong offset
= args
[2];
1256 target_ulong data
= args
[3];
1258 XiveSource
*xsrc
= &xive
->source
;
1260 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1264 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1268 if (lisn
>= xive
->nr_irqs
) {
1269 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1274 eas
= xive
->eat
[lisn
];
1275 if (!xive_eas_is_valid(&eas
)) {
1276 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1281 if (offset
> (1ull << xsrc
->esb_shift
)) {
1285 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1287 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1288 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1289 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1290 HWADDR_PRIx
"\n", mmio_addr
);
1293 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1298 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1299 * ensure any in flight events for the input lisn are in the event
1305 * Bits 0-63: Reserved
1306 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1307 * "ibm,xive-lisn-ranges" properties, or as returned by the
1308 * ibm,query-interrupt-source-number RTAS call, or as
1309 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1314 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1315 sPAPRMachineState
*spapr
,
1316 target_ulong opcode
,
1319 sPAPRXive
*xive
= spapr
->xive
;
1321 target_ulong flags
= args
[0];
1322 target_ulong lisn
= args
[1];
1324 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1332 if (lisn
>= xive
->nr_irqs
) {
1333 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1338 eas
= xive
->eat
[lisn
];
1339 if (!xive_eas_is_valid(&eas
)) {
1340 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1346 * H_STATE should be returned if a H_INT_RESET is in progress.
1347 * This is not needed when running the emulation under QEMU
1350 /* This is not real hardware. Nothing to be done */
1355 * The H_INT_RESET hcall() is used to reset all of the partition's
1356 * interrupt exploitation structures to their initial state. This
1357 * means losing all previously set interrupt state set via
1358 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1363 * Bits 0-63: Reserved
1368 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1369 sPAPRMachineState
*spapr
,
1370 target_ulong opcode
,
1373 sPAPRXive
*xive
= spapr
->xive
;
1374 target_ulong flags
= args
[0];
1376 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1384 device_reset(DEVICE(xive
));
1388 void spapr_xive_hcall_init(sPAPRMachineState
*spapr
)
1390 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1391 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1392 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1393 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1394 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1395 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1396 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1397 h_int_set_os_reporting_line
);
1398 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1399 h_int_get_os_reporting_line
);
1400 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1401 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1402 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1405 void spapr_dt_xive(sPAPRMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1408 sPAPRXive
*xive
= spapr
->xive
;
1410 uint64_t timas
[2 * 2];
1411 /* Interrupt number ranges for the IPIs */
1412 uint32_t lisn_ranges
[] = {
1414 cpu_to_be32(nr_servers
),
1417 * EQ size - the sizes of pages supported by the system 4K, 64K,
1418 * 2M, 16M. We only advertise 64K for the moment.
1420 uint32_t eq_sizes
[] = {
1421 cpu_to_be32(16), /* 64K */
1424 * The following array is in sync with the reserved priorities
1425 * defined by the 'spapr_xive_priority_is_reserved' routine.
1427 uint32_t plat_res_int_priorities
[] = {
1428 cpu_to_be32(7), /* start */
1429 cpu_to_be32(0xf8), /* count */
1433 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1434 timas
[0] = cpu_to_be64(xive
->tm_base
+
1435 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1436 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1437 timas
[2] = cpu_to_be64(xive
->tm_base
+
1438 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1439 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1441 nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
1442 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
1443 _FDT(node
= fdt_add_subnode(fdt
, 0, nodename
));
1446 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1447 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1449 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1450 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1452 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1453 sizeof(lisn_ranges
)));
1455 /* For Linux to link the LSIs to the interrupt controller. */
1456 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1457 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1460 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1461 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1464 * The "ibm,plat-res-int-priorities" property defines the priority
1465 * ranges reserved by the hypervisor
1467 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1468 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));