2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
30 # define TARGET_LONG_BITS 32
33 /* ARM processors have a weak memory model */
34 #define TCG_GUEST_DEFAULT_MO (0)
36 #define CPUArchState struct CPUARMState
38 #include "qemu-common.h"
40 #include "exec/cpu-defs.h"
42 #include "fpu/softfloat.h"
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
53 #define EXCP_HVC 11 /* HyperVisor Call */
54 #define EXCP_HYP_TRAP 12
55 #define EXCP_SMC 13 /* Secure Monitor Call */
58 #define EXCP_SEMIHOST 16 /* semihosting call */
59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
63 #define ARMV7M_EXCP_RESET 1
64 #define ARMV7M_EXCP_NMI 2
65 #define ARMV7M_EXCP_HARD 3
66 #define ARMV7M_EXCP_MEM 4
67 #define ARMV7M_EXCP_BUS 5
68 #define ARMV7M_EXCP_USAGE 6
69 #define ARMV7M_EXCP_SECURE 7
70 #define ARMV7M_EXCP_SVC 11
71 #define ARMV7M_EXCP_DEBUG 12
72 #define ARMV7M_EXCP_PENDSV 14
73 #define ARMV7M_EXCP_SYSTICK 15
75 /* For M profile, some registers are banked secure vs non-secure;
76 * these are represented as a 2-element array where the first element
77 * is the non-secure copy and the second is the secure copy.
78 * When the CPU does not have implement the security extension then
79 * only the first element is used.
80 * This means that the copy for the current security state can be
81 * accessed via env->registerfield[env->v7m.secure] (whether the security
82 * extension is implemented or not).
87 /* ARM-specific interrupt pending bits. */
88 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
89 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
90 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
92 /* The usual mapping for an AArch64 system register to its AArch32
93 * counterpart is for the 32 bit world to have access to the lower
94 * half only (with writes leaving the upper half untouched). It's
95 * therefore useful to be able to pass TCG the offset of the least
96 * significant half of a uint64_t struct member.
98 #ifdef HOST_WORDS_BIGENDIAN
99 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
100 #define offsetofhigh32(S, M) offsetof(S, M)
102 #define offsetoflow32(S, M) offsetof(S, M)
103 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
106 /* Meanings of the ARMCPU object's four inbound GPIO lines */
107 #define ARM_CPU_IRQ 0
108 #define ARM_CPU_FIQ 1
109 #define ARM_CPU_VIRQ 2
110 #define ARM_CPU_VFIQ 3
112 #define NB_MMU_MODES 7
113 /* ARM-specific extra insn start words:
114 * 1: Conditional execution bits
115 * 2: Partial exception syndrome for data aborts
117 #define TARGET_INSN_START_EXTRA_WORDS 2
119 /* The 2nd extra word holding syndrome info for data aborts does not use
120 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
121 * help the sleb128 encoder do a better job.
122 * When restoring the CPU state, we shift it back up.
124 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
125 #define ARM_INSN_START_WORD2_SHIFT 14
127 /* We currently assume float and double are IEEE single and double
128 precision respectively.
129 Doing runtime conversions is tricky because VFP registers may contain
130 integer values (eg. as the result of a FTOSI instruction).
131 s<2n> maps to the least significant half of d<n>
132 s<2n+1> maps to the most significant half of d<n>
135 /* CPU state for each instance of a generic timer (in cp15 c14) */
136 typedef struct ARMGenericTimer
{
137 uint64_t cval
; /* Timer CompareValue register */
138 uint64_t ctl
; /* Timer Control register */
141 #define GTIMER_PHYS 0
142 #define GTIMER_VIRT 1
145 #define NUM_GTIMERS 4
153 typedef struct CPUARMState
{
154 /* Regs for current mode. */
157 /* 32/64 switch only happens when taking and returning from
158 * exceptions so the overlap semantics are taken care of then
159 * instead of having a complicated union.
161 /* Regs for A64 mode. */
164 /* PSTATE isn't an architectural register for ARMv8. However, it is
165 * convenient for us to assemble the underlying state into a 32 bit format
166 * identical to the architectural format used for the SPSR. (This is also
167 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
168 * 'pstate' register are.) Of the PSTATE bits:
169 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
170 * semantics as for AArch32, as described in the comments on each field)
171 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
172 * DAIF (exception masks) are kept in env->daif
173 * all other bits are stored in their correct places in env->pstate
176 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
178 /* Frequently accessed CPSR bits are stored separately for efficiency.
179 This contains all the other bits. Use cpsr_{read,write} to access
181 uint32_t uncached_cpsr
;
184 /* Banked registers. */
185 uint64_t banked_spsr
[8];
186 uint32_t banked_r13
[8];
187 uint32_t banked_r14
[8];
189 /* These hold r8-r12. */
190 uint32_t usr_regs
[5];
191 uint32_t fiq_regs
[5];
193 /* cpsr flag cache for faster execution */
194 uint32_t CF
; /* 0 or 1 */
195 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
196 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
197 uint32_t ZF
; /* Z set if zero. */
198 uint32_t QF
; /* 0 or 1 */
199 uint32_t GE
; /* cpsr[19:16] */
200 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
201 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
202 uint64_t daif
; /* exception masks, in the bits they are in PSTATE */
204 uint64_t elr_el
[4]; /* AArch64 exception link regs */
205 uint64_t sp_el
[4]; /* AArch64 banked stack pointers */
207 /* System control coprocessor (cp15) */
210 union { /* Cache size selection */
212 uint64_t _unused_csselr0
;
214 uint64_t _unused_csselr1
;
217 uint64_t csselr_el
[4];
219 union { /* System control register. */
221 uint64_t _unused_sctlr
;
226 uint64_t sctlr_el
[4];
228 uint64_t cpacr_el1
; /* Architectural feature access control register */
229 uint64_t cptr_el
[4]; /* ARMv8 feature trap registers */
230 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
231 uint64_t sder
; /* Secure debug enable register. */
232 uint32_t nsacr
; /* Non-secure access control register. */
233 union { /* MMU translation table base 0. */
235 uint64_t _unused_ttbr0_0
;
237 uint64_t _unused_ttbr0_1
;
240 uint64_t ttbr0_el
[4];
242 union { /* MMU translation table base 1. */
244 uint64_t _unused_ttbr1_0
;
246 uint64_t _unused_ttbr1_1
;
249 uint64_t ttbr1_el
[4];
251 uint64_t vttbr_el2
; /* Virtualization Translation Table Base. */
252 /* MMU translation table base control. */
254 TCR vtcr_el2
; /* Virtualization Translation Control. */
255 uint32_t c2_data
; /* MPU data cacheable bits. */
256 uint32_t c2_insn
; /* MPU instruction cacheable bits. */
257 union { /* MMU domain access control register
258 * MPU write buffer control.
268 uint32_t pmsav5_data_ap
; /* PMSAv5 MPU data access permissions */
269 uint32_t pmsav5_insn_ap
; /* PMSAv5 MPU insn access permissions */
270 uint64_t hcr_el2
; /* Hypervisor configuration register */
271 uint64_t scr_el3
; /* Secure configuration register. */
272 union { /* Fault status registers. */
283 uint64_t _unused_dfsr
;
290 uint32_t c6_region
[8]; /* MPU base/size registers. */
291 union { /* Fault address registers. */
293 uint64_t _unused_far0
;
294 #ifdef HOST_WORDS_BIGENDIAN
305 uint64_t _unused_far3
;
311 union { /* Translation result. */
313 uint64_t _unused_par_0
;
315 uint64_t _unused_par_1
;
321 uint32_t c9_insn
; /* Cache lockdown registers. */
323 uint64_t c9_pmcr
; /* performance monitor control register */
324 uint64_t c9_pmcnten
; /* perf monitor counter enables */
325 uint32_t c9_pmovsr
; /* perf monitor overflow status */
326 uint32_t c9_pmuserenr
; /* perf monitor user enable */
327 uint64_t c9_pmselr
; /* perf monitor counter selection register */
328 uint64_t c9_pminten
; /* perf monitor interrupt enables */
329 union { /* Memory attribute redirection */
331 #ifdef HOST_WORDS_BIGENDIAN
332 uint64_t _unused_mair_0
;
335 uint64_t _unused_mair_1
;
339 uint64_t _unused_mair_0
;
342 uint64_t _unused_mair_1
;
349 union { /* vector base address register */
351 uint64_t _unused_vbar
;
358 uint32_t mvbar
; /* (monitor) vector base address register */
359 struct { /* FCSE PID. */
363 union { /* Context ID. */
365 uint64_t _unused_contextidr_0
;
366 uint64_t contextidr_ns
;
367 uint64_t _unused_contextidr_1
;
368 uint64_t contextidr_s
;
370 uint64_t contextidr_el
[4];
372 union { /* User RW Thread register. */
374 uint64_t tpidrurw_ns
;
375 uint64_t tpidrprw_ns
;
379 uint64_t tpidr_el
[4];
381 /* The secure banks of these registers don't map anywhere */
386 union { /* User RO Thread register. */
387 uint64_t tpidruro_ns
;
388 uint64_t tpidrro_el
[1];
390 uint64_t c14_cntfrq
; /* Counter Frequency register */
391 uint64_t c14_cntkctl
; /* Timer Control register */
392 uint32_t cnthctl_el2
; /* Counter/Timer Hyp Control register */
393 uint64_t cntvoff_el2
; /* Counter Virtual Offset register */
394 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
395 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
396 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
397 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
398 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
399 uint32_t c15_threadid
; /* TI debugger thread-ID. */
400 uint32_t c15_config_base_address
; /* SCU base address. */
401 uint32_t c15_diagnostic
; /* diagnostic register */
402 uint32_t c15_power_diagnostic
;
403 uint32_t c15_power_control
; /* power control */
404 uint64_t dbgbvr
[16]; /* breakpoint value registers */
405 uint64_t dbgbcr
[16]; /* breakpoint control registers */
406 uint64_t dbgwvr
[16]; /* watchpoint value registers */
407 uint64_t dbgwcr
[16]; /* watchpoint control registers */
409 uint64_t oslsr_el1
; /* OS Lock Status */
412 /* If the counter is enabled, this stores the last time the counter
413 * was reset. Otherwise it stores the counter value
416 uint64_t pmccfiltr_el0
; /* Performance Monitor Filter Register */
417 uint64_t vpidr_el2
; /* Virtualization Processor ID Register */
418 uint64_t vmpidr_el2
; /* Virtualization Multiprocessor ID Register */
422 /* M profile has up to 4 stack pointers:
423 * a Main Stack Pointer and a Process Stack Pointer for each
424 * of the Secure and Non-Secure states. (If the CPU doesn't support
425 * the security extension then it has only two SPs.)
426 * In QEMU we always store the currently active SP in regs[13],
427 * and the non-active SP for the current security state in
428 * v7m.other_sp. The stack pointers for the inactive security state
429 * are stored in other_ss_msp and other_ss_psp.
430 * switch_v7m_security_state() is responsible for rearranging them
431 * when we change security state.
434 uint32_t other_ss_msp
;
435 uint32_t other_ss_psp
;
439 uint32_t ccr
[2]; /* Configuration and Control */
440 uint32_t cfsr
[2]; /* Configurable Fault Status */
441 uint32_t hfsr
; /* HardFault Status */
442 uint32_t dfsr
; /* Debug Fault Status Register */
443 uint32_t mmfar
[2]; /* MemManage Fault Address */
444 uint32_t bfar
; /* BusFault Address */
445 unsigned mpu_ctrl
[2]; /* MPU_CTRL */
448 uint32_t faultmask
[2];
449 uint32_t secure
; /* Is CPU in Secure state? (not guest visible) */
452 /* Information associated with an exception about to be taken:
453 * code which raises an exception must set cs->exception_index and
454 * the relevant parts of this structure; the cpu_do_interrupt function
455 * will then set the guest-visible registers as part of the exception
459 uint32_t syndrome
; /* AArch64 format syndrome register */
460 uint32_t fsr
; /* AArch32 format fault status register info */
461 uint64_t vaddress
; /* virtual addr associated with exception, if any */
462 uint32_t target_el
; /* EL the exception should be targeted for */
463 /* If we implement EL2 we will also need to store information
464 * about the intermediate physical address for stage 2 faults.
468 /* Thumb-2 EE state. */
472 /* VFP coprocessor state. */
474 /* VFP/Neon register state. Note that the mapping between S, D and Q
475 * views of the register bank differs between AArch64 and AArch32:
477 * Qn = regs[2n+1]:regs[2n]
479 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
480 * (and regs[32] to regs[63] are inaccessible)
482 * Qn = regs[2n+1]:regs[2n]
484 * Sn = regs[2n] bits 31..0
485 * This corresponds to the architecturally defined mapping between
486 * the two execution states, and means we do not need to explicitly
487 * map these registers when changing states.
492 /* We store these fpcsr fields separately for convenience. */
496 /* scratch space when Tn are not sufficient. */
499 /* fp_status is the "normal" fp status. standard_fp_status retains
500 * values corresponding to the ARM "Standard FPSCR Value", ie
501 * default-NaN, flush-to-zero, round-to-nearest and is used by
502 * any operations (generally Neon) which the architecture defines
503 * as controlled by the standard FPSCR value rather than the FPSCR.
505 * To avoid having to transfer exception bits around, we simply
506 * say that the FPSCR cumulative exception flags are the logical
507 * OR of the flags in the two fp statuses. This relies on the
508 * only thing which needs to read the exception flags being
509 * an explicit FPSCR read.
511 float_status fp_status
;
512 float_status standard_fp_status
;
514 uint64_t exclusive_addr
;
515 uint64_t exclusive_val
;
516 uint64_t exclusive_high
;
518 /* iwMMXt coprocessor state. */
526 #if defined(CONFIG_USER_ONLY)
527 /* For usermode syscall translation. */
531 struct CPUBreakpoint
*cpu_breakpoint
[16];
532 struct CPUWatchpoint
*cpu_watchpoint
[16];
534 /* Fields up to this point are cleared by a CPU reset */
535 struct {} end_reset_fields
;
539 /* Fields after CPU_COMMON are preserved across CPU reset. */
541 /* Internal CPU feature flags. */
554 /* The PMSAv8 implementation also shares some PMSAv7 config
556 * pmsav7.rnr (region number register)
557 * pmsav7_dregion (number of configured regions)
566 const struct arm_boot_info
*boot_info
;
567 /* Store GICv3CPUState to access from this struct */
573 * type of a function which can be registered via arm_register_el_change_hook()
574 * to get callbacks when the CPU changes its exception level or mode.
576 typedef void ARMELChangeHook(ARMCPU
*cpu
, void *opaque
);
579 /* These values map onto the return values for
580 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
581 typedef enum ARMPSCIState
{
600 /* Coprocessor information */
602 /* For marshalling (mostly coprocessor) register state between the
603 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
604 * we use these arrays.
606 /* List of register indexes managed via these arrays; (full KVM style
607 * 64 bit indexes, not CPRegInfo 32 bit indexes)
609 uint64_t *cpreg_indexes
;
610 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
611 uint64_t *cpreg_values
;
612 /* Length of the indexes, values, reset_values arrays */
613 int32_t cpreg_array_len
;
614 /* These are used only for migration: incoming data arrives in
615 * these fields and is sanity checked in post_load before copying
616 * to the working data structures above.
618 uint64_t *cpreg_vmstate_indexes
;
619 uint64_t *cpreg_vmstate_values
;
620 int32_t cpreg_vmstate_array_len
;
622 /* Timers used by the generic (architected) timer */
623 QEMUTimer
*gt_timer
[NUM_GTIMERS
];
624 /* GPIO outputs for generic timer */
625 qemu_irq gt_timer_outputs
[NUM_GTIMERS
];
626 /* GPIO output for GICv3 maintenance interrupt signal */
627 qemu_irq gicv3_maintenance_interrupt
;
628 /* GPIO output for the PMU interrupt */
629 qemu_irq pmu_interrupt
;
631 /* MemoryRegion to use for secure physical accesses */
632 MemoryRegion
*secure_memory
;
634 /* 'compatible' string for this CPU for Linux device trees */
635 const char *dtb_compatible
;
637 /* PSCI version for this CPU
638 * Bits[31:16] = Major Version
639 * Bits[15:0] = Minor Version
641 uint32_t psci_version
;
643 /* Should CPU start in PSCI powered-off state? */
644 bool start_powered_off
;
646 /* Current power state, access guarded by BQL */
647 ARMPSCIState power_state
;
649 /* CPU has virtualization extension */
651 /* CPU has security extension */
653 /* CPU has PMU (Performance Monitor Unit) */
656 /* CPU has memory protection unit */
658 /* PMSAv7 MPU number of supported regions */
659 uint32_t pmsav7_dregion
;
661 /* PSCI conduit used to invoke PSCI methods
662 * 0 - disabled, 1 - smc, 2 - hvc
664 uint32_t psci_conduit
;
666 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
667 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
671 /* KVM init features for this CPU */
672 uint32_t kvm_init_features
[7];
674 /* Uniprocessor system with MP extensions */
677 /* The instance init functions for implementation-specific subclasses
678 * set these fields to specify the implementation-dependent values of
679 * various constant registers and reset values of non-constant
681 * Some of these might become QOM properties eventually.
682 * Field names match the official register names as defined in the
683 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
684 * is used for reset values of non-constant registers; no reset_
685 * prefix means a constant register.
689 uint32_t reset_fpsid
;
694 uint32_t reset_sctlr
;
712 uint64_t id_aa64pfr0
;
713 uint64_t id_aa64pfr1
;
714 uint64_t id_aa64dfr0
;
715 uint64_t id_aa64dfr1
;
716 uint64_t id_aa64afr0
;
717 uint64_t id_aa64afr1
;
718 uint64_t id_aa64isar0
;
719 uint64_t id_aa64isar1
;
720 uint64_t id_aa64mmfr0
;
721 uint64_t id_aa64mmfr1
;
724 uint64_t mp_affinity
; /* MP ID without feature bits */
725 /* The elements of this array are the CCSIDR values for each cache,
726 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
730 uint32_t reset_auxcr
;
732 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
733 uint32_t dcz_blocksize
;
736 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
737 int gic_num_lrs
; /* number of list registers */
738 int gic_vpribits
; /* number of virtual priority bits */
739 int gic_vprebits
; /* number of virtual preemption bits */
741 /* Whether the cfgend input is high (i.e. this CPU should reset into
742 * big-endian mode). This setting isn't used directly: instead it modifies
743 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
744 * architecture version.
748 ARMELChangeHook
*el_change_hook
;
749 void *el_change_hook_opaque
;
751 int32_t node_id
; /* NUMA node this CPU belongs to */
753 /* Used to synchronize KVM and QEMU in-kernel device levels */
754 uint8_t device_irq_level
;
757 static inline ARMCPU
*arm_env_get_cpu(CPUARMState
*env
)
759 return container_of(env
, ARMCPU
, env
);
762 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
);
764 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
766 #define ENV_OFFSET offsetof(ARMCPU, env)
768 #ifndef CONFIG_USER_ONLY
769 extern const struct VMStateDescription vmstate_arm_cpu
;
772 void arm_cpu_do_interrupt(CPUState
*cpu
);
773 void arm_v7m_cpu_do_interrupt(CPUState
*cpu
);
774 bool arm_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
776 void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
779 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
782 int arm_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
783 int arm_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
785 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cs
,
786 int cpuid
, void *opaque
);
787 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cs
,
788 int cpuid
, void *opaque
);
790 #ifdef TARGET_AARCH64
791 int aarch64_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
792 int aarch64_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
795 target_ulong
do_arm_semihosting(CPUARMState
*env
);
796 void aarch64_sync_32_to_64(CPUARMState
*env
);
797 void aarch64_sync_64_to_32(CPUARMState
*env
);
799 static inline bool is_a64(CPUARMState
*env
)
804 /* you can call this signal handler from your SIGBUS and SIGSEGV
805 signal handlers to inform the virtual CPU of exceptions. non zero
806 is returned if the signal was handled by the virtual CPU. */
807 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
814 * Synchronises the counter in the PMCCNTR. This must always be called twice,
815 * once before any action that might affect the timer and again afterwards.
816 * The function is used to swap the state of the register if required.
817 * This only happens when not in user mode (!CONFIG_USER_ONLY)
819 void pmccntr_sync(CPUARMState
*env
);
821 /* SCTLR bit meanings. Several bits have been reused in newer
822 * versions of the architecture; in that case we define constants
823 * for both old and new bit meanings. Code which tests against those
824 * bits should probably check or otherwise arrange that the CPU
825 * is the architectural version it expects.
827 #define SCTLR_M (1U << 0)
828 #define SCTLR_A (1U << 1)
829 #define SCTLR_C (1U << 2)
830 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
831 #define SCTLR_SA (1U << 3)
832 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
833 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
834 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
835 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
836 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
837 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
838 #define SCTLR_ITD (1U << 7) /* v8 onward */
839 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
840 #define SCTLR_SED (1U << 8) /* v8 onward */
841 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
842 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
843 #define SCTLR_F (1U << 10) /* up to v6 */
844 #define SCTLR_SW (1U << 10) /* v7 onward */
845 #define SCTLR_Z (1U << 11)
846 #define SCTLR_I (1U << 12)
847 #define SCTLR_V (1U << 13)
848 #define SCTLR_RR (1U << 14) /* up to v7 */
849 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
850 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
851 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
852 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
853 #define SCTLR_nTWI (1U << 16) /* v8 onward */
854 #define SCTLR_HA (1U << 17)
855 #define SCTLR_BR (1U << 17) /* PMSA only */
856 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
857 #define SCTLR_nTWE (1U << 18) /* v8 onward */
858 #define SCTLR_WXN (1U << 19)
859 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
860 #define SCTLR_UWXN (1U << 20) /* v7 onward */
861 #define SCTLR_FI (1U << 21)
862 #define SCTLR_U (1U << 22)
863 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
864 #define SCTLR_VE (1U << 24) /* up to v7 */
865 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
866 #define SCTLR_EE (1U << 25)
867 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
868 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
869 #define SCTLR_NMFI (1U << 27)
870 #define SCTLR_TRE (1U << 28)
871 #define SCTLR_AFE (1U << 29)
872 #define SCTLR_TE (1U << 30)
874 #define CPTR_TCPAC (1U << 31)
875 #define CPTR_TTA (1U << 20)
876 #define CPTR_TFP (1U << 10)
878 #define MDCR_EPMAD (1U << 21)
879 #define MDCR_EDAD (1U << 20)
880 #define MDCR_SPME (1U << 17)
881 #define MDCR_SDD (1U << 16)
882 #define MDCR_SPD (3U << 14)
883 #define MDCR_TDRA (1U << 11)
884 #define MDCR_TDOSA (1U << 10)
885 #define MDCR_TDA (1U << 9)
886 #define MDCR_TDE (1U << 8)
887 #define MDCR_HPME (1U << 7)
888 #define MDCR_TPM (1U << 6)
889 #define MDCR_TPMCR (1U << 5)
891 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
892 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
894 #define CPSR_M (0x1fU)
895 #define CPSR_T (1U << 5)
896 #define CPSR_F (1U << 6)
897 #define CPSR_I (1U << 7)
898 #define CPSR_A (1U << 8)
899 #define CPSR_E (1U << 9)
900 #define CPSR_IT_2_7 (0xfc00U)
901 #define CPSR_GE (0xfU << 16)
902 #define CPSR_IL (1U << 20)
903 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
904 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
905 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
906 * where it is live state but not accessible to the AArch32 code.
908 #define CPSR_RESERVED (0x7U << 21)
909 #define CPSR_J (1U << 24)
910 #define CPSR_IT_0_1 (3U << 25)
911 #define CPSR_Q (1U << 27)
912 #define CPSR_V (1U << 28)
913 #define CPSR_C (1U << 29)
914 #define CPSR_Z (1U << 30)
915 #define CPSR_N (1U << 31)
916 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
917 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
919 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
920 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
922 /* Bits writable in user mode. */
923 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
924 /* Execution state bits. MRS read as zero, MSR writes ignored. */
925 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
926 /* Mask of bits which may be set by exception return copying them from SPSR */
927 #define CPSR_ERET_MASK (~CPSR_RESERVED)
929 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
930 #define XPSR_EXCP 0x1ffU
931 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
932 #define XPSR_IT_2_7 CPSR_IT_2_7
933 #define XPSR_GE CPSR_GE
934 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
935 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
936 #define XPSR_IT_0_1 CPSR_IT_0_1
937 #define XPSR_Q CPSR_Q
938 #define XPSR_V CPSR_V
939 #define XPSR_C CPSR_C
940 #define XPSR_Z CPSR_Z
941 #define XPSR_N CPSR_N
942 #define XPSR_NZCV CPSR_NZCV
943 #define XPSR_IT CPSR_IT
945 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
946 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
947 #define TTBCR_PD0 (1U << 4)
948 #define TTBCR_PD1 (1U << 5)
949 #define TTBCR_EPD0 (1U << 7)
950 #define TTBCR_IRGN0 (3U << 8)
951 #define TTBCR_ORGN0 (3U << 10)
952 #define TTBCR_SH0 (3U << 12)
953 #define TTBCR_T1SZ (3U << 16)
954 #define TTBCR_A1 (1U << 22)
955 #define TTBCR_EPD1 (1U << 23)
956 #define TTBCR_IRGN1 (3U << 24)
957 #define TTBCR_ORGN1 (3U << 26)
958 #define TTBCR_SH1 (1U << 28)
959 #define TTBCR_EAE (1U << 31)
961 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
962 * Only these are valid when in AArch64 mode; in
963 * AArch32 mode SPSRs are basically CPSR-format.
965 #define PSTATE_SP (1U)
966 #define PSTATE_M (0xFU)
967 #define PSTATE_nRW (1U << 4)
968 #define PSTATE_F (1U << 6)
969 #define PSTATE_I (1U << 7)
970 #define PSTATE_A (1U << 8)
971 #define PSTATE_D (1U << 9)
972 #define PSTATE_IL (1U << 20)
973 #define PSTATE_SS (1U << 21)
974 #define PSTATE_V (1U << 28)
975 #define PSTATE_C (1U << 29)
976 #define PSTATE_Z (1U << 30)
977 #define PSTATE_N (1U << 31)
978 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
979 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
980 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
981 /* Mode values for AArch64 */
982 #define PSTATE_MODE_EL3h 13
983 #define PSTATE_MODE_EL3t 12
984 #define PSTATE_MODE_EL2h 9
985 #define PSTATE_MODE_EL2t 8
986 #define PSTATE_MODE_EL1h 5
987 #define PSTATE_MODE_EL1t 4
988 #define PSTATE_MODE_EL0t 0
990 /* Map EL and handler into a PSTATE_MODE. */
991 static inline unsigned int aarch64_pstate_mode(unsigned int el
, bool handler
)
993 return (el
<< 2) | handler
;
996 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
997 * interprocessing, so we don't attempt to sync with the cpsr state used by
998 * the 32 bit decoder.
1000 static inline uint32_t pstate_read(CPUARMState
*env
)
1004 ZF
= (env
->ZF
== 0);
1005 return (env
->NF
& 0x80000000) | (ZF
<< 30)
1006 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
1007 | env
->pstate
| env
->daif
;
1010 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
1012 env
->ZF
= (~val
) & PSTATE_Z
;
1014 env
->CF
= (val
>> 29) & 1;
1015 env
->VF
= (val
<< 3) & 0x80000000;
1016 env
->daif
= val
& PSTATE_DAIF
;
1017 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
1020 /* Return the current CPSR value. */
1021 uint32_t cpsr_read(CPUARMState
*env
);
1023 typedef enum CPSRWriteType
{
1024 CPSRWriteByInstr
= 0, /* from guest MSR or CPS */
1025 CPSRWriteExceptionReturn
= 1, /* from guest exception return insn */
1026 CPSRWriteRaw
= 2, /* trust values, do not switch reg banks */
1027 CPSRWriteByGDBStub
= 3, /* from the GDB stub */
1030 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
1031 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
1032 CPSRWriteType write_type
);
1034 /* Return the current xPSR value. */
1035 static inline uint32_t xpsr_read(CPUARMState
*env
)
1038 ZF
= (env
->ZF
== 0);
1039 return (env
->NF
& 0x80000000) | (ZF
<< 30)
1040 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1041 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
1042 | ((env
->condexec_bits
& 0xfc) << 8)
1043 | env
->v7m
.exception
;
1046 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1047 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1049 if (mask
& XPSR_NZCV
) {
1050 env
->ZF
= (~val
) & XPSR_Z
;
1052 env
->CF
= (val
>> 29) & 1;
1053 env
->VF
= (val
<< 3) & 0x80000000;
1055 if (mask
& XPSR_Q
) {
1056 env
->QF
= ((val
& XPSR_Q
) != 0);
1058 if (mask
& XPSR_T
) {
1059 env
->thumb
= ((val
& XPSR_T
) != 0);
1061 if (mask
& XPSR_IT_0_1
) {
1062 env
->condexec_bits
&= ~3;
1063 env
->condexec_bits
|= (val
>> 25) & 3;
1065 if (mask
& XPSR_IT_2_7
) {
1066 env
->condexec_bits
&= 3;
1067 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1069 if (mask
& XPSR_EXCP
) {
1070 env
->v7m
.exception
= val
& XPSR_EXCP
;
1074 #define HCR_VM (1ULL << 0)
1075 #define HCR_SWIO (1ULL << 1)
1076 #define HCR_PTW (1ULL << 2)
1077 #define HCR_FMO (1ULL << 3)
1078 #define HCR_IMO (1ULL << 4)
1079 #define HCR_AMO (1ULL << 5)
1080 #define HCR_VF (1ULL << 6)
1081 #define HCR_VI (1ULL << 7)
1082 #define HCR_VSE (1ULL << 8)
1083 #define HCR_FB (1ULL << 9)
1084 #define HCR_BSU_MASK (3ULL << 10)
1085 #define HCR_DC (1ULL << 12)
1086 #define HCR_TWI (1ULL << 13)
1087 #define HCR_TWE (1ULL << 14)
1088 #define HCR_TID0 (1ULL << 15)
1089 #define HCR_TID1 (1ULL << 16)
1090 #define HCR_TID2 (1ULL << 17)
1091 #define HCR_TID3 (1ULL << 18)
1092 #define HCR_TSC (1ULL << 19)
1093 #define HCR_TIDCP (1ULL << 20)
1094 #define HCR_TACR (1ULL << 21)
1095 #define HCR_TSW (1ULL << 22)
1096 #define HCR_TPC (1ULL << 23)
1097 #define HCR_TPU (1ULL << 24)
1098 #define HCR_TTLB (1ULL << 25)
1099 #define HCR_TVM (1ULL << 26)
1100 #define HCR_TGE (1ULL << 27)
1101 #define HCR_TDZ (1ULL << 28)
1102 #define HCR_HCD (1ULL << 29)
1103 #define HCR_TRVM (1ULL << 30)
1104 #define HCR_RW (1ULL << 31)
1105 #define HCR_CD (1ULL << 32)
1106 #define HCR_ID (1ULL << 33)
1107 #define HCR_MASK ((1ULL << 34) - 1)
1109 #define SCR_NS (1U << 0)
1110 #define SCR_IRQ (1U << 1)
1111 #define SCR_FIQ (1U << 2)
1112 #define SCR_EA (1U << 3)
1113 #define SCR_FW (1U << 4)
1114 #define SCR_AW (1U << 5)
1115 #define SCR_NET (1U << 6)
1116 #define SCR_SMD (1U << 7)
1117 #define SCR_HCE (1U << 8)
1118 #define SCR_SIF (1U << 9)
1119 #define SCR_RW (1U << 10)
1120 #define SCR_ST (1U << 11)
1121 #define SCR_TWI (1U << 12)
1122 #define SCR_TWE (1U << 13)
1123 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1124 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1126 /* Return the current FPSCR value. */
1127 uint32_t vfp_get_fpscr(CPUARMState
*env
);
1128 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
1130 /* For A64 the FPSCR is split into two logically distinct registers,
1131 * FPCR and FPSR. However since they still use non-overlapping bits
1132 * we store the underlying state in fpscr and just mask on read/write.
1134 #define FPSR_MASK 0xf800009f
1135 #define FPCR_MASK 0x07f79f00
1136 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
1138 return vfp_get_fpscr(env
) & FPSR_MASK
;
1141 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
1143 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
1144 vfp_set_fpscr(env
, new_fpscr
);
1147 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
1149 return vfp_get_fpscr(env
) & FPCR_MASK
;
1152 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
1154 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
1155 vfp_set_fpscr(env
, new_fpscr
);
1159 ARM_CPU_MODE_USR
= 0x10,
1160 ARM_CPU_MODE_FIQ
= 0x11,
1161 ARM_CPU_MODE_IRQ
= 0x12,
1162 ARM_CPU_MODE_SVC
= 0x13,
1163 ARM_CPU_MODE_MON
= 0x16,
1164 ARM_CPU_MODE_ABT
= 0x17,
1165 ARM_CPU_MODE_HYP
= 0x1a,
1166 ARM_CPU_MODE_UND
= 0x1b,
1167 ARM_CPU_MODE_SYS
= 0x1f
1170 /* VFP system registers. */
1171 #define ARM_VFP_FPSID 0
1172 #define ARM_VFP_FPSCR 1
1173 #define ARM_VFP_MVFR2 5
1174 #define ARM_VFP_MVFR1 6
1175 #define ARM_VFP_MVFR0 7
1176 #define ARM_VFP_FPEXC 8
1177 #define ARM_VFP_FPINST 9
1178 #define ARM_VFP_FPINST2 10
1180 /* iwMMXt coprocessor control registers. */
1181 #define ARM_IWMMXT_wCID 0
1182 #define ARM_IWMMXT_wCon 1
1183 #define ARM_IWMMXT_wCSSF 2
1184 #define ARM_IWMMXT_wCASF 3
1185 #define ARM_IWMMXT_wCGR0 8
1186 #define ARM_IWMMXT_wCGR1 9
1187 #define ARM_IWMMXT_wCGR2 10
1188 #define ARM_IWMMXT_wCGR3 11
1191 FIELD(V7M_CCR
, NONBASETHRDENA
, 0, 1)
1192 FIELD(V7M_CCR
, USERSETMPEND
, 1, 1)
1193 FIELD(V7M_CCR
, UNALIGN_TRP
, 3, 1)
1194 FIELD(V7M_CCR
, DIV_0_TRP
, 4, 1)
1195 FIELD(V7M_CCR
, BFHFNMIGN
, 8, 1)
1196 FIELD(V7M_CCR
, STKALIGN
, 9, 1)
1197 FIELD(V7M_CCR
, DC
, 16, 1)
1198 FIELD(V7M_CCR
, IC
, 17, 1)
1200 /* V7M CFSR bits for MMFSR */
1201 FIELD(V7M_CFSR
, IACCVIOL
, 0, 1)
1202 FIELD(V7M_CFSR
, DACCVIOL
, 1, 1)
1203 FIELD(V7M_CFSR
, MUNSTKERR
, 3, 1)
1204 FIELD(V7M_CFSR
, MSTKERR
, 4, 1)
1205 FIELD(V7M_CFSR
, MLSPERR
, 5, 1)
1206 FIELD(V7M_CFSR
, MMARVALID
, 7, 1)
1208 /* V7M CFSR bits for BFSR */
1209 FIELD(V7M_CFSR
, IBUSERR
, 8 + 0, 1)
1210 FIELD(V7M_CFSR
, PRECISERR
, 8 + 1, 1)
1211 FIELD(V7M_CFSR
, IMPRECISERR
, 8 + 2, 1)
1212 FIELD(V7M_CFSR
, UNSTKERR
, 8 + 3, 1)
1213 FIELD(V7M_CFSR
, STKERR
, 8 + 4, 1)
1214 FIELD(V7M_CFSR
, LSPERR
, 8 + 5, 1)
1215 FIELD(V7M_CFSR
, BFARVALID
, 8 + 7, 1)
1217 /* V7M CFSR bits for UFSR */
1218 FIELD(V7M_CFSR
, UNDEFINSTR
, 16 + 0, 1)
1219 FIELD(V7M_CFSR
, INVSTATE
, 16 + 1, 1)
1220 FIELD(V7M_CFSR
, INVPC
, 16 + 2, 1)
1221 FIELD(V7M_CFSR
, NOCP
, 16 + 3, 1)
1222 FIELD(V7M_CFSR
, UNALIGNED
, 16 + 8, 1)
1223 FIELD(V7M_CFSR
, DIVBYZERO
, 16 + 9, 1)
1225 /* V7M CFSR bit masks covering all of the subregister bits */
1226 FIELD(V7M_CFSR
, MMFSR
, 0, 8)
1227 FIELD(V7M_CFSR
, BFSR
, 8, 8)
1228 FIELD(V7M_CFSR
, UFSR
, 16, 16)
1231 FIELD(V7M_HFSR
, VECTTBL
, 1, 1)
1232 FIELD(V7M_HFSR
, FORCED
, 30, 1)
1233 FIELD(V7M_HFSR
, DEBUGEVT
, 31, 1)
1236 FIELD(V7M_DFSR
, HALTED
, 0, 1)
1237 FIELD(V7M_DFSR
, BKPT
, 1, 1)
1238 FIELD(V7M_DFSR
, DWTTRAP
, 2, 1)
1239 FIELD(V7M_DFSR
, VCATCH
, 3, 1)
1240 FIELD(V7M_DFSR
, EXTERNAL
, 4, 1)
1242 /* v7M MPU_CTRL bits */
1243 FIELD(V7M_MPU_CTRL
, ENABLE
, 0, 1)
1244 FIELD(V7M_MPU_CTRL
, HFNMIENA
, 1, 1)
1245 FIELD(V7M_MPU_CTRL
, PRIVDEFENA
, 2, 1)
1247 /* If adding a feature bit which corresponds to a Linux ELF
1248 * HWCAP bit, remember to update the feature-bit-to-hwcap
1249 * mapping in linux-user/elfload.c:get_elf_hwcap().
1253 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
1254 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
1255 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
1260 ARM_FEATURE_PMSA
, /* no MMU; may have Memory Protection Unit */
1262 ARM_FEATURE_VFP_FP16
,
1264 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
1265 ARM_FEATURE_M
, /* Microcontroller profile. */
1266 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
1267 ARM_FEATURE_THUMB2EE
,
1268 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
1271 ARM_FEATURE_STRONGARM
,
1272 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
1273 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
1274 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
1275 ARM_FEATURE_GENERIC_TIMER
,
1276 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
1277 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
1278 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
1279 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
1280 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
1281 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
1282 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
1283 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
1285 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
1286 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
1287 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
1288 ARM_FEATURE_CRC
, /* ARMv8 CRC instructions */
1289 ARM_FEATURE_CBAR_RO
, /* has cp15 CBAR and it is read-only */
1290 ARM_FEATURE_EL2
, /* has EL2 Virtualization support */
1291 ARM_FEATURE_EL3
, /* has EL3 Secure monitor support */
1292 ARM_FEATURE_V8_SHA1
, /* implements SHA1 part of v8 Crypto Extensions */
1293 ARM_FEATURE_V8_SHA256
, /* implements SHA256 part of v8 Crypto Extensions */
1294 ARM_FEATURE_V8_PMULL
, /* implements PMULL part of v8 Crypto Extensions */
1295 ARM_FEATURE_THUMB_DSP
, /* DSP insns supported in the Thumb encodings */
1296 ARM_FEATURE_PMU
, /* has PMU support */
1297 ARM_FEATURE_VBAR
, /* has cp15 VBAR */
1298 ARM_FEATURE_M_SECURITY
, /* M profile Security Extension */
1299 ARM_FEATURE_JAZELLE
, /* has (trivial) Jazelle implementation */
1302 static inline int arm_feature(CPUARMState
*env
, int feature
)
1304 return (env
->features
& (1ULL << feature
)) != 0;
1307 #if !defined(CONFIG_USER_ONLY)
1308 /* Return true if exception levels below EL3 are in secure state,
1309 * or would be following an exception return to that level.
1310 * Unlike arm_is_secure() (which is always a question about the
1311 * _current_ state of the CPU) this doesn't care about the current
1314 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
1316 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1317 return !(env
->cp15
.scr_el3
& SCR_NS
);
1319 /* If EL3 is not supported then the secure state is implementation
1320 * defined, in which case QEMU defaults to non-secure.
1326 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
1327 static inline bool arm_is_el3_or_mon(CPUARMState
*env
)
1329 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1330 if (is_a64(env
) && extract32(env
->pstate
, 2, 2) == 3) {
1331 /* CPU currently in AArch64 state and EL3 */
1333 } else if (!is_a64(env
) &&
1334 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
1335 /* CPU currently in AArch32 state and monitor mode */
1342 /* Return true if the processor is in secure state */
1343 static inline bool arm_is_secure(CPUARMState
*env
)
1345 if (arm_is_el3_or_mon(env
)) {
1348 return arm_is_secure_below_el3(env
);
1352 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
1357 static inline bool arm_is_secure(CPUARMState
*env
)
1363 /* Return true if the specified exception level is running in AArch64 state. */
1364 static inline bool arm_el_is_aa64(CPUARMState
*env
, int el
)
1366 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
1367 * and if we're not in EL0 then the state of EL0 isn't well defined.)
1369 assert(el
>= 1 && el
<= 3);
1370 bool aa64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
1372 /* The highest exception level is always at the maximum supported
1373 * register width, and then lower levels have a register width controlled
1374 * by bits in the SCR or HCR registers.
1380 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1381 aa64
= aa64
&& (env
->cp15
.scr_el3
& SCR_RW
);
1388 if (arm_feature(env
, ARM_FEATURE_EL2
) && !arm_is_secure_below_el3(env
)) {
1389 aa64
= aa64
&& (env
->cp15
.hcr_el2
& HCR_RW
);
1395 /* Function for determing whether guest cp register reads and writes should
1396 * access the secure or non-secure bank of a cp register. When EL3 is
1397 * operating in AArch32 state, the NS-bit determines whether the secure
1398 * instance of a cp register should be used. When EL3 is AArch64 (or if
1399 * it doesn't exist at all) then there is no register banking, and all
1400 * accesses are to the non-secure version.
1402 static inline bool access_secure_reg(CPUARMState
*env
)
1404 bool ret
= (arm_feature(env
, ARM_FEATURE_EL3
) &&
1405 !arm_el_is_aa64(env
, 3) &&
1406 !(env
->cp15
.scr_el3
& SCR_NS
));
1411 /* Macros for accessing a specified CP register bank */
1412 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
1413 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1415 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1418 (_env)->cp15._regname##_s = (_val); \
1420 (_env)->cp15._regname##_ns = (_val); \
1424 /* Macros for automatically accessing a specific CP register bank depending on
1425 * the current secure state of the system. These macros are not intended for
1426 * supporting instruction translation reads/writes as these are dependent
1427 * solely on the SCR.NS bit and not the mode.
1429 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1430 A32_BANKED_REG_GET((_env), _regname, \
1431 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1433 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1434 A32_BANKED_REG_SET((_env), _regname, \
1435 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1438 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
1439 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
1440 uint32_t cur_el
, bool secure
);
1442 /* Interface between CPU and Interrupt controller. */
1443 #ifndef CONFIG_USER_ONLY
1444 bool armv7m_nvic_can_take_pending_exception(void *opaque
);
1446 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque
)
1451 void armv7m_nvic_set_pending(void *opaque
, int irq
);
1452 void armv7m_nvic_acknowledge_irq(void *opaque
);
1454 * armv7m_nvic_complete_irq: complete specified interrupt or exception
1456 * @irq: the exception number to complete
1458 * Returns: -1 if the irq was not active
1459 * 1 if completing this irq brought us back to base (no active irqs)
1460 * 0 if there is still an irq active after this one was completed
1461 * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
1463 int armv7m_nvic_complete_irq(void *opaque
, int irq
);
1465 * armv7m_nvic_raw_execution_priority: return the raw execution priority
1468 * Returns: the raw execution priority as defined by the v8M architecture.
1469 * This is the execution priority minus the effects of AIRCR.PRIS,
1470 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
1471 * (v8M ARM ARM I_PKLD.)
1473 int armv7m_nvic_raw_execution_priority(void *opaque
);
1475 /* Interface for defining coprocessor registers.
1476 * Registers are defined in tables of arm_cp_reginfo structs
1477 * which are passed to define_arm_cp_regs().
1480 /* When looking up a coprocessor register we look for it
1481 * via an integer which encodes all of:
1482 * coprocessor number
1483 * Crn, Crm, opc1, opc2 fields
1484 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1485 * or via MRRC/MCRR?)
1486 * non-secure/secure bank (AArch32 only)
1487 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1488 * (In this case crn and opc2 should be zero.)
1489 * For AArch64, there is no 32/64 bit size distinction;
1490 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1491 * and 4 bit CRn and CRm. The encoding patterns are chosen
1492 * to be easy to convert to and from the KVM encodings, and also
1493 * so that the hashtable can contain both AArch32 and AArch64
1494 * registers (to allow for interprocessing where we might run
1495 * 32 bit code on a 64 bit core).
1497 /* This bit is private to our hashtable cpreg; in KVM register
1498 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1499 * in the upper bits of the 64 bit ID.
1501 #define CP_REG_AA64_SHIFT 28
1502 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1504 /* To enable banking of coprocessor registers depending on ns-bit we
1505 * add a bit to distinguish between secure and non-secure cpregs in the
1508 #define CP_REG_NS_SHIFT 29
1509 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1511 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1512 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1513 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1515 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1516 (CP_REG_AA64_MASK | \
1517 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1518 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1519 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1520 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1521 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1522 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1524 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1525 * version used as a key for the coprocessor register hashtable
1527 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
1529 uint32_t cpregid
= kvmid
;
1530 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
1531 cpregid
|= CP_REG_AA64_MASK
;
1533 if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
1534 cpregid
|= (1 << 15);
1537 /* KVM is always non-secure so add the NS flag on AArch32 register
1540 cpregid
|= 1 << CP_REG_NS_SHIFT
;
1545 /* Convert a truncated 32 bit hashtable key into the full
1546 * 64 bit KVM register ID.
1548 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
1552 if (cpregid
& CP_REG_AA64_MASK
) {
1553 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
1554 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
1556 kvmid
= cpregid
& ~(1 << 15);
1557 if (cpregid
& (1 << 15)) {
1558 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
1560 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
1566 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1567 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1568 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1569 * TCG can assume the value to be constant (ie load at translate time)
1570 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1571 * indicates that the TB should not be ended after a write to this register
1572 * (the default is that the TB ends after cp writes). OVERRIDE permits
1573 * a register definition to override a previous definition for the
1574 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1575 * old must have the OVERRIDE bit set.
1576 * ALIAS indicates that this register is an alias view of some underlying
1577 * state which is also visible via another register, and that the other
1578 * register is handling migration and reset; registers marked ALIAS will not be
1579 * migrated but may have their state set by syncing of register state from KVM.
1580 * NO_RAW indicates that this register has no underlying state and does not
1581 * support raw access for state saving/loading; it will not be used for either
1582 * migration or KVM state synchronization. (Typically this is for "registers"
1583 * which are actually used as instructions for cache maintenance and so on.)
1584 * IO indicates that this register does I/O and therefore its accesses
1585 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1586 * registers which implement clocks or timers require this.
1588 #define ARM_CP_SPECIAL 1
1589 #define ARM_CP_CONST 2
1590 #define ARM_CP_64BIT 4
1591 #define ARM_CP_SUPPRESS_TB_END 8
1592 #define ARM_CP_OVERRIDE 16
1593 #define ARM_CP_ALIAS 32
1594 #define ARM_CP_IO 64
1595 #define ARM_CP_NO_RAW 128
1596 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1597 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1598 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1599 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1600 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1601 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1602 /* Used only as a terminator for ARMCPRegInfo lists */
1603 #define ARM_CP_SENTINEL 0xffff
1604 /* Mask of only the flag bits in a type field */
1605 #define ARM_CP_FLAG_MASK 0xff
1607 /* Valid values for ARMCPRegInfo state field, indicating which of
1608 * the AArch32 and AArch64 execution states this register is visible in.
1609 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1610 * If the reginfo is declared to be visible in both states then a second
1611 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1612 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1613 * Note that we rely on the values of these enums as we iterate through
1614 * the various states in some places.
1617 ARM_CP_STATE_AA32
= 0,
1618 ARM_CP_STATE_AA64
= 1,
1619 ARM_CP_STATE_BOTH
= 2,
1622 /* ARM CP register secure state flags. These flags identify security state
1623 * attributes for a given CP register entry.
1624 * The existence of both or neither secure and non-secure flags indicates that
1625 * the register has both a secure and non-secure hash entry. A single one of
1626 * these flags causes the register to only be hashed for the specified
1628 * Although definitions may have any combination of the S/NS bits, each
1629 * registered entry will only have one to identify whether the entry is secure
1633 ARM_CP_SECSTATE_S
= (1 << 0), /* bit[0]: Secure state register */
1634 ARM_CP_SECSTATE_NS
= (1 << 1), /* bit[1]: Non-secure state register */
1637 /* Return true if cptype is a valid type field. This is used to try to
1638 * catch errors where the sentinel has been accidentally left off the end
1639 * of a list of registers.
1641 static inline bool cptype_valid(int cptype
)
1643 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
1644 || ((cptype
& ARM_CP_SPECIAL
) &&
1645 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
1649 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1650 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1651 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1652 * (ie any of the privileged modes in Secure state, or Monitor mode).
1653 * If a register is accessible in one privilege level it's always accessible
1654 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1655 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1656 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1657 * terminology a little and call this PL3.
1658 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1659 * with the ELx exception levels.
1661 * If access permissions for a register are more complex than can be
1662 * described with these bits, then use a laxer set of restrictions, and
1663 * do the more restrictive/complex check inside a helper function.
1667 #define PL2_R (0x20 | PL3_R)
1668 #define PL2_W (0x10 | PL3_W)
1669 #define PL1_R (0x08 | PL2_R)
1670 #define PL1_W (0x04 | PL2_W)
1671 #define PL0_R (0x02 | PL1_R)
1672 #define PL0_W (0x01 | PL1_W)
1674 #define PL3_RW (PL3_R | PL3_W)
1675 #define PL2_RW (PL2_R | PL2_W)
1676 #define PL1_RW (PL1_R | PL1_W)
1677 #define PL0_RW (PL0_R | PL0_W)
1679 /* Return the highest implemented Exception Level */
1680 static inline int arm_highest_el(CPUARMState
*env
)
1682 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1685 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1691 /* Return true if a v7M CPU is in Handler mode */
1692 static inline bool arm_v7m_is_handler_mode(CPUARMState
*env
)
1694 return env
->v7m
.exception
!= 0;
1697 /* Return the current Exception Level (as per ARMv8; note that this differs
1698 * from the ARMv7 Privilege Level).
1700 static inline int arm_current_el(CPUARMState
*env
)
1702 if (arm_feature(env
, ARM_FEATURE_M
)) {
1703 return arm_v7m_is_handler_mode(env
) ||
1704 !(env
->v7m
.control
[env
->v7m
.secure
] & 1);
1708 return extract32(env
->pstate
, 2, 2);
1711 switch (env
->uncached_cpsr
& 0x1f) {
1712 case ARM_CPU_MODE_USR
:
1714 case ARM_CPU_MODE_HYP
:
1716 case ARM_CPU_MODE_MON
:
1719 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
1720 /* If EL3 is 32-bit then all secure privileged modes run in
1730 typedef struct ARMCPRegInfo ARMCPRegInfo
;
1732 typedef enum CPAccessResult
{
1733 /* Access is permitted */
1735 /* Access fails due to a configurable trap or enable which would
1736 * result in a categorized exception syndrome giving information about
1737 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1738 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1739 * PL1 if in EL0, otherwise to the current EL).
1742 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1743 * Note that this is not a catch-all case -- the set of cases which may
1744 * result in this failure is specifically defined by the architecture.
1746 CP_ACCESS_TRAP_UNCATEGORIZED
= 2,
1747 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1748 CP_ACCESS_TRAP_EL2
= 3,
1749 CP_ACCESS_TRAP_EL3
= 4,
1750 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
1751 CP_ACCESS_TRAP_UNCATEGORIZED_EL2
= 5,
1752 CP_ACCESS_TRAP_UNCATEGORIZED_EL3
= 6,
1753 /* Access fails and results in an exception syndrome for an FP access,
1754 * trapped directly to EL2 or EL3
1756 CP_ACCESS_TRAP_FP_EL2
= 7,
1757 CP_ACCESS_TRAP_FP_EL3
= 8,
1760 /* Access functions for coprocessor registers. These cannot fail and
1761 * may not raise exceptions.
1763 typedef uint64_t CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1764 typedef void CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
1766 /* Access permission check functions for coprocessor registers. */
1767 typedef CPAccessResult
CPAccessFn(CPUARMState
*env
,
1768 const ARMCPRegInfo
*opaque
,
1770 /* Hook function for register reset */
1771 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1775 /* Definition of an ARM coprocessor register */
1776 struct ARMCPRegInfo
{
1777 /* Name of register (useful mainly for debugging, need not be unique) */
1779 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1780 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1781 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1782 * will be decoded to this register. The register read and write
1783 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1784 * used by the program, so it is possible to register a wildcard and
1785 * then behave differently on read/write if necessary.
1786 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1787 * must both be zero.
1788 * For AArch64-visible registers, opc0 is also used.
1789 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1790 * way to distinguish (for KVM's benefit) guest-visible system registers
1791 * from demuxed ones provided to preserve the "no side effects on
1792 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1793 * visible (to match KVM's encoding); cp==0 will be converted to
1794 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1802 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1804 /* Register type: ARM_CP_* bits/values */
1806 /* Access rights: PL*_[RW] */
1808 /* Security state: ARM_CP_SECSTATE_* bits/values */
1810 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1811 * this register was defined: can be used to hand data through to the
1812 * register read/write functions, since they are passed the ARMCPRegInfo*.
1815 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1816 * fieldoffset is non-zero, the reset value of the register.
1818 uint64_t resetvalue
;
1819 /* Offset of the field in CPUARMState for this register.
1821 * This is not needed if either:
1822 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1823 * 2. both readfn and writefn are specified
1825 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
1827 /* Offsets of the secure and non-secure fields in CPUARMState for the
1828 * register if it is banked. These fields are only used during the static
1829 * registration of a register. During hashing the bank associated
1830 * with a given security state is copied to fieldoffset which is used from
1833 * It is expected that register definitions use either fieldoffset or
1834 * bank_fieldoffsets in the definition but not both. It is also expected
1835 * that both bank offsets are set when defining a banked register. This
1836 * use indicates that a register is banked.
1838 ptrdiff_t bank_fieldoffsets
[2];
1840 /* Function for making any access checks for this register in addition to
1841 * those specified by the 'access' permissions bits. If NULL, no extra
1842 * checks required. The access check is performed at runtime, not at
1845 CPAccessFn
*accessfn
;
1846 /* Function for handling reads of this register. If NULL, then reads
1847 * will be done by loading from the offset into CPUARMState specified
1851 /* Function for handling writes of this register. If NULL, then writes
1852 * will be done by writing to the offset into CPUARMState specified
1856 /* Function for doing a "raw" read; used when we need to copy
1857 * coprocessor state to the kernel for KVM or out for
1858 * migration. This only needs to be provided if there is also a
1859 * readfn and it has side effects (for instance clear-on-read bits).
1861 CPReadFn
*raw_readfn
;
1862 /* Function for doing a "raw" write; used when we need to copy KVM
1863 * kernel coprocessor state into userspace, or for inbound
1864 * migration. This only needs to be provided if there is also a
1865 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1866 * or similar behaviour.
1868 CPWriteFn
*raw_writefn
;
1869 /* Function for resetting the register. If NULL, then reset will be done
1870 * by writing resetvalue to the field specified in fieldoffset. If
1871 * fieldoffset is 0 then no reset will be done.
1876 /* Macros which are lvalues for the field in CPUARMState for the
1879 #define CPREG_FIELD32(env, ri) \
1880 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1881 #define CPREG_FIELD64(env, ri) \
1882 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1884 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1886 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1887 const ARMCPRegInfo
*regs
, void *opaque
);
1888 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1889 const ARMCPRegInfo
*regs
, void *opaque
);
1890 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1892 define_arm_cp_regs_with_opaque(cpu
, regs
, 0);
1894 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1896 define_one_arm_cp_reg_with_opaque(cpu
, regs
, 0);
1898 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
1900 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1901 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1903 /* CPReadFn that can be used for read-as-zero behaviour */
1904 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1906 /* CPResetFn that does nothing, for use if no reset is required even
1907 * if fieldoffset is non zero.
1909 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1911 /* Return true if this reginfo struct's field in the cpu state struct
1914 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo
*ri
)
1916 return (ri
->state
== ARM_CP_STATE_AA64
) || (ri
->type
& ARM_CP_64BIT
);
1919 static inline bool cp_access_ok(int current_el
,
1920 const ARMCPRegInfo
*ri
, int isread
)
1922 return (ri
->access
>> ((current_el
* 2) + isread
)) & 1;
1925 /* Raw read of a coprocessor register (as needed for migration, etc) */
1926 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1929 * write_list_to_cpustate
1932 * For each register listed in the ARMCPU cpreg_indexes list, write
1933 * its value from the cpreg_values list into the ARMCPUState structure.
1934 * This updates TCG's working data structures from KVM data or
1935 * from incoming migration state.
1937 * Returns: true if all register values were updated correctly,
1938 * false if some register was unknown or could not be written.
1939 * Note that we do not stop early on failure -- we will attempt
1940 * writing all registers in the list.
1942 bool write_list_to_cpustate(ARMCPU
*cpu
);
1945 * write_cpustate_to_list:
1948 * For each register listed in the ARMCPU cpreg_indexes list, write
1949 * its value from the ARMCPUState structure into the cpreg_values list.
1950 * This is used to copy info from TCG's working data structures into
1951 * KVM or for outbound migration.
1953 * Returns: true if all register values were read correctly,
1954 * false if some register was unknown or could not be read.
1955 * Note that we do not stop early on failure -- we will attempt
1956 * reading all registers in the list.
1958 bool write_cpustate_to_list(ARMCPU
*cpu
);
1960 #define ARM_CPUID_TI915T 0x54029152
1961 #define ARM_CPUID_TI925T 0x54029252
1963 #if defined(CONFIG_USER_ONLY)
1964 #define TARGET_PAGE_BITS 12
1966 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
1967 * have to support 1K tiny pages.
1969 #define TARGET_PAGE_BITS_VARY
1970 #define TARGET_PAGE_BITS_MIN 10
1973 #if defined(TARGET_AARCH64)
1974 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1975 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1977 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1978 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1981 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
1982 unsigned int target_el
)
1984 CPUARMState
*env
= cs
->env_ptr
;
1985 unsigned int cur_el
= arm_current_el(env
);
1986 bool secure
= arm_is_secure(env
);
1987 bool pstate_unmasked
;
1988 int8_t unmasked
= 0;
1990 /* Don't take exceptions if they target a lower EL.
1991 * This check should catch any exceptions that would not be taken but left
1994 if (cur_el
> target_el
) {
2000 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
2004 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
2008 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_FMO
)) {
2009 /* VFIQs are only taken when hypervized and non-secure. */
2012 return !(env
->daif
& PSTATE_F
);
2014 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_IMO
)) {
2015 /* VIRQs are only taken when hypervized and non-secure. */
2018 return !(env
->daif
& PSTATE_I
);
2020 g_assert_not_reached();
2023 /* Use the target EL, current execution state and SCR/HCR settings to
2024 * determine whether the corresponding CPSR bit is used to mask the
2027 if ((target_el
> cur_el
) && (target_el
!= 1)) {
2028 /* Exceptions targeting a higher EL may not be maskable */
2029 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
2030 /* 64-bit masking rules are simple: exceptions to EL3
2031 * can't be masked, and exceptions to EL2 can only be
2032 * masked from Secure state. The HCR and SCR settings
2033 * don't affect the masking logic, only the interrupt routing.
2035 if (target_el
== 3 || !secure
) {
2039 /* The old 32-bit-only environment has a more complicated
2040 * masking setup. HCR and SCR bits not only affect interrupt
2041 * routing but also change the behaviour of masking.
2047 /* If FIQs are routed to EL3 or EL2 then there are cases where
2048 * we override the CPSR.F in determining if the exception is
2049 * masked or not. If neither of these are set then we fall back
2050 * to the CPSR.F setting otherwise we further assess the state
2053 hcr
= (env
->cp15
.hcr_el2
& HCR_FMO
);
2054 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
2056 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
2057 * CPSR.F bit masks FIQ interrupts when taken in non-secure
2058 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
2059 * when non-secure but only when FIQs are only routed to EL3.
2061 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
2064 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
2065 * we may override the CPSR.I masking when in non-secure state.
2066 * The SCR.IRQ setting has already been taken into consideration
2067 * when setting the target EL, so it does not have a further
2070 hcr
= (env
->cp15
.hcr_el2
& HCR_IMO
);
2074 g_assert_not_reached();
2077 if ((scr
|| hcr
) && !secure
) {
2083 /* The PSTATE bits only mask the interrupt if we have not overriden the
2086 return unmasked
|| pstate_unmasked
;
2089 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)
2091 #define cpu_signal_handler cpu_arm_signal_handler
2092 #define cpu_list arm_cpu_list
2094 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2097 * + NonSecure EL1 & 0 stage 1
2098 * + NonSecure EL1 & 0 stage 2
2100 * + Secure EL1 & EL0
2103 * + NonSecure PL1 & 0 stage 1
2104 * + NonSecure PL1 & 0 stage 2
2106 * + Secure PL0 & PL1
2107 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2109 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2110 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
2111 * may differ in access permissions even if the VA->PA map is the same
2112 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2113 * translation, which means that we have one mmu_idx that deals with two
2114 * concatenated translation regimes [this sort of combined s1+2 TLB is
2115 * architecturally permitted]
2116 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2117 * handling via the TLB. The only way to do a stage 1 translation without
2118 * the immediate stage 2 translation is via the ATS or AT system insns,
2119 * which can be slow-pathed and always do a page table walk.
2120 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2121 * translation regimes, because they map reasonably well to each other
2122 * and they can't both be active at the same time.
2123 * This gives us the following list of mmu_idx values:
2125 * NS EL0 (aka NS PL0) stage 1+2
2126 * NS EL1 (aka NS PL1) stage 1+2
2127 * NS EL2 (aka NS PL2)
2130 * S EL1 (not used if EL3 is 32 bit)
2133 * (The last of these is an mmu_idx because we want to be able to use the TLB
2134 * for the accesses done as part of a stage 1 page table walk, rather than
2135 * having to walk the stage 2 page table over and over.)
2137 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2138 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2139 * NS EL2 if we ever model a Cortex-R52).
2141 * M profile CPUs are rather different as they do not have a true MMU.
2142 * They have the following different MMU indexes:
2145 * Execution priority negative (this is like privileged, but the
2146 * MPU HFNMIENA bit means that it may have different access permission
2147 * check results to normal privileged code, so can't share a TLB).
2148 * If the CPU supports the v8M Security Extension then there are also:
2151 * Secure, execution priority negative
2153 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2154 * are not quite the same -- different CPU types (most notably M profile
2155 * vs A/R profile) would like to use MMU indexes with different semantics,
2156 * but since we don't ever need to use all of those in a single CPU we
2157 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
2158 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2159 * the same for any particular CPU.
2160 * Variables of type ARMMUIdx are always full values, and the core
2161 * index values are in variables of type 'int'.
2163 * Our enumeration includes at the end some entries which are not "true"
2164 * mmu_idx values in that they don't have corresponding TLBs and are only
2165 * valid for doing slow path page table walks.
2167 * The constant names here are patterned after the general style of the names
2168 * of the AT/ATS operations.
2169 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2171 #define ARM_MMU_IDX_A 0x10 /* A profile */
2172 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2173 #define ARM_MMU_IDX_M 0x40 /* M profile */
2175 #define ARM_MMU_IDX_TYPE_MASK (~0x7)
2176 #define ARM_MMU_IDX_COREIDX_MASK 0x7
2178 typedef enum ARMMMUIdx
{
2179 ARMMMUIdx_S12NSE0
= 0 | ARM_MMU_IDX_A
,
2180 ARMMMUIdx_S12NSE1
= 1 | ARM_MMU_IDX_A
,
2181 ARMMMUIdx_S1E2
= 2 | ARM_MMU_IDX_A
,
2182 ARMMMUIdx_S1E3
= 3 | ARM_MMU_IDX_A
,
2183 ARMMMUIdx_S1SE0
= 4 | ARM_MMU_IDX_A
,
2184 ARMMMUIdx_S1SE1
= 5 | ARM_MMU_IDX_A
,
2185 ARMMMUIdx_S2NS
= 6 | ARM_MMU_IDX_A
,
2186 ARMMMUIdx_MUser
= 0 | ARM_MMU_IDX_M
,
2187 ARMMMUIdx_MPriv
= 1 | ARM_MMU_IDX_M
,
2188 ARMMMUIdx_MNegPri
= 2 | ARM_MMU_IDX_M
,
2189 ARMMMUIdx_MSUser
= 3 | ARM_MMU_IDX_M
,
2190 ARMMMUIdx_MSPriv
= 4 | ARM_MMU_IDX_M
,
2191 ARMMMUIdx_MSNegPri
= 5 | ARM_MMU_IDX_M
,
2192 /* Indexes below here don't have TLBs and are used only for AT system
2193 * instructions or for the first stage of an S12 page table walk.
2195 ARMMMUIdx_S1NSE0
= 0 | ARM_MMU_IDX_NOTLB
,
2196 ARMMMUIdx_S1NSE1
= 1 | ARM_MMU_IDX_NOTLB
,
2199 /* Bit macros for the core-mmu-index values for each index,
2200 * for use when calling tlb_flush_by_mmuidx() and friends.
2202 typedef enum ARMMMUIdxBit
{
2203 ARMMMUIdxBit_S12NSE0
= 1 << 0,
2204 ARMMMUIdxBit_S12NSE1
= 1 << 1,
2205 ARMMMUIdxBit_S1E2
= 1 << 2,
2206 ARMMMUIdxBit_S1E3
= 1 << 3,
2207 ARMMMUIdxBit_S1SE0
= 1 << 4,
2208 ARMMMUIdxBit_S1SE1
= 1 << 5,
2209 ARMMMUIdxBit_S2NS
= 1 << 6,
2210 ARMMMUIdxBit_MUser
= 1 << 0,
2211 ARMMMUIdxBit_MPriv
= 1 << 1,
2212 ARMMMUIdxBit_MNegPri
= 1 << 2,
2213 ARMMMUIdxBit_MSUser
= 1 << 3,
2214 ARMMMUIdxBit_MSPriv
= 1 << 4,
2215 ARMMMUIdxBit_MSNegPri
= 1 << 5,
2218 #define MMU_USER_IDX 0
2220 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx
)
2222 return mmu_idx
& ARM_MMU_IDX_COREIDX_MASK
;
2225 static inline ARMMMUIdx
core_to_arm_mmu_idx(CPUARMState
*env
, int mmu_idx
)
2227 if (arm_feature(env
, ARM_FEATURE_M
)) {
2228 return mmu_idx
| ARM_MMU_IDX_M
;
2230 return mmu_idx
| ARM_MMU_IDX_A
;
2234 /* Return the exception level we're running at if this is our mmu_idx */
2235 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
2237 switch (mmu_idx
& ARM_MMU_IDX_TYPE_MASK
) {
2241 return (mmu_idx
== ARMMMUIdx_MUser
|| mmu_idx
== ARMMMUIdx_MSUser
)
2244 g_assert_not_reached();
2248 /* Determine the current mmu_idx to use for normal loads/stores */
2249 static inline int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
2251 int el
= arm_current_el(env
);
2253 if (arm_feature(env
, ARM_FEATURE_M
)) {
2254 ARMMMUIdx mmu_idx
= el
== 0 ? ARMMMUIdx_MUser
: ARMMMUIdx_MPriv
;
2256 /* Execution priority is negative if FAULTMASK is set or
2257 * we're in a HardFault or NMI handler.
2259 if ((env
->v7m
.exception
> 0 && env
->v7m
.exception
<= 3)
2260 || env
->v7m
.faultmask
[env
->v7m
.secure
]) {
2261 mmu_idx
= ARMMMUIdx_MNegPri
;
2264 if (env
->v7m
.secure
) {
2265 mmu_idx
+= ARMMMUIdx_MSUser
;
2268 return arm_to_core_mmu_idx(mmu_idx
);
2271 if (el
< 2 && arm_is_secure_below_el3(env
)) {
2272 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0
+ el
);
2277 /* Indexes used when registering address spaces with cpu_address_space_init */
2278 typedef enum ARMASIdx
{
2283 /* Return the Exception Level targeted by debug exceptions. */
2284 static inline int arm_debug_target_el(CPUARMState
*env
)
2286 bool secure
= arm_is_secure(env
);
2287 bool route_to_el2
= false;
2289 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
) {
2290 route_to_el2
= env
->cp15
.hcr_el2
& HCR_TGE
||
2291 env
->cp15
.mdcr_el2
& (1 << 8);
2296 } else if (arm_feature(env
, ARM_FEATURE_EL3
) &&
2297 !arm_el_is_aa64(env
, 3) && secure
) {
2304 static inline bool aa64_generate_debug_exceptions(CPUARMState
*env
)
2306 if (arm_is_secure(env
)) {
2307 /* MDCR_EL3.SDD disables debug events from Secure state */
2308 if (extract32(env
->cp15
.mdcr_el3
, 16, 1) != 0
2309 || arm_current_el(env
) == 3) {
2314 if (arm_current_el(env
) == arm_debug_target_el(env
)) {
2315 if ((extract32(env
->cp15
.mdscr_el1
, 13, 1) == 0)
2316 || (env
->daif
& PSTATE_D
)) {
2323 static inline bool aa32_generate_debug_exceptions(CPUARMState
*env
)
2325 int el
= arm_current_el(env
);
2327 if (el
== 0 && arm_el_is_aa64(env
, 1)) {
2328 return aa64_generate_debug_exceptions(env
);
2331 if (arm_is_secure(env
)) {
2334 if (el
== 0 && (env
->cp15
.sder
& 1)) {
2335 /* SDER.SUIDEN means debug exceptions from Secure EL0
2336 * are always enabled. Otherwise they are controlled by
2337 * SDCR.SPD like those from other Secure ELs.
2342 spd
= extract32(env
->cp15
.mdcr_el3
, 14, 2);
2345 /* SPD == 0b01 is reserved, but behaves as 0b00. */
2347 /* For 0b00 we return true if external secure invasive debug
2348 * is enabled. On real hardware this is controlled by external
2349 * signals to the core. QEMU always permits debug, and behaves
2350 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
2363 /* Return true if debugging exceptions are currently enabled.
2364 * This corresponds to what in ARM ARM pseudocode would be
2365 * if UsingAArch32() then
2366 * return AArch32.GenerateDebugExceptions()
2368 * return AArch64.GenerateDebugExceptions()
2369 * We choose to push the if() down into this function for clarity,
2370 * since the pseudocode has it at all callsites except for the one in
2371 * CheckSoftwareStep(), where it is elided because both branches would
2372 * always return the same value.
2374 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
2375 * don't yet implement those exception levels or their associated trap bits.
2377 static inline bool arm_generate_debug_exceptions(CPUARMState
*env
)
2380 return aa64_generate_debug_exceptions(env
);
2382 return aa32_generate_debug_exceptions(env
);
2386 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
2387 * implicitly means this always returns false in pre-v8 CPUs.)
2389 static inline bool arm_singlestep_active(CPUARMState
*env
)
2391 return extract32(env
->cp15
.mdscr_el1
, 0, 1)
2392 && arm_el_is_aa64(env
, arm_debug_target_el(env
))
2393 && arm_generate_debug_exceptions(env
);
2396 static inline bool arm_sctlr_b(CPUARMState
*env
)
2399 /* We need not implement SCTLR.ITD in user-mode emulation, so
2400 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2401 * This lets people run BE32 binaries with "-cpu any".
2403 #ifndef CONFIG_USER_ONLY
2404 !arm_feature(env
, ARM_FEATURE_V7
) &&
2406 (env
->cp15
.sctlr_el
[1] & SCTLR_B
) != 0;
2409 /* Return true if the processor is in big-endian mode. */
2410 static inline bool arm_cpu_data_is_big_endian(CPUARMState
*env
)
2414 /* In 32bit endianness is determined by looking at CPSR's E bit */
2417 #ifdef CONFIG_USER_ONLY
2418 /* In system mode, BE32 is modelled in line with the
2419 * architecture (as word-invariant big-endianness), where loads
2420 * and stores are done little endian but from addresses which
2421 * are adjusted by XORing with the appropriate constant. So the
2422 * endianness to use for the raw data access is not affected by
2424 * In user mode, however, we model BE32 as byte-invariant
2425 * big-endianness (because user-only code cannot tell the
2426 * difference), and so we need to use a data access endianness
2427 * that depends on SCTLR.B.
2431 ((env
->uncached_cpsr
& CPSR_E
) ? 1 : 0);
2434 cur_el
= arm_current_el(env
);
2437 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
2440 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
2443 #include "exec/cpu-all.h"
2445 /* Bit usage in the TB flags field: bit 31 indicates whether we are
2446 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
2447 * We put flags which are shared between 32 and 64 bit mode at the top
2448 * of the word, and flags which apply to only one mode at the bottom.
2450 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2451 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2452 #define ARM_TBFLAG_MMUIDX_SHIFT 28
2453 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2454 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2455 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2456 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2457 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2458 /* Target EL if we take a floating-point-disabled exception */
2459 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2460 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2462 /* Bit usage when in AArch32 state: */
2463 #define ARM_TBFLAG_THUMB_SHIFT 0
2464 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2465 #define ARM_TBFLAG_VECLEN_SHIFT 1
2466 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2467 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2468 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2469 #define ARM_TBFLAG_VFPEN_SHIFT 7
2470 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2471 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
2472 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2473 #define ARM_TBFLAG_SCTLR_B_SHIFT 16
2474 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2475 /* We store the bottom two bits of the CPAR as TB flags and handle
2476 * checks on the other bits at runtime
2478 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2479 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2480 /* Indicates whether cp register reads and writes by guest code should access
2481 * the secure or nonsecure bank of banked registers; note that this is not
2482 * the same thing as the current security state of the processor!
2484 #define ARM_TBFLAG_NS_SHIFT 19
2485 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2486 #define ARM_TBFLAG_BE_DATA_SHIFT 20
2487 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2488 /* For M profile only, Handler (ie not Thread) mode */
2489 #define ARM_TBFLAG_HANDLER_SHIFT 21
2490 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
2492 /* Bit usage when in AArch64 state */
2493 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
2494 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
2495 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */
2496 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
2498 /* some convenience accessor macros */
2499 #define ARM_TBFLAG_AARCH64_STATE(F) \
2500 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2501 #define ARM_TBFLAG_MMUIDX(F) \
2502 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2503 #define ARM_TBFLAG_SS_ACTIVE(F) \
2504 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2505 #define ARM_TBFLAG_PSTATE_SS(F) \
2506 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2507 #define ARM_TBFLAG_FPEXC_EL(F) \
2508 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2509 #define ARM_TBFLAG_THUMB(F) \
2510 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2511 #define ARM_TBFLAG_VECLEN(F) \
2512 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2513 #define ARM_TBFLAG_VECSTRIDE(F) \
2514 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2515 #define ARM_TBFLAG_VFPEN(F) \
2516 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2517 #define ARM_TBFLAG_CONDEXEC(F) \
2518 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2519 #define ARM_TBFLAG_SCTLR_B(F) \
2520 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2521 #define ARM_TBFLAG_XSCALE_CPAR(F) \
2522 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2523 #define ARM_TBFLAG_NS(F) \
2524 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2525 #define ARM_TBFLAG_BE_DATA(F) \
2526 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2527 #define ARM_TBFLAG_HANDLER(F) \
2528 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
2529 #define ARM_TBFLAG_TBI0(F) \
2530 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
2531 #define ARM_TBFLAG_TBI1(F) \
2532 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT)
2534 static inline bool bswap_code(bool sctlr_b
)
2536 #ifdef CONFIG_USER_ONLY
2537 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
2538 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
2539 * would also end up as a mixed-endian mode with BE code, LE data.
2542 #ifdef TARGET_WORDS_BIGENDIAN
2547 /* All code access in ARM is little endian, and there are no loaders
2548 * doing swaps that need to be reversed
2554 /* Return the exception level to which FP-disabled exceptions should
2555 * be taken, or 0 if FP is enabled.
2557 static inline int fp_exception_el(CPUARMState
*env
)
2560 int cur_el
= arm_current_el(env
);
2562 /* CPACR and the CPTR registers don't exist before v6, so FP is
2565 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
2569 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
2570 * 0, 2 : trap EL0 and EL1/PL1 accesses
2571 * 1 : trap only EL0 accesses
2572 * 3 : trap no accesses
2574 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
2578 if (cur_el
== 0 || cur_el
== 1) {
2579 /* Trap to PL1, which might be EL1 or EL3 */
2580 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
2585 if (cur_el
== 3 && !is_a64(env
)) {
2586 /* Secure PL1 running at EL3 */
2599 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
2600 * check because zero bits in the registers mean "don't trap".
2603 /* CPTR_EL2 : present in v7VE or v8 */
2604 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
2605 && !arm_is_secure_below_el3(env
)) {
2606 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
2610 /* CPTR_EL3 : present in v8 */
2611 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
2612 /* Trap all FP ops to EL3 */
2619 #ifdef CONFIG_USER_ONLY
2620 static inline bool arm_cpu_bswap_data(CPUARMState
*env
)
2623 #ifdef TARGET_WORDS_BIGENDIAN
2626 arm_cpu_data_is_big_endian(env
);
2630 #ifndef CONFIG_USER_ONLY
2634 * @mmu_idx: MMU index indicating required translation regime
2636 * Extracts the TBI0 value from the appropriate TCR for the current EL
2638 * Returns: the TBI0 value.
2640 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
2645 * @mmu_idx: MMU index indicating required translation regime
2647 * Extracts the TBI1 value from the appropriate TCR for the current EL
2649 * Returns: the TBI1 value.
2651 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
2653 /* We can't handle tagged addresses properly in user-only mode */
2654 static inline uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
2659 static inline uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
2665 static inline void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
2666 target_ulong
*cs_base
, uint32_t *flags
)
2668 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
2671 *flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
2672 /* Get control bits for tagged addresses */
2673 *flags
|= (arm_regime_tbi0(env
, mmu_idx
) << ARM_TBFLAG_TBI0_SHIFT
);
2674 *flags
|= (arm_regime_tbi1(env
, mmu_idx
) << ARM_TBFLAG_TBI1_SHIFT
);
2676 *pc
= env
->regs
[15];
2677 *flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
2678 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
2679 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
2680 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
2681 | (arm_sctlr_b(env
) << ARM_TBFLAG_SCTLR_B_SHIFT
);
2682 if (!(access_secure_reg(env
))) {
2683 *flags
|= ARM_TBFLAG_NS_MASK
;
2685 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
2686 || arm_el_is_aa64(env
, 1)) {
2687 *flags
|= ARM_TBFLAG_VFPEN_MASK
;
2689 *flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
2690 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
2693 *flags
|= (arm_to_core_mmu_idx(mmu_idx
) << ARM_TBFLAG_MMUIDX_SHIFT
);
2695 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
2696 * states defined in the ARM ARM for software singlestep:
2697 * SS_ACTIVE PSTATE.SS State
2698 * 0 x Inactive (the TB flag for SS is always 0)
2699 * 1 0 Active-pending
2700 * 1 1 Active-not-pending
2702 if (arm_singlestep_active(env
)) {
2703 *flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
2705 if (env
->pstate
& PSTATE_SS
) {
2706 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
2709 if (env
->uncached_cpsr
& PSTATE_SS
) {
2710 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
2714 if (arm_cpu_data_is_big_endian(env
)) {
2715 *flags
|= ARM_TBFLAG_BE_DATA_MASK
;
2717 *flags
|= fp_exception_el(env
) << ARM_TBFLAG_FPEXC_EL_SHIFT
;
2719 if (arm_v7m_is_handler_mode(env
)) {
2720 *flags
|= ARM_TBFLAG_HANDLER_MASK
;
2727 QEMU_PSCI_CONDUIT_DISABLED
= 0,
2728 QEMU_PSCI_CONDUIT_SMC
= 1,
2729 QEMU_PSCI_CONDUIT_HVC
= 2,
2732 #ifndef CONFIG_USER_ONLY
2733 /* Return the address space index to use for a memory access */
2734 static inline int arm_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
2736 return attrs
.secure
? ARMASIdx_S
: ARMASIdx_NS
;
2739 /* Return the AddressSpace to use for a memory access
2740 * (which depends on whether the access is S or NS, and whether
2741 * the board gave us a separate AddressSpace for S accesses).
2743 static inline AddressSpace
*arm_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
2745 return cpu_get_address_space(cs
, arm_asidx_from_attrs(cs
, attrs
));
2750 * arm_register_el_change_hook:
2751 * Register a hook function which will be called back whenever this
2752 * CPU changes exception level or mode. The hook function will be
2753 * passed a pointer to the ARMCPU and the opaque data pointer passed
2754 * to this function when the hook was registered.
2756 * Note that we currently only support registering a single hook function,
2757 * and will assert if this function is called twice.
2758 * This facility is intended for the use of the GICv3 emulation.
2760 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
2764 * arm_get_el_change_hook_opaque:
2765 * Return the opaque data that will be used by the el_change_hook
2768 static inline void *arm_get_el_change_hook_opaque(ARMCPU
*cpu
)
2770 return cpu
->el_change_hook_opaque
;