target/ppc/helper_regs.c

   1 /*
   2  *  PowerPC emulation special registers manipulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "qemu/main-loop.h"
  23 #include "exec/exec-all.h"
  24 #include "sysemu/kvm.h"
  25 #include "helper_regs.h"
  26 #include "power8-pmu.h"
  27 #include "cpu-models.h"
  28 #include "spr_common.h"
  29
  30 /* Swap temporary saved registers with GPRs */
  31 void hreg_swap_gpr_tgpr(CPUPPCState *env)
  32 {
  33     target_ulong tmp;
  34
  35     tmp = env->gpr[0];
  36     env->gpr[0] = env->tgpr[0];
  37     env->tgpr[0] = tmp;
  38     tmp = env->gpr[1];
  39     env->gpr[1] = env->tgpr[1];
  40     env->tgpr[1] = tmp;
  41     tmp = env->gpr[2];
  42     env->gpr[2] = env->tgpr[2];
  43     env->tgpr[2] = tmp;
  44     tmp = env->gpr[3];
  45     env->gpr[3] = env->tgpr[3];
  46     env->tgpr[3] = tmp;
  47 }
  48
  49 static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
  50 {
  51     target_ulong msr = env->msr;
  52     uint32_t ppc_flags = env->flags;
  53     uint32_t hflags = 0;
  54     uint32_t msr_mask;
  55
  56     /* Some bits come straight across from MSR. */
  57     QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
  58     QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
  59     QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
  60     QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
  61     msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
  62                 (1 << MSR_DR) | (1 << MSR_FP));
  63
  64     if (ppc_flags & POWERPC_FLAG_DE) {
  65         target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
  66         if ((dbcr0 & DBCR0_ICMP) && FIELD_EX64(env->msr, MSR, DE)) {
  67             hflags |= 1 << HFLAGS_SE;
  68         }
  69         if ((dbcr0 & DBCR0_BRT) && FIELD_EX64(env->msr, MSR, DE)) {
  70             hflags |= 1 << HFLAGS_BE;
  71         }
  72     } else {
  73         if (ppc_flags & POWERPC_FLAG_BE) {
  74             QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
  75             msr_mask |= 1 << MSR_BE;
  76         }
  77         if (ppc_flags & POWERPC_FLAG_SE) {
  78             QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
  79             msr_mask |= 1 << MSR_SE;
  80         }
  81     }
  82
  83     if (msr_is_64bit(env, msr)) {
  84         hflags |= 1 << HFLAGS_64;
  85     }
  86     if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
  87         hflags |= 1 << HFLAGS_SPE;
  88     }
  89     if (ppc_flags & POWERPC_FLAG_VRE) {
  90         QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
  91         msr_mask |= 1 << MSR_VR;
  92     }
  93     if (ppc_flags & POWERPC_FLAG_VSX) {
  94         QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
  95         msr_mask |= 1 << MSR_VSX;
  96     }
  97     if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
  98         hflags |= 1 << HFLAGS_TM;
  99     }
 100     if (env->spr[SPR_LPCR] & LPCR_GTSE) {
 101         hflags |= 1 << HFLAGS_GTSE;
 102     }
 103     if (env->spr[SPR_LPCR] & LPCR_HR) {
 104         hflags |= 1 << HFLAGS_HR;
 105     }
 106     if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) {
 107         hflags |= 1 << HFLAGS_PMCC0;
 108     }
 109     if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
 110         hflags |= 1 << HFLAGS_PMCC1;
 111     }
 112
 113 #ifndef CONFIG_USER_ONLY
 114     if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
 115         hflags |= 1 << HFLAGS_HV;
 116     }
 117
 118 #if defined(TARGET_PPC64)
 119     if (env->pmc_ins_cnt) {
 120         hflags |= 1 << HFLAGS_INSN_CNT;
 121     }
 122 #endif
 123
 124     /*
 125      * This is our encoding for server processors. The architecture
 126      * specifies that there is no such thing as userspace with
 127      * translation off, however it appears that MacOS does it and some
 128      * 32-bit CPUs support it. Weird...
 129      *
 130      *   0 = Guest User space virtual mode
 131      *   1 = Guest Kernel space virtual mode
 132      *   2 = Guest User space real mode
 133      *   3 = Guest Kernel space real mode
 134      *   4 = HV User space virtual mode
 135      *   5 = HV Kernel space virtual mode
 136      *   6 = HV User space real mode
 137      *   7 = HV Kernel space real mode
 138      *
 139      * For BookE, we need 8 MMU modes as follow:
 140      *
 141      *  0 = AS 0 HV User space
 142      *  1 = AS 0 HV Kernel space
 143      *  2 = AS 1 HV User space
 144      *  3 = AS 1 HV Kernel space
 145      *  4 = AS 0 Guest User space
 146      *  5 = AS 0 Guest Kernel space
 147      *  6 = AS 1 Guest User space
 148      *  7 = AS 1 Guest Kernel space
 149      */
 150     unsigned immu_idx, dmmu_idx;
 151     dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1;
 152     if (env->mmu_model == POWERPC_MMU_BOOKE ||
 153         env->mmu_model == POWERPC_MMU_BOOKE206) {
 154         dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0;
 155         immu_idx = dmmu_idx;
 156         immu_idx |= msr & (1 << MSR_IS) ? 2 : 0;
 157         dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0;
 158     } else {
 159         dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0;
 160         immu_idx = dmmu_idx;
 161         immu_idx |= msr & (1 << MSR_IR) ? 0 : 2;
 162         dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2;
 163     }
 164     hflags |= immu_idx << HFLAGS_IMMU_IDX;
 165     hflags |= dmmu_idx << HFLAGS_DMMU_IDX;
 166 #endif
 167
 168     return hflags | (msr & msr_mask);
 169 }
 170
 171 void hreg_compute_hflags(CPUPPCState *env)
 172 {
 173     env->hflags = hreg_compute_hflags_value(env);
 174 }
 175
 176 #ifdef CONFIG_DEBUG_TCG
 177 void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
 178                           target_ulong *cs_base, uint32_t *flags)
 179 {
 180     uint32_t hflags_current = env->hflags;
 181     uint32_t hflags_rebuilt;
 182
 183     *pc = env->nip;
 184     *cs_base = 0;
 185     *flags = hflags_current;
 186
 187     hflags_rebuilt = hreg_compute_hflags_value(env);
 188     if (unlikely(hflags_current != hflags_rebuilt)) {
 189         cpu_abort(env_cpu(env),
 190                   "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
 191                   hflags_current, hflags_rebuilt);
 192     }
 193 }
 194 #endif
 195
 196 void cpu_interrupt_exittb(CPUState *cs)
 197 {
 198     /*
 199      * We don't need to worry about translation blocks
 200      * when running with KVM.
 201      */
 202     if (kvm_enabled()) {
 203         return;
 204     }
 205
 206     if (!qemu_mutex_iothread_locked()) {
 207         qemu_mutex_lock_iothread();
 208         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 209         qemu_mutex_unlock_iothread();
 210     } else {
 211         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 212     }
 213 }
 214
 215 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
 216 {
 217     int excp;
 218 #if !defined(CONFIG_USER_ONLY)
 219     CPUState *cs = env_cpu(env);
 220 #endif
 221
 222     excp = 0;
 223     value &= env->msr_mask;
 224 #if !defined(CONFIG_USER_ONLY)
 225     /* Neither mtmsr nor guest state can alter HV */
 226     if (!alter_hv || !(env->msr & MSR_HVB)) {
 227         value &= ~MSR_HVB;
 228         value |= env->msr & MSR_HVB;
 229     }
 230     if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
 231         cpu_interrupt_exittb(cs);
 232     }
 233     if ((env->mmu_model == POWERPC_MMU_BOOKE ||
 234          env->mmu_model == POWERPC_MMU_BOOKE206) &&
 235         ((value ^ env->msr) & R_MSR_GS_MASK)) {
 236         cpu_interrupt_exittb(cs);
 237     }
 238     if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
 239                  ((value ^ env->msr) & (1 << MSR_TGPR)))) {
 240         /* Swap temporary saved registers with GPRs */
 241         hreg_swap_gpr_tgpr(env);
 242     }
 243     if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) {
 244         env->excp_prefix = FIELD_EX64(value, MSR, EP) * 0xFFF00000;
 245     }
 246     /*
 247      * If PR=1 then EE, IR and DR must be 1
 248      *
 249      * Note: We only enforce this on 64-bit server processors.
 250      * It appears that:
 251      * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
 252      *   exploits it.
 253      * - 64-bit embedded implementations do not need any operation to be
 254      *   performed when PR is set.
 255      */
 256     if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
 257         value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
 258     }
 259 #endif
 260     env->msr = value;
 261     hreg_compute_hflags(env);
 262 #if !defined(CONFIG_USER_ONLY)
 263     if (unlikely(FIELD_EX64(env->msr, MSR, POW))) {
 264         if (!env->pending_interrupts && (*env->check_pow)(env)) {
 265             cs->halted = 1;
 266             excp = EXCP_HALTED;
 267         }
 268     }
 269 #endif
 270
 271     return excp;
 272 }
 273
 274 #ifdef CONFIG_SOFTMMU
 275 void store_40x_sler(CPUPPCState *env, uint32_t val)
 276 {
 277     /* XXX: TO BE FIXED */
 278     if (val != 0x00000000) {
 279         cpu_abort(env_cpu(env),
 280                   "Little-endian regions are not supported by now\n");
 281     }
 282     env->spr[SPR_405_SLER] = val;
 283 }
 284 #endif /* CONFIG_SOFTMMU */
 285
 286 #ifndef CONFIG_USER_ONLY
 287 void check_tlb_flush(CPUPPCState *env, bool global)
 288 {
 289     CPUState *cs = env_cpu(env);
 290
 291     /* Handle global flushes first */
 292     if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
 293         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
 294         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 295         tlb_flush_all_cpus(cs);
 296         return;
 297     }
 298
 299     /* Then handle local ones */
 300     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
 301         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 302         tlb_flush(cs);
 303     }
 304 }
 305 #endif
 306
 307 /**
 308  * _spr_register
 309  *
 310  * Register an SPR with all the callbacks required for tcg,
 311  * and the ID number for KVM.
 312  *
 313  * The reason for the conditional compilation is that the tcg functions
 314  * may be compiled out, and the system kvm header may not be available
 315  * for supplying the ID numbers.  This is ugly, but the best we can do.
 316  */
 317 void _spr_register(CPUPPCState *env, int num, const char *name,
 318                    USR_ARG(spr_callback *uea_read)
 319                    USR_ARG(spr_callback *uea_write)
 320                    SYS_ARG(spr_callback *oea_read)
 321                    SYS_ARG(spr_callback *oea_write)
 322                    SYS_ARG(spr_callback *hea_read)
 323                    SYS_ARG(spr_callback *hea_write)
 324                    KVM_ARG(uint64_t one_reg_id)
 325                    target_ulong initial_value)
 326 {
 327     ppc_spr_t *spr = &env->spr_cb[num];
 328
 329     /* No SPR should be registered twice. */
 330     assert(spr->name == NULL);
 331     assert(name != NULL);
 332
 333     spr->name = name;
 334     spr->default_value = initial_value;
 335     env->spr[num] = initial_value;
 336
 337 #ifdef CONFIG_TCG
 338     spr->uea_read = uea_read;
 339     spr->uea_write = uea_write;
 340 # ifndef CONFIG_USER_ONLY
 341     spr->oea_read = oea_read;
 342     spr->oea_write = oea_write;
 343     spr->hea_read = hea_read;
 344     spr->hea_write = hea_write;
 345 # endif
 346 #endif
 347 #ifdef CONFIG_KVM
 348     spr->one_reg_id = one_reg_id;
 349 #endif
 350 }
 351
 352 /* Generic PowerPC SPRs */
 353 void register_generic_sprs(PowerPCCPU *cpu)
 354 {
 355     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 356     CPUPPCState *env = &cpu->env;
 357
 358     /* Integer processing */
 359     spr_register(env, SPR_XER, "XER",
 360                  &spr_read_xer, &spr_write_xer,
 361                  &spr_read_xer, &spr_write_xer,
 362                  0x00000000);
 363     /* Branch control */
 364     spr_register(env, SPR_LR, "LR",
 365                  &spr_read_lr, &spr_write_lr,
 366                  &spr_read_lr, &spr_write_lr,
 367                  0x00000000);
 368     spr_register(env, SPR_CTR, "CTR",
 369                  &spr_read_ctr, &spr_write_ctr,
 370                  &spr_read_ctr, &spr_write_ctr,
 371                  0x00000000);
 372     /* Interrupt processing */
 373     spr_register(env, SPR_SRR0, "SRR0",
 374                  SPR_NOACCESS, SPR_NOACCESS,
 375                  &spr_read_generic, &spr_write_generic,
 376                  0x00000000);
 377     spr_register(env, SPR_SRR1, "SRR1",
 378                  SPR_NOACCESS, SPR_NOACCESS,
 379                  &spr_read_generic, &spr_write_generic,
 380                  0x00000000);
 381     /* Processor control */
 382     spr_register(env, SPR_SPRG0, "SPRG0",
 383                  SPR_NOACCESS, SPR_NOACCESS,
 384                  &spr_read_generic, &spr_write_generic,
 385                  0x00000000);
 386     spr_register(env, SPR_SPRG1, "SPRG1",
 387                  SPR_NOACCESS, SPR_NOACCESS,
 388                  &spr_read_generic, &spr_write_generic,
 389                  0x00000000);
 390     spr_register(env, SPR_SPRG2, "SPRG2",
 391                  SPR_NOACCESS, SPR_NOACCESS,
 392                  &spr_read_generic, &spr_write_generic,
 393                  0x00000000);
 394     spr_register(env, SPR_SPRG3, "SPRG3",
 395                  SPR_NOACCESS, SPR_NOACCESS,
 396                  &spr_read_generic, &spr_write_generic,
 397                  0x00000000);
 398
 399     spr_register(env, SPR_PVR, "PVR",
 400                  /* Linux permits userspace to read PVR */
 401 #if defined(CONFIG_LINUX_USER)
 402                  &spr_read_generic,
 403 #else
 404                  SPR_NOACCESS,
 405 #endif
 406                  SPR_NOACCESS,
 407                  &spr_read_generic, SPR_NOACCESS,
 408                  pcc->pvr);
 409
 410     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
 411     if (pcc->svr != POWERPC_SVR_NONE) {
 412         if (pcc->svr & POWERPC_SVR_E500) {
 413             spr_register(env, SPR_E500_SVR, "SVR",
 414                          SPR_NOACCESS, SPR_NOACCESS,
 415                          &spr_read_generic, SPR_NOACCESS,
 416                          pcc->svr & ~POWERPC_SVR_E500);
 417         } else {
 418             spr_register(env, SPR_SVR, "SVR",
 419                          SPR_NOACCESS, SPR_NOACCESS,
 420                          &spr_read_generic, SPR_NOACCESS,
 421                          pcc->svr);
 422         }
 423     }
 424
 425     /* Time base */
 426     spr_register(env, SPR_VTBL,  "TBL",
 427                  &spr_read_tbl, SPR_NOACCESS,
 428                  &spr_read_tbl, SPR_NOACCESS,
 429                  0x00000000);
 430     spr_register(env, SPR_TBL,   "TBL",
 431                  &spr_read_tbl, SPR_NOACCESS,
 432                  &spr_read_tbl, &spr_write_tbl,
 433                  0x00000000);
 434     spr_register(env, SPR_VTBU,  "TBU",
 435                  &spr_read_tbu, SPR_NOACCESS,
 436                  &spr_read_tbu, SPR_NOACCESS,
 437                  0x00000000);
 438     spr_register(env, SPR_TBU,   "TBU",
 439                  &spr_read_tbu, SPR_NOACCESS,
 440                  &spr_read_tbu, &spr_write_tbu,
 441                  0x00000000);
 442 }
 443
 444 void register_non_embedded_sprs(CPUPPCState *env)
 445 {
 446     /* Exception processing */
 447     spr_register_kvm(env, SPR_DSISR, "DSISR",
 448                      SPR_NOACCESS, SPR_NOACCESS,
 449                      &spr_read_generic, &spr_write_generic,
 450                      KVM_REG_PPC_DSISR, 0x00000000);
 451     spr_register_kvm(env, SPR_DAR, "DAR",
 452                      SPR_NOACCESS, SPR_NOACCESS,
 453                      &spr_read_generic, &spr_write_generic,
 454                      KVM_REG_PPC_DAR, 0x00000000);
 455     /* Timer */
 456     spr_register(env, SPR_DECR, "DECR",
 457                  SPR_NOACCESS, SPR_NOACCESS,
 458                  &spr_read_decr, &spr_write_decr,
 459                  0x00000000);
 460 }
 461
 462 /* Storage Description Register 1 */
 463 void register_sdr1_sprs(CPUPPCState *env)
 464 {
 465 #ifndef CONFIG_USER_ONLY
 466     if (env->has_hv_mode) {
 467         /*
 468          * SDR1 is a hypervisor resource on CPUs which have a
 469          * hypervisor mode
 470          */
 471         spr_register_hv(env, SPR_SDR1, "SDR1",
 472                         SPR_NOACCESS, SPR_NOACCESS,
 473                         SPR_NOACCESS, SPR_NOACCESS,
 474                         &spr_read_generic, &spr_write_sdr1,
 475                         0x00000000);
 476     } else {
 477         spr_register(env, SPR_SDR1, "SDR1",
 478                      SPR_NOACCESS, SPR_NOACCESS,
 479                      &spr_read_generic, &spr_write_sdr1,
 480                      0x00000000);
 481     }
 482 #endif
 483 }
 484
 485 /* BATs 0-3 */
 486 void register_low_BATs(CPUPPCState *env)
 487 {
 488 #if !defined(CONFIG_USER_ONLY)
 489     spr_register(env, SPR_IBAT0U, "IBAT0U",
 490                  SPR_NOACCESS, SPR_NOACCESS,
 491                  &spr_read_ibat, &spr_write_ibatu,
 492                  0x00000000);
 493     spr_register(env, SPR_IBAT0L, "IBAT0L",
 494                  SPR_NOACCESS, SPR_NOACCESS,
 495                  &spr_read_ibat, &spr_write_ibatl,
 496                  0x00000000);
 497     spr_register(env, SPR_IBAT1U, "IBAT1U",
 498                  SPR_NOACCESS, SPR_NOACCESS,
 499                  &spr_read_ibat, &spr_write_ibatu,
 500                  0x00000000);
 501     spr_register(env, SPR_IBAT1L, "IBAT1L",
 502                  SPR_NOACCESS, SPR_NOACCESS,
 503                  &spr_read_ibat, &spr_write_ibatl,
 504                  0x00000000);
 505     spr_register(env, SPR_IBAT2U, "IBAT2U",
 506                  SPR_NOACCESS, SPR_NOACCESS,
 507                  &spr_read_ibat, &spr_write_ibatu,
 508                  0x00000000);
 509     spr_register(env, SPR_IBAT2L, "IBAT2L",
 510                  SPR_NOACCESS, SPR_NOACCESS,
 511                  &spr_read_ibat, &spr_write_ibatl,
 512                  0x00000000);
 513     spr_register(env, SPR_IBAT3U, "IBAT3U",
 514                  SPR_NOACCESS, SPR_NOACCESS,
 515                  &spr_read_ibat, &spr_write_ibatu,
 516                  0x00000000);
 517     spr_register(env, SPR_IBAT3L, "IBAT3L",
 518                  SPR_NOACCESS, SPR_NOACCESS,
 519                  &spr_read_ibat, &spr_write_ibatl,
 520                  0x00000000);
 521     spr_register(env, SPR_DBAT0U, "DBAT0U",
 522                  SPR_NOACCESS, SPR_NOACCESS,
 523                  &spr_read_dbat, &spr_write_dbatu,
 524                  0x00000000);
 525     spr_register(env, SPR_DBAT0L, "DBAT0L",
 526                  SPR_NOACCESS, SPR_NOACCESS,
 527                  &spr_read_dbat, &spr_write_dbatl,
 528                  0x00000000);
 529     spr_register(env, SPR_DBAT1U, "DBAT1U",
 530                  SPR_NOACCESS, SPR_NOACCESS,
 531                  &spr_read_dbat, &spr_write_dbatu,
 532                  0x00000000);
 533     spr_register(env, SPR_DBAT1L, "DBAT1L",
 534                  SPR_NOACCESS, SPR_NOACCESS,
 535                  &spr_read_dbat, &spr_write_dbatl,
 536                  0x00000000);
 537     spr_register(env, SPR_DBAT2U, "DBAT2U",
 538                  SPR_NOACCESS, SPR_NOACCESS,
 539                  &spr_read_dbat, &spr_write_dbatu,
 540                  0x00000000);
 541     spr_register(env, SPR_DBAT2L, "DBAT2L",
 542                  SPR_NOACCESS, SPR_NOACCESS,
 543                  &spr_read_dbat, &spr_write_dbatl,
 544                  0x00000000);
 545     spr_register(env, SPR_DBAT3U, "DBAT3U",
 546                  SPR_NOACCESS, SPR_NOACCESS,
 547                  &spr_read_dbat, &spr_write_dbatu,
 548                  0x00000000);
 549     spr_register(env, SPR_DBAT3L, "DBAT3L",
 550                  SPR_NOACCESS, SPR_NOACCESS,
 551                  &spr_read_dbat, &spr_write_dbatl,
 552                  0x00000000);
 553     env->nb_BATs += 4;
 554 #endif
 555 }
 556
 557 /* BATs 4-7 */
 558 void register_high_BATs(CPUPPCState *env)
 559 {
 560 #if !defined(CONFIG_USER_ONLY)
 561     spr_register(env, SPR_IBAT4U, "IBAT4U",
 562                  SPR_NOACCESS, SPR_NOACCESS,
 563                  &spr_read_ibat_h, &spr_write_ibatu_h,
 564                  0x00000000);
 565     spr_register(env, SPR_IBAT4L, "IBAT4L",
 566                  SPR_NOACCESS, SPR_NOACCESS,
 567                  &spr_read_ibat_h, &spr_write_ibatl_h,
 568                  0x00000000);
 569     spr_register(env, SPR_IBAT5U, "IBAT5U",
 570                  SPR_NOACCESS, SPR_NOACCESS,
 571                  &spr_read_ibat_h, &spr_write_ibatu_h,
 572                  0x00000000);
 573     spr_register(env, SPR_IBAT5L, "IBAT5L",
 574                  SPR_NOACCESS, SPR_NOACCESS,
 575                  &spr_read_ibat_h, &spr_write_ibatl_h,
 576                  0x00000000);
 577     spr_register(env, SPR_IBAT6U, "IBAT6U",
 578                  SPR_NOACCESS, SPR_NOACCESS,
 579                  &spr_read_ibat_h, &spr_write_ibatu_h,
 580                  0x00000000);
 581     spr_register(env, SPR_IBAT6L, "IBAT6L",
 582                  SPR_NOACCESS, SPR_NOACCESS,
 583                  &spr_read_ibat_h, &spr_write_ibatl_h,
 584                  0x00000000);
 585     spr_register(env, SPR_IBAT7U, "IBAT7U",
 586                  SPR_NOACCESS, SPR_NOACCESS,
 587                  &spr_read_ibat_h, &spr_write_ibatu_h,
 588                  0x00000000);
 589     spr_register(env, SPR_IBAT7L, "IBAT7L",
 590                  SPR_NOACCESS, SPR_NOACCESS,
 591                  &spr_read_ibat_h, &spr_write_ibatl_h,
 592                  0x00000000);
 593     spr_register(env, SPR_DBAT4U, "DBAT4U",
 594                  SPR_NOACCESS, SPR_NOACCESS,
 595                  &spr_read_dbat_h, &spr_write_dbatu_h,
 596                  0x00000000);
 597     spr_register(env, SPR_DBAT4L, "DBAT4L",
 598                  SPR_NOACCESS, SPR_NOACCESS,
 599                  &spr_read_dbat_h, &spr_write_dbatl_h,
 600                  0x00000000);
 601     spr_register(env, SPR_DBAT5U, "DBAT5U",
 602                  SPR_NOACCESS, SPR_NOACCESS,
 603                  &spr_read_dbat_h, &spr_write_dbatu_h,
 604                  0x00000000);
 605     spr_register(env, SPR_DBAT5L, "DBAT5L",
 606                  SPR_NOACCESS, SPR_NOACCESS,
 607                  &spr_read_dbat_h, &spr_write_dbatl_h,
 608                  0x00000000);
 609     spr_register(env, SPR_DBAT6U, "DBAT6U",
 610                  SPR_NOACCESS, SPR_NOACCESS,
 611                  &spr_read_dbat_h, &spr_write_dbatu_h,
 612                  0x00000000);
 613     spr_register(env, SPR_DBAT6L, "DBAT6L",
 614                  SPR_NOACCESS, SPR_NOACCESS,
 615                  &spr_read_dbat_h, &spr_write_dbatl_h,
 616                  0x00000000);
 617     spr_register(env, SPR_DBAT7U, "DBAT7U",
 618                  SPR_NOACCESS, SPR_NOACCESS,
 619                  &spr_read_dbat_h, &spr_write_dbatu_h,
 620                  0x00000000);
 621     spr_register(env, SPR_DBAT7L, "DBAT7L",
 622                  SPR_NOACCESS, SPR_NOACCESS,
 623                  &spr_read_dbat_h, &spr_write_dbatl_h,
 624                  0x00000000);
 625     env->nb_BATs += 4;
 626 #endif
 627 }
 628
 629 /* Softare table search registers */
 630 void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
 631 {
 632 #if !defined(CONFIG_USER_ONLY)
 633     env->nb_tlb = nb_tlbs;
 634     env->nb_ways = nb_ways;
 635     env->id_tlbs = 1;
 636     env->tlb_type = TLB_6XX;
 637     spr_register(env, SPR_DMISS, "DMISS",
 638                  SPR_NOACCESS, SPR_NOACCESS,
 639                  &spr_read_generic, SPR_NOACCESS,
 640                  0x00000000);
 641     spr_register(env, SPR_DCMP, "DCMP",
 642                  SPR_NOACCESS, SPR_NOACCESS,
 643                  &spr_read_generic, SPR_NOACCESS,
 644                  0x00000000);
 645     spr_register(env, SPR_HASH1, "HASH1",
 646                  SPR_NOACCESS, SPR_NOACCESS,
 647                  &spr_read_generic, SPR_NOACCESS,
 648                  0x00000000);
 649     spr_register(env, SPR_HASH2, "HASH2",
 650                  SPR_NOACCESS, SPR_NOACCESS,
 651                  &spr_read_generic, SPR_NOACCESS,
 652                  0x00000000);
 653     spr_register(env, SPR_IMISS, "IMISS",
 654                  SPR_NOACCESS, SPR_NOACCESS,
 655                  &spr_read_generic, SPR_NOACCESS,
 656                  0x00000000);
 657     spr_register(env, SPR_ICMP, "ICMP",
 658                  SPR_NOACCESS, SPR_NOACCESS,
 659                  &spr_read_generic, SPR_NOACCESS,
 660                  0x00000000);
 661     spr_register(env, SPR_RPA, "RPA",
 662                  SPR_NOACCESS, SPR_NOACCESS,
 663                  &spr_read_generic, &spr_write_generic,
 664                  0x00000000);
 665 #endif
 666 }
 667
 668 void register_thrm_sprs(CPUPPCState *env)
 669 {
 670     /* Thermal management */
 671     spr_register(env, SPR_THRM1, "THRM1",
 672                  SPR_NOACCESS, SPR_NOACCESS,
 673                  &spr_read_thrm, &spr_write_generic,
 674                  0x00000000);
 675
 676     spr_register(env, SPR_THRM2, "THRM2",
 677                  SPR_NOACCESS, SPR_NOACCESS,
 678                  &spr_read_thrm, &spr_write_generic,
 679                  0x00000000);
 680
 681     spr_register(env, SPR_THRM3, "THRM3",
 682                  SPR_NOACCESS, SPR_NOACCESS,
 683                  &spr_read_thrm, &spr_write_generic,
 684                  0x00000000);
 685 }
 686
 687 void register_usprgh_sprs(CPUPPCState *env)
 688 {
 689     spr_register(env, SPR_USPRG4, "USPRG4",
 690                  &spr_read_ureg, SPR_NOACCESS,
 691                  &spr_read_ureg, SPR_NOACCESS,
 692                  0x00000000);
 693     spr_register(env, SPR_USPRG5, "USPRG5",
 694                  &spr_read_ureg, SPR_NOACCESS,
 695                  &spr_read_ureg, SPR_NOACCESS,
 696                  0x00000000);
 697     spr_register(env, SPR_USPRG6, "USPRG6",
 698                  &spr_read_ureg, SPR_NOACCESS,
 699                  &spr_read_ureg, SPR_NOACCESS,
 700                  0x00000000);
 701     spr_register(env, SPR_USPRG7, "USPRG7",
 702                  &spr_read_ureg, SPR_NOACCESS,
 703                  &spr_read_ureg, SPR_NOACCESS,
 704                  0x00000000);
 705 }