hw/sd/pxa2xx_mmci.c

   1 /*
   2  * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "hw/hw.h"
  16 #include "hw/sysbus.h"
  17 #include "hw/arm/pxa.h"
  18 #include "hw/sd/sd.h"
  19 #include "hw/qdev.h"
  20 #include "hw/qdev-properties.h"
  21 #include "qemu/error-report.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24 #include "trace.h"
  25
  26 #define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
  27 #define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
  28
  29 #define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
  30 #define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)
  31
  32 struct PXA2xxMMCIState {
  33     SysBusDevice parent_obj;
  34
  35     MemoryRegion iomem;
  36     qemu_irq irq;
  37     qemu_irq rx_dma;
  38     qemu_irq tx_dma;
  39     qemu_irq inserted;
  40     qemu_irq readonly;
  41
  42     BlockBackend *blk;
  43     SDBus sdbus;
  44
  45     uint32_t status;
  46     uint32_t clkrt;
  47     uint32_t spi;
  48     uint32_t cmdat;
  49     uint32_t resp_tout;
  50     uint32_t read_tout;
  51     int32_t blklen;
  52     int32_t numblk;
  53     uint32_t intmask;
  54     uint32_t intreq;
  55     int32_t cmd;
  56     uint32_t arg;
  57
  58     int32_t active;
  59     int32_t bytesleft;
  60     uint8_t tx_fifo[64];
  61     uint32_t tx_start;
  62     uint32_t tx_len;
  63     uint8_t rx_fifo[32];
  64     uint32_t rx_start;
  65     uint32_t rx_len;
  66     uint16_t resp_fifo[9];
  67     uint32_t resp_len;
  68
  69     int32_t cmdreq;
  70 };
  71
  72 static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
  73 {
  74     PXA2xxMMCIState *s = opaque;
  75
  76     return s->tx_start < ARRAY_SIZE(s->tx_fifo)
  77         && s->rx_start < ARRAY_SIZE(s->rx_fifo)
  78         && s->tx_len <= ARRAY_SIZE(s->tx_fifo)
  79         && s->rx_len <= ARRAY_SIZE(s->rx_fifo)
  80         && s->resp_len <= ARRAY_SIZE(s->resp_fifo);
  81 }
  82
  83
  84 static const VMStateDescription vmstate_pxa2xx_mmci = {
  85     .name = "pxa2xx-mmci",
  86     .version_id = 2,
  87     .minimum_version_id = 2,
  88     .fields = (VMStateField[]) {
  89         VMSTATE_UINT32(status, PXA2xxMMCIState),
  90         VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
  91         VMSTATE_UINT32(spi, PXA2xxMMCIState),
  92         VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
  93         VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
  94         VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
  95         VMSTATE_INT32(blklen, PXA2xxMMCIState),
  96         VMSTATE_INT32(numblk, PXA2xxMMCIState),
  97         VMSTATE_UINT32(intmask, PXA2xxMMCIState),
  98         VMSTATE_UINT32(intreq, PXA2xxMMCIState),
  99         VMSTATE_INT32(cmd, PXA2xxMMCIState),
 100         VMSTATE_UINT32(arg, PXA2xxMMCIState),
 101         VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
 102         VMSTATE_INT32(active, PXA2xxMMCIState),
 103         VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
 104         VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
 105         VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
 106         VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
 107         VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
 108         VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
 109         VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
 110         VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
 111         VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
 112         VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
 113         VMSTATE_END_OF_LIST()
 114     }
 115 };
 116
 117 #define MMC_STRPCL      0x00    /* MMC Clock Start/Stop register */
 118 #define MMC_STAT        0x04    /* MMC Status register */
 119 #define MMC_CLKRT       0x08    /* MMC Clock Rate register */
 120 #define MMC_SPI         0x0c    /* MMC SPI Mode register */
 121 #define MMC_CMDAT       0x10    /* MMC Command/Data register */
 122 #define MMC_RESTO       0x14    /* MMC Response Time-Out register */
 123 #define MMC_RDTO        0x18    /* MMC Read Time-Out register */
 124 #define MMC_BLKLEN      0x1c    /* MMC Block Length register */
 125 #define MMC_NUMBLK      0x20    /* MMC Number of Blocks register */
 126 #define MMC_PRTBUF      0x24    /* MMC Buffer Partly Full register */
 127 #define MMC_I_MASK      0x28    /* MMC Interrupt Mask register */
 128 #define MMC_I_REG       0x2c    /* MMC Interrupt Request register */
 129 #define MMC_CMD         0x30    /* MMC Command register */
 130 #define MMC_ARGH        0x34    /* MMC Argument High register */
 131 #define MMC_ARGL        0x38    /* MMC Argument Low register */
 132 #define MMC_RES         0x3c    /* MMC Response FIFO */
 133 #define MMC_RXFIFO      0x40    /* MMC Receive FIFO */
 134 #define MMC_TXFIFO      0x44    /* MMC Transmit FIFO */
 135 #define MMC_RDWAIT      0x48    /* MMC RD_WAIT register */
 136 #define MMC_BLKS_REM    0x4c    /* MMC Blocks Remaining register */
 137
 138 /* Bitfield masks */
 139 #define STRPCL_STOP_CLK (1 << 0)
 140 #define STRPCL_STRT_CLK (1 << 1)
 141 #define STAT_TOUT_RES   (1 << 1)
 142 #define STAT_CLK_EN     (1 << 8)
 143 #define STAT_DATA_DONE  (1 << 11)
 144 #define STAT_PRG_DONE   (1 << 12)
 145 #define STAT_END_CMDRES (1 << 13)
 146 #define SPI_SPI_MODE    (1 << 0)
 147 #define CMDAT_RES_TYPE  (3 << 0)
 148 #define CMDAT_DATA_EN   (1 << 2)
 149 #define CMDAT_WR_RD     (1 << 3)
 150 #define CMDAT_DMA_EN    (1 << 7)
 151 #define CMDAT_STOP_TRAN (1 << 10)
 152 #define INT_DATA_DONE   (1 << 0)
 153 #define INT_PRG_DONE    (1 << 1)
 154 #define INT_END_CMD     (1 << 2)
 155 #define INT_STOP_CMD    (1 << 3)
 156 #define INT_CLK_OFF     (1 << 4)
 157 #define INT_RXFIFO_REQ  (1 << 5)
 158 #define INT_TXFIFO_REQ  (1 << 6)
 159 #define INT_TINT        (1 << 7)
 160 #define INT_DAT_ERR     (1 << 8)
 161 #define INT_RES_ERR     (1 << 9)
 162 #define INT_RD_STALLED  (1 << 10)
 163 #define INT_SDIO_INT    (1 << 11)
 164 #define INT_SDIO_SACK   (1 << 12)
 165 #define PRTBUF_PRT_BUF  (1 << 0)
 166
 167 /* Route internal interrupt lines to the global IC and DMA */
 168 static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
 169 {
 170     uint32_t mask = s->intmask;
 171     if (s->cmdat & CMDAT_DMA_EN) {
 172         mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
 173
 174         qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
 175         qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
 176     }
 177
 178     qemu_set_irq(s->irq, !!(s->intreq & ~mask));
 179 }
 180
 181 static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
 182 {
 183     if (!s->active)
 184         return;
 185
 186     if (s->cmdat & CMDAT_WR_RD) {
 187         while (s->bytesleft && s->tx_len) {
 188             sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
 189             s->tx_start &= 0x1f;
 190             s->tx_len --;
 191             s->bytesleft --;
 192         }
 193         if (s->bytesleft)
 194             s->intreq |= INT_TXFIFO_REQ;
 195     } else
 196         while (s->bytesleft && s->rx_len < 32) {
 197             s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
 198                 sdbus_read_data(&s->sdbus);
 199             s->bytesleft --;
 200             s->intreq |= INT_RXFIFO_REQ;
 201         }
 202
 203     if (!s->bytesleft) {
 204         s->active = 0;
 205         s->intreq |= INT_DATA_DONE;
 206         s->status |= STAT_DATA_DONE;
 207
 208         if (s->cmdat & CMDAT_WR_RD) {
 209             s->intreq |= INT_PRG_DONE;
 210             s->status |= STAT_PRG_DONE;
 211         }
 212     }
 213
 214     pxa2xx_mmci_int_update(s);
 215 }
 216
 217 static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
 218 {
 219     int rsplen, i;
 220     SDRequest request;
 221     uint8_t response[16];
 222
 223     s->active = 1;
 224     s->rx_len = 0;
 225     s->tx_len = 0;
 226     s->cmdreq = 0;
 227
 228     request.cmd = s->cmd;
 229     request.arg = s->arg;
 230     request.crc = 0;    /* FIXME */
 231
 232     rsplen = sdbus_do_command(&s->sdbus, &request, response);
 233     s->intreq |= INT_END_CMD;
 234
 235     memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
 236     switch (s->cmdat & CMDAT_RES_TYPE) {
 237 #define PXAMMCI_RESP(wd, value0, value1)        \
 238         s->resp_fifo[(wd) + 0] |= (value0);     \
 239         s->resp_fifo[(wd) + 1] |= (value1) << 8;
 240     case 0:     /* No response */
 241         goto complete;
 242
 243     case 1:     /* R1, R4, R5 or R6 */
 244         if (rsplen < 4)
 245             goto timeout;
 246         goto complete;
 247
 248     case 2:     /* R2 */
 249         if (rsplen < 16)
 250             goto timeout;
 251         goto complete;
 252
 253     case 3:     /* R3 */
 254         if (rsplen < 4)
 255             goto timeout;
 256         goto complete;
 257
 258     complete:
 259         for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
 260             PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
 261         }
 262         s->status |= STAT_END_CMDRES;
 263
 264         if (!(s->cmdat & CMDAT_DATA_EN))
 265             s->active = 0;
 266         else
 267             s->bytesleft = s->numblk * s->blklen;
 268
 269         s->resp_len = 0;
 270         break;
 271
 272     timeout:
 273         s->active = 0;
 274         s->status |= STAT_TOUT_RES;
 275         break;
 276     }
 277
 278     pxa2xx_mmci_fifo_update(s);
 279 }
 280
 281 static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
 282 {
 283     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 284     uint32_t ret = 0;
 285
 286     switch (offset) {
 287     case MMC_STRPCL:
 288         break;
 289     case MMC_STAT:
 290         ret = s->status;
 291         break;
 292     case MMC_CLKRT:
 293         ret = s->clkrt;
 294         break;
 295     case MMC_SPI:
 296         ret = s->spi;
 297         break;
 298     case MMC_CMDAT:
 299         ret = s->cmdat;
 300         break;
 301     case MMC_RESTO:
 302         ret = s->resp_tout;
 303         break;
 304     case MMC_RDTO:
 305         ret = s->read_tout;
 306         break;
 307     case MMC_BLKLEN:
 308         ret = s->blklen;
 309         break;
 310     case MMC_NUMBLK:
 311         ret = s->numblk;
 312         break;
 313     case MMC_PRTBUF:
 314         break;
 315     case MMC_I_MASK:
 316         ret = s->intmask;
 317         break;
 318     case MMC_I_REG:
 319         ret = s->intreq;
 320         break;
 321     case MMC_CMD:
 322         ret = s->cmd | 0x40;
 323         break;
 324     case MMC_ARGH:
 325         ret = s->arg >> 16;
 326         break;
 327     case MMC_ARGL:
 328         ret = s->arg & 0xffff;
 329         break;
 330     case MMC_RES:
 331         ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
 332         break;
 333     case MMC_RXFIFO:
 334         while (size-- && s->rx_len) {
 335             ret |= s->rx_fifo[s->rx_start++] << (size << 3);
 336             s->rx_start &= 0x1f;
 337             s->rx_len --;
 338         }
 339         s->intreq &= ~INT_RXFIFO_REQ;
 340         pxa2xx_mmci_fifo_update(s);
 341         break;
 342     case MMC_RDWAIT:
 343         break;
 344     case MMC_BLKS_REM:
 345         ret = s->numblk;
 346         break;
 347     default:
 348         qemu_log_mask(LOG_GUEST_ERROR,
 349                       "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
 350                       __func__, offset);
 351     }
 352     trace_pxa2xx_mmci_read(size, offset, ret);
 353
 354     return ret;
 355 }
 356
 357 static void pxa2xx_mmci_write(void *opaque,
 358                               hwaddr offset, uint64_t value, unsigned size)
 359 {
 360     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 361
 362     trace_pxa2xx_mmci_write(size, offset, value);
 363     switch (offset) {
 364     case MMC_STRPCL:
 365         if (value & STRPCL_STRT_CLK) {
 366             s->status |= STAT_CLK_EN;
 367             s->intreq &= ~INT_CLK_OFF;
 368
 369             if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
 370                 s->status &= STAT_CLK_EN;
 371                 pxa2xx_mmci_wakequeues(s);
 372             }
 373         }
 374
 375         if (value & STRPCL_STOP_CLK) {
 376             s->status &= ~STAT_CLK_EN;
 377             s->intreq |= INT_CLK_OFF;
 378             s->active = 0;
 379         }
 380
 381         pxa2xx_mmci_int_update(s);
 382         break;
 383
 384     case MMC_CLKRT:
 385         s->clkrt = value & 7;
 386         break;
 387
 388     case MMC_SPI:
 389         s->spi = value & 0xf;
 390         if (value & SPI_SPI_MODE) {
 391             qemu_log_mask(LOG_GUEST_ERROR,
 392                           "%s: attempted to use card in SPI mode\n", __func__);
 393         }
 394         break;
 395
 396     case MMC_CMDAT:
 397         s->cmdat = value & 0x3dff;
 398         s->active = 0;
 399         s->cmdreq = 1;
 400         if (!(value & CMDAT_STOP_TRAN)) {
 401             s->status &= STAT_CLK_EN;
 402
 403             if (s->status & STAT_CLK_EN)
 404                 pxa2xx_mmci_wakequeues(s);
 405         }
 406
 407         pxa2xx_mmci_int_update(s);
 408         break;
 409
 410     case MMC_RESTO:
 411         s->resp_tout = value & 0x7f;
 412         break;
 413
 414     case MMC_RDTO:
 415         s->read_tout = value & 0xffff;
 416         break;
 417
 418     case MMC_BLKLEN:
 419         s->blklen = value & 0xfff;
 420         break;
 421
 422     case MMC_NUMBLK:
 423         s->numblk = value & 0xffff;
 424         break;
 425
 426     case MMC_PRTBUF:
 427         if (value & PRTBUF_PRT_BUF) {
 428             s->tx_start ^= 32;
 429             s->tx_len = 0;
 430         }
 431         pxa2xx_mmci_fifo_update(s);
 432         break;
 433
 434     case MMC_I_MASK:
 435         s->intmask = value & 0x1fff;
 436         pxa2xx_mmci_int_update(s);
 437         break;
 438
 439     case MMC_CMD:
 440         s->cmd = value & 0x3f;
 441         break;
 442
 443     case MMC_ARGH:
 444         s->arg &= 0x0000ffff;
 445         s->arg |= value << 16;
 446         break;
 447
 448     case MMC_ARGL:
 449         s->arg &= 0xffff0000;
 450         s->arg |= value & 0x0000ffff;
 451         break;
 452
 453     case MMC_TXFIFO:
 454         while (size-- && s->tx_len < 0x20)
 455             s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
 456                     (value >> (size << 3)) & 0xff;
 457         s->intreq &= ~INT_TXFIFO_REQ;
 458         pxa2xx_mmci_fifo_update(s);
 459         break;
 460
 461     case MMC_RDWAIT:
 462     case MMC_BLKS_REM:
 463         break;
 464
 465     default:
 466         qemu_log_mask(LOG_GUEST_ERROR,
 467                       "%s: incorrect reg 0x%02" HWADDR_PRIx " "
 468                       "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
 469     }
 470 }
 471
 472 static const MemoryRegionOps pxa2xx_mmci_ops = {
 473     .read = pxa2xx_mmci_read,
 474     .write = pxa2xx_mmci_write,
 475     .endianness = DEVICE_NATIVE_ENDIAN,
 476 };
 477
 478 PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
 479                 hwaddr base,
 480                 BlockBackend *blk, qemu_irq irq,
 481                 qemu_irq rx_dma, qemu_irq tx_dma)
 482 {
 483     DeviceState *dev, *carddev;
 484     SysBusDevice *sbd;
 485     PXA2xxMMCIState *s;
 486     Error *err = NULL;
 487
 488     dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
 489     s = PXA2XX_MMCI(dev);
 490     sbd = SYS_BUS_DEVICE(dev);
 491     sysbus_mmio_map(sbd, 0, base);
 492     sysbus_connect_irq(sbd, 0, irq);
 493     qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
 494     qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
 495
 496     /* Create and plug in the sd card */
 497     carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
 498     qdev_prop_set_drive(carddev, "drive", blk, &err);
 499     if (err) {
 500         error_report("failed to init SD card: %s", error_get_pretty(err));
 501         return NULL;
 502     }
 503     object_property_set_bool(OBJECT(carddev), true, "realized", &err);
 504     if (err) {
 505         error_report("failed to init SD card: %s", error_get_pretty(err));
 506         return NULL;
 507     }
 508
 509     return s;
 510 }
 511
 512 static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
 513 {
 514     PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
 515
 516     qemu_set_irq(s->inserted, inserted);
 517 }
 518
 519 static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
 520 {
 521     PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
 522
 523     qemu_set_irq(s->readonly, readonly);
 524 }
 525
 526 void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
 527                           qemu_irq coverswitch)
 528 {
 529     DeviceState *dev = DEVICE(s);
 530
 531     s->readonly = readonly;
 532     s->inserted = coverswitch;
 533
 534     pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
 535     pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
 536 }
 537
 538 static void pxa2xx_mmci_reset(DeviceState *d)
 539 {
 540     PXA2xxMMCIState *s = PXA2XX_MMCI(d);
 541
 542     s->status = 0;
 543     s->clkrt = 0;
 544     s->spi = 0;
 545     s->cmdat = 0;
 546     s->resp_tout = 0;
 547     s->read_tout = 0;
 548     s->blklen = 0;
 549     s->numblk = 0;
 550     s->intmask = 0;
 551     s->intreq = 0;
 552     s->cmd = 0;
 553     s->arg = 0;
 554     s->active = 0;
 555     s->bytesleft = 0;
 556     s->tx_start = 0;
 557     s->tx_len = 0;
 558     s->rx_start = 0;
 559     s->rx_len = 0;
 560     s->resp_len = 0;
 561     s->cmdreq = 0;
 562     memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
 563     memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
 564     memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
 565 }
 566
 567 static void pxa2xx_mmci_instance_init(Object *obj)
 568 {
 569     PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
 570     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 571     DeviceState *dev = DEVICE(obj);
 572
 573     memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
 574                           "pxa2xx-mmci", 0x00100000);
 575     sysbus_init_mmio(sbd, &s->iomem);
 576     sysbus_init_irq(sbd, &s->irq);
 577     qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
 578     qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
 579
 580     qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
 581                         TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
 582 }
 583
 584 static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
 585 {
 586     DeviceClass *dc = DEVICE_CLASS(klass);
 587
 588     dc->vmsd = &vmstate_pxa2xx_mmci;
 589     dc->reset = pxa2xx_mmci_reset;
 590 }
 591
 592 static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
 593 {
 594     SDBusClass *sbc = SD_BUS_CLASS(klass);
 595
 596     sbc->set_inserted = pxa2xx_mmci_set_inserted;
 597     sbc->set_readonly = pxa2xx_mmci_set_readonly;
 598 }
 599
 600 static const TypeInfo pxa2xx_mmci_info = {
 601     .name = TYPE_PXA2XX_MMCI,
 602     .parent = TYPE_SYS_BUS_DEVICE,
 603     .instance_size = sizeof(PXA2xxMMCIState),
 604     .instance_init = pxa2xx_mmci_instance_init,
 605     .class_init = pxa2xx_mmci_class_init,
 606 };
 607
 608 static const TypeInfo pxa2xx_mmci_bus_info = {
 609     .name = TYPE_PXA2XX_MMCI_BUS,
 610     .parent = TYPE_SD_BUS,
 611     .instance_size = sizeof(SDBus),
 612     .class_init = pxa2xx_mmci_bus_class_init,
 613 };
 614
 615 static void pxa2xx_mmci_register_types(void)
 616 {
 617     type_register_static(&pxa2xx_mmci_info);
 618     type_register_static(&pxa2xx_mmci_bus_info);
 619 }
 620
 621 type_init(pxa2xx_mmci_register_types)