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PPC: booke206: Implement tlbilx
[qemu/ar7.git] / hw / pxa2xx_lcd.c
blob4e9f7b48acad2dcc8766136f1bf641e99a9bcdc7
1 /*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "hw.h"
14 #include "console.h"
15 #include "pxa.h"
16 #include "pixel_ops.h"
17 /* FIXME: For graphic_rotate. Should probably be done in common code. */
18 #include "sysemu.h"
19 #include "framebuffer.h"
20
21 struct DMAChannel {
22 target_phys_addr_t branch;
23 uint8_t up;
24 uint8_t palette[1024];
25 uint8_t pbuffer[1024];
26 void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
27 int *miny, int *maxy);
28
29 target_phys_addr_t descriptor;
30 target_phys_addr_t source;
31 uint32_t id;
32 uint32_t command;
33 };
34
35 struct PXA2xxLCDState {
36 MemoryRegion *sysmem;
37 MemoryRegion iomem;
38 qemu_irq irq;
39 int irqlevel;
40
41 int invalidated;
42 DisplayState *ds;
43 drawfn *line_fn[2];
44 int dest_width;
45 int xres, yres;
46 int pal_for;
47 int transp;
48 enum {
49 pxa_lcdc_2bpp = 1,
50 pxa_lcdc_4bpp = 2,
51 pxa_lcdc_8bpp = 3,
52 pxa_lcdc_16bpp = 4,
53 pxa_lcdc_18bpp = 5,
54 pxa_lcdc_18pbpp = 6,
55 pxa_lcdc_19bpp = 7,
56 pxa_lcdc_19pbpp = 8,
57 pxa_lcdc_24bpp = 9,
58 pxa_lcdc_25bpp = 10,
59 } bpp;
60
61 uint32_t control[6];
62 uint32_t status[2];
63 uint32_t ovl1c[2];
64 uint32_t ovl2c[2];
65 uint32_t ccr;
66 uint32_t cmdcr;
67 uint32_t trgbr;
68 uint32_t tcr;
69 uint32_t liidr;
70 uint8_t bscntr;
71
72 struct DMAChannel dma_ch[7];
73
74 qemu_irq vsync_cb;
75 int orientation;
76 };
77
78 typedef struct QEMU_PACKED {
79 uint32_t fdaddr;
80 uint32_t fsaddr;
81 uint32_t fidr;
82 uint32_t ldcmd;
83 } PXAFrameDescriptor;
84
85 #define LCCR0 0x000 /* LCD Controller Control register 0 */
86 #define LCCR1 0x004 /* LCD Controller Control register 1 */
87 #define LCCR2 0x008 /* LCD Controller Control register 2 */
88 #define LCCR3 0x00c /* LCD Controller Control register 3 */
89 #define LCCR4 0x010 /* LCD Controller Control register 4 */
90 #define LCCR5 0x014 /* LCD Controller Control register 5 */
91
92 #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
93 #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
94 #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
95 #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
96 #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
97 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
98 #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
99
100 #define LCSR1 0x034 /* LCD Controller Status register 1 */
101 #define LCSR0 0x038 /* LCD Controller Status register 0 */
102 #define LIIDR 0x03c /* LCD Controller Interrupt ID register */
103
104 #define TRGBR 0x040 /* TMED RGB Seed register */
105 #define TCR 0x044 /* TMED Control register */
106
107 #define OVL1C1 0x050 /* Overlay 1 Control register 1 */
108 #define OVL1C2 0x060 /* Overlay 1 Control register 2 */
109 #define OVL2C1 0x070 /* Overlay 2 Control register 1 */
110 #define OVL2C2 0x080 /* Overlay 2 Control register 2 */
111 #define CCR 0x090 /* Cursor Control register */
112
113 #define CMDCR 0x100 /* Command Control register */
114 #define PRSR 0x104 /* Panel Read Status register */
115
116 #define PXA_LCDDMA_CHANS 7
117 #define DMA_FDADR 0x00 /* Frame Descriptor Address register */
118 #define DMA_FSADR 0x04 /* Frame Source Address register */
119 #define DMA_FIDR 0x08 /* Frame ID register */
120 #define DMA_LDCMD 0x0c /* Command register */
121
122 /* LCD Buffer Strength Control register */
123 #define BSCNTR 0x04000054
124
125 /* Bitfield masks */
126 #define LCCR0_ENB (1 << 0)
127 #define LCCR0_CMS (1 << 1)
128 #define LCCR0_SDS (1 << 2)
129 #define LCCR0_LDM (1 << 3)
130 #define LCCR0_SOFM0 (1 << 4)
131 #define LCCR0_IUM (1 << 5)
132 #define LCCR0_EOFM0 (1 << 6)
133 #define LCCR0_PAS (1 << 7)
134 #define LCCR0_DPD (1 << 9)
135 #define LCCR0_DIS (1 << 10)
136 #define LCCR0_QDM (1 << 11)
137 #define LCCR0_PDD (0xff << 12)
138 #define LCCR0_BSM0 (1 << 20)
139 #define LCCR0_OUM (1 << 21)
140 #define LCCR0_LCDT (1 << 22)
141 #define LCCR0_RDSTM (1 << 23)
142 #define LCCR0_CMDIM (1 << 24)
143 #define LCCR0_OUC (1 << 25)
144 #define LCCR0_LDDALT (1 << 26)
145 #define LCCR1_PPL(x) ((x) & 0x3ff)
146 #define LCCR2_LPP(x) ((x) & 0x3ff)
147 #define LCCR3_API (15 << 16)
148 #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
149 #define LCCR3_PDFOR(x) (((x) >> 30) & 3)
150 #define LCCR4_K1(x) (((x) >> 0) & 7)
151 #define LCCR4_K2(x) (((x) >> 3) & 7)
152 #define LCCR4_K3(x) (((x) >> 6) & 7)
153 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
154 #define LCCR5_SOFM(ch) (1 << (ch - 1))
155 #define LCCR5_EOFM(ch) (1 << (ch + 7))
156 #define LCCR5_BSM(ch) (1 << (ch + 15))
157 #define LCCR5_IUM(ch) (1 << (ch + 23))
158 #define OVLC1_EN (1 << 31)
159 #define CCR_CEN (1 << 31)
160 #define FBR_BRA (1 << 0)
161 #define FBR_BINT (1 << 1)
162 #define FBR_SRCADDR (0xfffffff << 4)
163 #define LCSR0_LDD (1 << 0)
164 #define LCSR0_SOF0 (1 << 1)
165 #define LCSR0_BER (1 << 2)
166 #define LCSR0_ABC (1 << 3)
167 #define LCSR0_IU0 (1 << 4)
168 #define LCSR0_IU1 (1 << 5)
169 #define LCSR0_OU (1 << 6)
170 #define LCSR0_QD (1 << 7)
171 #define LCSR0_EOF0 (1 << 8)
172 #define LCSR0_BS0 (1 << 9)
173 #define LCSR0_SINT (1 << 10)
174 #define LCSR0_RDST (1 << 11)
175 #define LCSR0_CMDINT (1 << 12)
176 #define LCSR0_BERCH(x) (((x) & 7) << 28)
177 #define LCSR1_SOF(ch) (1 << (ch - 1))
178 #define LCSR1_EOF(ch) (1 << (ch + 7))
179 #define LCSR1_BS(ch) (1 << (ch + 15))
180 #define LCSR1_IU(ch) (1 << (ch + 23))
181 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
182 #define LDCMD_EOFINT (1 << 21)
183 #define LDCMD_SOFINT (1 << 22)
184 #define LDCMD_PAL (1 << 26)
185
186 /* Route internal interrupt lines to the global IC */
187 static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
188 {
189 int level = 0;
190 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
191 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
192 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
193 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
194 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
195 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
196 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
197 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
198 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
199 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
200 level |= (s->status[1] & ~s->control[5]);
201
202 qemu_set_irq(s->irq, !!level);
203 s->irqlevel = level;
204 }
205
206 /* Set Branch Status interrupt high and poke associated registers */
207 static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
208 {
209 int unmasked;
210 if (ch == 0) {
211 s->status[0] |= LCSR0_BS0;
212 unmasked = !(s->control[0] & LCCR0_BSM0);
213 } else {
214 s->status[1] |= LCSR1_BS(ch);
215 unmasked = !(s->control[5] & LCCR5_BSM(ch));
216 }
217
218 if (unmasked) {
219 if (s->irqlevel)
220 s->status[0] |= LCSR0_SINT;
221 else
222 s->liidr = s->dma_ch[ch].id;
223 }
224 }
225
226 /* Set Start Of Frame Status interrupt high and poke associated registers */
227 static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
228 {
229 int unmasked;
230 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
231 return;
232
233 if (ch == 0) {
234 s->status[0] |= LCSR0_SOF0;
235 unmasked = !(s->control[0] & LCCR0_SOFM0);
236 } else {
237 s->status[1] |= LCSR1_SOF(ch);
238 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
239 }
240
241 if (unmasked) {
242 if (s->irqlevel)
243 s->status[0] |= LCSR0_SINT;
244 else
245 s->liidr = s->dma_ch[ch].id;
246 }
247 }
248
249 /* Set End Of Frame Status interrupt high and poke associated registers */
250 static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
251 {
252 int unmasked;
253 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
254 return;
255
256 if (ch == 0) {
257 s->status[0] |= LCSR0_EOF0;
258 unmasked = !(s->control[0] & LCCR0_EOFM0);
259 } else {
260 s->status[1] |= LCSR1_EOF(ch);
261 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
262 }
263
264 if (unmasked) {
265 if (s->irqlevel)
266 s->status[0] |= LCSR0_SINT;
267 else
268 s->liidr = s->dma_ch[ch].id;
269 }
270 }
271
272 /* Set Bus Error Status interrupt high and poke associated registers */
273 static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
274 {
275 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
276 if (s->irqlevel)
277 s->status[0] |= LCSR0_SINT;
278 else
279 s->liidr = s->dma_ch[ch].id;
280 }
281
282 /* Set Read Status interrupt high and poke associated registers */
283 static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
284 {
285 s->status[0] |= LCSR0_RDST;
286 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
287 s->status[0] |= LCSR0_SINT;
288 }
289
290 /* Load new Frame Descriptors from DMA */
291 static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
292 {
293 PXAFrameDescriptor desc;
294 target_phys_addr_t descptr;
295 int i;
296
297 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
298 s->dma_ch[i].source = 0;
299
300 if (!s->dma_ch[i].up)
301 continue;
302
303 if (s->dma_ch[i].branch & FBR_BRA) {
304 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
305 if (s->dma_ch[i].branch & FBR_BINT)
306 pxa2xx_dma_bs_set(s, i);
307 s->dma_ch[i].branch &= ~FBR_BRA;
308 } else
309 descptr = s->dma_ch[i].descriptor;
310
311 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
312 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
313 continue;
314
315 cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
316 s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
317 s->dma_ch[i].source = tswap32(desc.fsaddr);
318 s->dma_ch[i].id = tswap32(desc.fidr);
319 s->dma_ch[i].command = tswap32(desc.ldcmd);
320 }
321 }
322
323 static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
324 unsigned size)
325 {
326 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
327 int ch;
328
329 switch (offset) {
330 case LCCR0:
331 return s->control[0];
332 case LCCR1:
333 return s->control[1];
334 case LCCR2:
335 return s->control[2];
336 case LCCR3:
337 return s->control[3];
338 case LCCR4:
339 return s->control[4];
340 case LCCR5:
341 return s->control[5];
342
343 case OVL1C1:
344 return s->ovl1c[0];
345 case OVL1C2:
346 return s->ovl1c[1];
347 case OVL2C1:
348 return s->ovl2c[0];
349 case OVL2C2:
350 return s->ovl2c[1];
351
352 case CCR:
353 return s->ccr;
354
355 case CMDCR:
356 return s->cmdcr;
357
358 case TRGBR:
359 return s->trgbr;
360 case TCR:
361 return s->tcr;
362
363 case 0x200 ... 0x1000: /* DMA per-channel registers */
364 ch = (offset - 0x200) >> 4;
365 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
366 goto fail;
367
368 switch (offset & 0xf) {
369 case DMA_FDADR:
370 return s->dma_ch[ch].descriptor;
371 case DMA_FSADR:
372 return s->dma_ch[ch].source;
373 case DMA_FIDR:
374 return s->dma_ch[ch].id;
375 case DMA_LDCMD:
376 return s->dma_ch[ch].command;
377 default:
378 goto fail;
379 }
380
381 case FBR0:
382 return s->dma_ch[0].branch;
383 case FBR1:
384 return s->dma_ch[1].branch;
385 case FBR2:
386 return s->dma_ch[2].branch;
387 case FBR3:
388 return s->dma_ch[3].branch;
389 case FBR4:
390 return s->dma_ch[4].branch;
391 case FBR5:
392 return s->dma_ch[5].branch;
393 case FBR6:
394 return s->dma_ch[6].branch;
395
396 case BSCNTR:
397 return s->bscntr;
398
399 case PRSR:
400 return 0;
401
402 case LCSR0:
403 return s->status[0];
404 case LCSR1:
405 return s->status[1];
406 case LIIDR:
407 return s->liidr;
408
409 default:
410 fail:
411 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
412 }
413
414 return 0;
415 }
416
417 static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
418 uint64_t value, unsigned size)
419 {
420 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
421 int ch;
422
423 switch (offset) {
424 case LCCR0:
425 /* ACK Quick Disable done */
426 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
427 s->status[0] |= LCSR0_QD;
428
429 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
430 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
431
432 if ((s->control[3] & LCCR3_API) &&
433 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
434 s->status[0] |= LCSR0_ABC;
435
436 s->control[0] = value & 0x07ffffff;
437 pxa2xx_lcdc_int_update(s);
438
439 s->dma_ch[0].up = !!(value & LCCR0_ENB);
440 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
441 break;
442
443 case LCCR1:
444 s->control[1] = value;
445 break;
446
447 case LCCR2:
448 s->control[2] = value;
449 break;
450
451 case LCCR3:
452 s->control[3] = value & 0xefffffff;
453 s->bpp = LCCR3_BPP(value);
454 break;
455
456 case LCCR4:
457 s->control[4] = value & 0x83ff81ff;
458 break;
459
460 case LCCR5:
461 s->control[5] = value & 0x3f3f3f3f;
462 break;
463
464 case OVL1C1:
465 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
466 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
467
468 s->ovl1c[0] = value & 0x80ffffff;
469 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
470 break;
471
472 case OVL1C2:
473 s->ovl1c[1] = value & 0x000fffff;
474 break;
475
476 case OVL2C1:
477 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
478 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
479
480 s->ovl2c[0] = value & 0x80ffffff;
481 s->dma_ch[2].up = !!(value & OVLC1_EN);
482 s->dma_ch[3].up = !!(value & OVLC1_EN);
483 s->dma_ch[4].up = !!(value & OVLC1_EN);
484 break;
485
486 case OVL2C2:
487 s->ovl2c[1] = value & 0x007fffff;
488 break;
489
490 case CCR:
491 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
492 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
493
494 s->ccr = value & 0x81ffffe7;
495 s->dma_ch[5].up = !!(value & CCR_CEN);
496 break;
497
498 case CMDCR:
499 s->cmdcr = value & 0xff;
500 break;
501
502 case TRGBR:
503 s->trgbr = value & 0x00ffffff;
504 break;
505
506 case TCR:
507 s->tcr = value & 0x7fff;
508 break;
509
510 case 0x200 ... 0x1000: /* DMA per-channel registers */
511 ch = (offset - 0x200) >> 4;
512 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
513 goto fail;
514
515 switch (offset & 0xf) {
516 case DMA_FDADR:
517 s->dma_ch[ch].descriptor = value & 0xfffffff0;
518 break;
519
520 default:
521 goto fail;
522 }
523 break;
524
525 case FBR0:
526 s->dma_ch[0].branch = value & 0xfffffff3;
527 break;
528 case FBR1:
529 s->dma_ch[1].branch = value & 0xfffffff3;
530 break;
531 case FBR2:
532 s->dma_ch[2].branch = value & 0xfffffff3;
533 break;
534 case FBR3:
535 s->dma_ch[3].branch = value & 0xfffffff3;
536 break;
537 case FBR4:
538 s->dma_ch[4].branch = value & 0xfffffff3;
539 break;
540 case FBR5:
541 s->dma_ch[5].branch = value & 0xfffffff3;
542 break;
543 case FBR6:
544 s->dma_ch[6].branch = value & 0xfffffff3;
545 break;
546
547 case BSCNTR:
548 s->bscntr = value & 0xf;
549 break;
550
551 case PRSR:
552 break;
553
554 case LCSR0:
555 s->status[0] &= ~(value & 0xfff);
556 if (value & LCSR0_BER)
557 s->status[0] &= ~LCSR0_BERCH(7);
558 break;
559
560 case LCSR1:
561 s->status[1] &= ~(value & 0x3e3f3f);
562 break;
563
564 default:
565 fail:
566 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
567 }
568 }
569
570 static const MemoryRegionOps pxa2xx_lcdc_ops = {
571 .read = pxa2xx_lcdc_read,
572 .write = pxa2xx_lcdc_write,
573 .endianness = DEVICE_NATIVE_ENDIAN,
574 };
575
576 /* Load new palette for a given DMA channel, convert to internal format */
577 static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
578 {
579 int i, n, format, r, g, b, alpha;
580 uint32_t *dest;
581 uint8_t *src;
582 s->pal_for = LCCR4_PALFOR(s->control[4]);
583 format = s->pal_for;
584
585 switch (bpp) {
586 case pxa_lcdc_2bpp:
587 n = 4;
588 break;
589 case pxa_lcdc_4bpp:
590 n = 16;
591 break;
592 case pxa_lcdc_8bpp:
593 n = 256;
594 break;
595 default:
596 format = 0;
597 return;
598 }
599
600 src = (uint8_t *) s->dma_ch[ch].pbuffer;
601 dest = (uint32_t *) s->dma_ch[ch].palette;
602 alpha = r = g = b = 0;
603
604 for (i = 0; i < n; i ++) {
605 switch (format) {
606 case 0: /* 16 bpp, no transparency */
607 alpha = 0;
608 if (s->control[0] & LCCR0_CMS) {
609 r = g = b = *(uint16_t *) src & 0xff;
610 }
611 else {
612 r = (*(uint16_t *) src & 0xf800) >> 8;
613 g = (*(uint16_t *) src & 0x07e0) >> 3;
614 b = (*(uint16_t *) src & 0x001f) << 3;
615 }
616 src += 2;
617 break;
618 case 1: /* 16 bpp plus transparency */
619 alpha = *(uint16_t *) src & (1 << 24);
620 if (s->control[0] & LCCR0_CMS)
621 r = g = b = *(uint16_t *) src & 0xff;
622 else {
623 r = (*(uint16_t *) src & 0xf800) >> 8;
624 g = (*(uint16_t *) src & 0x07e0) >> 3;
625 b = (*(uint16_t *) src & 0x001f) << 3;
626 }
627 src += 2;
628 break;
629 case 2: /* 18 bpp plus transparency */
630 alpha = *(uint32_t *) src & (1 << 24);
631 if (s->control[0] & LCCR0_CMS)
632 r = g = b = *(uint32_t *) src & 0xff;
633 else {
634 r = (*(uint32_t *) src & 0xf80000) >> 16;
635 g = (*(uint32_t *) src & 0x00fc00) >> 8;
636 b = (*(uint32_t *) src & 0x0000f8);
637 }
638 src += 4;
639 break;
640 case 3: /* 24 bpp plus transparency */
641 alpha = *(uint32_t *) src & (1 << 24);
642 if (s->control[0] & LCCR0_CMS)
643 r = g = b = *(uint32_t *) src & 0xff;
644 else {
645 r = (*(uint32_t *) src & 0xff0000) >> 16;
646 g = (*(uint32_t *) src & 0x00ff00) >> 8;
647 b = (*(uint32_t *) src & 0x0000ff);
648 }
649 src += 4;
650 break;
651 }
652 switch (ds_get_bits_per_pixel(s->ds)) {
653 case 8:
654 *dest = rgb_to_pixel8(r, g, b) | alpha;
655 break;
656 case 15:
657 *dest = rgb_to_pixel15(r, g, b) | alpha;
658 break;
659 case 16:
660 *dest = rgb_to_pixel16(r, g, b) | alpha;
661 break;
662 case 24:
663 *dest = rgb_to_pixel24(r, g, b) | alpha;
664 break;
665 case 32:
666 *dest = rgb_to_pixel32(r, g, b) | alpha;
667 break;
668 }
669 dest ++;
670 }
671 }
672
673 static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
674 target_phys_addr_t addr, int *miny, int *maxy)
675 {
676 int src_width, dest_width;
677 drawfn fn = NULL;
678 if (s->dest_width)
679 fn = s->line_fn[s->transp][s->bpp];
680 if (!fn)
681 return;
682
683 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
684 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
685 src_width *= 3;
686 else if (s->bpp > pxa_lcdc_16bpp)
687 src_width *= 4;
688 else if (s->bpp > pxa_lcdc_8bpp)
689 src_width *= 2;
690
691 dest_width = s->xres * s->dest_width;
692 *miny = 0;
693 framebuffer_update_display(s->ds, s->sysmem,
694 addr, s->xres, s->yres,
695 src_width, dest_width, s->dest_width,
696 s->invalidated,
697 fn, s->dma_ch[0].palette, miny, maxy);
698 }
699
700 static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
701 target_phys_addr_t addr, int *miny, int *maxy)
702 {
703 int src_width, dest_width;
704 drawfn fn = NULL;
705 if (s->dest_width)
706 fn = s->line_fn[s->transp][s->bpp];
707 if (!fn)
708 return;
709
710 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
711 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
712 src_width *= 3;
713 else if (s->bpp > pxa_lcdc_16bpp)
714 src_width *= 4;
715 else if (s->bpp > pxa_lcdc_8bpp)
716 src_width *= 2;
717
718 dest_width = s->yres * s->dest_width;
719 *miny = 0;
720 framebuffer_update_display(s->ds, s->sysmem,
721 addr, s->xres, s->yres,
722 src_width, s->dest_width, -dest_width,
723 s->invalidated,
724 fn, s->dma_ch[0].palette,
725 miny, maxy);
726 }
727
728 static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
729 target_phys_addr_t addr, int *miny, int *maxy)
730 {
731 int src_width, dest_width;
732 drawfn fn = NULL;
733 if (s->dest_width) {
734 fn = s->line_fn[s->transp][s->bpp];
735 }
736 if (!fn) {
737 return;
738 }
739
740 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
741 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
742 src_width *= 3;
743 } else if (s->bpp > pxa_lcdc_16bpp) {
744 src_width *= 4;
745 } else if (s->bpp > pxa_lcdc_8bpp) {
746 src_width *= 2;
747 }
748
749 dest_width = s->xres * s->dest_width;
750 *miny = 0;
751 framebuffer_update_display(s->ds, s->sysmem,
752 addr, s->xres, s->yres,
753 src_width, -dest_width, -s->dest_width,
754 s->invalidated,
755 fn, s->dma_ch[0].palette, miny, maxy);
756 }
757
758 static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
759 target_phys_addr_t addr, int *miny, int *maxy)
760 {
761 int src_width, dest_width;
762 drawfn fn = NULL;
763 if (s->dest_width) {
764 fn = s->line_fn[s->transp][s->bpp];
765 }
766 if (!fn) {
767 return;
768 }
769
770 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
771 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
772 src_width *= 3;
773 } else if (s->bpp > pxa_lcdc_16bpp) {
774 src_width *= 4;
775 } else if (s->bpp > pxa_lcdc_8bpp) {
776 src_width *= 2;
777 }
778
779 dest_width = s->yres * s->dest_width;
780 *miny = 0;
781 framebuffer_update_display(s->ds, s->sysmem,
782 addr, s->xres, s->yres,
783 src_width, -s->dest_width, dest_width,
784 s->invalidated,
785 fn, s->dma_ch[0].palette,
786 miny, maxy);
787 }
788
789 static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
790 {
791 int width, height;
792 if (!(s->control[0] & LCCR0_ENB))
793 return;
794
795 width = LCCR1_PPL(s->control[1]) + 1;
796 height = LCCR2_LPP(s->control[2]) + 1;
797
798 if (width != s->xres || height != s->yres) {
799 if (s->orientation == 90 || s->orientation == 270) {
800 qemu_console_resize(s->ds, height, width);
801 } else {
802 qemu_console_resize(s->ds, width, height);
803 }
804 s->invalidated = 1;
805 s->xres = width;
806 s->yres = height;
807 }
808 }
809
810 static void pxa2xx_update_display(void *opaque)
811 {
812 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
813 target_phys_addr_t fbptr;
814 int miny, maxy;
815 int ch;
816 if (!(s->control[0] & LCCR0_ENB))
817 return;
818
819 pxa2xx_descriptor_load(s);
820
821 pxa2xx_lcdc_resize(s);
822 miny = s->yres;
823 maxy = 0;
824 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
825 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
826 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
827 if (s->dma_ch[ch].up) {
828 if (!s->dma_ch[ch].source) {
829 pxa2xx_dma_ber_set(s, ch);
830 continue;
831 }
832 fbptr = s->dma_ch[ch].source;
833 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
834 fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
835 pxa2xx_dma_ber_set(s, ch);
836 continue;
837 }
838
839 if (s->dma_ch[ch].command & LDCMD_PAL) {
840 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
841 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
842 sizeof(s->dma_ch[ch].pbuffer)));
843 pxa2xx_palette_parse(s, ch, s->bpp);
844 } else {
845 /* Do we need to reparse palette */
846 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
847 pxa2xx_palette_parse(s, ch, s->bpp);
848
849 /* ACK frame start */
850 pxa2xx_dma_sof_set(s, ch);
851
852 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
853 s->invalidated = 0;
854
855 /* ACK frame completed */
856 pxa2xx_dma_eof_set(s, ch);
857 }
858 }
859
860 if (s->control[0] & LCCR0_DIS) {
861 /* ACK last frame completed */
862 s->control[0] &= ~LCCR0_ENB;
863 s->status[0] |= LCSR0_LDD;
864 }
865
866 if (miny >= 0) {
867 switch (s->orientation) {
868 case 0:
869 dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
870 break;
871 case 90:
872 dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
873 break;
874 case 180:
875 maxy = s->yres - maxy - 1;
876 miny = s->yres - miny - 1;
877 dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
878 break;
879 case 270:
880 maxy = s->yres - maxy - 1;
881 miny = s->yres - miny - 1;
882 dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
883 break;
884 }
885 }
886 pxa2xx_lcdc_int_update(s);
887
888 qemu_irq_raise(s->vsync_cb);
889 }
890
891 static void pxa2xx_invalidate_display(void *opaque)
892 {
893 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
894 s->invalidated = 1;
895 }
896
897 static void pxa2xx_screen_dump(void *opaque, const char *filename)
898 {
899 /* TODO */
900 }
901
902 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
903 {
904 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
905
906 switch (angle) {
907 case 0:
908 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
909 break;
910 case 90:
911 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
912 break;
913 case 180:
914 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
915 break;
916 case 270:
917 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
918 break;
919 }
920
921 s->orientation = angle;
922 s->xres = s->yres = -1;
923 pxa2xx_lcdc_resize(s);
924 }
925
926 static const VMStateDescription vmstate_dma_channel = {
927 .name = "dma_channel",
928 .version_id = 0,
929 .minimum_version_id = 0,
930 .minimum_version_id_old = 0,
931 .fields = (VMStateField[]) {
932 VMSTATE_UINTTL(branch, struct DMAChannel),
933 VMSTATE_UINT8(up, struct DMAChannel),
934 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
935 VMSTATE_UINTTL(descriptor, struct DMAChannel),
936 VMSTATE_UINTTL(source, struct DMAChannel),
937 VMSTATE_UINT32(id, struct DMAChannel),
938 VMSTATE_UINT32(command, struct DMAChannel),
939 VMSTATE_END_OF_LIST()
940 }
941 };
942
943 static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
944 {
945 PXA2xxLCDState *s = opaque;
946
947 s->bpp = LCCR3_BPP(s->control[3]);
948 s->xres = s->yres = s->pal_for = -1;
949
950 return 0;
951 }
952
953 static const VMStateDescription vmstate_pxa2xx_lcdc = {
954 .name = "pxa2xx_lcdc",
955 .version_id = 0,
956 .minimum_version_id = 0,
957 .minimum_version_id_old = 0,
958 .post_load = pxa2xx_lcdc_post_load,
959 .fields = (VMStateField[]) {
960 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
961 VMSTATE_INT32(transp, PXA2xxLCDState),
962 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
963 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
964 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
965 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
966 VMSTATE_UINT32(ccr, PXA2xxLCDState),
967 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
968 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
969 VMSTATE_UINT32(tcr, PXA2xxLCDState),
970 VMSTATE_UINT32(liidr, PXA2xxLCDState),
971 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
972 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
973 vmstate_dma_channel, struct DMAChannel),
974 VMSTATE_END_OF_LIST()
975 }
976 };
977
978 #define BITS 8
979 #include "pxa2xx_template.h"
980 #define BITS 15
981 #include "pxa2xx_template.h"
982 #define BITS 16
983 #include "pxa2xx_template.h"
984 #define BITS 24
985 #include "pxa2xx_template.h"
986 #define BITS 32
987 #include "pxa2xx_template.h"
988
989 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
990 target_phys_addr_t base, qemu_irq irq)
991 {
992 PXA2xxLCDState *s;
993
994 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
995 s->invalidated = 1;
996 s->irq = irq;
997 s->sysmem = sysmem;
998
999 pxa2xx_lcdc_orientation(s, graphic_rotate);
1000
1001 memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
1002 "pxa2xx-lcd-controller", 0x00100000);
1003 memory_region_add_subregion(sysmem, base, &s->iomem);
1004
1005 s->ds = graphic_console_init(pxa2xx_update_display,
1006 pxa2xx_invalidate_display,
1007 pxa2xx_screen_dump, NULL, s);
1008
1009 switch (ds_get_bits_per_pixel(s->ds)) {
1010 case 0:
1011 s->dest_width = 0;
1012 break;
1013 case 8:
1014 s->line_fn[0] = pxa2xx_draw_fn_8;
1015 s->line_fn[1] = pxa2xx_draw_fn_8t;
1016 s->dest_width = 1;
1017 break;
1018 case 15:
1019 s->line_fn[0] = pxa2xx_draw_fn_15;
1020 s->line_fn[1] = pxa2xx_draw_fn_15t;
1021 s->dest_width = 2;
1022 break;
1023 case 16:
1024 s->line_fn[0] = pxa2xx_draw_fn_16;
1025 s->line_fn[1] = pxa2xx_draw_fn_16t;
1026 s->dest_width = 2;
1027 break;
1028 case 24:
1029 s->line_fn[0] = pxa2xx_draw_fn_24;
1030 s->line_fn[1] = pxa2xx_draw_fn_24t;
1031 s->dest_width = 3;
1032 break;
1033 case 32:
1034 s->line_fn[0] = pxa2xx_draw_fn_32;
1035 s->line_fn[1] = pxa2xx_draw_fn_32t;
1036 s->dest_width = 4;
1037 break;
1038 default:
1039 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1040 exit(1);
1041 }
1042
1043 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
1044
1045 return s;
1046 }
1047
1048 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
1049 {
1050 s->vsync_cb = handler;
1051 }
AR7 emulation for QEMU