hw/armv7m_nvic.c

   1 /*
   2  * ARM Nested Vectored Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  *
   9  * The ARMv7M System controller is fairly tightly tied in with the
  10  * NVIC.  Much of that is also implemented here.
  11  */
  12
  13 #include "sysbus.h"
  14 #include "qemu-timer.h"
  15 #include "arm-misc.h"
  16 #include "exec-memory.h"
  17
  18 #define NCPU 1
  19 #define NVIC 1
  20
  21 /* Only a single "CPU" interface is present.  */
  22 static inline int
  23 gic_get_current_cpu(void)
  24 {
  25     return 0;
  26 }
  27
  28 static uint32_t nvic_readl(void *opaque, uint32_t offset);
  29 static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
  30
  31 #include "arm_gic.c"
  32
  33 typedef struct {
  34     gic_state gic;
  35     struct {
  36         uint32_t control;
  37         uint32_t reload;
  38         int64_t tick;
  39         QEMUTimer *timer;
  40     } systick;
  41     uint32_t num_irq;
  42 } nvic_state;
  43
  44 /* qemu timers run at 1GHz.   We want something closer to 1MHz.  */
  45 #define SYSTICK_SCALE 1000ULL
  46
  47 #define SYSTICK_ENABLE    (1 << 0)
  48 #define SYSTICK_TICKINT   (1 << 1)
  49 #define SYSTICK_CLKSOURCE (1 << 2)
  50 #define SYSTICK_COUNTFLAG (1 << 16)
  51
  52 int system_clock_scale;
  53
  54 /* Conversion factor from qemu timer to SysTick frequencies.  */
  55 static inline int64_t systick_scale(nvic_state *s)
  56 {
  57     if (s->systick.control & SYSTICK_CLKSOURCE)
  58         return system_clock_scale;
  59     else
  60         return 1000;
  61 }
  62
  63 static void systick_reload(nvic_state *s, int reset)
  64 {
  65     if (reset)
  66         s->systick.tick = qemu_get_clock_ns(vm_clock);
  67     s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
  68     qemu_mod_timer(s->systick.timer, s->systick.tick);
  69 }
  70
  71 static void systick_timer_tick(void * opaque)
  72 {
  73     nvic_state *s = (nvic_state *)opaque;
  74     s->systick.control |= SYSTICK_COUNTFLAG;
  75     if (s->systick.control & SYSTICK_TICKINT) {
  76         /* Trigger the interrupt.  */
  77         armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
  78     }
  79     if (s->systick.reload == 0) {
  80         s->systick.control &= ~SYSTICK_ENABLE;
  81     } else {
  82         systick_reload(s, 0);
  83     }
  84 }
  85
  86 /* The external routines use the hardware vector numbering, ie. the first
  87    IRQ is #16.  The internal GIC routines use #32 as the first IRQ.  */
  88 void armv7m_nvic_set_pending(void *opaque, int irq)
  89 {
  90     nvic_state *s = (nvic_state *)opaque;
  91     if (irq >= 16)
  92         irq += 16;
  93     gic_set_pending_private(&s->gic, 0, irq);
  94 }
  95
  96 /* Make pending IRQ active.  */
  97 int armv7m_nvic_acknowledge_irq(void *opaque)
  98 {
  99     nvic_state *s = (nvic_state *)opaque;
 100     uint32_t irq;
 101
 102     irq = gic_acknowledge_irq(&s->gic, 0);
 103     if (irq == 1023)
 104         hw_error("Interrupt but no vector\n");
 105     if (irq >= 32)
 106         irq -= 16;
 107     return irq;
 108 }
 109
 110 void armv7m_nvic_complete_irq(void *opaque, int irq)
 111 {
 112     nvic_state *s = (nvic_state *)opaque;
 113     if (irq >= 16)
 114         irq += 16;
 115     gic_complete_irq(&s->gic, 0, irq);
 116 }
 117
 118 static uint32_t nvic_readl(void *opaque, uint32_t offset)
 119 {
 120     nvic_state *s = (nvic_state *)opaque;
 121     uint32_t val;
 122     int irq;
 123
 124     switch (offset) {
 125     case 4: /* Interrupt Control Type.  */
 126         return (s->num_irq / 32) - 1;
 127     case 0x10: /* SysTick Control and Status.  */
 128         val = s->systick.control;
 129         s->systick.control &= ~SYSTICK_COUNTFLAG;
 130         return val;
 131     case 0x14: /* SysTick Reload Value.  */
 132         return s->systick.reload;
 133     case 0x18: /* SysTick Current Value.  */
 134         {
 135             int64_t t;
 136             if ((s->systick.control & SYSTICK_ENABLE) == 0)
 137                 return 0;
 138             t = qemu_get_clock_ns(vm_clock);
 139             if (t >= s->systick.tick)
 140                 return 0;
 141             val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
 142             /* The interrupt in triggered when the timer reaches zero.
 143                However the counter is not reloaded until the next clock
 144                tick.  This is a hack to return zero during the first tick.  */
 145             if (val > s->systick.reload)
 146                 val = 0;
 147             return val;
 148         }
 149     case 0x1c: /* SysTick Calibration Value.  */
 150         return 10000;
 151     case 0xd00: /* CPUID Base.  */
 152         return cpu_single_env->cp15.c0_cpuid;
 153     case 0xd04: /* Interrypt Control State.  */
 154         /* VECTACTIVE */
 155         val = s->gic.running_irq[0];
 156         if (val == 1023) {
 157             val = 0;
 158         } else if (val >= 32) {
 159             val -= 16;
 160         }
 161         /* RETTOBASE */
 162         if (s->gic.running_irq[0] == 1023
 163                 || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
 164             val |= (1 << 11);
 165         }
 166         /* VECTPENDING */
 167         if (s->gic.current_pending[0] != 1023)
 168             val |= (s->gic.current_pending[0] << 12);
 169         /* ISRPENDING */
 170         for (irq = 32; irq < s->num_irq; irq++) {
 171             if (s->gic.irq_state[irq].pending) {
 172                 val |= (1 << 22);
 173                 break;
 174             }
 175         }
 176         /* PENDSTSET */
 177         if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
 178             val |= (1 << 26);
 179         /* PENDSVSET */
 180         if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
 181             val |= (1 << 28);
 182         /* NMIPENDSET */
 183         if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
 184             val |= (1 << 31);
 185         return val;
 186     case 0xd08: /* Vector Table Offset.  */
 187         return cpu_single_env->v7m.vecbase;
 188     case 0xd0c: /* Application Interrupt/Reset Control.  */
 189         return 0xfa05000;
 190     case 0xd10: /* System Control.  */
 191         /* TODO: Implement SLEEPONEXIT.  */
 192         return 0;
 193     case 0xd14: /* Configuration Control.  */
 194         /* TODO: Implement Configuration Control bits.  */
 195         return 0;
 196     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
 197         irq = offset - 0xd14;
 198         val = 0;
 199         val |= s->gic.priority1[irq++][0];
 200         val |= s->gic.priority1[irq++][0] << 8;
 201         val |= s->gic.priority1[irq++][0] << 16;
 202         val |= s->gic.priority1[irq][0] << 24;
 203         return val;
 204     case 0xd24: /* System Handler Status.  */
 205         val = 0;
 206         if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
 207         if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
 208         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
 209         if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
 210         if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
 211         if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
 212         if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
 213         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
 214         if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
 215         if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
 216         if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
 217         if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
 218         if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
 219         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
 220         return val;
 221     case 0xd28: /* Configurable Fault Status.  */
 222         /* TODO: Implement Fault Status.  */
 223         hw_error("Not implemented: Configurable Fault Status.");
 224         return 0;
 225     case 0xd2c: /* Hard Fault Status.  */
 226     case 0xd30: /* Debug Fault Status.  */
 227     case 0xd34: /* Mem Manage Address.  */
 228     case 0xd38: /* Bus Fault Address.  */
 229     case 0xd3c: /* Aux Fault Status.  */
 230         /* TODO: Implement fault status registers.  */
 231         goto bad_reg;
 232     case 0xd40: /* PFR0.  */
 233         return 0x00000030;
 234     case 0xd44: /* PRF1.  */
 235         return 0x00000200;
 236     case 0xd48: /* DFR0.  */
 237         return 0x00100000;
 238     case 0xd4c: /* AFR0.  */
 239         return 0x00000000;
 240     case 0xd50: /* MMFR0.  */
 241         return 0x00000030;
 242     case 0xd54: /* MMFR1.  */
 243         return 0x00000000;
 244     case 0xd58: /* MMFR2.  */
 245         return 0x00000000;
 246     case 0xd5c: /* MMFR3.  */
 247         return 0x00000000;
 248     case 0xd60: /* ISAR0.  */
 249         return 0x01141110;
 250     case 0xd64: /* ISAR1.  */
 251         return 0x02111000;
 252     case 0xd68: /* ISAR2.  */
 253         return 0x21112231;
 254     case 0xd6c: /* ISAR3.  */
 255         return 0x01111110;
 256     case 0xd70: /* ISAR4.  */
 257         return 0x01310102;
 258     /* TODO: Implement debug registers.  */
 259     default:
 260     bad_reg:
 261         hw_error("NVIC: Bad read offset 0x%x\n", offset);
 262     }
 263 }
 264
 265 static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
 266 {
 267     nvic_state *s = (nvic_state *)opaque;
 268     uint32_t oldval;
 269     switch (offset) {
 270     case 0x10: /* SysTick Control and Status.  */
 271         oldval = s->systick.control;
 272         s->systick.control &= 0xfffffff8;
 273         s->systick.control |= value & 7;
 274         if ((oldval ^ value) & SYSTICK_ENABLE) {
 275             int64_t now = qemu_get_clock_ns(vm_clock);
 276             if (value & SYSTICK_ENABLE) {
 277                 if (s->systick.tick) {
 278                     s->systick.tick += now;
 279                     qemu_mod_timer(s->systick.timer, s->systick.tick);
 280                 } else {
 281                     systick_reload(s, 1);
 282                 }
 283             } else {
 284                 qemu_del_timer(s->systick.timer);
 285                 s->systick.tick -= now;
 286                 if (s->systick.tick < 0)
 287                   s->systick.tick = 0;
 288             }
 289         } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
 290             /* This is a hack. Force the timer to be reloaded
 291                when the reference clock is changed.  */
 292             systick_reload(s, 1);
 293         }
 294         break;
 295     case 0x14: /* SysTick Reload Value.  */
 296         s->systick.reload = value;
 297         break;
 298     case 0x18: /* SysTick Current Value.  Writes reload the timer.  */
 299         systick_reload(s, 1);
 300         s->systick.control &= ~SYSTICK_COUNTFLAG;
 301         break;
 302     case 0xd04: /* Interrupt Control State.  */
 303         if (value & (1 << 31)) {
 304             armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
 305         }
 306         if (value & (1 << 28)) {
 307             armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
 308         } else if (value & (1 << 27)) {
 309             s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
 310             gic_update(&s->gic);
 311         }
 312         if (value & (1 << 26)) {
 313             armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
 314         } else if (value & (1 << 25)) {
 315             s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
 316             gic_update(&s->gic);
 317         }
 318         break;
 319     case 0xd08: /* Vector Table Offset.  */
 320         cpu_single_env->v7m.vecbase = value & 0xffffff80;
 321         break;
 322     case 0xd0c: /* Application Interrupt/Reset Control.  */
 323         if ((value >> 16) == 0x05fa) {
 324             if (value & 2) {
 325                 hw_error("VECTCLRACTIVE not implemented");
 326             }
 327             if (value & 5) {
 328                 hw_error("System reset");
 329             }
 330         }
 331         break;
 332     case 0xd10: /* System Control.  */
 333     case 0xd14: /* Configuration Control.  */
 334         /* TODO: Implement control registers.  */
 335         goto bad_reg;
 336     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
 337         {
 338             int irq;
 339             irq = offset - 0xd14;
 340             s->gic.priority1[irq++][0] = value & 0xff;
 341             s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
 342             s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
 343             s->gic.priority1[irq][0] = (value >> 24) & 0xff;
 344             gic_update(&s->gic);
 345         }
 346         break;
 347     case 0xd24: /* System Handler Control.  */
 348         /* TODO: Real hardware allows you to set/clear the active bits
 349            under some circumstances.  We don't implement this.  */
 350         s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
 351         s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
 352         s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
 353         break;
 354     case 0xd28: /* Configurable Fault Status.  */
 355     case 0xd2c: /* Hard Fault Status.  */
 356     case 0xd30: /* Debug Fault Status.  */
 357     case 0xd34: /* Mem Manage Address.  */
 358     case 0xd38: /* Bus Fault Address.  */
 359     case 0xd3c: /* Aux Fault Status.  */
 360         goto bad_reg;
 361     default:
 362     bad_reg:
 363         hw_error("NVIC: Bad write offset 0x%x\n", offset);
 364     }
 365 }
 366
 367 static const VMStateDescription vmstate_nvic = {
 368     .name = "armv7m_nvic",
 369     .version_id = 1,
 370     .minimum_version_id = 1,
 371     .minimum_version_id_old = 1,
 372     .fields      = (VMStateField[]) {
 373         VMSTATE_UINT32(systick.control, nvic_state),
 374         VMSTATE_UINT32(systick.reload, nvic_state),
 375         VMSTATE_INT64(systick.tick, nvic_state),
 376         VMSTATE_TIMER(systick.timer, nvic_state),
 377         VMSTATE_END_OF_LIST()
 378     }
 379 };
 380
 381 static int armv7m_nvic_init(SysBusDevice *dev)
 382 {
 383     nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
 384
 385    /* note that for the M profile gic_init() takes the number of external
 386     * interrupt lines only.
 387     */
 388     gic_init(&s->gic, s->num_irq);
 389     memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem);
 390     s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
 391     return 0;
 392 }
 393
 394 static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
 395 {
 396     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 397
 398     sdc->init = armv7m_nvic_init;
 399 }
 400
 401 static DeviceInfo armv7m_nvic_priv_info = {
 402     .name = "armv7m_nvic",
 403     .size = sizeof(nvic_state),
 404     .vmsd  = &vmstate_nvic,
 405     .class_init = armv7m_nvic_class_init,
 406     .props = (Property[]) {
 407         /* The ARM v7m may have anything from 0 to 496 external interrupt
 408          * IRQ lines. We default to 64. Other boards may differ and should
 409          * set this property appropriately.
 410          */
 411         DEFINE_PROP_UINT32("num-irq", nvic_state, num_irq, 64),
 412         DEFINE_PROP_END_OF_LIST(),
 413     }
 414 };
 415
 416 static void armv7m_nvic_register_devices(void)
 417 {
 418     sysbus_qdev_register(&armv7m_nvic_priv_info);
 419 }
 420
 421 device_init(armv7m_nvic_register_devices)