5 #include "exec/cpu-defs.h"
6 #include "fpu/softfloat-types.h"
9 #define TCG_GUEST_DEFAULT_MO (0)
11 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext
;
14 #define MSA_WRLEN (128)
16 typedef union wr_t wr_t
;
18 int8_t b
[MSA_WRLEN
/ 8];
19 int16_t h
[MSA_WRLEN
/ 16];
20 int32_t w
[MSA_WRLEN
/ 32];
21 int64_t d
[MSA_WRLEN
/ 64];
24 typedef union fpr_t fpr_t
;
26 float64 fd
; /* ieee double precision */
27 float32 fs
[2];/* ieee single precision */
28 uint64_t d
; /* binary double fixed-point */
29 uint32_t w
[2]; /* binary single fixed-point */
30 /* FPU/MSA register mapping is not tested on big-endian hosts. */
31 wr_t wr
; /* vector data */
34 *define FP_ENDIAN_IDX to access the same location
35 * in the fpr_t union regardless of the host endianness
37 #if defined(HOST_WORDS_BIGENDIAN)
38 # define FP_ENDIAN_IDX 1
40 # define FP_ENDIAN_IDX 0
43 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext
;
44 struct CPUMIPSFPUContext
{
45 /* Floating point registers */
47 float_status fp_status
;
48 /* fpu implementation/revision register (fir) */
52 #define FCR0_HAS2008 23
63 uint32_t fcr31_rw_bitmask
;
66 #define FCR31_ABS2008 19
67 #define FCR31_NAN2008 18
68 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \
69 ((num) ? (1 << ((num) + 24)) : \
72 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \
73 ~((num) ? (1 << ((num) + 24)) : \
76 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
77 (((env).fcr31 >> 23) & 0x1))
78 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
79 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
80 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
81 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
84 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \
87 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \
90 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0)
92 #define FP_UNDERFLOW 2
96 #define FP_UNIMPLEMENTED 32
99 #define TARGET_INSN_START_EXTRA_WORDS 2
101 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext
;
102 struct CPUMIPSMVPContext
{
103 int32_t CP0_MVPControl
;
104 #define CP0MVPCo_CPA 3
105 #define CP0MVPCo_STLB 2
106 #define CP0MVPCo_VPC 1
107 #define CP0MVPCo_EVP 0
108 int32_t CP0_MVPConf0
;
109 #define CP0MVPC0_M 31
110 #define CP0MVPC0_TLBS 29
111 #define CP0MVPC0_GS 28
112 #define CP0MVPC0_PCP 27
113 #define CP0MVPC0_PTLBE 16
114 #define CP0MVPC0_TCA 15
115 #define CP0MVPC0_PVPE 10
116 #define CP0MVPC0_PTC 0
117 int32_t CP0_MVPConf1
;
118 #define CP0MVPC1_CIM 31
119 #define CP0MVPC1_CIF 30
120 #define CP0MVPC1_PCX 20
121 #define CP0MVPC1_PCP2 10
122 #define CP0MVPC1_PCP1 0
125 typedef struct mips_def_t mips_def_t
;
127 #define MIPS_SHADOW_SET_MAX 16
128 #define MIPS_TC_MAX 5
129 #define MIPS_FPU_MAX 1
130 #define MIPS_DSP_ACC 4
131 #define MIPS_KSCRATCH_NUM 6
132 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
136 * Summary of CP0 registers
137 * ========================
140 * Register 0 Register 1 Register 2 Register 3
141 * ---------- ---------- ---------- ----------
143 * 0 Index Random EntryLo0 EntryLo1
144 * 1 MVPControl VPEControl TCStatus GlobalNumber
145 * 2 MVPConf0 VPEConf0 TCBind
146 * 3 MVPConf1 VPEConf1 TCRestart
147 * 4 VPControl YQMask TCHalt
148 * 5 VPESchedule TCContext
149 * 6 VPEScheFBack TCSchedule
150 * 7 VPEOpt TCScheFBack TCOpt
153 * Register 4 Register 5 Register 6 Register 7
154 * ---------- ---------- ---------- ----------
156 * 0 Context PageMask Wired HWREna
157 * 1 ContextConfig PageGrain SRSConf0
158 * 2 UserLocal SegCtl0 SRSConf1
159 * 3 XContextConfig SegCtl1 SRSConf2
160 * 4 DebugContextID SegCtl2 SRSConf3
161 * 5 MemoryMapID PWBase SRSConf4
166 * Register 8 Register 9 Register 10 Register 11
167 * ---------- ---------- ----------- -----------
169 * 0 BadVAddr Count EntryHi Compare
173 * 4 GuestCtl1 GuestCtl0Ext
179 * Register 12 Register 13 Register 14 Register 15
180 * ----------- ----------- ----------- -----------
182 * 0 Status Cause EPC PRId
184 * 2 SRSCtl NestedEPC CDMMBase
186 * 4 View_IPL View_RIPL BEVVA
187 * 5 SRSMap2 NestedExc
192 * Register 16 Register 17 Register 18 Register 19
193 * ----------- ----------- ----------- -----------
195 * 0 Config LLAddr WatchLo WatchHi
196 * 1 Config1 MAAR WatchLo WatchHi
197 * 2 Config2 MAARI WatchLo WatchHi
198 * 3 Config3 WatchLo WatchHi
199 * 4 Config4 WatchLo WatchHi
200 * 5 Config5 WatchLo WatchHi
205 * Register 20 Register 21 Register 22 Register 23
206 * ----------- ----------- ----------- -----------
218 * Register 24 Register 25 Register 26 Register 27
219 * ----------- ----------- ----------- -----------
221 * 0 DEPC PerfCnt ErrCtl CacheErr
223 * 2 TraceControl3 PerfCnt
224 * 3 UserTraceData2 PerfCnt
231 * Register 28 Register 29 Register 30 Register 31
232 * ----------- ----------- ----------- -----------
234 * 0 DataLo DataHi ErrorEPC DESAVE
236 * 2 DataLo DataHi KScratch<n>
237 * 3 TagLo TagHi KScratch<n>
238 * 4 DataLo DataHi KScratch<n>
239 * 5 TagLo TagHi KScratch<n>
240 * 6 DataLo DataHi KScratch<n>
241 * 7 TagLo TagHi KScratch<n>
244 #define CP0_REGISTER_00 0
245 #define CP0_REGISTER_01 1
246 #define CP0_REGISTER_02 2
247 #define CP0_REGISTER_03 3
248 #define CP0_REGISTER_04 4
249 #define CP0_REGISTER_05 5
250 #define CP0_REGISTER_06 6
251 #define CP0_REGISTER_07 7
252 #define CP0_REGISTER_08 8
253 #define CP0_REGISTER_09 9
254 #define CP0_REGISTER_10 10
255 #define CP0_REGISTER_11 11
256 #define CP0_REGISTER_12 12
257 #define CP0_REGISTER_13 13
258 #define CP0_REGISTER_14 14
259 #define CP0_REGISTER_15 15
260 #define CP0_REGISTER_16 16
261 #define CP0_REGISTER_17 17
262 #define CP0_REGISTER_18 18
263 #define CP0_REGISTER_19 19
264 #define CP0_REGISTER_20 20
265 #define CP0_REGISTER_21 21
266 #define CP0_REGISTER_22 22
267 #define CP0_REGISTER_23 23
268 #define CP0_REGISTER_24 24
269 #define CP0_REGISTER_25 25
270 #define CP0_REGISTER_26 26
271 #define CP0_REGISTER_27 27
272 #define CP0_REGISTER_28 28
273 #define CP0_REGISTER_29 29
274 #define CP0_REGISTER_30 30
275 #define CP0_REGISTER_31 31
278 /* CP0 Register 00 */
279 #define CP0_REG00__INDEX 0
280 #define CP0_REG00__MVPCONTROL 1
281 #define CP0_REG00__MVPCONF0 2
282 #define CP0_REG00__MVPCONF1 3
283 #define CP0_REG00__VPCONTROL 4
284 /* CP0 Register 01 */
285 #define CP0_REG01__RANDOM 0
286 #define CP0_REG01__VPECONTROL 1
287 #define CP0_REG01__VPECONF0 2
288 #define CP0_REG01__VPECONF1 3
289 #define CP0_REG01__YQMASK 4
290 #define CP0_REG01__VPESCHEDULE 5
291 #define CP0_REG01__VPESCHEFBACK 6
292 #define CP0_REG01__VPEOPT 7
293 /* CP0 Register 02 */
294 #define CP0_REG02__ENTRYLO0 0
295 #define CP0_REG02__TCSTATUS 1
296 #define CP0_REG02__TCBIND 2
297 #define CP0_REG02__TCRESTART 3
298 #define CP0_REG02__TCHALT 4
299 #define CP0_REG02__TCCONTEXT 5
300 #define CP0_REG02__TCSCHEDULE 6
301 #define CP0_REG02__TCSCHEFBACK 7
302 /* CP0 Register 03 */
303 #define CP0_REG03__ENTRYLO1 0
304 #define CP0_REG03__GLOBALNUM 1
305 /* CP0 Register 04 */
306 #define CP0_REG04__CONTEXT 0
307 #define CP0_REG04__USERLOCAL 2
308 #define CP0_REG04__DBGCONTEXTID 4
309 #define CP0_REG00__MMID 5
310 /* CP0 Register 05 */
311 #define CP0_REG05__PAGEMASK 0
312 #define CP0_REG05__PAGEGRAIN 1
313 /* CP0 Register 06 */
314 #define CP0_REG06__WIRED 0
315 /* CP0 Register 07 */
316 #define CP0_REG07__HWRENA 0
317 /* CP0 Register 08 */
318 #define CP0_REG08__BADVADDR 0
319 #define CP0_REG08__BADINSTR 1
320 #define CP0_REG08__BADINSTRP 2
321 /* CP0 Register 09 */
322 #define CP0_REG09__COUNT 0
323 #define CP0_REG09__SAARI 6
324 #define CP0_REG09__SAAR 7
325 /* CP0 Register 10 */
326 #define CP0_REG10__ENTRYHI 0
327 #define CP0_REG10__GUESTCTL1 4
328 #define CP0_REG10__GUESTCTL2 5
329 /* CP0 Register 11 */
330 #define CP0_REG11__COMPARE 0
331 #define CP0_REG11__GUESTCTL0EXT 4
332 /* CP0 Register 12 */
333 #define CP0_REG12__STATUS 0
334 #define CP0_REG12__INTCTL 1
335 #define CP0_REG12__SRSCTL 2
336 #define CP0_REG12__GUESTCTL0 6
337 #define CP0_REG12__GTOFFSET 7
338 /* CP0 Register 13 */
339 #define CP0_REG13__CAUSE 0
340 /* CP0 Register 14 */
341 #define CP0_REG14__EPC 0
342 /* CP0 Register 15 */
343 #define CP0_REG15__PRID 0
344 #define CP0_REG15__EBASE 1
345 #define CP0_REG15__CDMMBASE 2
346 #define CP0_REG15__CMGCRBASE 3
347 /* CP0 Register 16 */
348 #define CP0_REG16__CONFIG 0
349 #define CP0_REG16__CONFIG1 1
350 #define CP0_REG16__CONFIG2 2
351 #define CP0_REG16__CONFIG3 3
352 #define CP0_REG16__CONFIG4 4
353 #define CP0_REG16__CONFIG5 5
354 #define CP0_REG00__CONFIG7 7
355 /* CP0 Register 17 */
356 #define CP0_REG17__LLADDR 0
357 #define CP0_REG17__MAAR 1
358 #define CP0_REG17__MAARI 2
359 /* CP0 Register 18 */
360 #define CP0_REG18__WATCHLO0 0
361 #define CP0_REG18__WATCHLO1 1
362 #define CP0_REG18__WATCHLO2 2
363 #define CP0_REG18__WATCHLO3 3
364 /* CP0 Register 19 */
365 #define CP0_REG19__WATCHHI0 0
366 #define CP0_REG19__WATCHHI1 1
367 #define CP0_REG19__WATCHHI2 2
368 #define CP0_REG19__WATCHHI3 3
369 /* CP0 Register 20 */
370 #define CP0_REG20__XCONTEXT 0
371 /* CP0 Register 21 */
372 /* CP0 Register 22 */
373 /* CP0 Register 23 */
374 #define CP0_REG23__DEBUG 0
375 /* CP0 Register 24 */
376 #define CP0_REG24__DEPC 0
377 /* CP0 Register 25 */
378 #define CP0_REG25__PERFCTL0 0
379 #define CP0_REG25__PERFCNT0 1
380 #define CP0_REG25__PERFCTL1 2
381 #define CP0_REG25__PERFCNT1 3
382 #define CP0_REG25__PERFCTL2 4
383 #define CP0_REG25__PERFCNT2 5
384 #define CP0_REG25__PERFCTL3 6
385 #define CP0_REG25__PERFCNT3 7
386 /* CP0 Register 26 */
387 #define CP0_REG00__ERRCTL 0
388 /* CP0 Register 27 */
389 #define CP0_REG27__CACHERR 0
390 /* CP0 Register 28 */
391 #define CP0_REG28__ITAGLO 0
392 #define CP0_REG28__IDATALO 1
393 #define CP0_REG28__DTAGLO 2
394 #define CP0_REG28__DDATALO 3
395 /* CP0 Register 29 */
396 #define CP0_REG29__IDATAHI 1
397 #define CP0_REG29__DDATAHI 3
398 /* CP0 Register 30 */
399 #define CP0_REG30__ERROREPC 0
400 /* CP0 Register 31 */
401 #define CP0_REG31__DESAVE 0
402 #define CP0_REG31__KSCRATCH1 2
403 #define CP0_REG31__KSCRATCH2 3
404 #define CP0_REG31__KSCRATCH3 4
405 #define CP0_REG31__KSCRATCH4 5
406 #define CP0_REG31__KSCRATCH5 6
407 #define CP0_REG31__KSCRATCH6 7
410 typedef struct TCState TCState
;
412 target_ulong gpr
[32];
414 target_ulong HI
[MIPS_DSP_ACC
];
415 target_ulong LO
[MIPS_DSP_ACC
];
416 target_ulong ACX
[MIPS_DSP_ACC
];
417 target_ulong DSPControl
;
418 int32_t CP0_TCStatus
;
419 #define CP0TCSt_TCU3 31
420 #define CP0TCSt_TCU2 30
421 #define CP0TCSt_TCU1 29
422 #define CP0TCSt_TCU0 28
423 #define CP0TCSt_TMX 27
424 #define CP0TCSt_RNST 23
425 #define CP0TCSt_TDS 21
426 #define CP0TCSt_DT 20
427 #define CP0TCSt_DA 15
429 #define CP0TCSt_TKSU 11
430 #define CP0TCSt_IXMT 10
431 #define CP0TCSt_TASID 0
433 #define CP0TCBd_CurTC 21
434 #define CP0TCBd_TBE 17
435 #define CP0TCBd_CurVPE 0
436 target_ulong CP0_TCHalt
;
437 target_ulong CP0_TCContext
;
438 target_ulong CP0_TCSchedule
;
439 target_ulong CP0_TCScheFBack
;
440 int32_t CP0_Debug_tcstatus
;
441 target_ulong CP0_UserLocal
;
446 #define MSACSR_FS_MASK (1 << MSACSR_FS)
448 #define MSACSR_NX_MASK (1 << MSACSR_NX)
450 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
452 #define MSACSR_RM_MASK (0x3 << MSACSR_RM)
453 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
456 float_status msa_fp_status
;
458 /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
461 #define NUMBER_OF_MXU_REGISTERS 16
462 target_ulong mxu_gpr
[NUMBER_OF_MXU_REGISTERS
- 1];
466 #define MXU_CR_BIAS 2
467 #define MXU_CR_RD_EN 1
468 #define MXU_CR_MXU_EN 0
473 typedef struct CPUMIPSState CPUMIPSState
;
474 struct CPUMIPSState
{
476 CPUMIPSFPUContext active_fpu
;
479 uint32_t current_fpu
;
483 #if defined(TARGET_MIPS64)
484 # define PABITS_BASE 36
486 # define PABITS_BASE 32
488 target_ulong SEGMask
;
490 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
493 #define MSAIR_ProcID 8
500 /* CP0_MVP* are per MVP registers. */
501 int32_t CP0_VPControl
;
502 #define CP0VPCtl_DIS 0
507 int32_t CP0_VPEControl
;
508 #define CP0VPECo_YSI 21
509 #define CP0VPECo_GSI 20
510 #define CP0VPECo_EXCPT 16
511 #define CP0VPECo_TE 15
512 #define CP0VPECo_TargTC 0
513 int32_t CP0_VPEConf0
;
514 #define CP0VPEC0_M 31
515 #define CP0VPEC0_XTC 21
516 #define CP0VPEC0_TCS 19
517 #define CP0VPEC0_SCS 18
518 #define CP0VPEC0_DSC 17
519 #define CP0VPEC0_ICS 16
520 #define CP0VPEC0_MVP 1
521 #define CP0VPEC0_VPA 0
522 int32_t CP0_VPEConf1
;
523 #define CP0VPEC1_NCX 20
524 #define CP0VPEC1_NCP2 10
525 #define CP0VPEC1_NCP1 0
526 target_ulong CP0_YQMask
;
527 target_ulong CP0_VPESchedule
;
528 target_ulong CP0_VPEScheFBack
;
530 #define CP0VPEOpt_IWX7 15
531 #define CP0VPEOpt_IWX6 14
532 #define CP0VPEOpt_IWX5 13
533 #define CP0VPEOpt_IWX4 12
534 #define CP0VPEOpt_IWX3 11
535 #define CP0VPEOpt_IWX2 10
536 #define CP0VPEOpt_IWX1 9
537 #define CP0VPEOpt_IWX0 8
538 #define CP0VPEOpt_DWX7 7
539 #define CP0VPEOpt_DWX6 6
540 #define CP0VPEOpt_DWX5 5
541 #define CP0VPEOpt_DWX4 4
542 #define CP0VPEOpt_DWX3 3
543 #define CP0VPEOpt_DWX2 2
544 #define CP0VPEOpt_DWX1 1
545 #define CP0VPEOpt_DWX0 0
549 uint64_t CP0_EntryLo0
;
553 uint64_t CP0_EntryLo1
;
554 #if defined(TARGET_MIPS64)
555 # define CP0EnLo_RI 63
556 # define CP0EnLo_XI 62
558 # define CP0EnLo_RI 31
559 # define CP0EnLo_XI 30
561 int32_t CP0_GlobalNumber
;
566 target_ulong CP0_Context
;
567 target_ulong CP0_KScratch
[MIPS_KSCRATCH_NUM
];
568 int32_t CP0_MemoryMapID
;
572 int32_t CP0_PageMask
;
573 int32_t CP0_PageGrain_rw_bitmask
;
574 int32_t CP0_PageGrain
;
577 #define CP0PG_ELPA 29
579 target_ulong CP0_SegCtl0
;
580 target_ulong CP0_SegCtl1
;
581 target_ulong CP0_SegCtl2
;
583 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
584 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
586 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
587 #define CP0SC_AM_UK 0ULL
588 #define CP0SC_AM_MK 1ULL
589 #define CP0SC_AM_MSK 2ULL
590 #define CP0SC_AM_MUSK 3ULL
591 #define CP0SC_AM_MUSUK 4ULL
592 #define CP0SC_AM_USK 5ULL
593 #define CP0SC_AM_UUSK 7ULL
595 #define CP0SC_EU_MASK (1ULL << CP0SC_EU)
597 #define CP0SC_C_MASK (0x7ULL << CP0SC_C)
598 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
600 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
602 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16))
603 #define CP0SC1_XAM 59
604 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
605 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
607 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
608 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
609 target_ulong CP0_PWBase
;
610 target_ulong CP0_PWField
;
611 #if defined(TARGET_MIPS64)
612 #define CP0PF_BDI 32 /* 37..32 */
613 #define CP0PF_GDI 24 /* 29..24 */
614 #define CP0PF_UDI 18 /* 23..18 */
615 #define CP0PF_MDI 12 /* 17..12 */
616 #define CP0PF_PTI 6 /* 11..6 */
617 #define CP0PF_PTEI 0 /* 5..0 */
619 #define CP0PF_GDW 24 /* 29..24 */
620 #define CP0PF_UDW 18 /* 23..18 */
621 #define CP0PF_MDW 12 /* 17..12 */
622 #define CP0PF_PTW 6 /* 11..6 */
623 #define CP0PF_PTEW 0 /* 5..0 */
625 target_ulong CP0_PWSize
;
626 #if defined(TARGET_MIPS64)
627 #define CP0PS_BDW 32 /* 37..32 */
630 #define CP0PS_GDW 24 /* 29..24 */
631 #define CP0PS_UDW 18 /* 23..18 */
632 #define CP0PS_MDW 12 /* 17..12 */
633 #define CP0PS_PTW 6 /* 11..6 */
634 #define CP0PS_PTEW 0 /* 5..0 */
640 #define CP0PC_PWEN 31
641 #if defined(TARGET_MIPS64)
642 #define CP0PC_PWDIREXT 30
648 #define CP0PC_HUGEPG 6
649 #define CP0PC_PSN 0 /* 5..0 */
650 int32_t CP0_SRSConf0_rw_bitmask
;
651 int32_t CP0_SRSConf0
;
652 #define CP0SRSC0_M 31
653 #define CP0SRSC0_SRS3 20
654 #define CP0SRSC0_SRS2 10
655 #define CP0SRSC0_SRS1 0
656 int32_t CP0_SRSConf1_rw_bitmask
;
657 int32_t CP0_SRSConf1
;
658 #define CP0SRSC1_M 31
659 #define CP0SRSC1_SRS6 20
660 #define CP0SRSC1_SRS5 10
661 #define CP0SRSC1_SRS4 0
662 int32_t CP0_SRSConf2_rw_bitmask
;
663 int32_t CP0_SRSConf2
;
664 #define CP0SRSC2_M 31
665 #define CP0SRSC2_SRS9 20
666 #define CP0SRSC2_SRS8 10
667 #define CP0SRSC2_SRS7 0
668 int32_t CP0_SRSConf3_rw_bitmask
;
669 int32_t CP0_SRSConf3
;
670 #define CP0SRSC3_M 31
671 #define CP0SRSC3_SRS12 20
672 #define CP0SRSC3_SRS11 10
673 #define CP0SRSC3_SRS10 0
674 int32_t CP0_SRSConf4_rw_bitmask
;
675 int32_t CP0_SRSConf4
;
676 #define CP0SRSC4_SRS15 20
677 #define CP0SRSC4_SRS14 10
678 #define CP0SRSC4_SRS13 0
686 target_ulong CP0_BadVAddr
;
687 uint32_t CP0_BadInstr
;
688 uint32_t CP0_BadInstrP
;
689 uint32_t CP0_BadInstrX
;
695 #define CP0SAARI_TARGET 0 /* 5..0 */
696 uint64_t CP0_SAAR
[2];
697 #define CP0SAAR_BASE 12 /* 43..12 */
698 #define CP0SAAR_SIZE 1 /* 5..1 */
703 target_ulong CP0_EntryHi
;
704 #define CP0EnHi_EHINV 10
705 target_ulong CP0_EntryHi_ASID_mask
;
736 #define CP0IntCtl_IPTI 29
737 #define CP0IntCtl_IPPCI 26
738 #define CP0IntCtl_VS 5
740 #define CP0SRSCtl_HSS 26
741 #define CP0SRSCtl_EICSS 18
742 #define CP0SRSCtl_ESS 12
743 #define CP0SRSCtl_PSS 6
744 #define CP0SRSCtl_CSS 0
746 #define CP0SRSMap_SSV7 28
747 #define CP0SRSMap_SSV6 24
748 #define CP0SRSMap_SSV5 20
749 #define CP0SRSMap_SSV4 16
750 #define CP0SRSMap_SSV3 12
751 #define CP0SRSMap_SSV2 8
752 #define CP0SRSMap_SSV1 4
753 #define CP0SRSMap_SSV0 0
766 #define CP0Ca_IP_mask 0x0000FF00
771 target_ulong CP0_EPC
;
776 target_ulong CP0_EBase
;
777 target_ulong CP0_EBaseWG_rw_bitmask
;
778 #define CP0EBase_WG 11
779 target_ulong CP0_CMGCRBase
;
785 #define CP0C0_K23 28 /* 30..28 */
786 #define CP0C0_KU 25 /* 27..25 */
790 #define CP0C0_Impl 16 /* 24..16 */
792 #define CP0C0_AT 13 /* 14..13 */
793 #define CP0C0_AR 10 /* 12..10 */
794 #define CP0C0_MT 7 /* 9..7 */
796 #define CP0C0_K0 0 /* 2..0 */
799 #define CP0C1_MMU 25 /* 30..25 */
800 #define CP0C1_IS 22 /* 24..22 */
801 #define CP0C1_IL 19 /* 21..19 */
802 #define CP0C1_IA 16 /* 18..16 */
803 #define CP0C1_DS 13 /* 15..13 */
804 #define CP0C1_DL 10 /* 12..10 */
805 #define CP0C1_DA 7 /* 9..7 */
815 #define CP0C2_TU 28 /* 30..28 */
816 #define CP0C2_TS 24 /* 27..24 */
817 #define CP0C2_TL 20 /* 23..20 */
818 #define CP0C2_TA 16 /* 19..16 */
819 #define CP0C2_SU 12 /* 15..12 */
820 #define CP0C2_SS 8 /* 11..8 */
821 #define CP0C2_SL 4 /* 7..4 */
822 #define CP0C2_SA 0 /* 3..0 */
826 #define CP0C3_CMGCR 29
827 #define CP0C3_MSAP 28
833 #define CP0C3_IPLV 21 /* 22..21 */
834 #define CP0C3_MMAR 18 /* 20..18 */
836 #define CP0C3_ISA_ON_EXC 16
837 #define CP0C3_ISA 14 /* 15..14 */
838 #define CP0C3_ULRI 13
840 #define CP0C3_DSP2P 11
841 #define CP0C3_DSPP 10
842 #define CP0C3_CTXTC 9
853 int32_t CP0_Config4_rw_bitmask
;
855 #define CP0C4_IE 29 /* 30..29 */
857 #define CP0C4_VTLBSizeExt 24 /* 27..24 */
858 #define CP0C4_KScrExist 16
859 #define CP0C4_MMUExtDef 14
860 #define CP0C4_FTLBPageSize 8 /* 12..8 */
861 /* bit layout if MMUExtDef=1 */
862 #define CP0C4_MMUSizeExt 0 /* 7..0 */
863 /* bit layout if MMUExtDef=2 */
864 #define CP0C4_FTLBWays 4 /* 7..4 */
865 #define CP0C4_FTLBSets 0 /* 3..0 */
867 int32_t CP0_Config5_rw_bitmask
;
872 #define CP0C5_MSAEn 27
873 #define CP0C5_PMJ 23 /* 25..23 */
878 #define CP0C5_CRCP 18
880 #define CP0C5_GI 15 /* 16..15 */
893 #define CP0C5_NFExists 0
897 uint64_t CP0_MAAR
[MIPS_MAAR_MAX
];
899 /* XXX: Maybe make LLAddr per-TC? */
903 target_ulong lladdr
; /* LL virtual address compared against SC */
906 uint32_t llnewval_wp
;
907 uint64_t CP0_LLAddr_rw_bitmask
;
908 int CP0_LLAddr_shift
;
912 target_ulong CP0_WatchLo
[8];
916 int32_t CP0_WatchHi
[8];
917 #define CP0WH_ASID 16
921 target_ulong CP0_XContext
;
922 int32_t CP0_Framemask
;
929 #define CP0DB_LSNM 28
930 #define CP0DB_Doze 27
931 #define CP0DB_Halt 26
933 #define CP0DB_IBEP 24
934 #define CP0DB_DBEP 21
935 #define CP0DB_IEXI 20
948 target_ulong CP0_DEPC
;
952 int32_t CP0_Performance0
;
973 target_ulong CP0_ErrorEPC
;
979 /* We waste some space so we can handle shadow registers like TCs. */
980 TCState tcs
[MIPS_SHADOW_SET_MAX
];
981 CPUMIPSFPUContext fpus
[MIPS_FPU_MAX
];
984 #define EXCP_TLB_NOMATCH 0x1
985 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
986 uint32_t hflags
; /* CPU State */
987 /* TMASK defines different execution modes */
988 #define MIPS_HFLAG_TMASK 0x1F5807FF
989 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
991 * The KSU flags must be the lowest bits in hflags. The flag order
992 * must be the same as defined for CP0 Status. This allows to use
993 * the bits as the value of mmu_idx.
995 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
996 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
997 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
998 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
999 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
1000 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
1001 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
1002 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
1003 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
1005 * True if the MIPS IV COP1X instructions can be used. This also
1006 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1009 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
1010 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
1011 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
1012 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
1013 #define MIPS_HFLAG_M16_SHIFT 10
1015 * If translation is interrupted between the branch instruction and
1016 * the delay slot, record what type of branch it is so that we can
1017 * resume translation properly. It might be possible to reduce
1018 * this from three bits to two.
1020 #define MIPS_HFLAG_BMASK_BASE 0x803800
1021 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
1022 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
1023 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
1024 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
1025 /* Extra flags about the current pending branch. */
1026 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1027 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
1028 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
1029 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
1030 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
1031 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
1032 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1033 /* MIPS DSP resources access. */
1034 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */
1035 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */
1036 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1037 /* Extra flag about HWREna register. */
1038 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1039 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1040 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
1041 #define MIPS_HFLAG_MSA 0x1000000
1042 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
1043 #define MIPS_HFLAG_ELPA 0x4000000
1044 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
1045 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
1046 target_ulong btarget
; /* Jump / branch target */
1047 target_ulong bcond
; /* Branch condition (if needed) */
1049 int SYNCI_Step
; /* Address step size for SYNCI */
1050 int CCRes
; /* Cycle count resolution/divisor */
1051 uint32_t CP0_Status_rw_bitmask
; /* Read/write bits in CP0_Status */
1052 uint32_t CP0_TCStatus_rw_bitmask
; /* Read/write bits in CP0_TCStatus */
1053 uint64_t insn_flags
; /* Supported instruction set */
1056 /* Fields up to this point are cleared by a CPU reset */
1057 struct {} end_reset_fields
;
1059 /* Fields from here on are preserved across CPU reset. */
1060 CPUMIPSMVPContext
*mvp
;
1061 #if !defined(CONFIG_USER_ONLY)
1062 CPUMIPSTLBContext
*tlb
;
1065 const mips_def_t
*cpu_model
;
1067 QEMUTimer
*timer
; /* Internal timer */
1068 struct MIPSITUState
*itu
;
1069 MemoryRegion
*itc_tag
; /* ITC Configuration Tags */
1070 target_ulong exception_base
; /* ExceptionBase input to the core */
1075 * @env: #CPUMIPSState
1081 CPUState parent_obj
;
1084 CPUNegativeOffsetState neg
;
1089 void mips_cpu_list(void);
1091 #define cpu_signal_handler cpu_mips_signal_handler
1092 #define cpu_list mips_cpu_list
1094 extern void cpu_wrdsp(uint32_t rs
, uint32_t mask_num
, CPUMIPSState
*env
);
1095 extern uint32_t cpu_rddsp(uint32_t mask_num
, CPUMIPSState
*env
);
1098 * MMU modes definitions. We carefully match the indices with our
1101 #define MMU_MODE0_SUFFIX _kernel
1102 #define MMU_MODE1_SUFFIX _super
1103 #define MMU_MODE2_SUFFIX _user
1104 #define MMU_MODE3_SUFFIX _error
1105 #define MMU_USER_IDX 2
1107 static inline int hflags_mmu_index(uint32_t hflags
)
1109 if (hflags
& MIPS_HFLAG_ERL
) {
1112 return hflags
& MIPS_HFLAG_KSU
;
1116 static inline int cpu_mmu_index(CPUMIPSState
*env
, bool ifetch
)
1118 return hflags_mmu_index(env
->hflags
);
1121 typedef CPUMIPSState CPUArchState
;
1122 typedef MIPSCPU ArchCPU
;
1124 #include "exec/cpu-all.h"
1127 * Memory access type :
1128 * may be needed for precise access rights control and precise exceptions.
1131 /* 1 bit to define user level / supervisor access */
1133 ACCESS_SUPER
= 0x01,
1134 /* 1 bit to indicate direction */
1135 ACCESS_STORE
= 0x02,
1136 /* Type of instruction that generated the access */
1137 ACCESS_CODE
= 0x10, /* Code fetch access */
1138 ACCESS_INT
= 0x20, /* Integer load/store access */
1139 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
1153 EXCP_EXT_INTERRUPT
, /* 8 */
1169 EXCP_DWATCH
, /* 24 */
1177 EXCP_CACHE
, /* 32 */
1184 EXCP_LAST
= EXCP_TLBRI
,
1188 * This is an internally generated WAKE request line.
1189 * It is driven by the CPU itself. Raised when the MT
1190 * block wants to wake a VPE from an inactive state and
1191 * cleared when VPE goes from active to inactive.
1193 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1195 int cpu_mips_signal_handler(int host_signum
, void *pinfo
, void *puc
);
1197 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1198 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1199 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1201 bool cpu_supports_cps_smp(const char *cpu_type
);
1202 bool cpu_supports_isa(const char *cpu_type
, uint64_t isa
);
1203 void cpu_set_exception_base(int vp_index
, target_ulong address
);
1206 void cpu_mips_soft_irq(CPUMIPSState
*env
, int irq
, int level
);
1209 void itc_reconfigure(struct MIPSITUState
*tag
);
1212 target_ulong
exception_resume_pc(CPUMIPSState
*env
);
1214 static inline void cpu_get_tb_cpu_state(CPUMIPSState
*env
, target_ulong
*pc
,
1215 target_ulong
*cs_base
, uint32_t *flags
)
1217 *pc
= env
->active_tc
.PC
;
1219 *flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
|
1220 MIPS_HFLAG_HWRENA_ULR
);
1223 #endif /* MIPS_CPU_H */