2 * ARM page table walking.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/range.h"
13 #include "internals.h"
17 typedef struct S1Translate
{
24 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
26 MMUAccessType access_type
, bool s1_is_el0
,
27 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
28 __attribute__((nonnull
));
30 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
31 static const uint8_t pamax_map
[] = {
41 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
42 unsigned int arm_pamax(ARMCPU
*cpu
)
44 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
45 unsigned int parange
=
46 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
49 * id_aa64mmfr0 is a read-only register so values outside of the
50 * supported mappings can be considered an implementation error.
52 assert(parange
< ARRAY_SIZE(pamax_map
));
53 return pamax_map
[parange
];
57 * In machvirt_init, we call arm_pamax on a cpu that is not fully
58 * initialized, so we can't rely on the propagation done in realize.
60 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
) ||
61 arm_feature(&cpu
->env
, ARM_FEATURE_V7VE
)) {
70 * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
72 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
76 return ARMMMUIdx_Stage1_E0
;
78 return ARMMMUIdx_Stage1_E1
;
79 case ARMMMUIdx_E10_1_PAN
:
80 return ARMMMUIdx_Stage1_E1_PAN
;
86 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
88 return stage_1_mmu_idx(arm_mmu_idx(env
));
91 static bool regime_translation_big_endian(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
93 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
96 static bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
100 case ARMMMUIdx_Stage1_E0
:
101 case ARMMMUIdx_MUser
:
102 case ARMMMUIdx_MSUser
:
103 case ARMMMUIdx_MUserNegPri
:
104 case ARMMMUIdx_MSUserNegPri
:
108 case ARMMMUIdx_E10_0
:
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 g_assert_not_reached();
115 /* Return the TTBR associated with this translation regime */
116 static uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ttbrn
)
118 if (mmu_idx
== ARMMMUIdx_Stage2
) {
119 return env
->cp15
.vttbr_el2
;
121 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
122 return env
->cp15
.vsttbr_el2
;
125 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
127 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
131 /* Return true if the specified stage of address translation is disabled */
132 static bool regime_translation_disabled(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
137 if (arm_feature(env
, ARM_FEATURE_M
)) {
138 switch (env
->v7m
.mpu_ctrl
[is_secure
] &
139 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
140 case R_V7M_MPU_CTRL_ENABLE_MASK
:
141 /* Enabled, but not for HardFault and NMI */
142 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
143 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
144 /* Enabled for all cases */
149 * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
150 * we warned about that in armv7m_nvic.c when the guest set it.
156 hcr_el2
= arm_hcr_el2_eff_secstate(env
, is_secure
);
159 case ARMMMUIdx_Stage2
:
160 case ARMMMUIdx_Stage2_S
:
161 /* HCR.DC means HCR.VM behaves as 1 */
162 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
164 case ARMMMUIdx_E10_0
:
165 case ARMMMUIdx_E10_1
:
166 case ARMMMUIdx_E10_1_PAN
:
167 /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
168 if (hcr_el2
& HCR_TGE
) {
173 case ARMMMUIdx_Stage1_E0
:
174 case ARMMMUIdx_Stage1_E1
:
175 case ARMMMUIdx_Stage1_E1_PAN
:
176 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
177 if (hcr_el2
& HCR_DC
) {
182 case ARMMMUIdx_E20_0
:
183 case ARMMMUIdx_E20_2
:
184 case ARMMMUIdx_E20_2_PAN
:
189 case ARMMMUIdx_Phys_NS
:
190 case ARMMMUIdx_Phys_S
:
191 /* No translation for physical address spaces. */
195 g_assert_not_reached();
198 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
201 static bool ptw_attrs_are_device(uint64_t hcr
, ARMCacheAttrs cacheattrs
)
204 * For an S1 page table walk, the stage 1 attributes are always
205 * some form of "this is Normal memory". The combined S1+S2
206 * attributes are therefore only Device if stage 2 specifies Device.
207 * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
208 * ie when cacheattrs.attrs bits [3:2] are 0b00.
209 * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
210 * when cacheattrs.attrs bit [2] is 0.
212 assert(cacheattrs
.is_s2_format
);
214 return (cacheattrs
.attrs
& 0x4) == 0;
216 return (cacheattrs
.attrs
& 0xc) == 0;
220 /* Translate a S1 pagetable walk through S2 if needed. */
221 static bool S1_ptw_translate(CPUARMState
*env
, S1Translate
*ptw
,
222 hwaddr addr
, ARMMMUFaultInfo
*fi
)
224 bool is_secure
= ptw
->in_secure
;
225 ARMMMUIdx s2_mmu_idx
= is_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
227 if (arm_mmu_idx_is_stage1_of_2(ptw
->in_mmu_idx
) &&
228 !regime_translation_disabled(env
, s2_mmu_idx
, is_secure
)) {
229 GetPhysAddrResult s2
= {};
230 S1Translate s2ptw
= {
231 .in_mmu_idx
= s2_mmu_idx
,
232 .in_secure
= is_secure
,
237 ret
= get_phys_addr_lpae(env
, &s2ptw
, addr
, MMU_DATA_LOAD
,
240 assert(fi
->type
!= ARMFault_None
);
244 fi
->s1ns
= !is_secure
;
248 hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
249 if ((hcr
& HCR_PTW
) && ptw_attrs_are_device(hcr
, s2
.cacheattrs
)) {
251 * PTW set and S1 walk touched S2 Device memory:
252 * generate Permission fault.
254 fi
->type
= ARMFault_Permission
;
258 fi
->s1ns
= !is_secure
;
262 if (arm_is_secure_below_el3(env
)) {
263 /* Check if page table walk is to secure or non-secure PA space. */
265 is_secure
= !(env
->cp15
.vstcr_el2
& VSTCR_SW
);
267 is_secure
= !(env
->cp15
.vtcr_el2
& VTCR_NSW
);
273 addr
= s2
.f
.phys_addr
;
276 ptw
->out_secure
= is_secure
;
277 ptw
->out_phys
= addr
;
281 /* All loads done in the course of a page table walk go through here. */
282 static uint32_t arm_ldl_ptw(CPUARMState
*env
, S1Translate
*ptw
, hwaddr addr
,
285 CPUState
*cs
= env_cpu(env
);
286 MemTxAttrs attrs
= {};
287 MemTxResult result
= MEMTX_OK
;
291 if (!S1_ptw_translate(env
, ptw
, addr
, fi
)) {
294 addr
= ptw
->out_phys
;
295 attrs
.secure
= ptw
->out_secure
;
296 as
= arm_addressspace(cs
, attrs
);
297 if (regime_translation_big_endian(env
, ptw
->in_mmu_idx
)) {
298 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
300 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
302 if (result
== MEMTX_OK
) {
305 fi
->type
= ARMFault_SyncExternalOnWalk
;
306 fi
->ea
= arm_extabort_type(result
);
310 static uint64_t arm_ldq_ptw(CPUARMState
*env
, S1Translate
*ptw
, hwaddr addr
,
313 CPUState
*cs
= env_cpu(env
);
314 MemTxAttrs attrs
= {};
315 MemTxResult result
= MEMTX_OK
;
319 if (!S1_ptw_translate(env
, ptw
, addr
, fi
)) {
322 addr
= ptw
->out_phys
;
323 attrs
.secure
= ptw
->out_secure
;
324 as
= arm_addressspace(cs
, attrs
);
325 if (regime_translation_big_endian(env
, ptw
->in_mmu_idx
)) {
326 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
328 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
330 if (result
== MEMTX_OK
) {
333 fi
->type
= ARMFault_SyncExternalOnWalk
;
334 fi
->ea
= arm_extabort_type(result
);
338 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
339 uint32_t *table
, uint32_t address
)
341 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
342 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
343 int maskshift
= extract32(tcr
, 0, 3);
344 uint32_t mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
347 if (address
& mask
) {
348 if (tcr
& TTBCR_PD1
) {
349 /* Translation table walk disabled for TTBR1 */
352 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
354 if (tcr
& TTBCR_PD0
) {
355 /* Translation table walk disabled for TTBR0 */
358 base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
359 *table
= regime_ttbr(env
, mmu_idx
, 0) & base_mask
;
361 *table
|= (address
>> 18) & 0x3ffc;
366 * Translate section/page access permissions to page R/W protection flags
368 * @mmu_idx: MMU index indicating required translation regime
369 * @ap: The 3-bit access permissions (AP[2:0])
370 * @domain_prot: The 2-bit domain access permissions
372 static int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
373 int ap
, int domain_prot
)
375 bool is_user
= regime_is_user(env
, mmu_idx
);
377 if (domain_prot
== 3) {
378 return PAGE_READ
| PAGE_WRITE
;
383 if (arm_feature(env
, ARM_FEATURE_V7
)) {
386 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
388 return is_user
? 0 : PAGE_READ
;
395 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
400 return PAGE_READ
| PAGE_WRITE
;
403 return PAGE_READ
| PAGE_WRITE
;
404 case 4: /* Reserved. */
407 return is_user
? 0 : PAGE_READ
;
411 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
416 g_assert_not_reached();
421 * Translate section/page access permissions to page R/W protection flags.
422 * @ap: The 2-bit simple AP (AP[2:1])
423 * @is_user: TRUE if accessing from PL0
425 static int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
429 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
431 return PAGE_READ
| PAGE_WRITE
;
433 return is_user
? 0 : PAGE_READ
;
437 g_assert_not_reached();
441 static int simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
443 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
446 static bool get_phys_addr_v5(CPUARMState
*env
, S1Translate
*ptw
,
447 uint32_t address
, MMUAccessType access_type
,
448 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
460 /* Pagetable walk. */
461 /* Lookup l1 descriptor. */
462 if (!get_level1_table_address(env
, ptw
->in_mmu_idx
, &table
, address
)) {
463 /* Section translation fault if page walk is disabled by PD0 or PD1 */
464 fi
->type
= ARMFault_Translation
;
467 desc
= arm_ldl_ptw(env
, ptw
, table
, fi
);
468 if (fi
->type
!= ARMFault_None
) {
472 domain
= (desc
>> 5) & 0x0f;
473 if (regime_el(env
, ptw
->in_mmu_idx
) == 1) {
474 dacr
= env
->cp15
.dacr_ns
;
476 dacr
= env
->cp15
.dacr_s
;
478 domain_prot
= (dacr
>> (domain
* 2)) & 3;
480 /* Section translation fault. */
481 fi
->type
= ARMFault_Translation
;
487 if (domain_prot
== 0 || domain_prot
== 2) {
488 fi
->type
= ARMFault_Domain
;
493 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
494 ap
= (desc
>> 10) & 3;
495 result
->f
.lg_page_size
= 20; /* 1MB */
497 /* Lookup l2 entry. */
499 /* Coarse pagetable. */
500 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
502 /* Fine pagetable. */
503 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
505 desc
= arm_ldl_ptw(env
, ptw
, table
, fi
);
506 if (fi
->type
!= ARMFault_None
) {
510 case 0: /* Page translation fault. */
511 fi
->type
= ARMFault_Translation
;
513 case 1: /* 64k page. */
514 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
515 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
516 result
->f
.lg_page_size
= 16;
518 case 2: /* 4k page. */
519 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
520 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
521 result
->f
.lg_page_size
= 12;
523 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
525 /* ARMv6/XScale extended small page format */
526 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
527 || arm_feature(env
, ARM_FEATURE_V6
)) {
528 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
529 result
->f
.lg_page_size
= 12;
532 * UNPREDICTABLE in ARMv5; we choose to take a
533 * page translation fault.
535 fi
->type
= ARMFault_Translation
;
539 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
540 result
->f
.lg_page_size
= 10;
542 ap
= (desc
>> 4) & 3;
545 /* Never happens, but compiler isn't smart enough to tell. */
546 g_assert_not_reached();
549 result
->f
.prot
= ap_to_rw_prot(env
, ptw
->in_mmu_idx
, ap
, domain_prot
);
550 result
->f
.prot
|= result
->f
.prot
? PAGE_EXEC
: 0;
551 if (!(result
->f
.prot
& (1 << access_type
))) {
552 /* Access permission fault. */
553 fi
->type
= ARMFault_Permission
;
556 result
->f
.phys_addr
= phys_addr
;
564 static bool get_phys_addr_v6(CPUARMState
*env
, S1Translate
*ptw
,
565 uint32_t address
, MMUAccessType access_type
,
566 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
568 ARMCPU
*cpu
= env_archcpu(env
);
569 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
583 /* Pagetable walk. */
584 /* Lookup l1 descriptor. */
585 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
586 /* Section translation fault if page walk is disabled by PD0 or PD1 */
587 fi
->type
= ARMFault_Translation
;
590 desc
= arm_ldl_ptw(env
, ptw
, table
, fi
);
591 if (fi
->type
!= ARMFault_None
) {
595 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
596 /* Section translation fault, or attempt to use the encoding
597 * which is Reserved on implementations without PXN.
599 fi
->type
= ARMFault_Translation
;
602 if ((type
== 1) || !(desc
& (1 << 18))) {
603 /* Page or Section. */
604 domain
= (desc
>> 5) & 0x0f;
606 if (regime_el(env
, mmu_idx
) == 1) {
607 dacr
= env
->cp15
.dacr_ns
;
609 dacr
= env
->cp15
.dacr_s
;
614 domain_prot
= (dacr
>> (domain
* 2)) & 3;
615 if (domain_prot
== 0 || domain_prot
== 2) {
616 /* Section or Page domain fault */
617 fi
->type
= ARMFault_Domain
;
621 if (desc
& (1 << 18)) {
623 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
624 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
625 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
626 result
->f
.lg_page_size
= 24; /* 16MB */
629 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
630 result
->f
.lg_page_size
= 20; /* 1MB */
632 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
633 xn
= desc
& (1 << 4);
635 ns
= extract32(desc
, 19, 1);
637 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
638 pxn
= (desc
>> 2) & 1;
640 ns
= extract32(desc
, 3, 1);
641 /* Lookup l2 entry. */
642 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
643 desc
= arm_ldl_ptw(env
, ptw
, table
, fi
);
644 if (fi
->type
!= ARMFault_None
) {
647 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
649 case 0: /* Page translation fault. */
650 fi
->type
= ARMFault_Translation
;
652 case 1: /* 64k page. */
653 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
654 xn
= desc
& (1 << 15);
655 result
->f
.lg_page_size
= 16;
657 case 2: case 3: /* 4k page. */
658 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
660 result
->f
.lg_page_size
= 12;
663 /* Never happens, but compiler isn't smart enough to tell. */
664 g_assert_not_reached();
667 if (domain_prot
== 3) {
668 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
670 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
673 if (xn
&& access_type
== MMU_INST_FETCH
) {
674 fi
->type
= ARMFault_Permission
;
678 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
679 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
680 /* The simplified model uses AP[0] as an access control bit. */
682 /* Access flag fault. */
683 fi
->type
= ARMFault_AccessFlag
;
686 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
688 result
->f
.prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
690 if (result
->f
.prot
&& !xn
) {
691 result
->f
.prot
|= PAGE_EXEC
;
693 if (!(result
->f
.prot
& (1 << access_type
))) {
694 /* Access permission fault. */
695 fi
->type
= ARMFault_Permission
;
700 /* The NS bit will (as required by the architecture) have no effect if
701 * the CPU doesn't support TZ or this is a non-secure translation
702 * regime, because the attribute will already be non-secure.
704 result
->f
.attrs
.secure
= false;
706 result
->f
.phys_addr
= phys_addr
;
715 * Translate S2 section/page access permissions to protection flags
717 * @s2ap: The 2-bit stage2 access permissions (S2AP)
718 * @xn: XN (execute-never) bits
719 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
721 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
732 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
750 g_assert_not_reached();
753 if (!extract32(xn
, 1, 1)) {
754 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
763 * Translate section/page access permissions to protection flags
765 * @mmu_idx: MMU index indicating required translation regime
766 * @is_aa64: TRUE if AArch64
767 * @ap: The 2-bit simple AP (AP[2:1])
768 * @ns: NS (non-secure) bit
769 * @xn: XN (execute-never) bit
770 * @pxn: PXN (privileged execute-never) bit
772 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
773 int ap
, int ns
, int xn
, int pxn
)
775 bool is_user
= regime_is_user(env
, mmu_idx
);
776 int prot_rw
, user_rw
;
780 assert(mmu_idx
!= ARMMMUIdx_Stage2
);
781 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
783 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
787 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
788 /* PAN forbids data accesses but doesn't affect insn fetch */
791 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
795 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
799 /* TODO have_wxn should be replaced with
800 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
801 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
802 * compatible processors have EL2, which is required for [U]WXN.
804 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
807 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
811 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
812 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
814 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
815 switch (regime_el(env
, mmu_idx
)) {
819 xn
= xn
|| !(user_rw
& PAGE_READ
);
823 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
825 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
826 (uwxn
&& (user_rw
& PAGE_WRITE
));
836 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
839 return prot_rw
| PAGE_EXEC
;
842 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
845 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
846 uint32_t el
= regime_el(env
, mmu_idx
);
850 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
852 if (mmu_idx
== ARMMMUIdx_Stage2
) {
854 bool sext
= extract32(tcr
, 4, 1);
855 bool sign
= extract32(tcr
, 3, 1);
858 * If the sign-extend bit is not the same as t0sz[3], the result
859 * is unpredictable. Flag this as a guest error.
862 qemu_log_mask(LOG_GUEST_ERROR
,
863 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
865 tsz
= sextract32(tcr
, 0, 4) + 8;
869 } else if (el
== 2) {
871 tsz
= extract32(tcr
, 0, 3);
873 hpd
= extract64(tcr
, 24, 1);
876 int t0sz
= extract32(tcr
, 0, 3);
877 int t1sz
= extract32(tcr
, 16, 3);
880 select
= va
> (0xffffffffu
>> t0sz
);
882 /* Note that we will detect errors later. */
883 select
= va
>= ~(0xffffffffu
>> t1sz
);
887 epd
= extract32(tcr
, 7, 1);
888 hpd
= extract64(tcr
, 41, 1);
891 epd
= extract32(tcr
, 23, 1);
892 hpd
= extract64(tcr
, 42, 1);
894 /* For aarch32, hpd0 is not enabled without t2e as well. */
895 hpd
&= extract32(tcr
, 6, 1);
898 return (ARMVAParameters
) {
909 * @is_aa64: True if the translation regime is in AArch64 state
910 * @startlevel: Suggested starting level
911 * @inputsize: Bitsize of IPAs
912 * @stride: Page-table stride (See the ARM ARM)
914 * Returns true if the suggested S2 translation parameters are OK and
917 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
918 int inputsize
, int stride
, int outputsize
)
920 const int grainsize
= stride
+ 3;
924 * Negative levels are usually not allowed...
925 * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
926 * begins with level -1. Note that previous feature tests will have
927 * eliminated this combination if it is not enabled.
929 if (level
< (inputsize
== 52 && stride
== 9 ? -1 : 0)) {
933 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
934 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
940 case 13: /* 64KB Pages. */
941 if (level
== 0 || (level
== 1 && outputsize
<= 42)) {
945 case 11: /* 16KB Pages. */
946 if (level
== 0 || (level
== 1 && outputsize
<= 40)) {
950 case 9: /* 4KB Pages. */
951 if (level
== 0 && outputsize
<= 42) {
956 g_assert_not_reached();
959 /* Inputsize checks. */
960 if (inputsize
> outputsize
&&
961 (arm_el_is_aa64(&cpu
->env
, 1) || inputsize
> 40)) {
962 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
966 /* AArch32 only supports 4KB pages. Assert on that. */
977 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
979 * Returns false if the translation was successful. Otherwise, phys_ptr,
980 * attrs, prot and page_size may not be filled in, and the populated fsr
981 * value provides information on why the translation aborted, in the format
982 * of a long-format DFSR/IFSR fault register, with the following caveat:
983 * the WnR bit is never set (the caller must do this).
986 * @ptw: Current and next stage parameters for the walk.
987 * @address: virtual address to get physical address for
988 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
989 * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
990 * (so this is a stage 2 page table walk),
991 * must be true if this is stage 2 of a stage 1+2
992 * walk for an EL0 access. If @mmu_idx is anything else,
993 * @s1_is_el0 is ignored.
994 * @result: set on translation success,
995 * @fi: set to fault info if the translation fails
997 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
999 MMUAccessType access_type
, bool s1_is_el0
,
1000 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1002 ARMCPU
*cpu
= env_archcpu(env
);
1003 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1004 bool is_secure
= ptw
->in_secure
;
1005 /* Read an LPAE long-descriptor translation table. */
1006 ARMFaultType fault_type
= ARMFault_Translation
;
1008 ARMVAParameters param
;
1010 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
1011 uint32_t tableattrs
;
1012 target_ulong page_size
;
1015 int addrsize
, inputsize
, outputsize
;
1016 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1017 int ap
, ns
, xn
, pxn
;
1018 uint32_t el
= regime_el(env
, mmu_idx
);
1019 uint64_t descaddrmask
;
1020 bool aarch64
= arm_el_is_aa64(env
, el
);
1021 bool guarded
= false;
1023 /* TODO: This code does not support shareability levels. */
1027 param
= aa64_va_parameters(env
, address
, mmu_idx
,
1028 access_type
!= MMU_INST_FETCH
);
1032 * If TxSZ is programmed to a value larger than the maximum,
1033 * or smaller than the effective minimum, it is IMPLEMENTATION
1034 * DEFINED whether we behave as if the field were programmed
1035 * within bounds, or if a level 0 Translation fault is generated.
1037 * With FEAT_LVA, fault on less than minimum becomes required,
1038 * so our choice is to always raise the fault.
1040 if (param
.tsz_oob
) {
1041 fault_type
= ARMFault_Translation
;
1045 addrsize
= 64 - 8 * param
.tbi
;
1046 inputsize
= 64 - param
.tsz
;
1049 * Bound PS by PARANGE to find the effective output address size.
1050 * ID_AA64MMFR0 is a read-only register so values outside of the
1051 * supported mappings can be considered an implementation error.
1053 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
1054 ps
= MIN(ps
, param
.ps
);
1055 assert(ps
< ARRAY_SIZE(pamax_map
));
1056 outputsize
= pamax_map
[ps
];
1058 param
= aa32_va_parameters(env
, address
, mmu_idx
);
1060 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
1061 inputsize
= addrsize
- param
.tsz
;
1066 * We determined the region when collecting the parameters, but we
1067 * have not yet validated that the address is valid for the region.
1068 * Extract the top bits and verify that they all match select.
1070 * For aa32, if inputsize == addrsize, then we have selected the
1071 * region by exclusion in aa32_va_parameters and there is no more
1072 * validation to do here.
1074 if (inputsize
< addrsize
) {
1075 target_ulong top_bits
= sextract64(address
, inputsize
,
1076 addrsize
- inputsize
);
1077 if (-top_bits
!= param
.select
) {
1078 /* The gap between the two regions is a Translation fault */
1079 fault_type
= ARMFault_Translation
;
1084 stride
= arm_granule_bits(param
.gran
) - 3;
1087 * Note that QEMU ignores shareability and cacheability attributes,
1088 * so we don't need to do anything with the SH, ORGN, IRGN fields
1089 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
1090 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
1091 * implement any ASID-like capability so we can ignore it (instead
1092 * we will always flush the TLB any time the ASID is changed).
1094 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
1097 * Here we should have set up all the parameters for the translation:
1098 * inputsize, ttbr, epd, stride, tbi
1103 * Translation table walk disabled => Translation fault on TLB miss
1104 * Note: This is always 0 on 64-bit EL2 and EL3.
1109 if (mmu_idx
!= ARMMMUIdx_Stage2
&& mmu_idx
!= ARMMMUIdx_Stage2_S
) {
1111 * The starting level depends on the virtual address size (which can
1112 * be up to 48 bits) and the translation granule size. It indicates
1113 * the number of strides (stride bits at a time) needed to
1114 * consume the bits of the input address. In the pseudocode this is:
1115 * level = 4 - RoundUp((inputsize - grainsize) / stride)
1116 * where their 'inputsize' is our 'inputsize', 'grainsize' is
1117 * our 'stride + 3' and 'stride' is our 'stride'.
1118 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
1119 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
1120 * = 4 - (inputsize - 4) / stride;
1122 level
= 4 - (inputsize
- 4) / stride
;
1125 * For stage 2 translations the starting level is specified by the
1126 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
1128 uint32_t sl0
= extract32(tcr
, 6, 2);
1129 uint32_t sl2
= extract64(tcr
, 33, 1);
1130 uint32_t startlevel
;
1133 /* SL2 is RES0 unless DS=1 & 4kb granule. */
1134 if (param
.ds
&& stride
== 9 && sl2
) {
1137 fault_type
= ARMFault_Translation
;
1141 } else if (!aarch64
|| stride
== 9) {
1142 /* AArch32 or 4KB pages */
1143 startlevel
= 2 - sl0
;
1145 if (cpu_isar_feature(aa64_st
, cpu
)) {
1149 /* 16KB or 64KB pages */
1150 startlevel
= 3 - sl0
;
1153 /* Check that the starting level is valid. */
1154 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
1155 inputsize
, stride
, outputsize
);
1157 fault_type
= ARMFault_Translation
;
1163 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
1164 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
1166 /* Now we can extract the actual base address from the TTBR */
1167 descaddr
= extract64(ttbr
, 0, 48);
1170 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
1172 * Otherwise, if the base address is out of range, raise AddressSizeFault.
1173 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
1174 * but we've just cleared the bits above 47, so simplify the test.
1176 if (outputsize
> 48) {
1177 descaddr
|= extract64(ttbr
, 2, 4) << 48;
1178 } else if (descaddr
>> outputsize
) {
1180 fault_type
= ARMFault_AddressSize
;
1185 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
1186 * and also to mask out CnP (bit 0) which could validly be non-zero.
1188 descaddr
&= ~indexmask
;
1191 * For AArch32, the address field in the descriptor goes up to bit 39
1192 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
1193 * or an AddressSize fault is raised. So for v8 we extract those SBZ
1194 * bits as part of the address, which will be checked via outputsize.
1195 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
1196 * the highest bits of a 52-bit output are placed elsewhere.
1199 descaddrmask
= MAKE_64BIT_MASK(0, 50);
1200 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
1201 descaddrmask
= MAKE_64BIT_MASK(0, 48);
1203 descaddrmask
= MAKE_64BIT_MASK(0, 40);
1205 descaddrmask
&= ~indexmask_grainsize
;
1208 * Secure accesses start with the page table in secure memory and
1209 * can be downgraded to non-secure at any step. Non-secure accesses
1210 * remain non-secure. We implement this by just ORing in the NSTable/NS
1211 * bits at each step.
1213 tableattrs
= is_secure
? 0 : (1 << 4);
1215 uint64_t descriptor
;
1218 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
1220 nstable
= extract32(tableattrs
, 4, 1);
1221 ptw
->in_secure
= !nstable
;
1222 descriptor
= arm_ldq_ptw(env
, ptw
, descaddr
, fi
);
1223 if (fi
->type
!= ARMFault_None
) {
1227 if (!(descriptor
& 1) ||
1228 (!(descriptor
& 2) && (level
== 3))) {
1229 /* Invalid, or the Reserved level 3 encoding */
1233 descaddr
= descriptor
& descaddrmask
;
1236 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
1237 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
1238 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
1239 * raise AddressSizeFault.
1241 if (outputsize
> 48) {
1243 descaddr
|= extract64(descriptor
, 8, 2) << 50;
1245 descaddr
|= extract64(descriptor
, 12, 4) << 48;
1247 } else if (descaddr
>> outputsize
) {
1248 fault_type
= ARMFault_AddressSize
;
1252 if ((descriptor
& 2) && (level
< 3)) {
1254 * Table entry. The top five bits are attributes which may
1255 * propagate down through lower levels of the table (and
1256 * which are all arranged so that 0 means "no effect", so
1257 * we can gather them up by ORing in the bits at each level).
1259 tableattrs
|= extract64(descriptor
, 59, 5);
1261 indexmask
= indexmask_grainsize
;
1265 * Block entry at level 1 or 2, or page entry at level 3.
1266 * These are basically the same thing, although the number
1267 * of bits we pull in from the vaddr varies. Note that although
1268 * descaddrmask masks enough of the low bits of the descriptor
1269 * to give a correct page or table address, the address field
1270 * in a block descriptor is smaller; so we need to explicitly
1271 * clear the lower bits here before ORing in the low vaddr bits.
1273 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
1274 descaddr
&= ~(hwaddr
)(page_size
- 1);
1275 descaddr
|= (address
& (page_size
- 1));
1276 /* Extract attributes from the descriptor */
1277 attrs
= extract64(descriptor
, 2, 10)
1278 | (extract64(descriptor
, 52, 12) << 10);
1280 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
1281 /* Stage 2 table descriptors do not include any attribute fields */
1284 /* Merge in attributes from table descriptors */
1285 attrs
|= nstable
<< 3; /* NS */
1286 guarded
= extract64(descriptor
, 50, 1); /* GP */
1288 /* HPD disables all the table attributes except NSTable. */
1291 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
1293 * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
1294 * means "force PL1 access only", which means forcing AP[1] to 0.
1296 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
1297 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
1301 * Here descaddr is the final physical address, and attributes
1304 fault_type
= ARMFault_AccessFlag
;
1305 if ((attrs
& (1 << 8)) == 0) {
1310 ap
= extract32(attrs
, 4, 2);
1312 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
1313 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1314 xn
= extract32(attrs
, 11, 2);
1315 result
->f
.prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
1317 ns
= extract32(attrs
, 3, 1);
1318 xn
= extract32(attrs
, 12, 1);
1319 pxn
= extract32(attrs
, 11, 1);
1320 result
->f
.prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
1323 fault_type
= ARMFault_Permission
;
1324 if (!(result
->f
.prot
& (1 << access_type
))) {
1330 * The NS bit will (as required by the architecture) have no effect if
1331 * the CPU doesn't support TZ or this is a non-secure translation
1332 * regime, because the attribute will already be non-secure.
1334 result
->f
.attrs
.secure
= false;
1337 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
1338 if (aarch64
&& cpu_isar_feature(aa64_bti
, cpu
)) {
1339 result
->f
.guarded
= guarded
;
1342 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
1343 result
->cacheattrs
.is_s2_format
= true;
1344 result
->cacheattrs
.attrs
= extract32(attrs
, 0, 4);
1346 /* Index into MAIR registers for cache attributes */
1347 uint8_t attrindx
= extract32(attrs
, 0, 3);
1348 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
1349 assert(attrindx
<= 7);
1350 result
->cacheattrs
.is_s2_format
= false;
1351 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
1355 * For FEAT_LPA2 and effective DS, the SH field in the attributes
1356 * was re-purposed for output address bits. The SH attribute in
1357 * that case comes from TCR_ELx, which we extracted earlier.
1360 result
->cacheattrs
.shareability
= param
.sh
;
1362 result
->cacheattrs
.shareability
= extract32(attrs
, 6, 2);
1365 result
->f
.phys_addr
= descaddr
;
1366 result
->f
.lg_page_size
= ctz64(page_size
);
1370 fi
->type
= fault_type
;
1372 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
1373 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_Stage2
||
1374 mmu_idx
== ARMMMUIdx_Stage2_S
);
1375 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1379 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
1380 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1381 bool is_secure
, GetPhysAddrResult
*result
,
1382 ARMMMUFaultInfo
*fi
)
1387 bool is_user
= regime_is_user(env
, mmu_idx
);
1389 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
1391 result
->f
.phys_addr
= address
;
1392 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1396 result
->f
.phys_addr
= address
;
1397 for (n
= 7; n
>= 0; n
--) {
1398 base
= env
->cp15
.c6_region
[n
];
1399 if ((base
& 1) == 0) {
1402 mask
= 1 << ((base
>> 1) & 0x1f);
1403 /* Keep this shift separate from the above to avoid an
1404 (undefined) << 32. */
1405 mask
= (mask
<< 1) - 1;
1406 if (((base
^ address
) & ~mask
) == 0) {
1411 fi
->type
= ARMFault_Background
;
1415 if (access_type
== MMU_INST_FETCH
) {
1416 mask
= env
->cp15
.pmsav5_insn_ap
;
1418 mask
= env
->cp15
.pmsav5_data_ap
;
1420 mask
= (mask
>> (n
* 4)) & 0xf;
1423 fi
->type
= ARMFault_Permission
;
1428 fi
->type
= ARMFault_Permission
;
1432 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1435 result
->f
.prot
= PAGE_READ
;
1437 result
->f
.prot
|= PAGE_WRITE
;
1441 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1445 fi
->type
= ARMFault_Permission
;
1449 result
->f
.prot
= PAGE_READ
;
1452 result
->f
.prot
= PAGE_READ
;
1455 /* Bad permission. */
1456 fi
->type
= ARMFault_Permission
;
1460 result
->f
.prot
|= PAGE_EXEC
;
1464 static void get_phys_addr_pmsav7_default(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1465 int32_t address
, uint8_t *prot
)
1467 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1468 *prot
= PAGE_READ
| PAGE_WRITE
;
1470 case 0xF0000000 ... 0xFFFFFFFF:
1471 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
1472 /* hivecs execing is ok */
1476 case 0x00000000 ... 0x7FFFFFFF:
1481 /* Default system address map for M profile cores.
1482 * The architecture specifies which regions are execute-never;
1483 * at the MPU level no other checks are defined.
1486 case 0x00000000 ... 0x1fffffff: /* ROM */
1487 case 0x20000000 ... 0x3fffffff: /* SRAM */
1488 case 0x60000000 ... 0x7fffffff: /* RAM */
1489 case 0x80000000 ... 0x9fffffff: /* RAM */
1490 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1492 case 0x40000000 ... 0x5fffffff: /* Peripheral */
1493 case 0xa0000000 ... 0xbfffffff: /* Device */
1494 case 0xc0000000 ... 0xdfffffff: /* Device */
1495 case 0xe0000000 ... 0xffffffff: /* System */
1496 *prot
= PAGE_READ
| PAGE_WRITE
;
1499 g_assert_not_reached();
1504 static bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
1506 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
1507 return arm_feature(env
, ARM_FEATURE_M
) &&
1508 extract32(address
, 20, 12) == 0xe00;
1511 static bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
1514 * True if address is in the M profile system region
1515 * 0xe0000000 - 0xffffffff
1517 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
1520 static bool pmsav7_use_background_region(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
1521 bool is_secure
, bool is_user
)
1524 * Return true if we should use the default memory map as a
1525 * "background" region if there are no hits against any MPU regions.
1527 CPUARMState
*env
= &cpu
->env
;
1533 if (arm_feature(env
, ARM_FEATURE_M
)) {
1534 return env
->v7m
.mpu_ctrl
[is_secure
] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
1536 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
1540 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
1541 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1542 bool secure
, GetPhysAddrResult
*result
,
1543 ARMMMUFaultInfo
*fi
)
1545 ARMCPU
*cpu
= env_archcpu(env
);
1547 bool is_user
= regime_is_user(env
, mmu_idx
);
1549 result
->f
.phys_addr
= address
;
1550 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1553 if (regime_translation_disabled(env
, mmu_idx
, secure
) ||
1554 m_is_ppb_region(env
, address
)) {
1556 * MPU disabled or M profile PPB access: use default memory map.
1557 * The other case which uses the default memory map in the
1558 * v7M ARM ARM pseudocode is exception vector reads from the vector
1559 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
1560 * which always does a direct read using address_space_ldl(), rather
1561 * than going via this function, so we don't need to check that here.
1563 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
1564 } else { /* MPU enabled */
1565 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1567 uint32_t base
= env
->pmsav7
.drbar
[n
];
1568 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
1572 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
1577 qemu_log_mask(LOG_GUEST_ERROR
,
1578 "DRSR[%d]: Rsize field cannot be 0\n", n
);
1582 rmask
= (1ull << rsize
) - 1;
1585 qemu_log_mask(LOG_GUEST_ERROR
,
1586 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
1587 "to DRSR region size, mask = 0x%" PRIx32
"\n",
1592 if (address
< base
|| address
> base
+ rmask
) {
1594 * Address not in this region. We must check whether the
1595 * region covers addresses in the same page as our address.
1596 * In that case we must not report a size that covers the
1597 * whole page for a subsequent hit against a different MPU
1598 * region or the background region, because it would result in
1599 * incorrect TLB hits for subsequent accesses to addresses that
1600 * are in this MPU region.
1602 if (ranges_overlap(base
, rmask
,
1603 address
& TARGET_PAGE_MASK
,
1604 TARGET_PAGE_SIZE
)) {
1605 result
->f
.lg_page_size
= 0;
1610 /* Region matched */
1612 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
1614 uint32_t srdis_mask
;
1616 rsize
-= 3; /* sub region size (power of 2) */
1617 snd
= ((address
- base
) >> rsize
) & 0x7;
1618 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
1620 srdis_mask
= srdis
? 0x3 : 0x0;
1621 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
1623 * This will check in groups of 2, 4 and then 8, whether
1624 * the subregion bits are consistent. rsize is incremented
1625 * back up to give the region size, considering consistent
1626 * adjacent subregions as one region. Stop testing if rsize
1627 * is already big enough for an entire QEMU page.
1629 int snd_rounded
= snd
& ~(i
- 1);
1630 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
1631 snd_rounded
+ 8, i
);
1632 if (srdis_mask
^ srdis_multi
) {
1635 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
1642 if (rsize
< TARGET_PAGE_BITS
) {
1643 result
->f
.lg_page_size
= rsize
;
1648 if (n
== -1) { /* no hits */
1649 if (!pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1650 /* background fault */
1651 fi
->type
= ARMFault_Background
;
1654 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
,
1656 } else { /* a MPU hit! */
1657 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
1658 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
1660 if (m_is_system_region(env
, address
)) {
1661 /* System space is always execute never */
1665 if (is_user
) { /* User mode AP bit decoding */
1670 break; /* no access */
1672 result
->f
.prot
|= PAGE_WRITE
;
1676 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1679 /* for v7M, same as 6; for R profile a reserved value */
1680 if (arm_feature(env
, ARM_FEATURE_M
)) {
1681 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1686 qemu_log_mask(LOG_GUEST_ERROR
,
1687 "DRACR[%d]: Bad value for AP bits: 0x%"
1688 PRIx32
"\n", n
, ap
);
1690 } else { /* Priv. mode AP bits decoding */
1693 break; /* no access */
1697 result
->f
.prot
|= PAGE_WRITE
;
1701 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1704 /* for v7M, same as 6; for R profile a reserved value */
1705 if (arm_feature(env
, ARM_FEATURE_M
)) {
1706 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1711 qemu_log_mask(LOG_GUEST_ERROR
,
1712 "DRACR[%d]: Bad value for AP bits: 0x%"
1713 PRIx32
"\n", n
, ap
);
1719 result
->f
.prot
&= ~PAGE_EXEC
;
1724 fi
->type
= ARMFault_Permission
;
1726 return !(result
->f
.prot
& (1 << access_type
));
1729 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
1730 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1731 bool secure
, GetPhysAddrResult
*result
,
1732 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
1735 * Perform a PMSAv8 MPU lookup (without also doing the SAU check
1736 * that a full phys-to-virt translation does).
1737 * mregion is (if not NULL) set to the region number which matched,
1738 * or -1 if no region number is returned (MPU off, address did not
1739 * hit a region, address hit in multiple regions).
1740 * If the region hit doesn't cover the entire TARGET_PAGE the address
1741 * is within, then we set the result page_size to 1 to force the
1742 * memory system to use a subpage.
1744 ARMCPU
*cpu
= env_archcpu(env
);
1745 bool is_user
= regime_is_user(env
, mmu_idx
);
1747 int matchregion
= -1;
1749 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
1750 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
1752 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1753 result
->f
.phys_addr
= address
;
1760 * Unlike the ARM ARM pseudocode, we don't need to check whether this
1761 * was an exception vector read from the vector table (which is always
1762 * done using the default system address map), because those accesses
1763 * are done in arm_v7m_load_vector(), which always does a direct
1764 * read using address_space_ldl(), rather than going via this function.
1766 if (regime_translation_disabled(env
, mmu_idx
, secure
)) { /* MPU disabled */
1768 } else if (m_is_ppb_region(env
, address
)) {
1771 if (pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1775 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1778 * Note that the base address is bits [31:5] from the register
1779 * with bits [4:0] all zeroes, but the limit address is bits
1780 * [31:5] from the register with bits [4:0] all ones.
1782 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
1783 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
1785 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
1786 /* Region disabled */
1790 if (address
< base
|| address
> limit
) {
1792 * Address not in this region. We must check whether the
1793 * region covers addresses in the same page as our address.
1794 * In that case we must not report a size that covers the
1795 * whole page for a subsequent hit against a different MPU
1796 * region or the background region, because it would result in
1797 * incorrect TLB hits for subsequent accesses to addresses that
1798 * are in this MPU region.
1800 if (limit
>= base
&&
1801 ranges_overlap(base
, limit
- base
+ 1,
1803 TARGET_PAGE_SIZE
)) {
1804 result
->f
.lg_page_size
= 0;
1809 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
1810 result
->f
.lg_page_size
= 0;
1813 if (matchregion
!= -1) {
1815 * Multiple regions match -- always a failure (unlike
1816 * PMSAv7 where highest-numbered-region wins)
1818 fi
->type
= ARMFault_Permission
;
1829 /* background fault */
1830 fi
->type
= ARMFault_Background
;
1834 if (matchregion
== -1) {
1835 /* hit using the background region */
1836 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
1838 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
1839 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
1842 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
1843 pxn
= extract32(env
->pmsav8
.rlar
[secure
][matchregion
], 4, 1);
1846 if (m_is_system_region(env
, address
)) {
1847 /* System space is always execute never */
1851 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
1852 if (result
->f
.prot
&& !xn
&& !(pxn
&& !is_user
)) {
1853 result
->f
.prot
|= PAGE_EXEC
;
1856 * We don't need to look the attribute up in the MAIR0/MAIR1
1857 * registers because that only tells us about cacheability.
1860 *mregion
= matchregion
;
1864 fi
->type
= ARMFault_Permission
;
1866 return !(result
->f
.prot
& (1 << access_type
));
1869 static bool v8m_is_sau_exempt(CPUARMState
*env
,
1870 uint32_t address
, MMUAccessType access_type
)
1873 * The architecture specifies that certain address ranges are
1874 * exempt from v8M SAU/IDAU checks.
1877 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
1878 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
1879 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
1880 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
1881 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
1882 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
1885 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
1886 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1887 bool is_secure
, V8M_SAttributes
*sattrs
)
1890 * Look up the security attributes for this address. Compare the
1891 * pseudocode SecurityCheck() function.
1892 * We assume the caller has zero-initialized *sattrs.
1894 ARMCPU
*cpu
= env_archcpu(env
);
1896 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
1897 int idau_region
= IREGION_NOTVALID
;
1898 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
1899 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
1902 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
1903 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
1905 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
1909 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
1910 /* 0xf0000000..0xffffffff is always S for insn fetches */
1914 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
1915 sattrs
->ns
= !is_secure
;
1919 if (idau_region
!= IREGION_NOTVALID
) {
1920 sattrs
->irvalid
= true;
1921 sattrs
->iregion
= idau_region
;
1924 switch (env
->sau
.ctrl
& 3) {
1925 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
1927 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
1930 default: /* SAU.ENABLE == 1 */
1931 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
1932 if (env
->sau
.rlar
[r
] & 1) {
1933 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
1934 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
1936 if (base
<= address
&& limit
>= address
) {
1937 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
1938 sattrs
->subpage
= true;
1940 if (sattrs
->srvalid
) {
1942 * If we hit in more than one region then we must report
1943 * as Secure, not NS-Callable, with no valid region
1947 sattrs
->nsc
= false;
1948 sattrs
->sregion
= 0;
1949 sattrs
->srvalid
= false;
1952 if (env
->sau
.rlar
[r
] & 2) {
1957 sattrs
->srvalid
= true;
1958 sattrs
->sregion
= r
;
1962 * Address not in this region. We must check whether the
1963 * region covers addresses in the same page as our address.
1964 * In that case we must not report a size that covers the
1965 * whole page for a subsequent hit against a different MPU
1966 * region or the background region, because it would result
1967 * in incorrect TLB hits for subsequent accesses to
1968 * addresses that are in this MPU region.
1970 if (limit
>= base
&&
1971 ranges_overlap(base
, limit
- base
+ 1,
1973 TARGET_PAGE_SIZE
)) {
1974 sattrs
->subpage
= true;
1983 * The IDAU will override the SAU lookup results if it specifies
1984 * higher security than the SAU does.
1987 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
1989 sattrs
->nsc
= idau_nsc
;
1994 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
1995 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1996 bool secure
, GetPhysAddrResult
*result
,
1997 ARMMMUFaultInfo
*fi
)
1999 V8M_SAttributes sattrs
= {};
2002 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2003 v8m_security_lookup(env
, address
, access_type
, mmu_idx
,
2005 if (access_type
== MMU_INST_FETCH
) {
2007 * Instruction fetches always use the MMU bank and the
2008 * transaction attribute determined by the fetch address,
2009 * regardless of CPU state. This is painful for QEMU
2010 * to handle, because it would mean we need to encode
2011 * into the mmu_idx not just the (user, negpri) information
2012 * for the current security state but also that for the
2013 * other security state, which would balloon the number
2014 * of mmu_idx values needed alarmingly.
2015 * Fortunately we can avoid this because it's not actually
2016 * possible to arbitrarily execute code from memory with
2017 * the wrong security attribute: it will always generate
2018 * an exception of some kind or another, apart from the
2019 * special case of an NS CPU executing an SG instruction
2020 * in S&NSC memory. So we always just fail the translation
2021 * here and sort things out in the exception handler
2022 * (including possibly emulating an SG instruction).
2024 if (sattrs
.ns
!= !secure
) {
2026 fi
->type
= ARMFault_QEMU_NSCExec
;
2028 fi
->type
= ARMFault_QEMU_SFault
;
2030 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2031 result
->f
.phys_addr
= address
;
2037 * For data accesses we always use the MMU bank indicated
2038 * by the current CPU state, but the security attributes
2039 * might downgrade a secure access to nonsecure.
2042 result
->f
.attrs
.secure
= false;
2043 } else if (!secure
) {
2045 * NS access to S memory must fault.
2046 * Architecturally we should first check whether the
2047 * MPU information for this address indicates that we
2048 * are doing an unaligned access to Device memory, which
2049 * should generate a UsageFault instead. QEMU does not
2050 * currently check for that kind of unaligned access though.
2051 * If we added it we would need to do so as a special case
2052 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
2054 fi
->type
= ARMFault_QEMU_SFault
;
2055 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2056 result
->f
.phys_addr
= address
;
2063 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, secure
,
2065 if (sattrs
.subpage
) {
2066 result
->f
.lg_page_size
= 0;
2072 * Translate from the 4-bit stage 2 representation of
2073 * memory attributes (without cache-allocation hints) to
2074 * the 8-bit representation of the stage 1 MAIR registers
2075 * (which includes allocation hints).
2077 * ref: shared/translation/attrs/S2AttrDecode()
2078 * .../S2ConvertAttrsHints()
2080 static uint8_t convert_stage2_attrs(uint64_t hcr
, uint8_t s2attrs
)
2082 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
2083 uint8_t loattr
= extract32(s2attrs
, 0, 2);
2084 uint8_t hihint
= 0, lohint
= 0;
2086 if (hiattr
!= 0) { /* normal memory */
2087 if (hcr
& HCR_CD
) { /* cache disabled */
2088 hiattr
= loattr
= 1; /* non-cacheable */
2090 if (hiattr
!= 1) { /* Write-through or write-back */
2091 hihint
= 3; /* RW allocate */
2093 if (loattr
!= 1) { /* Write-through or write-back */
2094 lohint
= 3; /* RW allocate */
2099 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
2103 * Combine either inner or outer cacheability attributes for normal
2104 * memory, according to table D4-42 and pseudocode procedure
2105 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
2107 * NB: only stage 1 includes allocation hints (RW bits), leading to
2110 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
2112 if (s1
== 4 || s2
== 4) {
2113 /* non-cacheable has precedence */
2115 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
2116 /* stage 1 write-through takes precedence */
2118 } else if (extract32(s2
, 2, 2) == 2) {
2119 /* stage 2 write-through takes precedence, but the allocation hint
2120 * is still taken from stage 1
2122 return (2 << 2) | extract32(s1
, 0, 2);
2123 } else { /* write-back */
2129 * Combine the memory type and cacheability attributes of
2130 * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
2131 * combined attributes in MAIR_EL1 format.
2133 static uint8_t combined_attrs_nofwb(uint64_t hcr
,
2134 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2136 uint8_t s1lo
, s2lo
, s1hi
, s2hi
, s2_mair_attrs
, ret_attrs
;
2138 s2_mair_attrs
= convert_stage2_attrs(hcr
, s2
.attrs
);
2140 s1lo
= extract32(s1
.attrs
, 0, 4);
2141 s2lo
= extract32(s2_mair_attrs
, 0, 4);
2142 s1hi
= extract32(s1
.attrs
, 4, 4);
2143 s2hi
= extract32(s2_mair_attrs
, 4, 4);
2145 /* Combine memory type and cacheability attributes */
2146 if (s1hi
== 0 || s2hi
== 0) {
2147 /* Device has precedence over normal */
2148 if (s1lo
== 0 || s2lo
== 0) {
2149 /* nGnRnE has precedence over anything */
2151 } else if (s1lo
== 4 || s2lo
== 4) {
2152 /* non-Reordering has precedence over Reordering */
2153 ret_attrs
= 4; /* nGnRE */
2154 } else if (s1lo
== 8 || s2lo
== 8) {
2155 /* non-Gathering has precedence over Gathering */
2156 ret_attrs
= 8; /* nGRE */
2158 ret_attrs
= 0xc; /* GRE */
2160 } else { /* Normal memory */
2161 /* Outer/inner cacheability combine independently */
2162 ret_attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
2163 | combine_cacheattr_nibble(s1lo
, s2lo
);
2168 static uint8_t force_cacheattr_nibble_wb(uint8_t attr
)
2171 * Given the 4 bits specifying the outer or inner cacheability
2172 * in MAIR format, return a value specifying Normal Write-Back,
2173 * with the allocation and transient hints taken from the input
2174 * if the input specified some kind of cacheable attribute.
2176 if (attr
== 0 || attr
== 4) {
2178 * 0 == an UNPREDICTABLE encoding
2179 * 4 == Non-cacheable
2180 * Either way, force Write-Back RW allocate non-transient
2184 /* Change WriteThrough to WriteBack, keep allocation and transient hints */
2189 * Combine the memory type and cacheability attributes of
2190 * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
2191 * combined attributes in MAIR_EL1 format.
2193 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2197 /* Use stage 1 attributes */
2201 * Force Normal Write-Back. Note that if S1 is Normal cacheable
2202 * then we take the allocation hints from it; otherwise it is
2203 * RW allocate, non-transient.
2205 if ((s1
.attrs
& 0xf0) == 0) {
2209 /* Need to check the Inner and Outer nibbles separately */
2210 return force_cacheattr_nibble_wb(s1
.attrs
& 0xf) |
2211 force_cacheattr_nibble_wb(s1
.attrs
>> 4) << 4;
2213 /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
2214 if ((s1
.attrs
& 0xf0) == 0) {
2219 /* Force Device, of subtype specified by S2 */
2220 return s2
.attrs
<< 2;
2223 * RESERVED values (including RES0 descriptor bit [5] being nonzero);
2224 * arbitrarily force Device.
2231 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
2232 * and CombineS1S2Desc()
2235 * @s1: Attributes from stage 1 walk
2236 * @s2: Attributes from stage 2 walk
2238 static ARMCacheAttrs
combine_cacheattrs(uint64_t hcr
,
2239 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2242 bool tagged
= false;
2244 assert(s2
.is_s2_format
&& !s1
.is_s2_format
);
2245 ret
.is_s2_format
= false;
2247 if (s1
.attrs
== 0xf0) {
2252 /* Combine shareability attributes (table D4-43) */
2253 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
2254 /* if either are outer-shareable, the result is outer-shareable */
2255 ret
.shareability
= 2;
2256 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
2257 /* if either are inner-shareable, the result is inner-shareable */
2258 ret
.shareability
= 3;
2260 /* both non-shareable */
2261 ret
.shareability
= 0;
2264 /* Combine memory type and cacheability attributes */
2265 if (hcr
& HCR_FWB
) {
2266 ret
.attrs
= combined_attrs_fwb(s1
, s2
);
2268 ret
.attrs
= combined_attrs_nofwb(hcr
, s1
, s2
);
2272 * Any location for which the resultant memory type is any
2273 * type of Device memory is always treated as Outer Shareable.
2274 * Any location for which the resultant memory type is Normal
2275 * Inner Non-cacheable, Outer Non-cacheable is always treated
2276 * as Outer Shareable.
2277 * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
2279 if ((ret
.attrs
& 0xf0) == 0 || ret
.attrs
== 0x44) {
2280 ret
.shareability
= 2;
2283 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
2284 if (tagged
&& ret
.attrs
== 0xff) {
2292 * MMU disabled. S1 addresses within aa64 translation regimes are
2293 * still checked for bounds -- see AArch64.S1DisabledOutput().
2295 static bool get_phys_addr_disabled(CPUARMState
*env
, target_ulong address
,
2296 MMUAccessType access_type
,
2297 ARMMMUIdx mmu_idx
, bool is_secure
,
2298 GetPhysAddrResult
*result
,
2299 ARMMMUFaultInfo
*fi
)
2301 uint8_t memattr
= 0x00; /* Device nGnRnE */
2302 uint8_t shareability
= 0; /* non-sharable */
2306 case ARMMMUIdx_Stage2
:
2307 case ARMMMUIdx_Stage2_S
:
2308 case ARMMMUIdx_Phys_NS
:
2309 case ARMMMUIdx_Phys_S
:
2313 r_el
= regime_el(env
, mmu_idx
);
2314 if (arm_el_is_aa64(env
, r_el
)) {
2315 int pamax
= arm_pamax(env_archcpu(env
));
2316 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
];
2319 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
2320 if (access_type
== MMU_INST_FETCH
) {
2321 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
2323 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
2324 addrtop
= (tbi
? 55 : 63);
2326 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
2327 fi
->type
= ARMFault_AddressSize
;
2334 * When TBI is disabled, we've just validated that all of the
2335 * bits above PAMax are zero, so logically we only need to
2336 * clear the top byte for TBI. But it's clearer to follow
2337 * the pseudocode set of addrdesc.paddress.
2339 address
= extract64(address
, 0, 52);
2342 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
2344 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2346 if (hcr
& HCR_DCT
) {
2347 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
2349 memattr
= 0xff; /* Normal, WB, RWA */
2353 if (memattr
== 0 && access_type
== MMU_INST_FETCH
) {
2354 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
2355 memattr
= 0xee; /* Normal, WT, RA, NT */
2357 memattr
= 0x44; /* Normal, NC, No */
2359 shareability
= 2; /* outer sharable */
2361 result
->cacheattrs
.is_s2_format
= false;
2365 result
->f
.phys_addr
= address
;
2366 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2367 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2368 result
->cacheattrs
.shareability
= shareability
;
2369 result
->cacheattrs
.attrs
= memattr
;
2373 bool get_phys_addr_with_secure(CPUARMState
*env
, target_ulong address
,
2374 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2375 bool is_secure
, GetPhysAddrResult
*result
,
2376 ARMMMUFaultInfo
*fi
)
2378 ARMMMUIdx s1_mmu_idx
= stage_1_mmu_idx(mmu_idx
);
2381 if (mmu_idx
!= s1_mmu_idx
) {
2383 * Call ourselves recursively to do the stage 1 and then stage 2
2384 * translations if mmu_idx is a two-stage regime.
2386 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2390 bool ipa_secure
, s2walk_secure
;
2391 ARMCacheAttrs cacheattrs1
;
2395 ret
= get_phys_addr_with_secure(env
, address
, access_type
,
2396 s1_mmu_idx
, is_secure
, result
, fi
);
2398 /* If S1 fails or S2 is disabled, return early. */
2399 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
,
2404 ipa
= result
->f
.phys_addr
;
2405 ipa_secure
= result
->f
.attrs
.secure
;
2407 /* Select TCR based on the NS bit from the S1 walk. */
2408 s2walk_secure
= !(ipa_secure
2409 ? env
->cp15
.vstcr_el2
& VSTCR_SW
2410 : env
->cp15
.vtcr_el2
& VTCR_NSW
);
2412 assert(!ipa_secure
);
2413 s2walk_secure
= false;
2417 s2walk_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2418 ptw
.in_secure
= s2walk_secure
;
2419 is_el0
= mmu_idx
== ARMMMUIdx_E10_0
;
2422 * S1 is done, now do S2 translation.
2423 * Save the stage1 results so that we may merge
2424 * prot and cacheattrs later.
2426 s1_prot
= result
->f
.prot
;
2427 cacheattrs1
= result
->cacheattrs
;
2428 memset(result
, 0, sizeof(*result
));
2430 ret
= get_phys_addr_lpae(env
, &ptw
, ipa
, access_type
,
2431 is_el0
, result
, fi
);
2434 /* Combine the S1 and S2 perms. */
2435 result
->f
.prot
&= s1_prot
;
2437 /* If S2 fails, return early. */
2442 /* Combine the S1 and S2 cache attributes. */
2443 hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2446 * HCR.DC forces the first stage attributes to
2447 * Normal Non-Shareable,
2448 * Inner Write-Back Read-Allocate Write-Allocate,
2449 * Outer Write-Back Read-Allocate Write-Allocate.
2450 * Do not overwrite Tagged within attrs.
2452 if (cacheattrs1
.attrs
!= 0xf0) {
2453 cacheattrs1
.attrs
= 0xff;
2455 cacheattrs1
.shareability
= 0;
2457 result
->cacheattrs
= combine_cacheattrs(hcr
, cacheattrs1
,
2458 result
->cacheattrs
);
2461 * Check if IPA translates to secure or non-secure PA space.
2462 * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
2464 result
->f
.attrs
.secure
=
2466 && !(env
->cp15
.vstcr_el2
& (VSTCR_SA
| VSTCR_SW
))
2468 || !(env
->cp15
.vtcr_el2
& (VTCR_NSA
| VTCR_NSW
))));
2473 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
2475 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
2480 * The page table entries may downgrade secure to non-secure, but
2481 * cannot upgrade an non-secure translation regime's attributes
2484 result
->f
.attrs
.secure
= is_secure
;
2485 result
->f
.attrs
.user
= regime_is_user(env
, mmu_idx
);
2488 * Fast Context Switch Extension. This doesn't exist at all in v8.
2489 * In v7 and earlier it affects all stage 1 translations.
2491 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
2492 && !arm_feature(env
, ARM_FEATURE_V8
)) {
2493 if (regime_el(env
, mmu_idx
) == 3) {
2494 address
+= env
->cp15
.fcseidr_s
;
2496 address
+= env
->cp15
.fcseidr_ns
;
2500 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2502 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2504 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2506 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
2507 is_secure
, result
, fi
);
2508 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2510 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
2511 is_secure
, result
, fi
);
2514 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
2515 is_secure
, result
, fi
);
2517 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
2518 " mmu_idx %u -> %s (prot %c%c%c)\n",
2519 access_type
== MMU_DATA_LOAD
? "reading" :
2520 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
2521 (uint32_t)address
, mmu_idx
,
2522 ret
? "Miss" : "Hit",
2523 result
->f
.prot
& PAGE_READ
? 'r' : '-',
2524 result
->f
.prot
& PAGE_WRITE
? 'w' : '-',
2525 result
->f
.prot
& PAGE_EXEC
? 'x' : '-');
2530 /* Definitely a real MMU, not an MPU */
2532 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
2533 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2534 is_secure
, result
, fi
);
2537 ptw
.in_mmu_idx
= mmu_idx
;
2538 ptw
.in_secure
= is_secure
;
2540 if (regime_using_lpae_format(env
, mmu_idx
)) {
2541 return get_phys_addr_lpae(env
, &ptw
, address
, access_type
, false,
2543 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
2544 return get_phys_addr_v6(env
, &ptw
, address
, access_type
, result
, fi
);
2546 return get_phys_addr_v5(env
, &ptw
, address
, access_type
, result
, fi
);
2550 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
2551 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2552 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
2557 case ARMMMUIdx_E10_0
:
2558 case ARMMMUIdx_E10_1
:
2559 case ARMMMUIdx_E10_1_PAN
:
2560 case ARMMMUIdx_E20_0
:
2561 case ARMMMUIdx_E20_2
:
2562 case ARMMMUIdx_E20_2_PAN
:
2563 case ARMMMUIdx_Stage1_E0
:
2564 case ARMMMUIdx_Stage1_E1
:
2565 case ARMMMUIdx_Stage1_E1_PAN
:
2567 is_secure
= arm_is_secure_below_el3(env
);
2569 case ARMMMUIdx_Stage2
:
2570 case ARMMMUIdx_Phys_NS
:
2571 case ARMMMUIdx_MPrivNegPri
:
2572 case ARMMMUIdx_MUserNegPri
:
2573 case ARMMMUIdx_MPriv
:
2574 case ARMMMUIdx_MUser
:
2578 case ARMMMUIdx_Stage2_S
:
2579 case ARMMMUIdx_Phys_S
:
2580 case ARMMMUIdx_MSPrivNegPri
:
2581 case ARMMMUIdx_MSUserNegPri
:
2582 case ARMMMUIdx_MSPriv
:
2583 case ARMMMUIdx_MSUser
:
2587 g_assert_not_reached();
2589 return get_phys_addr_with_secure(env
, address
, access_type
, mmu_idx
,
2590 is_secure
, result
, fi
);
2593 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
2596 ARMCPU
*cpu
= ARM_CPU(cs
);
2597 CPUARMState
*env
= &cpu
->env
;
2598 GetPhysAddrResult res
= {};
2599 ARMMMUFaultInfo fi
= {};
2600 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
2603 ret
= get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &res
, &fi
);
2604 *attrs
= res
.f
.attrs
;
2609 return res
.f
.phys_addr
;