4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
29 #include "translate.h"
30 #include "internals.h"
31 #include "qemu/host-utils.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X
[32];
41 static TCGv_i64 cpu_pc
;
42 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
44 /* Load/store exclusive handling */
45 static TCGv_i64 cpu_exclusive_addr
;
46 static TCGv_i64 cpu_exclusive_val
;
47 static TCGv_i64 cpu_exclusive_high
;
48 #ifdef CONFIG_USER_ONLY
49 static TCGv_i64 cpu_exclusive_test
;
50 static TCGv_i32 cpu_exclusive_info
;
53 static const char *regnames
[] = {
54 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
55 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
56 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
57 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
61 A64_SHIFT_TYPE_LSL
= 0,
62 A64_SHIFT_TYPE_LSR
= 1,
63 A64_SHIFT_TYPE_ASR
= 2,
64 A64_SHIFT_TYPE_ROR
= 3
67 /* Table based decoder typedefs - used when the relevant bits for decode
68 * are too awkwardly scattered across the instruction (eg SIMD).
70 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
72 typedef struct AArch64DecodeTable
{
75 AArch64DecodeFn
*disas_fn
;
78 /* Function prototype for gen_ functions for calling Neon helpers */
79 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
80 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
81 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
82 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
83 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
84 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
85 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
86 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
87 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
88 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
89 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
90 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
91 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
93 /* initialize TCG globals. */
94 void a64_translate_init(void)
98 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
99 offsetof(CPUARMState
, pc
),
101 for (i
= 0; i
< 32; i
++) {
102 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
103 offsetof(CPUARMState
, xregs
[i
]),
107 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
108 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
109 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
110 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
112 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
113 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
114 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
116 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
117 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
118 #ifdef CONFIG_USER_ONLY
119 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
120 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
121 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
122 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
126 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
127 fprintf_function cpu_fprintf
, int flags
)
129 ARMCPU
*cpu
= ARM_CPU(cs
);
130 CPUARMState
*env
= &cpu
->env
;
131 uint32_t psr
= pstate_read(env
);
134 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
135 env
->pc
, env
->xregs
[31]);
136 for (i
= 0; i
< 31; i
++) {
137 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
139 cpu_fprintf(f
, "\n");
144 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
146 psr
& PSTATE_N
? 'N' : '-',
147 psr
& PSTATE_Z
? 'Z' : '-',
148 psr
& PSTATE_C
? 'C' : '-',
149 psr
& PSTATE_V
? 'V' : '-');
150 cpu_fprintf(f
, "\n");
152 if (flags
& CPU_DUMP_FPU
) {
154 for (i
= 0; i
< numvfpregs
; i
+= 2) {
155 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
156 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
157 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
159 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
160 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
161 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
164 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
165 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
169 void gen_a64_set_pc_im(uint64_t val
)
171 tcg_gen_movi_i64(cpu_pc
, val
);
174 static void gen_exception_internal(int excp
)
176 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
178 assert(excp_is_internal(excp
));
179 gen_helper_exception_internal(cpu_env
, tcg_excp
);
180 tcg_temp_free_i32(tcg_excp
);
183 static void gen_exception(int excp
, uint32_t syndrome
)
185 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
186 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
188 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
, tcg_syn
);
189 tcg_temp_free_i32(tcg_syn
);
190 tcg_temp_free_i32(tcg_excp
);
193 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
195 gen_a64_set_pc_im(s
->pc
- offset
);
196 gen_exception_internal(excp
);
197 s
->is_jmp
= DISAS_EXC
;
200 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
203 gen_a64_set_pc_im(s
->pc
- offset
);
204 gen_exception(excp
, syndrome
);
205 s
->is_jmp
= DISAS_EXC
;
208 static void gen_ss_advance(DisasContext
*s
)
210 /* If the singlestep state is Active-not-pending, advance to
215 gen_helper_clear_pstate_ss(cpu_env
);
219 static void gen_step_complete_exception(DisasContext
*s
)
221 /* We just completed step of an insn. Move from Active-not-pending
222 * to Active-pending, and then also take the swstep exception.
223 * This corresponds to making the (IMPDEF) choice to prioritize
224 * swstep exceptions over asynchronous exceptions taken to an exception
225 * level where debug is disabled. This choice has the advantage that
226 * we do not need to maintain internal state corresponding to the
227 * ISV/EX syndrome bits between completion of the step and generation
228 * of the exception, and our syndrome information is always correct.
231 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
));
232 s
->is_jmp
= DISAS_EXC
;
235 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
237 /* No direct tb linking with singlestep (either QEMU's or the ARM
238 * debug architecture kind) or deterministic io
240 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
244 /* Only link tbs from inside the same guest page */
245 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
252 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
254 TranslationBlock
*tb
;
257 if (use_goto_tb(s
, n
, dest
)) {
259 gen_a64_set_pc_im(dest
);
260 tcg_gen_exit_tb((intptr_t)tb
+ n
);
261 s
->is_jmp
= DISAS_TB_JUMP
;
263 gen_a64_set_pc_im(dest
);
265 gen_step_complete_exception(s
);
266 } else if (s
->singlestep_enabled
) {
267 gen_exception_internal(EXCP_DEBUG
);
270 s
->is_jmp
= DISAS_TB_JUMP
;
275 static void unallocated_encoding(DisasContext
*s
)
277 /* Unallocated and reserved encodings are uncategorized */
278 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized());
281 #define unsupported_encoding(s, insn) \
283 qemu_log_mask(LOG_UNIMP, \
284 "%s:%d: unsupported instruction encoding 0x%08x " \
285 "at pc=%016" PRIx64 "\n", \
286 __FILE__, __LINE__, insn, s->pc - 4); \
287 unallocated_encoding(s); \
290 static void init_tmp_a64_array(DisasContext
*s
)
292 #ifdef CONFIG_DEBUG_TCG
294 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
295 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
298 s
->tmp_a64_count
= 0;
301 static void free_tmp_a64(DisasContext
*s
)
304 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
305 tcg_temp_free_i64(s
->tmp_a64
[i
]);
307 init_tmp_a64_array(s
);
310 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
312 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
313 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
316 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
318 TCGv_i64 t
= new_tmp_a64(s
);
319 tcg_gen_movi_i64(t
, 0);
324 * Register access functions
326 * These functions are used for directly accessing a register in where
327 * changes to the final register value are likely to be made. If you
328 * need to use a register for temporary calculation (e.g. index type
329 * operations) use the read_* form.
331 * B1.2.1 Register mappings
333 * In instruction register encoding 31 can refer to ZR (zero register) or
334 * the SP (stack pointer) depending on context. In QEMU's case we map SP
335 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
336 * This is the point of the _sp forms.
338 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
341 return new_tmp_a64_zero(s
);
347 /* register access for when 31 == SP */
348 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
353 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
354 * representing the register contents. This TCGv is an auto-freed
355 * temporary so it need not be explicitly freed, and may be modified.
357 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
359 TCGv_i64 v
= new_tmp_a64(s
);
362 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
364 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
367 tcg_gen_movi_i64(v
, 0);
372 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
374 TCGv_i64 v
= new_tmp_a64(s
);
376 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
378 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
383 /* We should have at some point before trying to access an FP register
384 * done the necessary access check, so assert that
385 * (a) we did the check and
386 * (b) we didn't then just plough ahead anyway if it failed.
387 * Print the instruction pattern in the abort message so we can figure
388 * out what we need to fix if a user encounters this problem in the wild.
390 static inline void assert_fp_access_checked(DisasContext
*s
)
392 #ifdef CONFIG_DEBUG_TCG
393 if (unlikely(!s
->fp_access_checked
|| !s
->cpacr_fpen
)) {
394 fprintf(stderr
, "target-arm: FP access check missing for "
395 "instruction 0x%08x\n", s
->insn
);
401 /* Return the offset into CPUARMState of an element of specified
402 * size, 'element' places in from the least significant end of
403 * the FP/vector register Qn.
405 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
406 int element
, TCGMemOp size
)
408 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
409 #ifdef HOST_WORDS_BIGENDIAN
410 /* This is complicated slightly because vfp.regs[2n] is
411 * still the low half and vfp.regs[2n+1] the high half
412 * of the 128 bit vector, even on big endian systems.
413 * Calculate the offset assuming a fully bigendian 128 bits,
414 * then XOR to account for the order of the two 64 bit halves.
416 offs
+= (16 - ((element
+ 1) * (1 << size
)));
419 offs
+= element
* (1 << size
);
421 assert_fp_access_checked(s
);
425 /* Return the offset into CPUARMState of a slice (from
426 * the least significant end) of FP register Qn (ie
428 * (Note that this is not the same mapping as for A32; see cpu.h)
430 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
432 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
433 #ifdef HOST_WORDS_BIGENDIAN
434 offs
+= (8 - (1 << size
));
436 assert_fp_access_checked(s
);
440 /* Offset of the high half of the 128 bit vector Qn */
441 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
443 assert_fp_access_checked(s
);
444 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
447 /* Convenience accessors for reading and writing single and double
448 * FP registers. Writing clears the upper parts of the associated
449 * 128 bit vector register, as required by the architecture.
450 * Note that unlike the GP register accessors, the values returned
451 * by the read functions must be manually freed.
453 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
455 TCGv_i64 v
= tcg_temp_new_i64();
457 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
461 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
463 TCGv_i32 v
= tcg_temp_new_i32();
465 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
469 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
471 TCGv_i64 tcg_zero
= tcg_const_i64(0);
473 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
474 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
475 tcg_temp_free_i64(tcg_zero
);
478 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
480 TCGv_i64 tmp
= tcg_temp_new_i64();
482 tcg_gen_extu_i32_i64(tmp
, v
);
483 write_fp_dreg(s
, reg
, tmp
);
484 tcg_temp_free_i64(tmp
);
487 static TCGv_ptr
get_fpstatus_ptr(void)
489 TCGv_ptr statusptr
= tcg_temp_new_ptr();
492 /* In A64 all instructions (both FP and Neon) use the FPCR;
493 * there is no equivalent of the A32 Neon "standard FPSCR value"
494 * and all operations use vfp.fp_status.
496 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
497 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
501 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
502 * than the 32 bit equivalent.
504 static inline void gen_set_NZ64(TCGv_i64 result
)
506 TCGv_i64 flag
= tcg_temp_new_i64();
508 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
509 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
510 tcg_gen_shri_i64(flag
, result
, 32);
511 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
512 tcg_temp_free_i64(flag
);
515 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
516 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
519 gen_set_NZ64(result
);
521 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
522 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
524 tcg_gen_movi_i32(cpu_CF
, 0);
525 tcg_gen_movi_i32(cpu_VF
, 0);
528 /* dest = T0 + T1; compute C, N, V and Z flags */
529 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
532 TCGv_i64 result
, flag
, tmp
;
533 result
= tcg_temp_new_i64();
534 flag
= tcg_temp_new_i64();
535 tmp
= tcg_temp_new_i64();
537 tcg_gen_movi_i64(tmp
, 0);
538 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
540 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
542 gen_set_NZ64(result
);
544 tcg_gen_xor_i64(flag
, result
, t0
);
545 tcg_gen_xor_i64(tmp
, t0
, t1
);
546 tcg_gen_andc_i64(flag
, flag
, tmp
);
547 tcg_temp_free_i64(tmp
);
548 tcg_gen_shri_i64(flag
, flag
, 32);
549 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
551 tcg_gen_mov_i64(dest
, result
);
552 tcg_temp_free_i64(result
);
553 tcg_temp_free_i64(flag
);
555 /* 32 bit arithmetic */
556 TCGv_i32 t0_32
= tcg_temp_new_i32();
557 TCGv_i32 t1_32
= tcg_temp_new_i32();
558 TCGv_i32 tmp
= tcg_temp_new_i32();
560 tcg_gen_movi_i32(tmp
, 0);
561 tcg_gen_trunc_i64_i32(t0_32
, t0
);
562 tcg_gen_trunc_i64_i32(t1_32
, t1
);
563 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
564 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
565 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
566 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
567 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
568 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
570 tcg_temp_free_i32(tmp
);
571 tcg_temp_free_i32(t0_32
);
572 tcg_temp_free_i32(t1_32
);
576 /* dest = T0 - T1; compute C, N, V and Z flags */
577 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
580 /* 64 bit arithmetic */
581 TCGv_i64 result
, flag
, tmp
;
583 result
= tcg_temp_new_i64();
584 flag
= tcg_temp_new_i64();
585 tcg_gen_sub_i64(result
, t0
, t1
);
587 gen_set_NZ64(result
);
589 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
590 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
592 tcg_gen_xor_i64(flag
, result
, t0
);
593 tmp
= tcg_temp_new_i64();
594 tcg_gen_xor_i64(tmp
, t0
, t1
);
595 tcg_gen_and_i64(flag
, flag
, tmp
);
596 tcg_temp_free_i64(tmp
);
597 tcg_gen_shri_i64(flag
, flag
, 32);
598 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
599 tcg_gen_mov_i64(dest
, result
);
600 tcg_temp_free_i64(flag
);
601 tcg_temp_free_i64(result
);
603 /* 32 bit arithmetic */
604 TCGv_i32 t0_32
= tcg_temp_new_i32();
605 TCGv_i32 t1_32
= tcg_temp_new_i32();
608 tcg_gen_trunc_i64_i32(t0_32
, t0
);
609 tcg_gen_trunc_i64_i32(t1_32
, t1
);
610 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
611 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
612 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
613 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
614 tmp
= tcg_temp_new_i32();
615 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
616 tcg_temp_free_i32(t0_32
);
617 tcg_temp_free_i32(t1_32
);
618 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
619 tcg_temp_free_i32(tmp
);
620 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
624 /* dest = T0 + T1 + CF; do not compute flags. */
625 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
627 TCGv_i64 flag
= tcg_temp_new_i64();
628 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
629 tcg_gen_add_i64(dest
, t0
, t1
);
630 tcg_gen_add_i64(dest
, dest
, flag
);
631 tcg_temp_free_i64(flag
);
634 tcg_gen_ext32u_i64(dest
, dest
);
638 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
639 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
642 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
643 result
= tcg_temp_new_i64();
644 cf_64
= tcg_temp_new_i64();
645 vf_64
= tcg_temp_new_i64();
646 tmp
= tcg_const_i64(0);
648 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
649 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
650 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
651 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
652 gen_set_NZ64(result
);
654 tcg_gen_xor_i64(vf_64
, result
, t0
);
655 tcg_gen_xor_i64(tmp
, t0
, t1
);
656 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
657 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
658 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
660 tcg_gen_mov_i64(dest
, result
);
662 tcg_temp_free_i64(tmp
);
663 tcg_temp_free_i64(vf_64
);
664 tcg_temp_free_i64(cf_64
);
665 tcg_temp_free_i64(result
);
667 TCGv_i32 t0_32
, t1_32
, tmp
;
668 t0_32
= tcg_temp_new_i32();
669 t1_32
= tcg_temp_new_i32();
670 tmp
= tcg_const_i32(0);
672 tcg_gen_trunc_i64_i32(t0_32
, t0
);
673 tcg_gen_trunc_i64_i32(t1_32
, t1
);
674 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
675 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
677 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
678 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
679 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
680 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
681 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
683 tcg_temp_free_i32(tmp
);
684 tcg_temp_free_i32(t1_32
);
685 tcg_temp_free_i32(t0_32
);
690 * Load/Store generators
694 * Store from GPR register to memory.
696 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
697 TCGv_i64 tcg_addr
, int size
, int memidx
)
700 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
703 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
704 TCGv_i64 tcg_addr
, int size
)
706 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
710 * Load from memory to GPR register
712 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
713 int size
, bool is_signed
, bool extend
, int memidx
)
715 TCGMemOp memop
= MO_TE
+ size
;
723 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
725 if (extend
&& is_signed
) {
727 tcg_gen_ext32u_i64(dest
, dest
);
731 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
732 int size
, bool is_signed
, bool extend
)
734 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
739 * Store from FP register to memory
741 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
743 /* This writes the bottom N bits of a 128 bit wide vector to memory */
744 TCGv_i64 tmp
= tcg_temp_new_i64();
745 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
747 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
749 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
750 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
751 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
752 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
753 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
754 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
755 tcg_temp_free_i64(tcg_hiaddr
);
758 tcg_temp_free_i64(tmp
);
762 * Load from memory to FP register
764 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
766 /* This always zero-extends and writes to a full 128 bit wide vector */
767 TCGv_i64 tmplo
= tcg_temp_new_i64();
771 TCGMemOp memop
= MO_TE
+ size
;
772 tmphi
= tcg_const_i64(0);
773 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
776 tmphi
= tcg_temp_new_i64();
777 tcg_hiaddr
= tcg_temp_new_i64();
779 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
780 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
781 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
782 tcg_temp_free_i64(tcg_hiaddr
);
785 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
786 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
788 tcg_temp_free_i64(tmplo
);
789 tcg_temp_free_i64(tmphi
);
793 * Vector load/store helpers.
795 * The principal difference between this and a FP load is that we don't
796 * zero extend as we are filling a partial chunk of the vector register.
797 * These functions don't support 128 bit loads/stores, which would be
798 * normal load/store operations.
800 * The _i32 versions are useful when operating on 32 bit quantities
801 * (eg for floating point single or using Neon helper functions).
804 /* Get value of an element within a vector register */
805 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
806 int element
, TCGMemOp memop
)
808 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
811 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
814 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
817 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
820 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
823 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
826 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
830 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
833 g_assert_not_reached();
837 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
838 int element
, TCGMemOp memop
)
840 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
843 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
846 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
849 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
852 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
856 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
859 g_assert_not_reached();
863 /* Set value of an element within a vector register */
864 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
865 int element
, TCGMemOp memop
)
867 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
870 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
873 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
876 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
879 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
882 g_assert_not_reached();
886 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
887 int destidx
, int element
, TCGMemOp memop
)
889 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
892 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
895 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
898 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
901 g_assert_not_reached();
905 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
906 * vector ops all need to do this).
908 static void clear_vec_high(DisasContext
*s
, int rd
)
910 TCGv_i64 tcg_zero
= tcg_const_i64(0);
912 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
913 tcg_temp_free_i64(tcg_zero
);
916 /* Store from vector register to memory */
917 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
918 TCGv_i64 tcg_addr
, int size
)
920 TCGMemOp memop
= MO_TE
+ size
;
921 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
923 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
924 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
926 tcg_temp_free_i64(tcg_tmp
);
929 /* Load from memory to vector register */
930 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
931 TCGv_i64 tcg_addr
, int size
)
933 TCGMemOp memop
= MO_TE
+ size
;
934 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
936 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
937 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
939 tcg_temp_free_i64(tcg_tmp
);
942 /* Check that FP/Neon access is enabled. If it is, return
943 * true. If not, emit code to generate an appropriate exception,
944 * and return false; the caller should not emit any code for
945 * the instruction. Note that this check must happen after all
946 * unallocated-encoding checks (otherwise the syndrome information
947 * for the resulting exception will be incorrect).
949 static inline bool fp_access_check(DisasContext
*s
)
951 assert(!s
->fp_access_checked
);
952 s
->fp_access_checked
= true;
958 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false));
963 * This utility function is for doing register extension with an
964 * optional shift. You will likely want to pass a temporary for the
965 * destination register. See DecodeRegExtend() in the ARM ARM.
967 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
968 int option
, unsigned int shift
)
970 int extsize
= extract32(option
, 0, 2);
971 bool is_signed
= extract32(option
, 2, 1);
976 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
979 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
982 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
985 tcg_gen_mov_i64(tcg_out
, tcg_in
);
991 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
994 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
997 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1000 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1006 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1010 static inline void gen_check_sp_alignment(DisasContext
*s
)
1012 /* The AArch64 architecture mandates that (if enabled via PSTATE
1013 * or SCTLR bits) there is a check that SP is 16-aligned on every
1014 * SP-relative load or store (with an exception generated if it is not).
1015 * In line with general QEMU practice regarding misaligned accesses,
1016 * we omit these checks for the sake of guest program performance.
1017 * This function is provided as a hook so we can more easily add these
1018 * checks in future (possibly as a "favour catching guest program bugs
1019 * over speed" user selectable option).
1024 * This provides a simple table based table lookup decoder. It is
1025 * intended to be used when the relevant bits for decode are too
1026 * awkwardly placed and switch/if based logic would be confusing and
1027 * deeply nested. Since it's a linear search through the table, tables
1028 * should be kept small.
1030 * It returns the first handler where insn & mask == pattern, or
1031 * NULL if there is no match.
1032 * The table is terminated by an empty mask (i.e. 0)
1034 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1037 const AArch64DecodeTable
*tptr
= table
;
1039 while (tptr
->mask
) {
1040 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1041 return tptr
->disas_fn
;
1049 * the instruction disassembly implemented here matches
1050 * the instruction encoding classifications in chapter 3 (C3)
1051 * of the ARM Architecture Reference Manual (DDI0487A_a)
1054 /* C3.2.7 Unconditional branch (immediate)
1056 * +----+-----------+-------------------------------------+
1057 * | op | 0 0 1 0 1 | imm26 |
1058 * +----+-----------+-------------------------------------+
1060 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1062 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1064 if (insn
& (1 << 31)) {
1065 /* C5.6.26 BL Branch with link */
1066 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1069 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1070 gen_goto_tb(s
, 0, addr
);
1073 /* C3.2.1 Compare & branch (immediate)
1074 * 31 30 25 24 23 5 4 0
1075 * +----+-------------+----+---------------------+--------+
1076 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1077 * +----+-------------+----+---------------------+--------+
1079 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1081 unsigned int sf
, op
, rt
;
1086 sf
= extract32(insn
, 31, 1);
1087 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1088 rt
= extract32(insn
, 0, 5);
1089 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1091 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1092 label_match
= gen_new_label();
1094 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1095 tcg_cmp
, 0, label_match
);
1097 gen_goto_tb(s
, 0, s
->pc
);
1098 gen_set_label(label_match
);
1099 gen_goto_tb(s
, 1, addr
);
1102 /* C3.2.5 Test & branch (immediate)
1103 * 31 30 25 24 23 19 18 5 4 0
1104 * +----+-------------+----+-------+-------------+------+
1105 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1106 * +----+-------------+----+-------+-------------+------+
1108 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1110 unsigned int bit_pos
, op
, rt
;
1115 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1116 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1117 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1118 rt
= extract32(insn
, 0, 5);
1120 tcg_cmp
= tcg_temp_new_i64();
1121 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1122 label_match
= gen_new_label();
1123 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1124 tcg_cmp
, 0, label_match
);
1125 tcg_temp_free_i64(tcg_cmp
);
1126 gen_goto_tb(s
, 0, s
->pc
);
1127 gen_set_label(label_match
);
1128 gen_goto_tb(s
, 1, addr
);
1131 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1132 * 31 25 24 23 5 4 3 0
1133 * +---------------+----+---------------------+----+------+
1134 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1135 * +---------------+----+---------------------+----+------+
1137 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1142 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1143 unallocated_encoding(s
);
1146 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1147 cond
= extract32(insn
, 0, 4);
1150 /* genuinely conditional branches */
1151 int label_match
= gen_new_label();
1152 arm_gen_test_cc(cond
, label_match
);
1153 gen_goto_tb(s
, 0, s
->pc
);
1154 gen_set_label(label_match
);
1155 gen_goto_tb(s
, 1, addr
);
1157 /* 0xe and 0xf are both "always" conditions */
1158 gen_goto_tb(s
, 0, addr
);
1163 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1164 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1166 unsigned int selector
= crm
<< 3 | op2
;
1169 unallocated_encoding(s
);
1177 s
->is_jmp
= DISAS_WFI
;
1181 s
->is_jmp
= DISAS_WFE
;
1185 /* we treat all as NOP at least for now */
1188 /* default specified as NOP equivalent */
1193 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1195 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1198 /* CLREX, DSB, DMB, ISB */
1199 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1200 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1203 unallocated_encoding(s
);
1214 /* We don't emulate caches so barriers are no-ops */
1217 unallocated_encoding(s
);
1222 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1223 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1224 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1226 int op
= op1
<< 3 | op2
;
1228 case 0x05: /* SPSel */
1229 if (s
->current_pl
== 0) {
1230 unallocated_encoding(s
);
1234 case 0x1e: /* DAIFSet */
1235 case 0x1f: /* DAIFClear */
1237 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1238 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1239 gen_a64_set_pc_im(s
->pc
- 4);
1240 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1241 tcg_temp_free_i32(tcg_imm
);
1242 tcg_temp_free_i32(tcg_op
);
1243 s
->is_jmp
= DISAS_UPDATE
;
1247 unallocated_encoding(s
);
1252 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1254 TCGv_i32 tmp
= tcg_temp_new_i32();
1255 TCGv_i32 nzcv
= tcg_temp_new_i32();
1257 /* build bit 31, N */
1258 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1259 /* build bit 30, Z */
1260 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1261 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1262 /* build bit 29, C */
1263 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1264 /* build bit 28, V */
1265 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1266 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1267 /* generate result */
1268 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1270 tcg_temp_free_i32(nzcv
);
1271 tcg_temp_free_i32(tmp
);
1274 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1277 TCGv_i32 nzcv
= tcg_temp_new_i32();
1279 /* take NZCV from R[t] */
1280 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1283 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1285 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1286 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1288 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1289 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1291 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1292 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1293 tcg_temp_free_i32(nzcv
);
1296 /* C5.6.129 MRS - move from system register
1297 * C5.6.131 MSR (register) - move to system register
1300 * These are all essentially the same insn in 'read' and 'write'
1301 * versions, with varying op0 fields.
1303 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1304 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1305 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1307 const ARMCPRegInfo
*ri
;
1310 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1311 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1312 crn
, crm
, op0
, op1
, op2
));
1315 /* Unknown register; this might be a guest error or a QEMU
1316 * unimplemented feature.
1318 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1319 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1320 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1321 unallocated_encoding(s
);
1325 /* Check access permissions */
1326 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
1327 unallocated_encoding(s
);
1332 /* Emit code to perform further access permissions checks at
1333 * runtime; this may result in an exception.
1339 gen_a64_set_pc_im(s
->pc
- 4);
1340 tmpptr
= tcg_const_ptr(ri
);
1341 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1342 tcg_syn
= tcg_const_i32(syndrome
);
1343 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
);
1344 tcg_temp_free_ptr(tmpptr
);
1345 tcg_temp_free_i32(tcg_syn
);
1348 /* Handle special cases first */
1349 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1353 tcg_rt
= cpu_reg(s
, rt
);
1355 gen_get_nzcv(tcg_rt
);
1357 gen_set_nzcv(tcg_rt
);
1360 case ARM_CP_CURRENTEL
:
1361 /* Reads as current EL value from pstate, which is
1362 * guaranteed to be constant by the tb flags.
1364 tcg_rt
= cpu_reg(s
, rt
);
1365 tcg_gen_movi_i64(tcg_rt
, s
->current_pl
<< 2);
1368 /* Writes clear the aligned block of memory which rt points into. */
1369 tcg_rt
= cpu_reg(s
, rt
);
1370 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1376 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1380 tcg_rt
= cpu_reg(s
, rt
);
1383 if (ri
->type
& ARM_CP_CONST
) {
1384 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1385 } else if (ri
->readfn
) {
1387 tmpptr
= tcg_const_ptr(ri
);
1388 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1389 tcg_temp_free_ptr(tmpptr
);
1391 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1394 if (ri
->type
& ARM_CP_CONST
) {
1395 /* If not forbidden by access permissions, treat as WI */
1397 } else if (ri
->writefn
) {
1399 tmpptr
= tcg_const_ptr(ri
);
1400 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1401 tcg_temp_free_ptr(tmpptr
);
1403 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1407 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1408 /* I/O operations must end the TB here (whether read or write) */
1410 s
->is_jmp
= DISAS_UPDATE
;
1411 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1412 /* We default to ending the TB on a coprocessor register write,
1413 * but allow this to be suppressed by the register definition
1414 * (usually only necessary to work around guest bugs).
1416 s
->is_jmp
= DISAS_UPDATE
;
1421 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1422 * +---------------------+---+-----+-----+-------+-------+-----+------+
1423 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1424 * +---------------------+---+-----+-----+-------+-------+-----+------+
1426 static void disas_system(DisasContext
*s
, uint32_t insn
)
1428 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1429 l
= extract32(insn
, 21, 1);
1430 op0
= extract32(insn
, 19, 2);
1431 op1
= extract32(insn
, 16, 3);
1432 crn
= extract32(insn
, 12, 4);
1433 crm
= extract32(insn
, 8, 4);
1434 op2
= extract32(insn
, 5, 3);
1435 rt
= extract32(insn
, 0, 5);
1438 if (l
|| rt
!= 31) {
1439 unallocated_encoding(s
);
1443 case 2: /* C5.6.68 HINT */
1444 handle_hint(s
, insn
, op1
, op2
, crm
);
1446 case 3: /* CLREX, DSB, DMB, ISB */
1447 handle_sync(s
, insn
, op1
, op2
, crm
);
1449 case 4: /* C5.6.130 MSR (immediate) */
1450 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1453 unallocated_encoding(s
);
1458 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1461 /* C3.2.3 Exception generation
1463 * 31 24 23 21 20 5 4 2 1 0
1464 * +-----------------+-----+------------------------+-----+----+
1465 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1466 * +-----------------------+------------------------+----------+
1468 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1470 int opc
= extract32(insn
, 21, 3);
1471 int op2_ll
= extract32(insn
, 0, 5);
1472 int imm16
= extract32(insn
, 5, 16);
1476 /* SVC, HVC, SMC; since we don't support the Virtualization
1477 * or TrustZone extensions these all UNDEF except SVC.
1480 unallocated_encoding(s
);
1483 /* For SVC, HVC and SMC we advance the single-step state
1484 * machine before taking the exception. This is architecturally
1485 * mandated, to ensure that single-stepping a system call
1486 * instruction works properly.
1489 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
));
1493 unallocated_encoding(s
);
1497 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
));
1501 unallocated_encoding(s
);
1505 unsupported_encoding(s
, insn
);
1508 if (op2_ll
< 1 || op2_ll
> 3) {
1509 unallocated_encoding(s
);
1512 /* DCPS1, DCPS2, DCPS3 */
1513 unsupported_encoding(s
, insn
);
1516 unallocated_encoding(s
);
1521 /* C3.2.7 Unconditional branch (register)
1522 * 31 25 24 21 20 16 15 10 9 5 4 0
1523 * +---------------+-------+-------+-------+------+-------+
1524 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1525 * +---------------+-------+-------+-------+------+-------+
1527 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1529 unsigned int opc
, op2
, op3
, rn
, op4
;
1531 opc
= extract32(insn
, 21, 4);
1532 op2
= extract32(insn
, 16, 5);
1533 op3
= extract32(insn
, 10, 6);
1534 rn
= extract32(insn
, 5, 5);
1535 op4
= extract32(insn
, 0, 5);
1537 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1538 unallocated_encoding(s
);
1545 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1548 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1549 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1552 if (s
->current_pl
== 0) {
1553 unallocated_encoding(s
);
1556 gen_helper_exception_return(cpu_env
);
1557 s
->is_jmp
= DISAS_JUMP
;
1561 unallocated_encoding(s
);
1563 unsupported_encoding(s
, insn
);
1567 unallocated_encoding(s
);
1571 s
->is_jmp
= DISAS_JUMP
;
1574 /* C3.2 Branches, exception generating and system instructions */
1575 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1577 switch (extract32(insn
, 25, 7)) {
1578 case 0x0a: case 0x0b:
1579 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1580 disas_uncond_b_imm(s
, insn
);
1582 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1583 disas_comp_b_imm(s
, insn
);
1585 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1586 disas_test_b_imm(s
, insn
);
1588 case 0x2a: /* Conditional branch (immediate) */
1589 disas_cond_b_imm(s
, insn
);
1591 case 0x6a: /* Exception generation / System */
1592 if (insn
& (1 << 24)) {
1593 disas_system(s
, insn
);
1598 case 0x6b: /* Unconditional branch (register) */
1599 disas_uncond_b_reg(s
, insn
);
1602 unallocated_encoding(s
);
1608 * Load/Store exclusive instructions are implemented by remembering
1609 * the value/address loaded, and seeing if these are the same
1610 * when the store is performed. This is not actually the architecturally
1611 * mandated semantics, but it works for typical guest code sequences
1612 * and avoids having to monitor regular stores.
1614 * In system emulation mode only one CPU will be running at once, so
1615 * this sequence is effectively atomic. In user emulation mode we
1616 * throw an exception and handle the atomic operation elsewhere.
1618 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1619 TCGv_i64 addr
, int size
, bool is_pair
)
1621 TCGv_i64 tmp
= tcg_temp_new_i64();
1622 TCGMemOp memop
= MO_TE
+ size
;
1624 g_assert(size
<= 3);
1625 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1628 TCGv_i64 addr2
= tcg_temp_new_i64();
1629 TCGv_i64 hitmp
= tcg_temp_new_i64();
1631 g_assert(size
>= 2);
1632 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1633 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1634 tcg_temp_free_i64(addr2
);
1635 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1636 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1637 tcg_temp_free_i64(hitmp
);
1640 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1641 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1643 tcg_temp_free_i64(tmp
);
1644 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1647 #ifdef CONFIG_USER_ONLY
1648 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1649 TCGv_i64 addr
, int size
, int is_pair
)
1651 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1652 tcg_gen_movi_i32(cpu_exclusive_info
,
1653 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1654 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1657 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1658 TCGv_i64 inaddr
, int size
, int is_pair
)
1660 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1661 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1664 * [addr + datasize] = {Rt2};
1670 * env->exclusive_addr = -1;
1672 int fail_label
= gen_new_label();
1673 int done_label
= gen_new_label();
1674 TCGv_i64 addr
= tcg_temp_local_new_i64();
1677 /* Copy input into a local temp so it is not trashed when the
1678 * basic block ends at the branch insn.
1680 tcg_gen_mov_i64(addr
, inaddr
);
1681 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1683 tmp
= tcg_temp_new_i64();
1684 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1685 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1686 tcg_temp_free_i64(tmp
);
1689 TCGv_i64 addrhi
= tcg_temp_new_i64();
1690 TCGv_i64 tmphi
= tcg_temp_new_i64();
1692 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1693 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1694 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1696 tcg_temp_free_i64(tmphi
);
1697 tcg_temp_free_i64(addrhi
);
1700 /* We seem to still have the exclusive monitor, so do the store */
1701 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1703 TCGv_i64 addrhi
= tcg_temp_new_i64();
1705 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1706 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1707 get_mem_index(s
), MO_TE
+ size
);
1708 tcg_temp_free_i64(addrhi
);
1711 tcg_temp_free_i64(addr
);
1713 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1714 tcg_gen_br(done_label
);
1715 gen_set_label(fail_label
);
1716 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1717 gen_set_label(done_label
);
1718 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1723 /* C3.3.6 Load/store exclusive
1725 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1726 * +-----+-------------+----+---+----+------+----+-------+------+------+
1727 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1728 * +-----+-------------+----+---+----+------+----+-------+------+------+
1730 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1731 * L: 0 -> store, 1 -> load
1732 * o2: 0 -> exclusive, 1 -> not
1733 * o1: 0 -> single register, 1 -> register pair
1734 * o0: 1 -> load-acquire/store-release, 0 -> not
1736 * o0 == 0 AND o2 == 1 is un-allocated
1737 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1739 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1741 int rt
= extract32(insn
, 0, 5);
1742 int rn
= extract32(insn
, 5, 5);
1743 int rt2
= extract32(insn
, 10, 5);
1744 int is_lasr
= extract32(insn
, 15, 1);
1745 int rs
= extract32(insn
, 16, 5);
1746 int is_pair
= extract32(insn
, 21, 1);
1747 int is_store
= !extract32(insn
, 22, 1);
1748 int is_excl
= !extract32(insn
, 23, 1);
1749 int size
= extract32(insn
, 30, 2);
1752 if ((!is_excl
&& !is_lasr
) ||
1753 (is_pair
&& size
< 2)) {
1754 unallocated_encoding(s
);
1759 gen_check_sp_alignment(s
);
1761 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1763 /* Note that since TCG is single threaded load-acquire/store-release
1764 * semantics require no extra if (is_lasr) { ... } handling.
1770 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1772 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1775 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1777 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1779 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1782 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1783 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1785 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1787 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1794 * C3.3.5 Load register (literal)
1796 * 31 30 29 27 26 25 24 23 5 4 0
1797 * +-----+-------+---+-----+-------------------+-------+
1798 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1799 * +-----+-------+---+-----+-------------------+-------+
1801 * V: 1 -> vector (simd/fp)
1802 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1803 * 10-> 32 bit signed, 11 -> prefetch
1804 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1806 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1808 int rt
= extract32(insn
, 0, 5);
1809 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1810 bool is_vector
= extract32(insn
, 26, 1);
1811 int opc
= extract32(insn
, 30, 2);
1812 bool is_signed
= false;
1814 TCGv_i64 tcg_rt
, tcg_addr
;
1818 unallocated_encoding(s
);
1822 if (!fp_access_check(s
)) {
1827 /* PRFM (literal) : prefetch */
1830 size
= 2 + extract32(opc
, 0, 1);
1831 is_signed
= extract32(opc
, 1, 1);
1834 tcg_rt
= cpu_reg(s
, rt
);
1836 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1838 do_fp_ld(s
, rt
, tcg_addr
, size
);
1840 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1842 tcg_temp_free_i64(tcg_addr
);
1846 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1847 * C5.6.81 LDP (Load Pair - non vector)
1848 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1849 * C5.6.176 STNP (Store Pair - non-temporal hint)
1850 * C5.6.177 STP (Store Pair - non vector)
1851 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1852 * C6.3.165 LDP (Load Pair of SIMD&FP)
1853 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1854 * C6.3.284 STP (Store Pair of SIMD&FP)
1856 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1857 * +-----+-------+---+---+-------+---+-----------------------------+
1858 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1859 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1861 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1863 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1864 * V: 0 -> GPR, 1 -> Vector
1865 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1866 * 10 -> signed offset, 11 -> pre-index
1867 * L: 0 -> Store 1 -> Load
1869 * Rt, Rt2 = GPR or SIMD registers to be stored
1870 * Rn = general purpose register containing address
1871 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1873 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1875 int rt
= extract32(insn
, 0, 5);
1876 int rn
= extract32(insn
, 5, 5);
1877 int rt2
= extract32(insn
, 10, 5);
1878 int64_t offset
= sextract32(insn
, 15, 7);
1879 int index
= extract32(insn
, 23, 2);
1880 bool is_vector
= extract32(insn
, 26, 1);
1881 bool is_load
= extract32(insn
, 22, 1);
1882 int opc
= extract32(insn
, 30, 2);
1884 bool is_signed
= false;
1885 bool postindex
= false;
1888 TCGv_i64 tcg_addr
; /* calculated address */
1892 unallocated_encoding(s
);
1899 size
= 2 + extract32(opc
, 1, 1);
1900 is_signed
= extract32(opc
, 0, 1);
1901 if (!is_load
&& is_signed
) {
1902 unallocated_encoding(s
);
1908 case 1: /* post-index */
1913 /* signed offset with "non-temporal" hint. Since we don't emulate
1914 * caches we don't care about hints to the cache system about
1915 * data access patterns, and handle this identically to plain
1919 /* There is no non-temporal-hint version of LDPSW */
1920 unallocated_encoding(s
);
1925 case 2: /* signed offset, rn not updated */
1928 case 3: /* pre-index */
1934 if (is_vector
&& !fp_access_check(s
)) {
1941 gen_check_sp_alignment(s
);
1944 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1947 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1952 do_fp_ld(s
, rt
, tcg_addr
, size
);
1954 do_fp_st(s
, rt
, tcg_addr
, size
);
1957 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1959 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1961 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1964 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1967 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1969 do_fp_st(s
, rt2
, tcg_addr
, size
);
1972 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1974 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1976 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1982 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1984 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1986 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1991 * C3.3.8 Load/store (immediate post-indexed)
1992 * C3.3.9 Load/store (immediate pre-indexed)
1993 * C3.3.12 Load/store (unscaled immediate)
1995 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1996 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1997 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1998 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2000 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2002 * V = 0 -> non-vector
2003 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2004 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2006 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
2008 int rt
= extract32(insn
, 0, 5);
2009 int rn
= extract32(insn
, 5, 5);
2010 int imm9
= sextract32(insn
, 12, 9);
2011 int opc
= extract32(insn
, 22, 2);
2012 int size
= extract32(insn
, 30, 2);
2013 int idx
= extract32(insn
, 10, 2);
2014 bool is_signed
= false;
2015 bool is_store
= false;
2016 bool is_extended
= false;
2017 bool is_unpriv
= (idx
== 2);
2018 bool is_vector
= extract32(insn
, 26, 1);
2025 size
|= (opc
& 2) << 1;
2026 if (size
> 4 || is_unpriv
) {
2027 unallocated_encoding(s
);
2030 is_store
= ((opc
& 1) == 0);
2031 if (!fp_access_check(s
)) {
2035 if (size
== 3 && opc
== 2) {
2036 /* PRFM - prefetch */
2038 unallocated_encoding(s
);
2043 if (opc
== 3 && size
> 1) {
2044 unallocated_encoding(s
);
2047 is_store
= (opc
== 0);
2048 is_signed
= opc
& (1<<1);
2049 is_extended
= (size
< 3) && (opc
& 1);
2069 gen_check_sp_alignment(s
);
2071 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2074 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2079 do_fp_st(s
, rt
, tcg_addr
, size
);
2081 do_fp_ld(s
, rt
, tcg_addr
, size
);
2084 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2085 int memidx
= is_unpriv
? 1 : get_mem_index(s
);
2088 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2090 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2091 is_signed
, is_extended
, memidx
);
2096 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2098 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2100 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2105 * C3.3.10 Load/store (register offset)
2107 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2108 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2109 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2110 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2113 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2114 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2116 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2117 * opc<0>: 0 -> store, 1 -> load
2118 * V: 1 -> vector/simd
2119 * opt: extend encoding (see DecodeRegExtend)
2120 * S: if S=1 then scale (essentially index by sizeof(size))
2121 * Rt: register to transfer into/out of
2122 * Rn: address register or SP for base
2123 * Rm: offset register or ZR for offset
2125 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2127 int rt
= extract32(insn
, 0, 5);
2128 int rn
= extract32(insn
, 5, 5);
2129 int shift
= extract32(insn
, 12, 1);
2130 int rm
= extract32(insn
, 16, 5);
2131 int opc
= extract32(insn
, 22, 2);
2132 int opt
= extract32(insn
, 13, 3);
2133 int size
= extract32(insn
, 30, 2);
2134 bool is_signed
= false;
2135 bool is_store
= false;
2136 bool is_extended
= false;
2137 bool is_vector
= extract32(insn
, 26, 1);
2142 if (extract32(opt
, 1, 1) == 0) {
2143 unallocated_encoding(s
);
2148 size
|= (opc
& 2) << 1;
2150 unallocated_encoding(s
);
2153 is_store
= !extract32(opc
, 0, 1);
2154 if (!fp_access_check(s
)) {
2158 if (size
== 3 && opc
== 2) {
2159 /* PRFM - prefetch */
2162 if (opc
== 3 && size
> 1) {
2163 unallocated_encoding(s
);
2166 is_store
= (opc
== 0);
2167 is_signed
= extract32(opc
, 1, 1);
2168 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2172 gen_check_sp_alignment(s
);
2174 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2176 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2177 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2179 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2183 do_fp_st(s
, rt
, tcg_addr
, size
);
2185 do_fp_ld(s
, rt
, tcg_addr
, size
);
2188 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2190 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2192 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2198 * C3.3.13 Load/store (unsigned immediate)
2200 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2201 * +----+-------+---+-----+-----+------------+-------+------+
2202 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2203 * +----+-------+---+-----+-----+------------+-------+------+
2206 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2207 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2209 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2210 * opc<0>: 0 -> store, 1 -> load
2211 * Rn: base address register (inc SP)
2212 * Rt: target register
2214 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2216 int rt
= extract32(insn
, 0, 5);
2217 int rn
= extract32(insn
, 5, 5);
2218 unsigned int imm12
= extract32(insn
, 10, 12);
2219 bool is_vector
= extract32(insn
, 26, 1);
2220 int size
= extract32(insn
, 30, 2);
2221 int opc
= extract32(insn
, 22, 2);
2222 unsigned int offset
;
2227 bool is_signed
= false;
2228 bool is_extended
= false;
2231 size
|= (opc
& 2) << 1;
2233 unallocated_encoding(s
);
2236 is_store
= !extract32(opc
, 0, 1);
2237 if (!fp_access_check(s
)) {
2241 if (size
== 3 && opc
== 2) {
2242 /* PRFM - prefetch */
2245 if (opc
== 3 && size
> 1) {
2246 unallocated_encoding(s
);
2249 is_store
= (opc
== 0);
2250 is_signed
= extract32(opc
, 1, 1);
2251 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2255 gen_check_sp_alignment(s
);
2257 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2258 offset
= imm12
<< size
;
2259 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2263 do_fp_st(s
, rt
, tcg_addr
, size
);
2265 do_fp_ld(s
, rt
, tcg_addr
, size
);
2268 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2270 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2272 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2277 /* Load/store register (all forms) */
2278 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2280 switch (extract32(insn
, 24, 2)) {
2282 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2283 disas_ldst_reg_roffset(s
, insn
);
2285 /* Load/store register (unscaled immediate)
2286 * Load/store immediate pre/post-indexed
2287 * Load/store register unprivileged
2289 disas_ldst_reg_imm9(s
, insn
);
2293 disas_ldst_reg_unsigned_imm(s
, insn
);
2296 unallocated_encoding(s
);
2301 /* C3.3.1 AdvSIMD load/store multiple structures
2303 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2304 * +---+---+---------------+---+-------------+--------+------+------+------+
2305 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2306 * +---+---+---------------+---+-------------+--------+------+------+------+
2308 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2310 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2311 * +---+---+---------------+---+---+---------+--------+------+------+------+
2312 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2313 * +---+---+---------------+---+---+---------+--------+------+------+------+
2315 * Rt: first (or only) SIMD&FP register to be transferred
2316 * Rn: base address or SP
2317 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2319 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2321 int rt
= extract32(insn
, 0, 5);
2322 int rn
= extract32(insn
, 5, 5);
2323 int size
= extract32(insn
, 10, 2);
2324 int opcode
= extract32(insn
, 12, 4);
2325 bool is_store
= !extract32(insn
, 22, 1);
2326 bool is_postidx
= extract32(insn
, 23, 1);
2327 bool is_q
= extract32(insn
, 30, 1);
2328 TCGv_i64 tcg_addr
, tcg_rn
;
2330 int ebytes
= 1 << size
;
2331 int elements
= (is_q
? 128 : 64) / (8 << size
);
2332 int rpt
; /* num iterations */
2333 int selem
; /* structure elements */
2336 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2337 unallocated_encoding(s
);
2341 /* From the shared decode logic */
2372 unallocated_encoding(s
);
2376 if (size
== 3 && !is_q
&& selem
!= 1) {
2378 unallocated_encoding(s
);
2382 if (!fp_access_check(s
)) {
2387 gen_check_sp_alignment(s
);
2390 tcg_rn
= cpu_reg_sp(s
, rn
);
2391 tcg_addr
= tcg_temp_new_i64();
2392 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2394 for (r
= 0; r
< rpt
; r
++) {
2396 for (e
= 0; e
< elements
; e
++) {
2397 int tt
= (rt
+ r
) % 32;
2399 for (xs
= 0; xs
< selem
; xs
++) {
2401 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2403 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2405 /* For non-quad operations, setting a slice of the low
2406 * 64 bits of the register clears the high 64 bits (in
2407 * the ARM ARM pseudocode this is implicit in the fact
2408 * that 'rval' is a 64 bit wide variable). We optimize
2409 * by noticing that we only need to do this the first
2410 * time we touch a register.
2412 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2413 clear_vec_high(s
, tt
);
2416 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2423 int rm
= extract32(insn
, 16, 5);
2425 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2427 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2430 tcg_temp_free_i64(tcg_addr
);
2433 /* C3.3.3 AdvSIMD load/store single structure
2435 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2436 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2437 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2438 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2440 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2442 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2443 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2444 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2445 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2447 * Rt: first (or only) SIMD&FP register to be transferred
2448 * Rn: base address or SP
2449 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2450 * index = encoded in Q:S:size dependent on size
2452 * lane_size = encoded in R, opc
2453 * transfer width = encoded in opc, S, size
2455 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2457 int rt
= extract32(insn
, 0, 5);
2458 int rn
= extract32(insn
, 5, 5);
2459 int size
= extract32(insn
, 10, 2);
2460 int S
= extract32(insn
, 12, 1);
2461 int opc
= extract32(insn
, 13, 3);
2462 int R
= extract32(insn
, 21, 1);
2463 int is_load
= extract32(insn
, 22, 1);
2464 int is_postidx
= extract32(insn
, 23, 1);
2465 int is_q
= extract32(insn
, 30, 1);
2467 int scale
= extract32(opc
, 1, 2);
2468 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2469 bool replicate
= false;
2470 int index
= is_q
<< 3 | S
<< 2 | size
;
2472 TCGv_i64 tcg_addr
, tcg_rn
;
2476 if (!is_load
|| S
) {
2477 unallocated_encoding(s
);
2486 if (extract32(size
, 0, 1)) {
2487 unallocated_encoding(s
);
2493 if (extract32(size
, 1, 1)) {
2494 unallocated_encoding(s
);
2497 if (!extract32(size
, 0, 1)) {
2501 unallocated_encoding(s
);
2509 g_assert_not_reached();
2512 if (!fp_access_check(s
)) {
2516 ebytes
= 1 << scale
;
2519 gen_check_sp_alignment(s
);
2522 tcg_rn
= cpu_reg_sp(s
, rn
);
2523 tcg_addr
= tcg_temp_new_i64();
2524 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2526 for (xs
= 0; xs
< selem
; xs
++) {
2528 /* Load and replicate to all elements */
2530 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2532 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2533 get_mem_index(s
), MO_TE
+ scale
);
2536 mulconst
= 0x0101010101010101ULL
;
2539 mulconst
= 0x0001000100010001ULL
;
2542 mulconst
= 0x0000000100000001ULL
;
2548 g_assert_not_reached();
2551 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2553 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2555 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2557 clear_vec_high(s
, rt
);
2559 tcg_temp_free_i64(tcg_tmp
);
2561 /* Load/store one element per register */
2563 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2565 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2568 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2573 int rm
= extract32(insn
, 16, 5);
2575 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2577 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2580 tcg_temp_free_i64(tcg_addr
);
2583 /* C3.3 Loads and stores */
2584 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2586 switch (extract32(insn
, 24, 6)) {
2587 case 0x08: /* Load/store exclusive */
2588 disas_ldst_excl(s
, insn
);
2590 case 0x18: case 0x1c: /* Load register (literal) */
2591 disas_ld_lit(s
, insn
);
2593 case 0x28: case 0x29:
2594 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2595 disas_ldst_pair(s
, insn
);
2597 case 0x38: case 0x39:
2598 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2599 disas_ldst_reg(s
, insn
);
2601 case 0x0c: /* AdvSIMD load/store multiple structures */
2602 disas_ldst_multiple_struct(s
, insn
);
2604 case 0x0d: /* AdvSIMD load/store single structure */
2605 disas_ldst_single_struct(s
, insn
);
2608 unallocated_encoding(s
);
2613 /* C3.4.6 PC-rel. addressing
2614 * 31 30 29 28 24 23 5 4 0
2615 * +----+-------+-----------+-------------------+------+
2616 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2617 * +----+-------+-----------+-------------------+------+
2619 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2621 unsigned int page
, rd
;
2625 page
= extract32(insn
, 31, 1);
2626 /* SignExtend(immhi:immlo) -> offset */
2627 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2628 rd
= extract32(insn
, 0, 5);
2632 /* ADRP (page based) */
2637 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2641 * C3.4.1 Add/subtract (immediate)
2643 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2644 * +--+--+--+-----------+-----+-------------+-----+-----+
2645 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2646 * +--+--+--+-----------+-----+-------------+-----+-----+
2648 * sf: 0 -> 32bit, 1 -> 64bit
2649 * op: 0 -> add , 1 -> sub
2651 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2653 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2655 int rd
= extract32(insn
, 0, 5);
2656 int rn
= extract32(insn
, 5, 5);
2657 uint64_t imm
= extract32(insn
, 10, 12);
2658 int shift
= extract32(insn
, 22, 2);
2659 bool setflags
= extract32(insn
, 29, 1);
2660 bool sub_op
= extract32(insn
, 30, 1);
2661 bool is_64bit
= extract32(insn
, 31, 1);
2663 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2664 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2665 TCGv_i64 tcg_result
;
2674 unallocated_encoding(s
);
2678 tcg_result
= tcg_temp_new_i64();
2681 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2683 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2686 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2688 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2690 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2692 tcg_temp_free_i64(tcg_imm
);
2696 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2698 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2701 tcg_temp_free_i64(tcg_result
);
2704 /* The input should be a value in the bottom e bits (with higher
2705 * bits zero); returns that value replicated into every element
2706 * of size e in a 64 bit integer.
2708 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2718 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2719 static inline uint64_t bitmask64(unsigned int length
)
2721 assert(length
> 0 && length
<= 64);
2722 return ~0ULL >> (64 - length
);
2725 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2726 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2727 * value (ie should cause a guest UNDEF exception), and true if they are
2728 * valid, in which case the decoded bit pattern is written to result.
2730 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2731 unsigned int imms
, unsigned int immr
)
2734 unsigned e
, levels
, s
, r
;
2737 assert(immn
< 2 && imms
< 64 && immr
< 64);
2739 /* The bit patterns we create here are 64 bit patterns which
2740 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2741 * 64 bits each. Each element contains the same value: a run
2742 * of between 1 and e-1 non-zero bits, rotated within the
2743 * element by between 0 and e-1 bits.
2745 * The element size and run length are encoded into immn (1 bit)
2746 * and imms (6 bits) as follows:
2747 * 64 bit elements: immn = 1, imms = <length of run - 1>
2748 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2749 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2750 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2751 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2752 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2753 * Notice that immn = 0, imms = 11111x is the only combination
2754 * not covered by one of the above options; this is reserved.
2755 * Further, <length of run - 1> all-ones is a reserved pattern.
2757 * In all cases the rotation is by immr % e (and immr is 6 bits).
2760 /* First determine the element size */
2761 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2763 /* This is the immn == 0, imms == 0x11111x case */
2773 /* <length of run - 1> mustn't be all-ones. */
2777 /* Create the value of one element: s+1 set bits rotated
2778 * by r within the element (which is e bits wide)...
2780 mask
= bitmask64(s
+ 1);
2781 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2782 /* ...then replicate the element over the whole 64 bit value */
2783 mask
= bitfield_replicate(mask
, e
);
2788 /* C3.4.4 Logical (immediate)
2789 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2790 * +----+-----+-------------+---+------+------+------+------+
2791 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2792 * +----+-----+-------------+---+------+------+------+------+
2794 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2796 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2797 TCGv_i64 tcg_rd
, tcg_rn
;
2799 bool is_and
= false;
2801 sf
= extract32(insn
, 31, 1);
2802 opc
= extract32(insn
, 29, 2);
2803 is_n
= extract32(insn
, 22, 1);
2804 immr
= extract32(insn
, 16, 6);
2805 imms
= extract32(insn
, 10, 6);
2806 rn
= extract32(insn
, 5, 5);
2807 rd
= extract32(insn
, 0, 5);
2810 unallocated_encoding(s
);
2814 if (opc
== 0x3) { /* ANDS */
2815 tcg_rd
= cpu_reg(s
, rd
);
2817 tcg_rd
= cpu_reg_sp(s
, rd
);
2819 tcg_rn
= cpu_reg(s
, rn
);
2821 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2822 /* some immediate field values are reserved */
2823 unallocated_encoding(s
);
2828 wmask
&= 0xffffffff;
2832 case 0x3: /* ANDS */
2834 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2838 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2841 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2844 assert(FALSE
); /* must handle all above */
2848 if (!sf
&& !is_and
) {
2849 /* zero extend final result; we know we can skip this for AND
2850 * since the immediate had the high 32 bits clear.
2852 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2855 if (opc
== 3) { /* ANDS */
2856 gen_logic_CC(sf
, tcg_rd
);
2861 * C3.4.5 Move wide (immediate)
2863 * 31 30 29 28 23 22 21 20 5 4 0
2864 * +--+-----+-------------+-----+----------------+------+
2865 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2866 * +--+-----+-------------+-----+----------------+------+
2868 * sf: 0 -> 32 bit, 1 -> 64 bit
2869 * opc: 00 -> N, 10 -> Z, 11 -> K
2870 * hw: shift/16 (0,16, and sf only 32, 48)
2872 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2874 int rd
= extract32(insn
, 0, 5);
2875 uint64_t imm
= extract32(insn
, 5, 16);
2876 int sf
= extract32(insn
, 31, 1);
2877 int opc
= extract32(insn
, 29, 2);
2878 int pos
= extract32(insn
, 21, 2) << 4;
2879 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2882 if (!sf
&& (pos
>= 32)) {
2883 unallocated_encoding(s
);
2897 tcg_gen_movi_i64(tcg_rd
, imm
);
2900 tcg_imm
= tcg_const_i64(imm
);
2901 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2902 tcg_temp_free_i64(tcg_imm
);
2904 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2908 unallocated_encoding(s
);
2914 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2915 * +----+-----+-------------+---+------+------+------+------+
2916 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2917 * +----+-----+-------------+---+------+------+------+------+
2919 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2921 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2922 TCGv_i64 tcg_rd
, tcg_tmp
;
2924 sf
= extract32(insn
, 31, 1);
2925 opc
= extract32(insn
, 29, 2);
2926 n
= extract32(insn
, 22, 1);
2927 ri
= extract32(insn
, 16, 6);
2928 si
= extract32(insn
, 10, 6);
2929 rn
= extract32(insn
, 5, 5);
2930 rd
= extract32(insn
, 0, 5);
2931 bitsize
= sf
? 64 : 32;
2933 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2934 unallocated_encoding(s
);
2938 tcg_rd
= cpu_reg(s
, rd
);
2939 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2941 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2943 if (opc
!= 1) { /* SBFM or UBFM */
2944 tcg_gen_movi_i64(tcg_rd
, 0);
2947 /* do the bit move operation */
2949 /* Wd<s-r:0> = Wn<s:r> */
2950 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2952 len
= (si
- ri
) + 1;
2954 /* Wd<32+s-r,32-r> = Wn<s:0> */
2959 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2961 if (opc
== 0) { /* SBFM - sign extend the destination field */
2962 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2963 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2966 if (!sf
) { /* zero extend final result */
2967 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2972 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2973 * +----+------+-------------+---+----+------+--------+------+------+
2974 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2975 * +----+------+-------------+---+----+------+--------+------+------+
2977 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2979 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2981 sf
= extract32(insn
, 31, 1);
2982 n
= extract32(insn
, 22, 1);
2983 rm
= extract32(insn
, 16, 5);
2984 imm
= extract32(insn
, 10, 6);
2985 rn
= extract32(insn
, 5, 5);
2986 rd
= extract32(insn
, 0, 5);
2987 op21
= extract32(insn
, 29, 2);
2988 op0
= extract32(insn
, 21, 1);
2989 bitsize
= sf
? 64 : 32;
2991 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2992 unallocated_encoding(s
);
2994 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2996 tcg_rd
= cpu_reg(s
, rd
);
2999 /* OPTME: we can special case rm==rn as a rotate */
3000 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3001 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3002 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3003 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3004 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3006 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3009 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3010 * so an extract from bit 0 is a special case.
3013 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3015 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3022 /* C3.4 Data processing - immediate */
3023 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3025 switch (extract32(insn
, 23, 6)) {
3026 case 0x20: case 0x21: /* PC-rel. addressing */
3027 disas_pc_rel_adr(s
, insn
);
3029 case 0x22: case 0x23: /* Add/subtract (immediate) */
3030 disas_add_sub_imm(s
, insn
);
3032 case 0x24: /* Logical (immediate) */
3033 disas_logic_imm(s
, insn
);
3035 case 0x25: /* Move wide (immediate) */
3036 disas_movw_imm(s
, insn
);
3038 case 0x26: /* Bitfield */
3039 disas_bitfield(s
, insn
);
3041 case 0x27: /* Extract */
3042 disas_extract(s
, insn
);
3045 unallocated_encoding(s
);
3050 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3051 * Note that it is the caller's responsibility to ensure that the
3052 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3053 * mandated semantics for out of range shifts.
3055 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3056 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3058 switch (shift_type
) {
3059 case A64_SHIFT_TYPE_LSL
:
3060 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3062 case A64_SHIFT_TYPE_LSR
:
3063 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3065 case A64_SHIFT_TYPE_ASR
:
3067 tcg_gen_ext32s_i64(dst
, src
);
3069 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3071 case A64_SHIFT_TYPE_ROR
:
3073 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3076 t0
= tcg_temp_new_i32();
3077 t1
= tcg_temp_new_i32();
3078 tcg_gen_trunc_i64_i32(t0
, src
);
3079 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
3080 tcg_gen_rotr_i32(t0
, t0
, t1
);
3081 tcg_gen_extu_i32_i64(dst
, t0
);
3082 tcg_temp_free_i32(t0
);
3083 tcg_temp_free_i32(t1
);
3087 assert(FALSE
); /* all shift types should be handled */
3091 if (!sf
) { /* zero extend final result */
3092 tcg_gen_ext32u_i64(dst
, dst
);
3096 /* Shift a TCGv src by immediate, put result in dst.
3097 * The shift amount must be in range (this should always be true as the
3098 * relevant instructions will UNDEF on bad shift immediates).
3100 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3101 enum a64_shift_type shift_type
, unsigned int shift_i
)
3103 assert(shift_i
< (sf
? 64 : 32));
3106 tcg_gen_mov_i64(dst
, src
);
3108 TCGv_i64 shift_const
;
3110 shift_const
= tcg_const_i64(shift_i
);
3111 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3112 tcg_temp_free_i64(shift_const
);
3116 /* C3.5.10 Logical (shifted register)
3117 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3118 * +----+-----+-----------+-------+---+------+--------+------+------+
3119 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3120 * +----+-----+-----------+-------+---+------+--------+------+------+
3122 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3124 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3125 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3127 sf
= extract32(insn
, 31, 1);
3128 opc
= extract32(insn
, 29, 2);
3129 shift_type
= extract32(insn
, 22, 2);
3130 invert
= extract32(insn
, 21, 1);
3131 rm
= extract32(insn
, 16, 5);
3132 shift_amount
= extract32(insn
, 10, 6);
3133 rn
= extract32(insn
, 5, 5);
3134 rd
= extract32(insn
, 0, 5);
3136 if (!sf
&& (shift_amount
& (1 << 5))) {
3137 unallocated_encoding(s
);
3141 tcg_rd
= cpu_reg(s
, rd
);
3143 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3144 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3145 * register-register MOV and MVN, so it is worth special casing.
3147 tcg_rm
= cpu_reg(s
, rm
);
3149 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3151 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3155 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3157 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3163 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3166 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3169 tcg_rn
= cpu_reg(s
, rn
);
3171 switch (opc
| (invert
<< 2)) {
3174 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3177 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3180 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3184 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3187 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3190 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3198 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3202 gen_logic_CC(sf
, tcg_rd
);
3207 * C3.5.1 Add/subtract (extended register)
3209 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3210 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3211 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3212 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3214 * sf: 0 -> 32bit, 1 -> 64bit
3215 * op: 0 -> add , 1 -> sub
3218 * option: extension type (see DecodeRegExtend)
3219 * imm3: optional shift to Rm
3221 * Rd = Rn + LSL(extend(Rm), amount)
3223 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3225 int rd
= extract32(insn
, 0, 5);
3226 int rn
= extract32(insn
, 5, 5);
3227 int imm3
= extract32(insn
, 10, 3);
3228 int option
= extract32(insn
, 13, 3);
3229 int rm
= extract32(insn
, 16, 5);
3230 bool setflags
= extract32(insn
, 29, 1);
3231 bool sub_op
= extract32(insn
, 30, 1);
3232 bool sf
= extract32(insn
, 31, 1);
3234 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3236 TCGv_i64 tcg_result
;
3239 unallocated_encoding(s
);
3243 /* non-flag setting ops may use SP */
3245 tcg_rd
= cpu_reg_sp(s
, rd
);
3247 tcg_rd
= cpu_reg(s
, rd
);
3249 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3251 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3252 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3254 tcg_result
= tcg_temp_new_i64();
3258 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3260 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3264 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3266 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3271 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3273 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3276 tcg_temp_free_i64(tcg_result
);
3280 * C3.5.2 Add/subtract (shifted register)
3282 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3283 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3284 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3285 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3287 * sf: 0 -> 32bit, 1 -> 64bit
3288 * op: 0 -> add , 1 -> sub
3290 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3291 * imm6: Shift amount to apply to Rm before the add/sub
3293 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3295 int rd
= extract32(insn
, 0, 5);
3296 int rn
= extract32(insn
, 5, 5);
3297 int imm6
= extract32(insn
, 10, 6);
3298 int rm
= extract32(insn
, 16, 5);
3299 int shift_type
= extract32(insn
, 22, 2);
3300 bool setflags
= extract32(insn
, 29, 1);
3301 bool sub_op
= extract32(insn
, 30, 1);
3302 bool sf
= extract32(insn
, 31, 1);
3304 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3305 TCGv_i64 tcg_rn
, tcg_rm
;
3306 TCGv_i64 tcg_result
;
3308 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3309 unallocated_encoding(s
);
3313 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3314 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3316 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3318 tcg_result
= tcg_temp_new_i64();
3322 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3324 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3328 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3330 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3335 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3337 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3340 tcg_temp_free_i64(tcg_result
);
3343 /* C3.5.9 Data-processing (3 source)
3345 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3346 +--+------+-----------+------+------+----+------+------+------+
3347 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3348 +--+------+-----------+------+------+----+------+------+------+
3351 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3353 int rd
= extract32(insn
, 0, 5);
3354 int rn
= extract32(insn
, 5, 5);
3355 int ra
= extract32(insn
, 10, 5);
3356 int rm
= extract32(insn
, 16, 5);
3357 int op_id
= (extract32(insn
, 29, 3) << 4) |
3358 (extract32(insn
, 21, 3) << 1) |
3359 extract32(insn
, 15, 1);
3360 bool sf
= extract32(insn
, 31, 1);
3361 bool is_sub
= extract32(op_id
, 0, 1);
3362 bool is_high
= extract32(op_id
, 2, 1);
3363 bool is_signed
= false;
3368 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3370 case 0x42: /* SMADDL */
3371 case 0x43: /* SMSUBL */
3372 case 0x44: /* SMULH */
3375 case 0x0: /* MADD (32bit) */
3376 case 0x1: /* MSUB (32bit) */
3377 case 0x40: /* MADD (64bit) */
3378 case 0x41: /* MSUB (64bit) */
3379 case 0x4a: /* UMADDL */
3380 case 0x4b: /* UMSUBL */
3381 case 0x4c: /* UMULH */
3384 unallocated_encoding(s
);
3389 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3390 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3391 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3392 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3395 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3397 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3400 tcg_temp_free_i64(low_bits
);
3404 tcg_op1
= tcg_temp_new_i64();
3405 tcg_op2
= tcg_temp_new_i64();
3406 tcg_tmp
= tcg_temp_new_i64();
3409 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3410 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3413 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3414 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3416 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3417 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3421 if (ra
== 31 && !is_sub
) {
3422 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3423 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3425 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3427 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3429 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3434 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3437 tcg_temp_free_i64(tcg_op1
);
3438 tcg_temp_free_i64(tcg_op2
);
3439 tcg_temp_free_i64(tcg_tmp
);
3442 /* C3.5.3 - Add/subtract (with carry)
3443 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3444 * +--+--+--+------------------------+------+---------+------+-----+
3445 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3446 * +--+--+--+------------------------+------+---------+------+-----+
3450 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3452 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3453 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3455 if (extract32(insn
, 10, 6) != 0) {
3456 unallocated_encoding(s
);
3460 sf
= extract32(insn
, 31, 1);
3461 op
= extract32(insn
, 30, 1);
3462 setflags
= extract32(insn
, 29, 1);
3463 rm
= extract32(insn
, 16, 5);
3464 rn
= extract32(insn
, 5, 5);
3465 rd
= extract32(insn
, 0, 5);
3467 tcg_rd
= cpu_reg(s
, rd
);
3468 tcg_rn
= cpu_reg(s
, rn
);
3471 tcg_y
= new_tmp_a64(s
);
3472 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3474 tcg_y
= cpu_reg(s
, rm
);
3478 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3480 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3484 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3485 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3486 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3487 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3488 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3491 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3493 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3494 int label_continue
= -1;
3495 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3497 if (!extract32(insn
, 29, 1)) {
3498 unallocated_encoding(s
);
3501 if (insn
& (1 << 10 | 1 << 4)) {
3502 unallocated_encoding(s
);
3505 sf
= extract32(insn
, 31, 1);
3506 op
= extract32(insn
, 30, 1);
3507 is_imm
= extract32(insn
, 11, 1);
3508 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3509 cond
= extract32(insn
, 12, 4);
3510 rn
= extract32(insn
, 5, 5);
3511 nzcv
= extract32(insn
, 0, 4);
3513 if (cond
< 0x0e) { /* not always */
3514 int label_match
= gen_new_label();
3515 label_continue
= gen_new_label();
3516 arm_gen_test_cc(cond
, label_match
);
3518 tcg_tmp
= tcg_temp_new_i64();
3519 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3520 gen_set_nzcv(tcg_tmp
);
3521 tcg_temp_free_i64(tcg_tmp
);
3522 tcg_gen_br(label_continue
);
3523 gen_set_label(label_match
);
3525 /* match, or condition is always */
3527 tcg_y
= new_tmp_a64(s
);
3528 tcg_gen_movi_i64(tcg_y
, y
);
3530 tcg_y
= cpu_reg(s
, y
);
3532 tcg_rn
= cpu_reg(s
, rn
);
3534 tcg_tmp
= tcg_temp_new_i64();
3536 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3538 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3540 tcg_temp_free_i64(tcg_tmp
);
3542 if (cond
< 0x0e) { /* continue */
3543 gen_set_label(label_continue
);
3547 /* C3.5.6 Conditional select
3548 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3549 * +----+----+---+-----------------+------+------+-----+------+------+
3550 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3551 * +----+----+---+-----------------+------+------+-----+------+------+
3553 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3555 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3556 TCGv_i64 tcg_rd
, tcg_src
;
3558 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3559 /* S == 1 or op2<1> == 1 */
3560 unallocated_encoding(s
);
3563 sf
= extract32(insn
, 31, 1);
3564 else_inv
= extract32(insn
, 30, 1);
3565 rm
= extract32(insn
, 16, 5);
3566 cond
= extract32(insn
, 12, 4);
3567 else_inc
= extract32(insn
, 10, 1);
3568 rn
= extract32(insn
, 5, 5);
3569 rd
= extract32(insn
, 0, 5);
3572 /* silly no-op write; until we use movcond we must special-case
3573 * this to avoid a dead temporary across basic blocks.
3578 tcg_rd
= cpu_reg(s
, rd
);
3580 if (cond
>= 0x0e) { /* condition "always" */
3581 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3582 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3584 /* OPTME: we could use movcond here, at the cost of duplicating
3585 * a lot of the arm_gen_test_cc() logic.
3587 int label_match
= gen_new_label();
3588 int label_continue
= gen_new_label();
3590 arm_gen_test_cc(cond
, label_match
);
3592 tcg_src
= cpu_reg(s
, rm
);
3594 if (else_inv
&& else_inc
) {
3595 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3596 } else if (else_inv
) {
3597 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3598 } else if (else_inc
) {
3599 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3601 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3604 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3606 tcg_gen_br(label_continue
);
3608 gen_set_label(label_match
);
3609 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3610 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3612 gen_set_label(label_continue
);
3616 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3617 unsigned int rn
, unsigned int rd
)
3619 TCGv_i64 tcg_rd
, tcg_rn
;
3620 tcg_rd
= cpu_reg(s
, rd
);
3621 tcg_rn
= cpu_reg(s
, rn
);
3624 gen_helper_clz64(tcg_rd
, tcg_rn
);
3626 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3627 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3628 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3629 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3630 tcg_temp_free_i32(tcg_tmp32
);
3634 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3635 unsigned int rn
, unsigned int rd
)
3637 TCGv_i64 tcg_rd
, tcg_rn
;
3638 tcg_rd
= cpu_reg(s
, rd
);
3639 tcg_rn
= cpu_reg(s
, rn
);
3642 gen_helper_cls64(tcg_rd
, tcg_rn
);
3644 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3645 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3646 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3647 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3648 tcg_temp_free_i32(tcg_tmp32
);
3652 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3653 unsigned int rn
, unsigned int rd
)
3655 TCGv_i64 tcg_rd
, tcg_rn
;
3656 tcg_rd
= cpu_reg(s
, rd
);
3657 tcg_rn
= cpu_reg(s
, rn
);
3660 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3662 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3663 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3664 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3665 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3666 tcg_temp_free_i32(tcg_tmp32
);
3670 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3671 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3672 unsigned int rn
, unsigned int rd
)
3675 unallocated_encoding(s
);
3678 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3681 /* C5.6.149 REV with sf==0, opcode==2
3682 * C5.6.151 REV32 (sf==1, opcode==2)
3684 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3685 unsigned int rn
, unsigned int rd
)
3687 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3690 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3691 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3693 /* bswap32_i64 requires zero high word */
3694 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3695 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3696 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3697 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3698 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3700 tcg_temp_free_i64(tcg_tmp
);
3702 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3703 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3707 /* C5.6.150 REV16 (opcode==1) */
3708 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3709 unsigned int rn
, unsigned int rd
)
3711 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3712 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3713 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3715 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3716 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3718 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3719 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3720 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3721 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3724 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3725 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3726 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3727 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3729 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3730 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3731 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3734 tcg_temp_free_i64(tcg_tmp
);
3737 /* C3.5.7 Data-processing (1 source)
3738 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3739 * +----+---+---+-----------------+---------+--------+------+------+
3740 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3741 * +----+---+---+-----------------+---------+--------+------+------+
3743 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3745 unsigned int sf
, opcode
, rn
, rd
;
3747 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3748 unallocated_encoding(s
);
3752 sf
= extract32(insn
, 31, 1);
3753 opcode
= extract32(insn
, 10, 6);
3754 rn
= extract32(insn
, 5, 5);
3755 rd
= extract32(insn
, 0, 5);
3759 handle_rbit(s
, sf
, rn
, rd
);
3762 handle_rev16(s
, sf
, rn
, rd
);
3765 handle_rev32(s
, sf
, rn
, rd
);
3768 handle_rev64(s
, sf
, rn
, rd
);
3771 handle_clz(s
, sf
, rn
, rd
);
3774 handle_cls(s
, sf
, rn
, rd
);
3779 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3780 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3782 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3783 tcg_rd
= cpu_reg(s
, rd
);
3785 if (!sf
&& is_signed
) {
3786 tcg_n
= new_tmp_a64(s
);
3787 tcg_m
= new_tmp_a64(s
);
3788 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3789 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3791 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3792 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3796 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3798 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3801 if (!sf
) { /* zero extend final result */
3802 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3806 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3807 static void handle_shift_reg(DisasContext
*s
,
3808 enum a64_shift_type shift_type
, unsigned int sf
,
3809 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3811 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3812 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3813 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3815 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3816 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3817 tcg_temp_free_i64(tcg_shift
);
3820 /* CRC32[BHWX], CRC32C[BHWX] */
3821 static void handle_crc32(DisasContext
*s
,
3822 unsigned int sf
, unsigned int sz
, bool crc32c
,
3823 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3825 TCGv_i64 tcg_acc
, tcg_val
;
3828 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
3829 || (sf
== 1 && sz
!= 3)
3830 || (sf
== 0 && sz
== 3)) {
3831 unallocated_encoding(s
);
3836 tcg_val
= cpu_reg(s
, rm
);
3850 g_assert_not_reached();
3852 tcg_val
= new_tmp_a64(s
);
3853 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
3856 tcg_acc
= cpu_reg(s
, rn
);
3857 tcg_bytes
= tcg_const_i32(1 << sz
);
3860 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3862 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3865 tcg_temp_free_i32(tcg_bytes
);
3868 /* C3.5.8 Data-processing (2 source)
3869 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3870 * +----+---+---+-----------------+------+--------+------+------+
3871 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3872 * +----+---+---+-----------------+------+--------+------+------+
3874 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3876 unsigned int sf
, rm
, opcode
, rn
, rd
;
3877 sf
= extract32(insn
, 31, 1);
3878 rm
= extract32(insn
, 16, 5);
3879 opcode
= extract32(insn
, 10, 6);
3880 rn
= extract32(insn
, 5, 5);
3881 rd
= extract32(insn
, 0, 5);
3883 if (extract32(insn
, 29, 1)) {
3884 unallocated_encoding(s
);
3890 handle_div(s
, false, sf
, rm
, rn
, rd
);
3893 handle_div(s
, true, sf
, rm
, rn
, rd
);
3896 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3899 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3902 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3905 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3914 case 23: /* CRC32 */
3916 int sz
= extract32(opcode
, 0, 2);
3917 bool crc32c
= extract32(opcode
, 2, 1);
3918 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
3922 unallocated_encoding(s
);
3927 /* C3.5 Data processing - register */
3928 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3930 switch (extract32(insn
, 24, 5)) {
3931 case 0x0a: /* Logical (shifted register) */
3932 disas_logic_reg(s
, insn
);
3934 case 0x0b: /* Add/subtract */
3935 if (insn
& (1 << 21)) { /* (extended register) */
3936 disas_add_sub_ext_reg(s
, insn
);
3938 disas_add_sub_reg(s
, insn
);
3941 case 0x1b: /* Data-processing (3 source) */
3942 disas_data_proc_3src(s
, insn
);
3945 switch (extract32(insn
, 21, 3)) {
3946 case 0x0: /* Add/subtract (with carry) */
3947 disas_adc_sbc(s
, insn
);
3949 case 0x2: /* Conditional compare */
3950 disas_cc(s
, insn
); /* both imm and reg forms */
3952 case 0x4: /* Conditional select */
3953 disas_cond_select(s
, insn
);
3955 case 0x6: /* Data-processing */
3956 if (insn
& (1 << 30)) { /* (1 source) */
3957 disas_data_proc_1src(s
, insn
);
3958 } else { /* (2 source) */
3959 disas_data_proc_2src(s
, insn
);
3963 unallocated_encoding(s
);
3968 unallocated_encoding(s
);
3973 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3974 unsigned int rn
, unsigned int rm
,
3975 bool cmp_with_zero
, bool signal_all_nans
)
3977 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3978 TCGv_ptr fpst
= get_fpstatus_ptr();
3981 TCGv_i64 tcg_vn
, tcg_vm
;
3983 tcg_vn
= read_fp_dreg(s
, rn
);
3984 if (cmp_with_zero
) {
3985 tcg_vm
= tcg_const_i64(0);
3987 tcg_vm
= read_fp_dreg(s
, rm
);
3989 if (signal_all_nans
) {
3990 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3992 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3994 tcg_temp_free_i64(tcg_vn
);
3995 tcg_temp_free_i64(tcg_vm
);
3997 TCGv_i32 tcg_vn
, tcg_vm
;
3999 tcg_vn
= read_fp_sreg(s
, rn
);
4000 if (cmp_with_zero
) {
4001 tcg_vm
= tcg_const_i32(0);
4003 tcg_vm
= read_fp_sreg(s
, rm
);
4005 if (signal_all_nans
) {
4006 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4008 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4010 tcg_temp_free_i32(tcg_vn
);
4011 tcg_temp_free_i32(tcg_vm
);
4014 tcg_temp_free_ptr(fpst
);
4016 gen_set_nzcv(tcg_flags
);
4018 tcg_temp_free_i64(tcg_flags
);
4021 /* C3.6.22 Floating point compare
4022 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4023 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4024 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4025 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4027 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4029 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4031 mos
= extract32(insn
, 29, 3);
4032 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4033 rm
= extract32(insn
, 16, 5);
4034 op
= extract32(insn
, 14, 2);
4035 rn
= extract32(insn
, 5, 5);
4036 opc
= extract32(insn
, 3, 2);
4037 op2r
= extract32(insn
, 0, 3);
4039 if (mos
|| op
|| op2r
|| type
> 1) {
4040 unallocated_encoding(s
);
4044 if (!fp_access_check(s
)) {
4048 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4051 /* C3.6.23 Floating point conditional compare
4052 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4053 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4054 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4055 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4057 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4059 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4061 int label_continue
= -1;
4063 mos
= extract32(insn
, 29, 3);
4064 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4065 rm
= extract32(insn
, 16, 5);
4066 cond
= extract32(insn
, 12, 4);
4067 rn
= extract32(insn
, 5, 5);
4068 op
= extract32(insn
, 4, 1);
4069 nzcv
= extract32(insn
, 0, 4);
4071 if (mos
|| type
> 1) {
4072 unallocated_encoding(s
);
4076 if (!fp_access_check(s
)) {
4080 if (cond
< 0x0e) { /* not always */
4081 int label_match
= gen_new_label();
4082 label_continue
= gen_new_label();
4083 arm_gen_test_cc(cond
, label_match
);
4085 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4086 gen_set_nzcv(tcg_flags
);
4087 tcg_temp_free_i64(tcg_flags
);
4088 tcg_gen_br(label_continue
);
4089 gen_set_label(label_match
);
4092 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4095 gen_set_label(label_continue
);
4099 /* copy src FP register to dst FP register; type specifies single or double */
4100 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
4103 TCGv_i64 v
= read_fp_dreg(s
, src
);
4104 write_fp_dreg(s
, dst
, v
);
4105 tcg_temp_free_i64(v
);
4107 TCGv_i32 v
= read_fp_sreg(s
, src
);
4108 write_fp_sreg(s
, dst
, v
);
4109 tcg_temp_free_i32(v
);
4113 /* C3.6.24 Floating point conditional select
4114 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4115 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4116 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4117 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4119 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4121 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4122 int label_continue
= -1;
4124 mos
= extract32(insn
, 29, 3);
4125 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4126 rm
= extract32(insn
, 16, 5);
4127 cond
= extract32(insn
, 12, 4);
4128 rn
= extract32(insn
, 5, 5);
4129 rd
= extract32(insn
, 0, 5);
4131 if (mos
|| type
> 1) {
4132 unallocated_encoding(s
);
4136 if (!fp_access_check(s
)) {
4140 if (cond
< 0x0e) { /* not always */
4141 int label_match
= gen_new_label();
4142 label_continue
= gen_new_label();
4143 arm_gen_test_cc(cond
, label_match
);
4145 gen_mov_fp2fp(s
, type
, rd
, rm
);
4146 tcg_gen_br(label_continue
);
4147 gen_set_label(label_match
);
4150 gen_mov_fp2fp(s
, type
, rd
, rn
);
4152 if (cond
< 0x0e) { /* continue */
4153 gen_set_label(label_continue
);
4157 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4158 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4164 fpst
= get_fpstatus_ptr();
4165 tcg_op
= read_fp_sreg(s
, rn
);
4166 tcg_res
= tcg_temp_new_i32();
4169 case 0x0: /* FMOV */
4170 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4172 case 0x1: /* FABS */
4173 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4175 case 0x2: /* FNEG */
4176 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4178 case 0x3: /* FSQRT */
4179 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4181 case 0x8: /* FRINTN */
4182 case 0x9: /* FRINTP */
4183 case 0xa: /* FRINTM */
4184 case 0xb: /* FRINTZ */
4185 case 0xc: /* FRINTA */
4187 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4189 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4190 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4192 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4193 tcg_temp_free_i32(tcg_rmode
);
4196 case 0xe: /* FRINTX */
4197 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4199 case 0xf: /* FRINTI */
4200 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4206 write_fp_sreg(s
, rd
, tcg_res
);
4208 tcg_temp_free_ptr(fpst
);
4209 tcg_temp_free_i32(tcg_op
);
4210 tcg_temp_free_i32(tcg_res
);
4213 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4214 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4220 fpst
= get_fpstatus_ptr();
4221 tcg_op
= read_fp_dreg(s
, rn
);
4222 tcg_res
= tcg_temp_new_i64();
4225 case 0x0: /* FMOV */
4226 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4228 case 0x1: /* FABS */
4229 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4231 case 0x2: /* FNEG */
4232 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4234 case 0x3: /* FSQRT */
4235 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4237 case 0x8: /* FRINTN */
4238 case 0x9: /* FRINTP */
4239 case 0xa: /* FRINTM */
4240 case 0xb: /* FRINTZ */
4241 case 0xc: /* FRINTA */
4243 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4245 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4246 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4248 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4249 tcg_temp_free_i32(tcg_rmode
);
4252 case 0xe: /* FRINTX */
4253 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4255 case 0xf: /* FRINTI */
4256 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4262 write_fp_dreg(s
, rd
, tcg_res
);
4264 tcg_temp_free_ptr(fpst
);
4265 tcg_temp_free_i64(tcg_op
);
4266 tcg_temp_free_i64(tcg_res
);
4269 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4270 int rd
, int rn
, int dtype
, int ntype
)
4275 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4277 /* Single to double */
4278 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4279 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4280 write_fp_dreg(s
, rd
, tcg_rd
);
4281 tcg_temp_free_i64(tcg_rd
);
4283 /* Single to half */
4284 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4285 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4286 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4287 write_fp_sreg(s
, rd
, tcg_rd
);
4288 tcg_temp_free_i32(tcg_rd
);
4290 tcg_temp_free_i32(tcg_rn
);
4295 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4296 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4298 /* Double to single */
4299 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4301 /* Double to half */
4302 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4303 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4305 write_fp_sreg(s
, rd
, tcg_rd
);
4306 tcg_temp_free_i32(tcg_rd
);
4307 tcg_temp_free_i64(tcg_rn
);
4312 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4313 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4315 /* Half to single */
4316 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4317 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4318 write_fp_sreg(s
, rd
, tcg_rd
);
4319 tcg_temp_free_i32(tcg_rd
);
4321 /* Half to double */
4322 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4323 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4324 write_fp_dreg(s
, rd
, tcg_rd
);
4325 tcg_temp_free_i64(tcg_rd
);
4327 tcg_temp_free_i32(tcg_rn
);
4335 /* C3.6.25 Floating point data-processing (1 source)
4336 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4337 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4338 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4339 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4341 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4343 int type
= extract32(insn
, 22, 2);
4344 int opcode
= extract32(insn
, 15, 6);
4345 int rn
= extract32(insn
, 5, 5);
4346 int rd
= extract32(insn
, 0, 5);
4349 case 0x4: case 0x5: case 0x7:
4351 /* FCVT between half, single and double precision */
4352 int dtype
= extract32(opcode
, 0, 2);
4353 if (type
== 2 || dtype
== type
) {
4354 unallocated_encoding(s
);
4357 if (!fp_access_check(s
)) {
4361 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4367 /* 32-to-32 and 64-to-64 ops */
4370 if (!fp_access_check(s
)) {
4374 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4377 if (!fp_access_check(s
)) {
4381 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4384 unallocated_encoding(s
);
4388 unallocated_encoding(s
);
4393 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4394 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4395 int rd
, int rn
, int rm
)
4402 tcg_res
= tcg_temp_new_i32();
4403 fpst
= get_fpstatus_ptr();
4404 tcg_op1
= read_fp_sreg(s
, rn
);
4405 tcg_op2
= read_fp_sreg(s
, rm
);
4408 case 0x0: /* FMUL */
4409 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4411 case 0x1: /* FDIV */
4412 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4414 case 0x2: /* FADD */
4415 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4417 case 0x3: /* FSUB */
4418 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4420 case 0x4: /* FMAX */
4421 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4423 case 0x5: /* FMIN */
4424 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4426 case 0x6: /* FMAXNM */
4427 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4429 case 0x7: /* FMINNM */
4430 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4432 case 0x8: /* FNMUL */
4433 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4434 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4438 write_fp_sreg(s
, rd
, tcg_res
);
4440 tcg_temp_free_ptr(fpst
);
4441 tcg_temp_free_i32(tcg_op1
);
4442 tcg_temp_free_i32(tcg_op2
);
4443 tcg_temp_free_i32(tcg_res
);
4446 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4447 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4448 int rd
, int rn
, int rm
)
4455 tcg_res
= tcg_temp_new_i64();
4456 fpst
= get_fpstatus_ptr();
4457 tcg_op1
= read_fp_dreg(s
, rn
);
4458 tcg_op2
= read_fp_dreg(s
, rm
);
4461 case 0x0: /* FMUL */
4462 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4464 case 0x1: /* FDIV */
4465 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4467 case 0x2: /* FADD */
4468 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4470 case 0x3: /* FSUB */
4471 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4473 case 0x4: /* FMAX */
4474 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4476 case 0x5: /* FMIN */
4477 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4479 case 0x6: /* FMAXNM */
4480 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4482 case 0x7: /* FMINNM */
4483 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4485 case 0x8: /* FNMUL */
4486 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4487 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4491 write_fp_dreg(s
, rd
, tcg_res
);
4493 tcg_temp_free_ptr(fpst
);
4494 tcg_temp_free_i64(tcg_op1
);
4495 tcg_temp_free_i64(tcg_op2
);
4496 tcg_temp_free_i64(tcg_res
);
4499 /* C3.6.26 Floating point data-processing (2 source)
4500 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4501 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4502 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4503 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4505 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4507 int type
= extract32(insn
, 22, 2);
4508 int rd
= extract32(insn
, 0, 5);
4509 int rn
= extract32(insn
, 5, 5);
4510 int rm
= extract32(insn
, 16, 5);
4511 int opcode
= extract32(insn
, 12, 4);
4514 unallocated_encoding(s
);
4520 if (!fp_access_check(s
)) {
4523 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4526 if (!fp_access_check(s
)) {
4529 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4532 unallocated_encoding(s
);
4536 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4537 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4538 int rd
, int rn
, int rm
, int ra
)
4540 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4541 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4542 TCGv_ptr fpst
= get_fpstatus_ptr();
4544 tcg_op1
= read_fp_sreg(s
, rn
);
4545 tcg_op2
= read_fp_sreg(s
, rm
);
4546 tcg_op3
= read_fp_sreg(s
, ra
);
4548 /* These are fused multiply-add, and must be done as one
4549 * floating point operation with no rounding between the
4550 * multiplication and addition steps.
4551 * NB that doing the negations here as separate steps is
4552 * correct : an input NaN should come out with its sign bit
4553 * flipped if it is a negated-input.
4556 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4560 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4563 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4565 write_fp_sreg(s
, rd
, tcg_res
);
4567 tcg_temp_free_ptr(fpst
);
4568 tcg_temp_free_i32(tcg_op1
);
4569 tcg_temp_free_i32(tcg_op2
);
4570 tcg_temp_free_i32(tcg_op3
);
4571 tcg_temp_free_i32(tcg_res
);
4574 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4575 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4576 int rd
, int rn
, int rm
, int ra
)
4578 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4579 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4580 TCGv_ptr fpst
= get_fpstatus_ptr();
4582 tcg_op1
= read_fp_dreg(s
, rn
);
4583 tcg_op2
= read_fp_dreg(s
, rm
);
4584 tcg_op3
= read_fp_dreg(s
, ra
);
4586 /* These are fused multiply-add, and must be done as one
4587 * floating point operation with no rounding between the
4588 * multiplication and addition steps.
4589 * NB that doing the negations here as separate steps is
4590 * correct : an input NaN should come out with its sign bit
4591 * flipped if it is a negated-input.
4594 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4598 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4601 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4603 write_fp_dreg(s
, rd
, tcg_res
);
4605 tcg_temp_free_ptr(fpst
);
4606 tcg_temp_free_i64(tcg_op1
);
4607 tcg_temp_free_i64(tcg_op2
);
4608 tcg_temp_free_i64(tcg_op3
);
4609 tcg_temp_free_i64(tcg_res
);
4612 /* C3.6.27 Floating point data-processing (3 source)
4613 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4614 * +---+---+---+-----------+------+----+------+----+------+------+------+
4615 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4616 * +---+---+---+-----------+------+----+------+----+------+------+------+
4618 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4620 int type
= extract32(insn
, 22, 2);
4621 int rd
= extract32(insn
, 0, 5);
4622 int rn
= extract32(insn
, 5, 5);
4623 int ra
= extract32(insn
, 10, 5);
4624 int rm
= extract32(insn
, 16, 5);
4625 bool o0
= extract32(insn
, 15, 1);
4626 bool o1
= extract32(insn
, 21, 1);
4630 if (!fp_access_check(s
)) {
4633 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4636 if (!fp_access_check(s
)) {
4639 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4642 unallocated_encoding(s
);
4646 /* C3.6.28 Floating point immediate
4647 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4648 * +---+---+---+-----------+------+---+------------+-------+------+------+
4649 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4650 * +---+---+---+-----------+------+---+------------+-------+------+------+
4652 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4654 int rd
= extract32(insn
, 0, 5);
4655 int imm8
= extract32(insn
, 13, 8);
4656 int is_double
= extract32(insn
, 22, 2);
4660 if (is_double
> 1) {
4661 unallocated_encoding(s
);
4665 if (!fp_access_check(s
)) {
4669 /* The imm8 encodes the sign bit, enough bits to represent
4670 * an exponent in the range 01....1xx to 10....0xx,
4671 * and the most significant 4 bits of the mantissa; see
4672 * VFPExpandImm() in the v8 ARM ARM.
4675 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4676 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4677 extract32(imm8
, 0, 6);
4680 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4681 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4682 (extract32(imm8
, 0, 6) << 3);
4686 tcg_res
= tcg_const_i64(imm
);
4687 write_fp_dreg(s
, rd
, tcg_res
);
4688 tcg_temp_free_i64(tcg_res
);
4691 /* Handle floating point <=> fixed point conversions. Note that we can
4692 * also deal with fp <=> integer conversions as a special case (scale == 64)
4693 * OPTME: consider handling that special case specially or at least skipping
4694 * the call to scalbn in the helpers for zero shifts.
4696 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4697 bool itof
, int rmode
, int scale
, int sf
, int type
)
4699 bool is_signed
= !(opcode
& 1);
4700 bool is_double
= type
;
4701 TCGv_ptr tcg_fpstatus
;
4704 tcg_fpstatus
= get_fpstatus_ptr();
4706 tcg_shift
= tcg_const_i32(64 - scale
);
4709 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4711 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4714 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4716 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4719 tcg_int
= tcg_extend
;
4723 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4725 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4726 tcg_shift
, tcg_fpstatus
);
4728 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4729 tcg_shift
, tcg_fpstatus
);
4731 write_fp_dreg(s
, rd
, tcg_double
);
4732 tcg_temp_free_i64(tcg_double
);
4734 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4736 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4737 tcg_shift
, tcg_fpstatus
);
4739 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4740 tcg_shift
, tcg_fpstatus
);
4742 write_fp_sreg(s
, rd
, tcg_single
);
4743 tcg_temp_free_i32(tcg_single
);
4746 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4749 if (extract32(opcode
, 2, 1)) {
4750 /* There are too many rounding modes to all fit into rmode,
4751 * so FCVTA[US] is a special case.
4753 rmode
= FPROUNDING_TIEAWAY
;
4756 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4758 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4761 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4764 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4765 tcg_shift
, tcg_fpstatus
);
4767 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4768 tcg_shift
, tcg_fpstatus
);
4772 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4773 tcg_shift
, tcg_fpstatus
);
4775 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4776 tcg_shift
, tcg_fpstatus
);
4779 tcg_temp_free_i64(tcg_double
);
4781 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4784 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4785 tcg_shift
, tcg_fpstatus
);
4787 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4788 tcg_shift
, tcg_fpstatus
);
4791 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4793 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4794 tcg_shift
, tcg_fpstatus
);
4796 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4797 tcg_shift
, tcg_fpstatus
);
4799 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4800 tcg_temp_free_i32(tcg_dest
);
4802 tcg_temp_free_i32(tcg_single
);
4805 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4806 tcg_temp_free_i32(tcg_rmode
);
4809 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4813 tcg_temp_free_ptr(tcg_fpstatus
);
4814 tcg_temp_free_i32(tcg_shift
);
4817 /* C3.6.29 Floating point <-> fixed point conversions
4818 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4819 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4820 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4821 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4823 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4825 int rd
= extract32(insn
, 0, 5);
4826 int rn
= extract32(insn
, 5, 5);
4827 int scale
= extract32(insn
, 10, 6);
4828 int opcode
= extract32(insn
, 16, 3);
4829 int rmode
= extract32(insn
, 19, 2);
4830 int type
= extract32(insn
, 22, 2);
4831 bool sbit
= extract32(insn
, 29, 1);
4832 bool sf
= extract32(insn
, 31, 1);
4835 if (sbit
|| (type
> 1)
4836 || (!sf
&& scale
< 32)) {
4837 unallocated_encoding(s
);
4841 switch ((rmode
<< 3) | opcode
) {
4842 case 0x2: /* SCVTF */
4843 case 0x3: /* UCVTF */
4846 case 0x18: /* FCVTZS */
4847 case 0x19: /* FCVTZU */
4851 unallocated_encoding(s
);
4855 if (!fp_access_check(s
)) {
4859 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4862 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4864 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4865 * without conversion.
4869 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4875 TCGv_i64 tmp
= tcg_temp_new_i64();
4876 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4877 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4878 tcg_gen_movi_i64(tmp
, 0);
4879 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4880 tcg_temp_free_i64(tmp
);
4886 TCGv_i64 tmp
= tcg_const_i64(0);
4887 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4888 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4889 tcg_temp_free_i64(tmp
);
4893 /* 64 bit to top half. */
4894 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4898 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4903 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
4907 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
4910 /* 64 bits from top half */
4911 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
4917 /* C3.6.30 Floating point <-> integer conversions
4918 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4919 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4920 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4921 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4923 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4925 int rd
= extract32(insn
, 0, 5);
4926 int rn
= extract32(insn
, 5, 5);
4927 int opcode
= extract32(insn
, 16, 3);
4928 int rmode
= extract32(insn
, 19, 2);
4929 int type
= extract32(insn
, 22, 2);
4930 bool sbit
= extract32(insn
, 29, 1);
4931 bool sf
= extract32(insn
, 31, 1);
4934 unallocated_encoding(s
);
4940 bool itof
= opcode
& 1;
4943 unallocated_encoding(s
);
4947 switch (sf
<< 3 | type
<< 1 | rmode
) {
4948 case 0x0: /* 32 bit */
4949 case 0xa: /* 64 bit */
4950 case 0xd: /* 64 bit to top half of quad */
4953 /* all other sf/type/rmode combinations are invalid */
4954 unallocated_encoding(s
);
4958 if (!fp_access_check(s
)) {
4961 handle_fmov(s
, rd
, rn
, type
, itof
);
4963 /* actual FP conversions */
4964 bool itof
= extract32(opcode
, 1, 1);
4966 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
4967 unallocated_encoding(s
);
4971 if (!fp_access_check(s
)) {
4974 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
4978 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
4979 * 31 30 29 28 25 24 0
4980 * +---+---+---+---------+-----------------------------+
4981 * | | 0 | | 1 1 1 1 | |
4982 * +---+---+---+---------+-----------------------------+
4984 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
4986 if (extract32(insn
, 24, 1)) {
4987 /* Floating point data-processing (3 source) */
4988 disas_fp_3src(s
, insn
);
4989 } else if (extract32(insn
, 21, 1) == 0) {
4990 /* Floating point to fixed point conversions */
4991 disas_fp_fixed_conv(s
, insn
);
4993 switch (extract32(insn
, 10, 2)) {
4995 /* Floating point conditional compare */
4996 disas_fp_ccomp(s
, insn
);
4999 /* Floating point data-processing (2 source) */
5000 disas_fp_2src(s
, insn
);
5003 /* Floating point conditional select */
5004 disas_fp_csel(s
, insn
);
5007 switch (ctz32(extract32(insn
, 12, 4))) {
5008 case 0: /* [15:12] == xxx1 */
5009 /* Floating point immediate */
5010 disas_fp_imm(s
, insn
);
5012 case 1: /* [15:12] == xx10 */
5013 /* Floating point compare */
5014 disas_fp_compare(s
, insn
);
5016 case 2: /* [15:12] == x100 */
5017 /* Floating point data-processing (1 source) */
5018 disas_fp_1src(s
, insn
);
5020 case 3: /* [15:12] == 1000 */
5021 unallocated_encoding(s
);
5023 default: /* [15:12] == 0000 */
5024 /* Floating point <-> integer conversions */
5025 disas_fp_int_conv(s
, insn
);
5033 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5036 /* Extract 64 bits from the middle of two concatenated 64 bit
5037 * vector register slices left:right. The extracted bits start
5038 * at 'pos' bits into the right (least significant) side.
5039 * We return the result in tcg_right, and guarantee not to
5042 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5043 assert(pos
> 0 && pos
< 64);
5045 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5046 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5047 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5049 tcg_temp_free_i64(tcg_tmp
);
5053 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5054 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5055 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5056 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5058 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5060 int is_q
= extract32(insn
, 30, 1);
5061 int op2
= extract32(insn
, 22, 2);
5062 int imm4
= extract32(insn
, 11, 4);
5063 int rm
= extract32(insn
, 16, 5);
5064 int rn
= extract32(insn
, 5, 5);
5065 int rd
= extract32(insn
, 0, 5);
5066 int pos
= imm4
<< 3;
5067 TCGv_i64 tcg_resl
, tcg_resh
;
5069 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5070 unallocated_encoding(s
);
5074 if (!fp_access_check(s
)) {
5078 tcg_resh
= tcg_temp_new_i64();
5079 tcg_resl
= tcg_temp_new_i64();
5081 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5082 * either extracting 128 bits from a 128:128 concatenation, or
5083 * extracting 64 bits from a 64:64 concatenation.
5086 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5088 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5089 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5091 tcg_gen_movi_i64(tcg_resh
, 0);
5098 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5099 EltPosns
*elt
= eltposns
;
5106 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5108 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5111 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5112 tcg_hh
= tcg_temp_new_i64();
5113 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5114 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5115 tcg_temp_free_i64(tcg_hh
);
5119 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5120 tcg_temp_free_i64(tcg_resl
);
5121 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5122 tcg_temp_free_i64(tcg_resh
);
5126 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5127 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5128 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5129 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5131 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5133 int op2
= extract32(insn
, 22, 2);
5134 int is_q
= extract32(insn
, 30, 1);
5135 int rm
= extract32(insn
, 16, 5);
5136 int rn
= extract32(insn
, 5, 5);
5137 int rd
= extract32(insn
, 0, 5);
5138 int is_tblx
= extract32(insn
, 12, 1);
5139 int len
= extract32(insn
, 13, 2);
5140 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5141 TCGv_i32 tcg_regno
, tcg_numregs
;
5144 unallocated_encoding(s
);
5148 if (!fp_access_check(s
)) {
5152 /* This does a table lookup: for every byte element in the input
5153 * we index into a table formed from up to four vector registers,
5154 * and then the output is the result of the lookups. Our helper
5155 * function does the lookup operation for a single 64 bit part of
5158 tcg_resl
= tcg_temp_new_i64();
5159 tcg_resh
= tcg_temp_new_i64();
5162 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5164 tcg_gen_movi_i64(tcg_resl
, 0);
5166 if (is_tblx
&& is_q
) {
5167 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5169 tcg_gen_movi_i64(tcg_resh
, 0);
5172 tcg_idx
= tcg_temp_new_i64();
5173 tcg_regno
= tcg_const_i32(rn
);
5174 tcg_numregs
= tcg_const_i32(len
+ 1);
5175 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5176 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5177 tcg_regno
, tcg_numregs
);
5179 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5180 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5181 tcg_regno
, tcg_numregs
);
5183 tcg_temp_free_i64(tcg_idx
);
5184 tcg_temp_free_i32(tcg_regno
);
5185 tcg_temp_free_i32(tcg_numregs
);
5187 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5188 tcg_temp_free_i64(tcg_resl
);
5189 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5190 tcg_temp_free_i64(tcg_resh
);
5193 /* C3.6.3 ZIP/UZP/TRN
5194 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5195 * +---+---+-------------+------+---+------+---+------------------+------+
5196 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5197 * +---+---+-------------+------+---+------+---+------------------+------+
5199 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5201 int rd
= extract32(insn
, 0, 5);
5202 int rn
= extract32(insn
, 5, 5);
5203 int rm
= extract32(insn
, 16, 5);
5204 int size
= extract32(insn
, 22, 2);
5205 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5206 * bit 2 indicates 1 vs 2 variant of the insn.
5208 int opcode
= extract32(insn
, 12, 2);
5209 bool part
= extract32(insn
, 14, 1);
5210 bool is_q
= extract32(insn
, 30, 1);
5211 int esize
= 8 << size
;
5213 int datasize
= is_q
? 128 : 64;
5214 int elements
= datasize
/ esize
;
5215 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5217 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5218 unallocated_encoding(s
);
5222 if (!fp_access_check(s
)) {
5226 tcg_resl
= tcg_const_i64(0);
5227 tcg_resh
= tcg_const_i64(0);
5228 tcg_res
= tcg_temp_new_i64();
5230 for (i
= 0; i
< elements
; i
++) {
5232 case 1: /* UZP1/2 */
5234 int midpoint
= elements
/ 2;
5236 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5238 read_vec_element(s
, tcg_res
, rm
,
5239 2 * (i
- midpoint
) + part
, size
);
5243 case 2: /* TRN1/2 */
5245 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5247 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5250 case 3: /* ZIP1/2 */
5252 int base
= part
* elements
/ 2;
5254 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5256 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5261 g_assert_not_reached();
5266 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5267 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5269 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5270 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5274 tcg_temp_free_i64(tcg_res
);
5276 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5277 tcg_temp_free_i64(tcg_resl
);
5278 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5279 tcg_temp_free_i64(tcg_resh
);
5282 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5283 int opc
, bool is_min
, TCGv_ptr fpst
)
5285 /* Helper function for disas_simd_across_lanes: do a single precision
5286 * min/max operation on the specified two inputs,
5287 * and return the result in tcg_elt1.
5291 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5293 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5298 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5300 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5305 /* C3.6.4 AdvSIMD across lanes
5306 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5307 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5308 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5309 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5311 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5313 int rd
= extract32(insn
, 0, 5);
5314 int rn
= extract32(insn
, 5, 5);
5315 int size
= extract32(insn
, 22, 2);
5316 int opcode
= extract32(insn
, 12, 5);
5317 bool is_q
= extract32(insn
, 30, 1);
5318 bool is_u
= extract32(insn
, 29, 1);
5320 bool is_min
= false;
5324 TCGv_i64 tcg_res
, tcg_elt
;
5327 case 0x1b: /* ADDV */
5329 unallocated_encoding(s
);
5333 case 0x3: /* SADDLV, UADDLV */
5334 case 0xa: /* SMAXV, UMAXV */
5335 case 0x1a: /* SMINV, UMINV */
5336 if (size
== 3 || (size
== 2 && !is_q
)) {
5337 unallocated_encoding(s
);
5341 case 0xc: /* FMAXNMV, FMINNMV */
5342 case 0xf: /* FMAXV, FMINV */
5343 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5344 unallocated_encoding(s
);
5347 /* Bit 1 of size field encodes min vs max, and actual size is always
5348 * 32 bits: adjust the size variable so following code can rely on it
5350 is_min
= extract32(size
, 1, 1);
5355 unallocated_encoding(s
);
5359 if (!fp_access_check(s
)) {
5364 elements
= (is_q
? 128 : 64) / esize
;
5366 tcg_res
= tcg_temp_new_i64();
5367 tcg_elt
= tcg_temp_new_i64();
5369 /* These instructions operate across all lanes of a vector
5370 * to produce a single result. We can guarantee that a 64
5371 * bit intermediate is sufficient:
5372 * + for [US]ADDLV the maximum element size is 32 bits, and
5373 * the result type is 64 bits
5374 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5375 * same as the element size, which is 32 bits at most
5376 * For the integer operations we can choose to work at 64
5377 * or 32 bits and truncate at the end; for simplicity
5378 * we use 64 bits always. The floating point
5379 * ops do require 32 bit intermediates, though.
5382 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5384 for (i
= 1; i
< elements
; i
++) {
5385 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5388 case 0x03: /* SADDLV / UADDLV */
5389 case 0x1b: /* ADDV */
5390 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5392 case 0x0a: /* SMAXV / UMAXV */
5393 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5395 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5397 case 0x1a: /* SMINV / UMINV */
5398 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5400 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5404 g_assert_not_reached();
5409 /* Floating point ops which work on 32 bit (single) intermediates.
5410 * Note that correct NaN propagation requires that we do these
5411 * operations in exactly the order specified by the pseudocode.
5413 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5414 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5415 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5416 TCGv_ptr fpst
= get_fpstatus_ptr();
5418 assert(esize
== 32);
5419 assert(elements
== 4);
5421 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5422 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5423 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5424 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5426 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5428 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5429 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5430 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5431 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5433 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5435 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5437 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5438 tcg_temp_free_i32(tcg_elt1
);
5439 tcg_temp_free_i32(tcg_elt2
);
5440 tcg_temp_free_i32(tcg_elt3
);
5441 tcg_temp_free_ptr(fpst
);
5444 tcg_temp_free_i64(tcg_elt
);
5446 /* Now truncate the result to the width required for the final output */
5447 if (opcode
== 0x03) {
5448 /* SADDLV, UADDLV: result is 2*esize */
5454 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5457 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5460 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5465 g_assert_not_reached();
5468 write_fp_dreg(s
, rd
, tcg_res
);
5469 tcg_temp_free_i64(tcg_res
);
5472 /* C6.3.31 DUP (Element, Vector)
5474 * 31 30 29 21 20 16 15 10 9 5 4 0
5475 * +---+---+-------------------+--------+-------------+------+------+
5476 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5477 * +---+---+-------------------+--------+-------------+------+------+
5479 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5481 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5484 int size
= ctz32(imm5
);
5485 int esize
= 8 << size
;
5486 int elements
= (is_q
? 128 : 64) / esize
;
5490 if (size
> 3 || (size
== 3 && !is_q
)) {
5491 unallocated_encoding(s
);
5495 if (!fp_access_check(s
)) {
5499 index
= imm5
>> (size
+ 1);
5501 tmp
= tcg_temp_new_i64();
5502 read_vec_element(s
, tmp
, rn
, index
, size
);
5504 for (i
= 0; i
< elements
; i
++) {
5505 write_vec_element(s
, tmp
, rd
, i
, size
);
5509 clear_vec_high(s
, rd
);
5512 tcg_temp_free_i64(tmp
);
5515 /* C6.3.31 DUP (element, scalar)
5516 * 31 21 20 16 15 10 9 5 4 0
5517 * +-----------------------+--------+-------------+------+------+
5518 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5519 * +-----------------------+--------+-------------+------+------+
5521 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5524 int size
= ctz32(imm5
);
5529 unallocated_encoding(s
);
5533 if (!fp_access_check(s
)) {
5537 index
= imm5
>> (size
+ 1);
5539 /* This instruction just extracts the specified element and
5540 * zero-extends it into the bottom of the destination register.
5542 tmp
= tcg_temp_new_i64();
5543 read_vec_element(s
, tmp
, rn
, index
, size
);
5544 write_fp_dreg(s
, rd
, tmp
);
5545 tcg_temp_free_i64(tmp
);
5548 /* C6.3.32 DUP (General)
5550 * 31 30 29 21 20 16 15 10 9 5 4 0
5551 * +---+---+-------------------+--------+-------------+------+------+
5552 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5553 * +---+---+-------------------+--------+-------------+------+------+
5555 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5557 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5560 int size
= ctz32(imm5
);
5561 int esize
= 8 << size
;
5562 int elements
= (is_q
? 128 : 64)/esize
;
5565 if (size
> 3 || ((size
== 3) && !is_q
)) {
5566 unallocated_encoding(s
);
5570 if (!fp_access_check(s
)) {
5574 for (i
= 0; i
< elements
; i
++) {
5575 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5578 clear_vec_high(s
, rd
);
5582 /* C6.3.150 INS (Element)
5584 * 31 21 20 16 15 14 11 10 9 5 4 0
5585 * +-----------------------+--------+------------+---+------+------+
5586 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5587 * +-----------------------+--------+------------+---+------+------+
5589 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5590 * index: encoded in imm5<4:size+1>
5592 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5595 int size
= ctz32(imm5
);
5596 int src_index
, dst_index
;
5600 unallocated_encoding(s
);
5604 if (!fp_access_check(s
)) {
5608 dst_index
= extract32(imm5
, 1+size
, 5);
5609 src_index
= extract32(imm4
, size
, 4);
5611 tmp
= tcg_temp_new_i64();
5613 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5614 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5616 tcg_temp_free_i64(tmp
);
5620 /* C6.3.151 INS (General)
5622 * 31 21 20 16 15 10 9 5 4 0
5623 * +-----------------------+--------+-------------+------+------+
5624 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5625 * +-----------------------+--------+-------------+------+------+
5627 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5628 * index: encoded in imm5<4:size+1>
5630 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5632 int size
= ctz32(imm5
);
5636 unallocated_encoding(s
);
5640 if (!fp_access_check(s
)) {
5644 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5645 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5649 * C6.3.321 UMOV (General)
5650 * C6.3.237 SMOV (General)
5652 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5653 * +---+---+-------------------+--------+-------------+------+------+
5654 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5655 * +---+---+-------------------+--------+-------------+------+------+
5657 * U: unsigned when set
5658 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5660 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5661 int rn
, int rd
, int imm5
)
5663 int size
= ctz32(imm5
);
5667 /* Check for UnallocatedEncodings */
5669 if (size
> 2 || (size
== 2 && !is_q
)) {
5670 unallocated_encoding(s
);
5675 || (size
< 3 && is_q
)
5676 || (size
== 3 && !is_q
)) {
5677 unallocated_encoding(s
);
5682 if (!fp_access_check(s
)) {
5686 element
= extract32(imm5
, 1+size
, 4);
5688 tcg_rd
= cpu_reg(s
, rd
);
5689 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5690 if (is_signed
&& !is_q
) {
5691 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5695 /* C3.6.5 AdvSIMD copy
5696 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5697 * +---+---+----+-----------------+------+---+------+---+------+------+
5698 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5699 * +---+---+----+-----------------+------+---+------+---+------+------+
5701 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5703 int rd
= extract32(insn
, 0, 5);
5704 int rn
= extract32(insn
, 5, 5);
5705 int imm4
= extract32(insn
, 11, 4);
5706 int op
= extract32(insn
, 29, 1);
5707 int is_q
= extract32(insn
, 30, 1);
5708 int imm5
= extract32(insn
, 16, 5);
5713 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5715 unallocated_encoding(s
);
5720 /* DUP (element - vector) */
5721 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5725 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5730 handle_simd_insg(s
, rd
, rn
, imm5
);
5732 unallocated_encoding(s
);
5737 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5738 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5741 unallocated_encoding(s
);
5747 /* C3.6.6 AdvSIMD modified immediate
5748 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5749 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5750 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5751 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5753 * There are a number of operations that can be carried out here:
5754 * MOVI - move (shifted) imm into register
5755 * MVNI - move inverted (shifted) imm into register
5756 * ORR - bitwise OR of (shifted) imm with register
5757 * BIC - bitwise clear of (shifted) imm with register
5759 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5761 int rd
= extract32(insn
, 0, 5);
5762 int cmode
= extract32(insn
, 12, 4);
5763 int cmode_3_1
= extract32(cmode
, 1, 3);
5764 int cmode_0
= extract32(cmode
, 0, 1);
5765 int o2
= extract32(insn
, 11, 1);
5766 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5767 bool is_neg
= extract32(insn
, 29, 1);
5768 bool is_q
= extract32(insn
, 30, 1);
5770 TCGv_i64 tcg_rd
, tcg_imm
;
5773 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5774 unallocated_encoding(s
);
5778 if (!fp_access_check(s
)) {
5782 /* See AdvSIMDExpandImm() in ARM ARM */
5783 switch (cmode_3_1
) {
5784 case 0: /* Replicate(Zeros(24):imm8, 2) */
5785 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5786 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5787 case 3: /* Replicate(imm8:Zeros(24), 2) */
5789 int shift
= cmode_3_1
* 8;
5790 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5793 case 4: /* Replicate(Zeros(8):imm8, 4) */
5794 case 5: /* Replicate(imm8:Zeros(8), 4) */
5796 int shift
= (cmode_3_1
& 0x1) * 8;
5797 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5802 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5803 imm
= (abcdefgh
<< 16) | 0xffff;
5805 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5806 imm
= (abcdefgh
<< 8) | 0xff;
5808 imm
= bitfield_replicate(imm
, 32);
5811 if (!cmode_0
&& !is_neg
) {
5812 imm
= bitfield_replicate(abcdefgh
, 8);
5813 } else if (!cmode_0
&& is_neg
) {
5816 for (i
= 0; i
< 8; i
++) {
5817 if ((abcdefgh
) & (1 << i
)) {
5818 imm
|= 0xffULL
<< (i
* 8);
5821 } else if (cmode_0
) {
5823 imm
= (abcdefgh
& 0x3f) << 48;
5824 if (abcdefgh
& 0x80) {
5825 imm
|= 0x8000000000000000ULL
;
5827 if (abcdefgh
& 0x40) {
5828 imm
|= 0x3fc0000000000000ULL
;
5830 imm
|= 0x4000000000000000ULL
;
5833 imm
= (abcdefgh
& 0x3f) << 19;
5834 if (abcdefgh
& 0x80) {
5837 if (abcdefgh
& 0x40) {
5848 if (cmode_3_1
!= 7 && is_neg
) {
5852 tcg_imm
= tcg_const_i64(imm
);
5853 tcg_rd
= new_tmp_a64(s
);
5855 for (i
= 0; i
< 2; i
++) {
5856 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
5858 if (i
== 1 && !is_q
) {
5859 /* non-quad ops clear high half of vector */
5860 tcg_gen_movi_i64(tcg_rd
, 0);
5861 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5862 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5865 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5868 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5872 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5874 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5877 tcg_temp_free_i64(tcg_imm
);
5880 /* C3.6.7 AdvSIMD scalar copy
5881 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5882 * +-----+----+-----------------+------+---+------+---+------+------+
5883 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5884 * +-----+----+-----------------+------+---+------+---+------+------+
5886 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5888 int rd
= extract32(insn
, 0, 5);
5889 int rn
= extract32(insn
, 5, 5);
5890 int imm4
= extract32(insn
, 11, 4);
5891 int imm5
= extract32(insn
, 16, 5);
5892 int op
= extract32(insn
, 29, 1);
5894 if (op
!= 0 || imm4
!= 0) {
5895 unallocated_encoding(s
);
5899 /* DUP (element, scalar) */
5900 handle_simd_dupes(s
, rd
, rn
, imm5
);
5903 /* C3.6.8 AdvSIMD scalar pairwise
5904 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5905 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5906 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5907 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5909 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5911 int u
= extract32(insn
, 29, 1);
5912 int size
= extract32(insn
, 22, 2);
5913 int opcode
= extract32(insn
, 12, 5);
5914 int rn
= extract32(insn
, 5, 5);
5915 int rd
= extract32(insn
, 0, 5);
5918 /* For some ops (the FP ones), size[1] is part of the encoding.
5919 * For ADDP strictly it is not but size[1] is always 1 for valid
5922 opcode
|= (extract32(size
, 1, 1) << 5);
5925 case 0x3b: /* ADDP */
5926 if (u
|| size
!= 3) {
5927 unallocated_encoding(s
);
5930 if (!fp_access_check(s
)) {
5934 TCGV_UNUSED_PTR(fpst
);
5936 case 0xc: /* FMAXNMP */
5937 case 0xd: /* FADDP */
5938 case 0xf: /* FMAXP */
5939 case 0x2c: /* FMINNMP */
5940 case 0x2f: /* FMINP */
5941 /* FP op, size[0] is 32 or 64 bit */
5943 unallocated_encoding(s
);
5946 if (!fp_access_check(s
)) {
5950 size
= extract32(size
, 0, 1) ? 3 : 2;
5951 fpst
= get_fpstatus_ptr();
5954 unallocated_encoding(s
);
5959 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5960 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5961 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5963 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5964 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
5967 case 0x3b: /* ADDP */
5968 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
5970 case 0xc: /* FMAXNMP */
5971 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5973 case 0xd: /* FADDP */
5974 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5976 case 0xf: /* FMAXP */
5977 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5979 case 0x2c: /* FMINNMP */
5980 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5982 case 0x2f: /* FMINP */
5983 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5986 g_assert_not_reached();
5989 write_fp_dreg(s
, rd
, tcg_res
);
5991 tcg_temp_free_i64(tcg_op1
);
5992 tcg_temp_free_i64(tcg_op2
);
5993 tcg_temp_free_i64(tcg_res
);
5995 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
5996 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
5997 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5999 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6000 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6003 case 0xc: /* FMAXNMP */
6004 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6006 case 0xd: /* FADDP */
6007 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6009 case 0xf: /* FMAXP */
6010 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6012 case 0x2c: /* FMINNMP */
6013 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6015 case 0x2f: /* FMINP */
6016 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6019 g_assert_not_reached();
6022 write_fp_sreg(s
, rd
, tcg_res
);
6024 tcg_temp_free_i32(tcg_op1
);
6025 tcg_temp_free_i32(tcg_op2
);
6026 tcg_temp_free_i32(tcg_res
);
6029 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6030 tcg_temp_free_ptr(fpst
);
6035 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6037 * This code is handles the common shifting code and is used by both
6038 * the vector and scalar code.
6040 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6041 TCGv_i64 tcg_rnd
, bool accumulate
,
6042 bool is_u
, int size
, int shift
)
6044 bool extended_result
= false;
6045 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6047 TCGv_i64 tcg_src_hi
;
6049 if (round
&& size
== 3) {
6050 extended_result
= true;
6051 ext_lshift
= 64 - shift
;
6052 tcg_src_hi
= tcg_temp_new_i64();
6053 } else if (shift
== 64) {
6054 if (!accumulate
&& is_u
) {
6055 /* result is zero */
6056 tcg_gen_movi_i64(tcg_res
, 0);
6061 /* Deal with the rounding step */
6063 if (extended_result
) {
6064 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6066 /* take care of sign extending tcg_res */
6067 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6068 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6069 tcg_src
, tcg_src_hi
,
6072 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6076 tcg_temp_free_i64(tcg_zero
);
6078 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6082 /* Now do the shift right */
6083 if (round
&& extended_result
) {
6084 /* extended case, >64 bit precision required */
6085 if (ext_lshift
== 0) {
6086 /* special case, only high bits matter */
6087 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6089 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6090 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6091 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6096 /* essentially shifting in 64 zeros */
6097 tcg_gen_movi_i64(tcg_src
, 0);
6099 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6103 /* effectively extending the sign-bit */
6104 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6106 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6112 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6114 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6117 if (extended_result
) {
6118 tcg_temp_free_i64(tcg_src_hi
);
6122 /* Common SHL/SLI - Shift left with an optional insert */
6123 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6124 bool insert
, int shift
)
6126 if (insert
) { /* SLI */
6127 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6129 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6133 /* SRI: shift right with insert */
6134 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6135 int size
, int shift
)
6137 int esize
= 8 << size
;
6139 /* shift count same as element size is valid but does nothing;
6140 * special case to avoid potential shift by 64.
6142 if (shift
!= esize
) {
6143 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6144 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6148 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6149 static void handle_scalar_simd_shri(DisasContext
*s
,
6150 bool is_u
, int immh
, int immb
,
6151 int opcode
, int rn
, int rd
)
6154 int immhb
= immh
<< 3 | immb
;
6155 int shift
= 2 * (8 << size
) - immhb
;
6156 bool accumulate
= false;
6158 bool insert
= false;
6163 if (!extract32(immh
, 3, 1)) {
6164 unallocated_encoding(s
);
6168 if (!fp_access_check(s
)) {
6173 case 0x02: /* SSRA / USRA (accumulate) */
6176 case 0x04: /* SRSHR / URSHR (rounding) */
6179 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6180 accumulate
= round
= true;
6182 case 0x08: /* SRI */
6188 uint64_t round_const
= 1ULL << (shift
- 1);
6189 tcg_round
= tcg_const_i64(round_const
);
6191 TCGV_UNUSED_I64(tcg_round
);
6194 tcg_rn
= read_fp_dreg(s
, rn
);
6195 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6198 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6200 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6201 accumulate
, is_u
, size
, shift
);
6204 write_fp_dreg(s
, rd
, tcg_rd
);
6206 tcg_temp_free_i64(tcg_rn
);
6207 tcg_temp_free_i64(tcg_rd
);
6209 tcg_temp_free_i64(tcg_round
);
6213 /* SHL/SLI - Scalar shift left */
6214 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6215 int immh
, int immb
, int opcode
,
6218 int size
= 32 - clz32(immh
) - 1;
6219 int immhb
= immh
<< 3 | immb
;
6220 int shift
= immhb
- (8 << size
);
6221 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6222 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6224 if (!extract32(immh
, 3, 1)) {
6225 unallocated_encoding(s
);
6229 if (!fp_access_check(s
)) {
6233 tcg_rn
= read_fp_dreg(s
, rn
);
6234 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6236 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6238 write_fp_dreg(s
, rd
, tcg_rd
);
6240 tcg_temp_free_i64(tcg_rn
);
6241 tcg_temp_free_i64(tcg_rd
);
6244 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6245 * (signed/unsigned) narrowing */
6246 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6247 bool is_u_shift
, bool is_u_narrow
,
6248 int immh
, int immb
, int opcode
,
6251 int immhb
= immh
<< 3 | immb
;
6252 int size
= 32 - clz32(immh
) - 1;
6253 int esize
= 8 << size
;
6254 int shift
= (2 * esize
) - immhb
;
6255 int elements
= is_scalar
? 1 : (64 / esize
);
6256 bool round
= extract32(opcode
, 0, 1);
6257 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6258 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6259 TCGv_i32 tcg_rd_narrowed
;
6262 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6263 { gen_helper_neon_narrow_sat_s8
,
6264 gen_helper_neon_unarrow_sat8
},
6265 { gen_helper_neon_narrow_sat_s16
,
6266 gen_helper_neon_unarrow_sat16
},
6267 { gen_helper_neon_narrow_sat_s32
,
6268 gen_helper_neon_unarrow_sat32
},
6271 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6272 gen_helper_neon_narrow_sat_u8
,
6273 gen_helper_neon_narrow_sat_u16
,
6274 gen_helper_neon_narrow_sat_u32
,
6277 NeonGenNarrowEnvFn
*narrowfn
;
6283 if (extract32(immh
, 3, 1)) {
6284 unallocated_encoding(s
);
6288 if (!fp_access_check(s
)) {
6293 narrowfn
= unsigned_narrow_fns
[size
];
6295 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6298 tcg_rn
= tcg_temp_new_i64();
6299 tcg_rd
= tcg_temp_new_i64();
6300 tcg_rd_narrowed
= tcg_temp_new_i32();
6301 tcg_final
= tcg_const_i64(0);
6304 uint64_t round_const
= 1ULL << (shift
- 1);
6305 tcg_round
= tcg_const_i64(round_const
);
6307 TCGV_UNUSED_I64(tcg_round
);
6310 for (i
= 0; i
< elements
; i
++) {
6311 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6312 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6313 false, is_u_shift
, size
+1, shift
);
6314 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6315 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6316 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6320 clear_vec_high(s
, rd
);
6321 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6323 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6327 tcg_temp_free_i64(tcg_round
);
6329 tcg_temp_free_i64(tcg_rn
);
6330 tcg_temp_free_i64(tcg_rd
);
6331 tcg_temp_free_i32(tcg_rd_narrowed
);
6332 tcg_temp_free_i64(tcg_final
);
6336 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6337 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6338 bool src_unsigned
, bool dst_unsigned
,
6339 int immh
, int immb
, int rn
, int rd
)
6341 int immhb
= immh
<< 3 | immb
;
6342 int size
= 32 - clz32(immh
) - 1;
6343 int shift
= immhb
- (8 << size
);
6347 assert(!(scalar
&& is_q
));
6350 if (!is_q
&& extract32(immh
, 3, 1)) {
6351 unallocated_encoding(s
);
6355 /* Since we use the variable-shift helpers we must
6356 * replicate the shift count into each element of
6357 * the tcg_shift value.
6361 shift
|= shift
<< 8;
6364 shift
|= shift
<< 16;
6370 g_assert_not_reached();
6374 if (!fp_access_check(s
)) {
6379 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6380 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6381 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6382 { NULL
, gen_helper_neon_qshl_u64
},
6384 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6385 int maxpass
= is_q
? 2 : 1;
6387 for (pass
= 0; pass
< maxpass
; pass
++) {
6388 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6390 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6391 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6392 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6394 tcg_temp_free_i64(tcg_op
);
6396 tcg_temp_free_i64(tcg_shift
);
6399 clear_vec_high(s
, rd
);
6402 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6403 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6405 { gen_helper_neon_qshl_s8
,
6406 gen_helper_neon_qshl_s16
,
6407 gen_helper_neon_qshl_s32
},
6408 { gen_helper_neon_qshlu_s8
,
6409 gen_helper_neon_qshlu_s16
,
6410 gen_helper_neon_qshlu_s32
}
6412 { NULL
, NULL
, NULL
},
6413 { gen_helper_neon_qshl_u8
,
6414 gen_helper_neon_qshl_u16
,
6415 gen_helper_neon_qshl_u32
}
6418 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6419 TCGMemOp memop
= scalar
? size
: MO_32
;
6420 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6422 for (pass
= 0; pass
< maxpass
; pass
++) {
6423 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6425 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6426 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6430 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6433 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6438 g_assert_not_reached();
6440 write_fp_sreg(s
, rd
, tcg_op
);
6442 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6445 tcg_temp_free_i32(tcg_op
);
6447 tcg_temp_free_i32(tcg_shift
);
6449 if (!is_q
&& !scalar
) {
6450 clear_vec_high(s
, rd
);
6455 /* Common vector code for handling integer to FP conversion */
6456 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6457 int elements
, int is_signed
,
6458 int fracbits
, int size
)
6460 bool is_double
= size
== 3 ? true : false;
6461 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6462 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6463 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6464 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6467 for (pass
= 0; pass
< elements
; pass
++) {
6468 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6471 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6473 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6474 tcg_shift
, tcg_fpst
);
6476 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6477 tcg_shift
, tcg_fpst
);
6479 if (elements
== 1) {
6480 write_fp_dreg(s
, rd
, tcg_double
);
6482 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6484 tcg_temp_free_i64(tcg_double
);
6486 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6488 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6489 tcg_shift
, tcg_fpst
);
6491 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6492 tcg_shift
, tcg_fpst
);
6494 if (elements
== 1) {
6495 write_fp_sreg(s
, rd
, tcg_single
);
6497 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6499 tcg_temp_free_i32(tcg_single
);
6503 if (!is_double
&& elements
== 2) {
6504 clear_vec_high(s
, rd
);
6507 tcg_temp_free_i64(tcg_int
);
6508 tcg_temp_free_ptr(tcg_fpst
);
6509 tcg_temp_free_i32(tcg_shift
);
6512 /* UCVTF/SCVTF - Integer to FP conversion */
6513 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6514 bool is_q
, bool is_u
,
6515 int immh
, int immb
, int opcode
,
6518 bool is_double
= extract32(immh
, 3, 1);
6519 int size
= is_double
? MO_64
: MO_32
;
6521 int immhb
= immh
<< 3 | immb
;
6522 int fracbits
= (is_double
? 128 : 64) - immhb
;
6524 if (!extract32(immh
, 2, 2)) {
6525 unallocated_encoding(s
);
6532 elements
= is_double
? 2 : is_q
? 4 : 2;
6533 if (is_double
&& !is_q
) {
6534 unallocated_encoding(s
);
6539 if (!fp_access_check(s
)) {
6543 /* immh == 0 would be a failure of the decode logic */
6546 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6549 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6550 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6551 bool is_q
, bool is_u
,
6552 int immh
, int immb
, int rn
, int rd
)
6554 bool is_double
= extract32(immh
, 3, 1);
6555 int immhb
= immh
<< 3 | immb
;
6556 int fracbits
= (is_double
? 128 : 64) - immhb
;
6558 TCGv_ptr tcg_fpstatus
;
6559 TCGv_i32 tcg_rmode
, tcg_shift
;
6561 if (!extract32(immh
, 2, 2)) {
6562 unallocated_encoding(s
);
6566 if (!is_scalar
&& !is_q
&& is_double
) {
6567 unallocated_encoding(s
);
6571 if (!fp_access_check(s
)) {
6575 assert(!(is_scalar
&& is_q
));
6577 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6578 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6579 tcg_fpstatus
= get_fpstatus_ptr();
6580 tcg_shift
= tcg_const_i32(fracbits
);
6583 int maxpass
= is_scalar
? 1 : 2;
6585 for (pass
= 0; pass
< maxpass
; pass
++) {
6586 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6588 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6590 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6592 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6594 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6595 tcg_temp_free_i64(tcg_op
);
6598 clear_vec_high(s
, rd
);
6601 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6602 for (pass
= 0; pass
< maxpass
; pass
++) {
6603 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6605 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6607 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6609 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6612 write_fp_sreg(s
, rd
, tcg_op
);
6614 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6616 tcg_temp_free_i32(tcg_op
);
6618 if (!is_q
&& !is_scalar
) {
6619 clear_vec_high(s
, rd
);
6623 tcg_temp_free_ptr(tcg_fpstatus
);
6624 tcg_temp_free_i32(tcg_shift
);
6625 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6626 tcg_temp_free_i32(tcg_rmode
);
6629 /* C3.6.9 AdvSIMD scalar shift by immediate
6630 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6631 * +-----+---+-------------+------+------+--------+---+------+------+
6632 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6633 * +-----+---+-------------+------+------+--------+---+------+------+
6635 * This is the scalar version so it works on a fixed sized registers
6637 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6639 int rd
= extract32(insn
, 0, 5);
6640 int rn
= extract32(insn
, 5, 5);
6641 int opcode
= extract32(insn
, 11, 5);
6642 int immb
= extract32(insn
, 16, 3);
6643 int immh
= extract32(insn
, 19, 4);
6644 bool is_u
= extract32(insn
, 29, 1);
6647 unallocated_encoding(s
);
6652 case 0x08: /* SRI */
6654 unallocated_encoding(s
);
6658 case 0x00: /* SSHR / USHR */
6659 case 0x02: /* SSRA / USRA */
6660 case 0x04: /* SRSHR / URSHR */
6661 case 0x06: /* SRSRA / URSRA */
6662 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6664 case 0x0a: /* SHL / SLI */
6665 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6667 case 0x1c: /* SCVTF, UCVTF */
6668 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6671 case 0x10: /* SQSHRUN, SQSHRUN2 */
6672 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6674 unallocated_encoding(s
);
6677 handle_vec_simd_sqshrn(s
, true, false, false, true,
6678 immh
, immb
, opcode
, rn
, rd
);
6680 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6681 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6682 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6683 immh
, immb
, opcode
, rn
, rd
);
6685 case 0xc: /* SQSHLU */
6687 unallocated_encoding(s
);
6690 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6692 case 0xe: /* SQSHL, UQSHL */
6693 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6695 case 0x1f: /* FCVTZS, FCVTZU */
6696 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6699 unallocated_encoding(s
);
6704 /* C3.6.10 AdvSIMD scalar three different
6705 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6706 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6707 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6708 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6710 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6712 bool is_u
= extract32(insn
, 29, 1);
6713 int size
= extract32(insn
, 22, 2);
6714 int opcode
= extract32(insn
, 12, 4);
6715 int rm
= extract32(insn
, 16, 5);
6716 int rn
= extract32(insn
, 5, 5);
6717 int rd
= extract32(insn
, 0, 5);
6720 unallocated_encoding(s
);
6725 case 0x9: /* SQDMLAL, SQDMLAL2 */
6726 case 0xb: /* SQDMLSL, SQDMLSL2 */
6727 case 0xd: /* SQDMULL, SQDMULL2 */
6728 if (size
== 0 || size
== 3) {
6729 unallocated_encoding(s
);
6734 unallocated_encoding(s
);
6738 if (!fp_access_check(s
)) {
6743 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6744 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6745 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6747 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6748 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6750 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6751 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6754 case 0xd: /* SQDMULL, SQDMULL2 */
6756 case 0xb: /* SQDMLSL, SQDMLSL2 */
6757 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6759 case 0x9: /* SQDMLAL, SQDMLAL2 */
6760 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6761 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6765 g_assert_not_reached();
6768 write_fp_dreg(s
, rd
, tcg_res
);
6770 tcg_temp_free_i64(tcg_op1
);
6771 tcg_temp_free_i64(tcg_op2
);
6772 tcg_temp_free_i64(tcg_res
);
6774 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6775 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6776 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6778 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6779 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6781 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6782 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6785 case 0xd: /* SQDMULL, SQDMULL2 */
6787 case 0xb: /* SQDMLSL, SQDMLSL2 */
6788 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6790 case 0x9: /* SQDMLAL, SQDMLAL2 */
6792 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6793 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6794 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6796 tcg_temp_free_i64(tcg_op3
);
6800 g_assert_not_reached();
6803 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6804 write_fp_dreg(s
, rd
, tcg_res
);
6806 tcg_temp_free_i32(tcg_op1
);
6807 tcg_temp_free_i32(tcg_op2
);
6808 tcg_temp_free_i64(tcg_res
);
6812 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6813 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6815 /* Handle 64x64->64 opcodes which are shared between the scalar
6816 * and vector 3-same groups. We cover every opcode where size == 3
6817 * is valid in either the three-reg-same (integer, not pairwise)
6818 * or scalar-three-reg-same groups. (Some opcodes are not yet
6824 case 0x1: /* SQADD */
6826 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6828 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6831 case 0x5: /* SQSUB */
6833 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6835 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6838 case 0x6: /* CMGT, CMHI */
6839 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6840 * We implement this using setcond (test) and then negating.
6842 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6844 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6845 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6847 case 0x7: /* CMGE, CMHS */
6848 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6850 case 0x11: /* CMTST, CMEQ */
6855 /* CMTST : test is "if (X & Y != 0)". */
6856 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6857 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6858 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6860 case 0x8: /* SSHL, USHL */
6862 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6864 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6867 case 0x9: /* SQSHL, UQSHL */
6869 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6871 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6874 case 0xa: /* SRSHL, URSHL */
6876 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6878 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6881 case 0xb: /* SQRSHL, UQRSHL */
6883 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6885 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6888 case 0x10: /* ADD, SUB */
6890 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6892 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6896 g_assert_not_reached();
6900 /* Handle the 3-same-operands float operations; shared by the scalar
6901 * and vector encodings. The caller must filter out any encodings
6902 * not allocated for the encoding it is dealing with.
6904 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6905 int fpopcode
, int rd
, int rn
, int rm
)
6908 TCGv_ptr fpst
= get_fpstatus_ptr();
6910 for (pass
= 0; pass
< elements
; pass
++) {
6913 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6914 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6915 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6917 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6918 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6921 case 0x39: /* FMLS */
6922 /* As usual for ARM, separate negation for fused multiply-add */
6923 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6925 case 0x19: /* FMLA */
6926 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6927 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6930 case 0x18: /* FMAXNM */
6931 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6933 case 0x1a: /* FADD */
6934 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6936 case 0x1b: /* FMULX */
6937 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6939 case 0x1c: /* FCMEQ */
6940 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6942 case 0x1e: /* FMAX */
6943 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6945 case 0x1f: /* FRECPS */
6946 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6948 case 0x38: /* FMINNM */
6949 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6951 case 0x3a: /* FSUB */
6952 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6954 case 0x3e: /* FMIN */
6955 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6957 case 0x3f: /* FRSQRTS */
6958 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6960 case 0x5b: /* FMUL */
6961 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6963 case 0x5c: /* FCMGE */
6964 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6966 case 0x5d: /* FACGE */
6967 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6969 case 0x5f: /* FDIV */
6970 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6972 case 0x7a: /* FABD */
6973 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6974 gen_helper_vfp_absd(tcg_res
, tcg_res
);
6976 case 0x7c: /* FCMGT */
6977 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6979 case 0x7d: /* FACGT */
6980 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6983 g_assert_not_reached();
6986 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6988 tcg_temp_free_i64(tcg_res
);
6989 tcg_temp_free_i64(tcg_op1
);
6990 tcg_temp_free_i64(tcg_op2
);
6993 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6994 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6995 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6997 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
6998 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7001 case 0x39: /* FMLS */
7002 /* As usual for ARM, separate negation for fused multiply-add */
7003 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7005 case 0x19: /* FMLA */
7006 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7007 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7010 case 0x1a: /* FADD */
7011 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7013 case 0x1b: /* FMULX */
7014 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7016 case 0x1c: /* FCMEQ */
7017 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7019 case 0x1e: /* FMAX */
7020 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7022 case 0x1f: /* FRECPS */
7023 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7025 case 0x18: /* FMAXNM */
7026 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7028 case 0x38: /* FMINNM */
7029 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7031 case 0x3a: /* FSUB */
7032 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7034 case 0x3e: /* FMIN */
7035 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7037 case 0x3f: /* FRSQRTS */
7038 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7040 case 0x5b: /* FMUL */
7041 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7043 case 0x5c: /* FCMGE */
7044 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7046 case 0x5d: /* FACGE */
7047 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7049 case 0x5f: /* FDIV */
7050 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7052 case 0x7a: /* FABD */
7053 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7054 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7056 case 0x7c: /* FCMGT */
7057 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7059 case 0x7d: /* FACGT */
7060 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7063 g_assert_not_reached();
7066 if (elements
== 1) {
7067 /* scalar single so clear high part */
7068 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7070 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7071 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7072 tcg_temp_free_i64(tcg_tmp
);
7074 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7077 tcg_temp_free_i32(tcg_res
);
7078 tcg_temp_free_i32(tcg_op1
);
7079 tcg_temp_free_i32(tcg_op2
);
7083 tcg_temp_free_ptr(fpst
);
7085 if ((elements
<< size
) < 4) {
7086 /* scalar, or non-quad vector op */
7087 clear_vec_high(s
, rd
);
7091 /* C3.6.11 AdvSIMD scalar three same
7092 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7093 * +-----+---+-----------+------+---+------+--------+---+------+------+
7094 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7095 * +-----+---+-----------+------+---+------+--------+---+------+------+
7097 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7099 int rd
= extract32(insn
, 0, 5);
7100 int rn
= extract32(insn
, 5, 5);
7101 int opcode
= extract32(insn
, 11, 5);
7102 int rm
= extract32(insn
, 16, 5);
7103 int size
= extract32(insn
, 22, 2);
7104 bool u
= extract32(insn
, 29, 1);
7107 if (opcode
>= 0x18) {
7108 /* Floating point: U, size[1] and opcode indicate operation */
7109 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7111 case 0x1b: /* FMULX */
7112 case 0x1f: /* FRECPS */
7113 case 0x3f: /* FRSQRTS */
7114 case 0x5d: /* FACGE */
7115 case 0x7d: /* FACGT */
7116 case 0x1c: /* FCMEQ */
7117 case 0x5c: /* FCMGE */
7118 case 0x7c: /* FCMGT */
7119 case 0x7a: /* FABD */
7122 unallocated_encoding(s
);
7126 if (!fp_access_check(s
)) {
7130 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7135 case 0x1: /* SQADD, UQADD */
7136 case 0x5: /* SQSUB, UQSUB */
7137 case 0x9: /* SQSHL, UQSHL */
7138 case 0xb: /* SQRSHL, UQRSHL */
7140 case 0x8: /* SSHL, USHL */
7141 case 0xa: /* SRSHL, URSHL */
7142 case 0x6: /* CMGT, CMHI */
7143 case 0x7: /* CMGE, CMHS */
7144 case 0x11: /* CMTST, CMEQ */
7145 case 0x10: /* ADD, SUB (vector) */
7147 unallocated_encoding(s
);
7151 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7152 if (size
!= 1 && size
!= 2) {
7153 unallocated_encoding(s
);
7158 unallocated_encoding(s
);
7162 if (!fp_access_check(s
)) {
7166 tcg_rd
= tcg_temp_new_i64();
7169 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7170 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7172 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7173 tcg_temp_free_i64(tcg_rn
);
7174 tcg_temp_free_i64(tcg_rm
);
7176 /* Do a single operation on the lowest element in the vector.
7177 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7178 * no side effects for all these operations.
7179 * OPTME: special-purpose helpers would avoid doing some
7180 * unnecessary work in the helper for the 8 and 16 bit cases.
7182 NeonGenTwoOpEnvFn
*genenvfn
;
7183 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7184 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7185 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7187 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7188 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7191 case 0x1: /* SQADD, UQADD */
7193 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7194 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7195 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7196 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7198 genenvfn
= fns
[size
][u
];
7201 case 0x5: /* SQSUB, UQSUB */
7203 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7204 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7205 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7206 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7208 genenvfn
= fns
[size
][u
];
7211 case 0x9: /* SQSHL, UQSHL */
7213 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7214 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7215 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7216 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7218 genenvfn
= fns
[size
][u
];
7221 case 0xb: /* SQRSHL, UQRSHL */
7223 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7224 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7225 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7226 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7228 genenvfn
= fns
[size
][u
];
7231 case 0x16: /* SQDMULH, SQRDMULH */
7233 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7234 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7235 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7237 assert(size
== 1 || size
== 2);
7238 genenvfn
= fns
[size
- 1][u
];
7242 g_assert_not_reached();
7245 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7246 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7247 tcg_temp_free_i32(tcg_rd32
);
7248 tcg_temp_free_i32(tcg_rn
);
7249 tcg_temp_free_i32(tcg_rm
);
7252 write_fp_dreg(s
, rd
, tcg_rd
);
7254 tcg_temp_free_i64(tcg_rd
);
7257 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7258 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7259 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7261 /* Handle 64->64 opcodes which are shared between the scalar and
7262 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7263 * is valid in either group and also the double-precision fp ops.
7264 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7270 case 0x4: /* CLS, CLZ */
7272 gen_helper_clz64(tcg_rd
, tcg_rn
);
7274 gen_helper_cls64(tcg_rd
, tcg_rn
);
7278 /* This opcode is shared with CNT and RBIT but we have earlier
7279 * enforced that size == 3 if and only if this is the NOT insn.
7281 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7283 case 0x7: /* SQABS, SQNEG */
7285 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7287 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7290 case 0xa: /* CMLT */
7291 /* 64 bit integer comparison against zero, result is
7292 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7297 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7298 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7300 case 0x8: /* CMGT, CMGE */
7301 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7303 case 0x9: /* CMEQ, CMLE */
7304 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7306 case 0xb: /* ABS, NEG */
7308 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7310 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7311 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7312 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7314 tcg_temp_free_i64(tcg_zero
);
7317 case 0x2f: /* FABS */
7318 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7320 case 0x6f: /* FNEG */
7321 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7323 case 0x7f: /* FSQRT */
7324 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7326 case 0x1a: /* FCVTNS */
7327 case 0x1b: /* FCVTMS */
7328 case 0x1c: /* FCVTAS */
7329 case 0x3a: /* FCVTPS */
7330 case 0x3b: /* FCVTZS */
7332 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7333 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7334 tcg_temp_free_i32(tcg_shift
);
7337 case 0x5a: /* FCVTNU */
7338 case 0x5b: /* FCVTMU */
7339 case 0x5c: /* FCVTAU */
7340 case 0x7a: /* FCVTPU */
7341 case 0x7b: /* FCVTZU */
7343 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7344 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7345 tcg_temp_free_i32(tcg_shift
);
7348 case 0x18: /* FRINTN */
7349 case 0x19: /* FRINTM */
7350 case 0x38: /* FRINTP */
7351 case 0x39: /* FRINTZ */
7352 case 0x58: /* FRINTA */
7353 case 0x79: /* FRINTI */
7354 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7356 case 0x59: /* FRINTX */
7357 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7360 g_assert_not_reached();
7364 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7365 bool is_scalar
, bool is_u
, bool is_q
,
7366 int size
, int rn
, int rd
)
7368 bool is_double
= (size
== 3);
7371 if (!fp_access_check(s
)) {
7375 fpst
= get_fpstatus_ptr();
7378 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7379 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7380 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7381 NeonGenTwoDoubleOPFn
*genfn
;
7386 case 0x2e: /* FCMLT (zero) */
7389 case 0x2c: /* FCMGT (zero) */
7390 genfn
= gen_helper_neon_cgt_f64
;
7392 case 0x2d: /* FCMEQ (zero) */
7393 genfn
= gen_helper_neon_ceq_f64
;
7395 case 0x6d: /* FCMLE (zero) */
7398 case 0x6c: /* FCMGE (zero) */
7399 genfn
= gen_helper_neon_cge_f64
;
7402 g_assert_not_reached();
7405 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7406 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7408 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7410 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7412 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7415 clear_vec_high(s
, rd
);
7418 tcg_temp_free_i64(tcg_res
);
7419 tcg_temp_free_i64(tcg_zero
);
7420 tcg_temp_free_i64(tcg_op
);
7422 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7423 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7424 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7425 NeonGenTwoSingleOPFn
*genfn
;
7427 int pass
, maxpasses
;
7430 case 0x2e: /* FCMLT (zero) */
7433 case 0x2c: /* FCMGT (zero) */
7434 genfn
= gen_helper_neon_cgt_f32
;
7436 case 0x2d: /* FCMEQ (zero) */
7437 genfn
= gen_helper_neon_ceq_f32
;
7439 case 0x6d: /* FCMLE (zero) */
7442 case 0x6c: /* FCMGE (zero) */
7443 genfn
= gen_helper_neon_cge_f32
;
7446 g_assert_not_reached();
7452 maxpasses
= is_q
? 4 : 2;
7455 for (pass
= 0; pass
< maxpasses
; pass
++) {
7456 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7458 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7460 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7463 write_fp_sreg(s
, rd
, tcg_res
);
7465 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7468 tcg_temp_free_i32(tcg_res
);
7469 tcg_temp_free_i32(tcg_zero
);
7470 tcg_temp_free_i32(tcg_op
);
7471 if (!is_q
&& !is_scalar
) {
7472 clear_vec_high(s
, rd
);
7476 tcg_temp_free_ptr(fpst
);
7479 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7480 bool is_scalar
, bool is_u
, bool is_q
,
7481 int size
, int rn
, int rd
)
7483 bool is_double
= (size
== 3);
7484 TCGv_ptr fpst
= get_fpstatus_ptr();
7487 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7488 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7491 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7492 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7494 case 0x3d: /* FRECPE */
7495 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7497 case 0x3f: /* FRECPX */
7498 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7500 case 0x7d: /* FRSQRTE */
7501 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7504 g_assert_not_reached();
7506 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7509 clear_vec_high(s
, rd
);
7512 tcg_temp_free_i64(tcg_res
);
7513 tcg_temp_free_i64(tcg_op
);
7515 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7516 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7517 int pass
, maxpasses
;
7522 maxpasses
= is_q
? 4 : 2;
7525 for (pass
= 0; pass
< maxpasses
; pass
++) {
7526 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7529 case 0x3c: /* URECPE */
7530 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7532 case 0x3d: /* FRECPE */
7533 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7535 case 0x3f: /* FRECPX */
7536 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7538 case 0x7d: /* FRSQRTE */
7539 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7542 g_assert_not_reached();
7546 write_fp_sreg(s
, rd
, tcg_res
);
7548 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7551 tcg_temp_free_i32(tcg_res
);
7552 tcg_temp_free_i32(tcg_op
);
7553 if (!is_q
&& !is_scalar
) {
7554 clear_vec_high(s
, rd
);
7557 tcg_temp_free_ptr(fpst
);
7560 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7561 int opcode
, bool u
, bool is_q
,
7562 int size
, int rn
, int rd
)
7564 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7565 * in the source becomes a size element in the destination).
7568 TCGv_i32 tcg_res
[2];
7569 int destelt
= is_q
? 2 : 0;
7570 int passes
= scalar
? 1 : 2;
7573 tcg_res
[1] = tcg_const_i32(0);
7576 for (pass
= 0; pass
< passes
; pass
++) {
7577 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7578 NeonGenNarrowFn
*genfn
= NULL
;
7579 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7582 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7584 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7586 tcg_res
[pass
] = tcg_temp_new_i32();
7589 case 0x12: /* XTN, SQXTUN */
7591 static NeonGenNarrowFn
* const xtnfns
[3] = {
7592 gen_helper_neon_narrow_u8
,
7593 gen_helper_neon_narrow_u16
,
7594 tcg_gen_trunc_i64_i32
,
7596 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7597 gen_helper_neon_unarrow_sat8
,
7598 gen_helper_neon_unarrow_sat16
,
7599 gen_helper_neon_unarrow_sat32
,
7602 genenvfn
= sqxtunfns
[size
];
7604 genfn
= xtnfns
[size
];
7608 case 0x14: /* SQXTN, UQXTN */
7610 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7611 { gen_helper_neon_narrow_sat_s8
,
7612 gen_helper_neon_narrow_sat_u8
},
7613 { gen_helper_neon_narrow_sat_s16
,
7614 gen_helper_neon_narrow_sat_u16
},
7615 { gen_helper_neon_narrow_sat_s32
,
7616 gen_helper_neon_narrow_sat_u32
},
7618 genenvfn
= fns
[size
][u
];
7621 case 0x16: /* FCVTN, FCVTN2 */
7622 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7624 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7626 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7627 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7628 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
7629 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7630 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
7631 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
7632 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7633 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7634 tcg_temp_free_i32(tcg_lo
);
7635 tcg_temp_free_i32(tcg_hi
);
7638 case 0x56: /* FCVTXN, FCVTXN2 */
7639 /* 64 bit to 32 bit float conversion
7640 * with von Neumann rounding (round to odd)
7643 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7646 g_assert_not_reached();
7650 genfn(tcg_res
[pass
], tcg_op
);
7651 } else if (genenvfn
) {
7652 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7655 tcg_temp_free_i64(tcg_op
);
7658 for (pass
= 0; pass
< 2; pass
++) {
7659 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7660 tcg_temp_free_i32(tcg_res
[pass
]);
7663 clear_vec_high(s
, rd
);
7667 /* Remaining saturating accumulating ops */
7668 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7669 bool is_q
, int size
, int rn
, int rd
)
7671 bool is_double
= (size
== 3);
7674 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7675 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7678 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7679 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7680 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7682 if (is_u
) { /* USQADD */
7683 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7684 } else { /* SUQADD */
7685 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7687 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7690 clear_vec_high(s
, rd
);
7693 tcg_temp_free_i64(tcg_rd
);
7694 tcg_temp_free_i64(tcg_rn
);
7696 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7697 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7698 int pass
, maxpasses
;
7703 maxpasses
= is_q
? 4 : 2;
7706 for (pass
= 0; pass
< maxpasses
; pass
++) {
7708 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7709 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7711 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7712 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7715 if (is_u
) { /* USQADD */
7718 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7721 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7724 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7727 g_assert_not_reached();
7729 } else { /* SUQADD */
7732 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7735 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7738 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7741 g_assert_not_reached();
7746 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7747 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7748 tcg_temp_free_i64(tcg_zero
);
7750 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7754 clear_vec_high(s
, rd
);
7757 tcg_temp_free_i32(tcg_rd
);
7758 tcg_temp_free_i32(tcg_rn
);
7762 /* C3.6.12 AdvSIMD scalar two reg misc
7763 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7764 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7765 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7766 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7768 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7770 int rd
= extract32(insn
, 0, 5);
7771 int rn
= extract32(insn
, 5, 5);
7772 int opcode
= extract32(insn
, 12, 5);
7773 int size
= extract32(insn
, 22, 2);
7774 bool u
= extract32(insn
, 29, 1);
7775 bool is_fcvt
= false;
7778 TCGv_ptr tcg_fpstatus
;
7781 case 0x3: /* USQADD / SUQADD*/
7782 if (!fp_access_check(s
)) {
7785 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7787 case 0x7: /* SQABS / SQNEG */
7789 case 0xa: /* CMLT */
7791 unallocated_encoding(s
);
7795 case 0x8: /* CMGT, CMGE */
7796 case 0x9: /* CMEQ, CMLE */
7797 case 0xb: /* ABS, NEG */
7799 unallocated_encoding(s
);
7803 case 0x12: /* SQXTUN */
7805 unallocated_encoding(s
);
7809 case 0x14: /* SQXTN, UQXTN */
7811 unallocated_encoding(s
);
7814 if (!fp_access_check(s
)) {
7817 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7822 /* Floating point: U, size[1] and opcode indicate operation;
7823 * size[0] indicates single or double precision.
7825 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7826 size
= extract32(size
, 0, 1) ? 3 : 2;
7828 case 0x2c: /* FCMGT (zero) */
7829 case 0x2d: /* FCMEQ (zero) */
7830 case 0x2e: /* FCMLT (zero) */
7831 case 0x6c: /* FCMGE (zero) */
7832 case 0x6d: /* FCMLE (zero) */
7833 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7835 case 0x1d: /* SCVTF */
7836 case 0x5d: /* UCVTF */
7838 bool is_signed
= (opcode
== 0x1d);
7839 if (!fp_access_check(s
)) {
7842 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7845 case 0x3d: /* FRECPE */
7846 case 0x3f: /* FRECPX */
7847 case 0x7d: /* FRSQRTE */
7848 if (!fp_access_check(s
)) {
7851 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7853 case 0x1a: /* FCVTNS */
7854 case 0x1b: /* FCVTMS */
7855 case 0x3a: /* FCVTPS */
7856 case 0x3b: /* FCVTZS */
7857 case 0x5a: /* FCVTNU */
7858 case 0x5b: /* FCVTMU */
7859 case 0x7a: /* FCVTPU */
7860 case 0x7b: /* FCVTZU */
7862 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7864 case 0x1c: /* FCVTAS */
7865 case 0x5c: /* FCVTAU */
7866 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7868 rmode
= FPROUNDING_TIEAWAY
;
7870 case 0x56: /* FCVTXN, FCVTXN2 */
7872 unallocated_encoding(s
);
7875 if (!fp_access_check(s
)) {
7878 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
7881 unallocated_encoding(s
);
7886 unallocated_encoding(s
);
7890 if (!fp_access_check(s
)) {
7895 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7896 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7897 tcg_fpstatus
= get_fpstatus_ptr();
7899 TCGV_UNUSED_I32(tcg_rmode
);
7900 TCGV_UNUSED_PTR(tcg_fpstatus
);
7904 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7905 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7907 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7908 write_fp_dreg(s
, rd
, tcg_rd
);
7909 tcg_temp_free_i64(tcg_rd
);
7910 tcg_temp_free_i64(tcg_rn
);
7912 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7913 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7915 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7918 case 0x7: /* SQABS, SQNEG */
7920 NeonGenOneOpEnvFn
*genfn
;
7921 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
7922 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
7923 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
7924 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
7926 genfn
= fns
[size
][u
];
7927 genfn(tcg_rd
, cpu_env
, tcg_rn
);
7930 case 0x1a: /* FCVTNS */
7931 case 0x1b: /* FCVTMS */
7932 case 0x1c: /* FCVTAS */
7933 case 0x3a: /* FCVTPS */
7934 case 0x3b: /* FCVTZS */
7936 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7937 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7938 tcg_temp_free_i32(tcg_shift
);
7941 case 0x5a: /* FCVTNU */
7942 case 0x5b: /* FCVTMU */
7943 case 0x5c: /* FCVTAU */
7944 case 0x7a: /* FCVTPU */
7945 case 0x7b: /* FCVTZU */
7947 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7948 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7949 tcg_temp_free_i32(tcg_shift
);
7953 g_assert_not_reached();
7956 write_fp_sreg(s
, rd
, tcg_rd
);
7957 tcg_temp_free_i32(tcg_rd
);
7958 tcg_temp_free_i32(tcg_rn
);
7962 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7963 tcg_temp_free_i32(tcg_rmode
);
7964 tcg_temp_free_ptr(tcg_fpstatus
);
7968 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
7969 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
7970 int immh
, int immb
, int opcode
, int rn
, int rd
)
7972 int size
= 32 - clz32(immh
) - 1;
7973 int immhb
= immh
<< 3 | immb
;
7974 int shift
= 2 * (8 << size
) - immhb
;
7975 bool accumulate
= false;
7977 bool insert
= false;
7978 int dsize
= is_q
? 128 : 64;
7979 int esize
= 8 << size
;
7980 int elements
= dsize
/esize
;
7981 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
7982 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7983 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7987 if (extract32(immh
, 3, 1) && !is_q
) {
7988 unallocated_encoding(s
);
7992 if (size
> 3 && !is_q
) {
7993 unallocated_encoding(s
);
7997 if (!fp_access_check(s
)) {
8002 case 0x02: /* SSRA / USRA (accumulate) */
8005 case 0x04: /* SRSHR / URSHR (rounding) */
8008 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8009 accumulate
= round
= true;
8011 case 0x08: /* SRI */
8017 uint64_t round_const
= 1ULL << (shift
- 1);
8018 tcg_round
= tcg_const_i64(round_const
);
8020 TCGV_UNUSED_I64(tcg_round
);
8023 for (i
= 0; i
< elements
; i
++) {
8024 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8025 if (accumulate
|| insert
) {
8026 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8030 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8032 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8033 accumulate
, is_u
, size
, shift
);
8036 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8040 clear_vec_high(s
, rd
);
8044 tcg_temp_free_i64(tcg_round
);
8048 /* SHL/SLI - Vector shift left */
8049 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8050 int immh
, int immb
, int opcode
, int rn
, int rd
)
8052 int size
= 32 - clz32(immh
) - 1;
8053 int immhb
= immh
<< 3 | immb
;
8054 int shift
= immhb
- (8 << size
);
8055 int dsize
= is_q
? 128 : 64;
8056 int esize
= 8 << size
;
8057 int elements
= dsize
/esize
;
8058 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8059 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8062 if (extract32(immh
, 3, 1) && !is_q
) {
8063 unallocated_encoding(s
);
8067 if (size
> 3 && !is_q
) {
8068 unallocated_encoding(s
);
8072 if (!fp_access_check(s
)) {
8076 for (i
= 0; i
< elements
; i
++) {
8077 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8079 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8082 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8084 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8088 clear_vec_high(s
, rd
);
8092 /* USHLL/SHLL - Vector shift left with widening */
8093 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8094 int immh
, int immb
, int opcode
, int rn
, int rd
)
8096 int size
= 32 - clz32(immh
) - 1;
8097 int immhb
= immh
<< 3 | immb
;
8098 int shift
= immhb
- (8 << size
);
8100 int esize
= 8 << size
;
8101 int elements
= dsize
/esize
;
8102 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8103 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8107 unallocated_encoding(s
);
8111 if (!fp_access_check(s
)) {
8115 /* For the LL variants the store is larger than the load,
8116 * so if rd == rn we would overwrite parts of our input.
8117 * So load everything right now and use shifts in the main loop.
8119 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8121 for (i
= 0; i
< elements
; i
++) {
8122 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8123 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8124 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8125 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8129 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8130 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8131 int immh
, int immb
, int opcode
, int rn
, int rd
)
8133 int immhb
= immh
<< 3 | immb
;
8134 int size
= 32 - clz32(immh
) - 1;
8136 int esize
= 8 << size
;
8137 int elements
= dsize
/esize
;
8138 int shift
= (2 * esize
) - immhb
;
8139 bool round
= extract32(opcode
, 0, 1);
8140 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8144 if (extract32(immh
, 3, 1)) {
8145 unallocated_encoding(s
);
8149 if (!fp_access_check(s
)) {
8153 tcg_rn
= tcg_temp_new_i64();
8154 tcg_rd
= tcg_temp_new_i64();
8155 tcg_final
= tcg_temp_new_i64();
8156 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8159 uint64_t round_const
= 1ULL << (shift
- 1);
8160 tcg_round
= tcg_const_i64(round_const
);
8162 TCGV_UNUSED_I64(tcg_round
);
8165 for (i
= 0; i
< elements
; i
++) {
8166 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8167 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8168 false, true, size
+1, shift
);
8170 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8174 clear_vec_high(s
, rd
);
8175 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8177 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8181 tcg_temp_free_i64(tcg_round
);
8183 tcg_temp_free_i64(tcg_rn
);
8184 tcg_temp_free_i64(tcg_rd
);
8185 tcg_temp_free_i64(tcg_final
);
8190 /* C3.6.14 AdvSIMD shift by immediate
8191 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8192 * +---+---+---+-------------+------+------+--------+---+------+------+
8193 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8194 * +---+---+---+-------------+------+------+--------+---+------+------+
8196 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8198 int rd
= extract32(insn
, 0, 5);
8199 int rn
= extract32(insn
, 5, 5);
8200 int opcode
= extract32(insn
, 11, 5);
8201 int immb
= extract32(insn
, 16, 3);
8202 int immh
= extract32(insn
, 19, 4);
8203 bool is_u
= extract32(insn
, 29, 1);
8204 bool is_q
= extract32(insn
, 30, 1);
8207 case 0x08: /* SRI */
8209 unallocated_encoding(s
);
8213 case 0x00: /* SSHR / USHR */
8214 case 0x02: /* SSRA / USRA (accumulate) */
8215 case 0x04: /* SRSHR / URSHR (rounding) */
8216 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8217 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8219 case 0x0a: /* SHL / SLI */
8220 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8222 case 0x10: /* SHRN */
8223 case 0x11: /* RSHRN / SQRSHRUN */
8225 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8228 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8231 case 0x12: /* SQSHRN / UQSHRN */
8232 case 0x13: /* SQRSHRN / UQRSHRN */
8233 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8236 case 0x14: /* SSHLL / USHLL */
8237 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8239 case 0x1c: /* SCVTF / UCVTF */
8240 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8243 case 0xc: /* SQSHLU */
8245 unallocated_encoding(s
);
8248 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8250 case 0xe: /* SQSHL, UQSHL */
8251 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8253 case 0x1f: /* FCVTZS/ FCVTZU */
8254 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8257 unallocated_encoding(s
);
8262 /* Generate code to do a "long" addition or subtraction, ie one done in
8263 * TCGv_i64 on vector lanes twice the width specified by size.
8265 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8266 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8268 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8269 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8270 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8271 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8273 NeonGenTwo64OpFn
*genfn
;
8276 genfn
= fns
[size
][is_sub
];
8277 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8280 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8281 int opcode
, int rd
, int rn
, int rm
)
8283 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8284 TCGv_i64 tcg_res
[2];
8287 tcg_res
[0] = tcg_temp_new_i64();
8288 tcg_res
[1] = tcg_temp_new_i64();
8290 /* Does this op do an adding accumulate, a subtracting accumulate,
8291 * or no accumulate at all?
8309 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8310 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8313 /* size == 2 means two 32x32->64 operations; this is worth special
8314 * casing because we can generally handle it inline.
8317 for (pass
= 0; pass
< 2; pass
++) {
8318 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8319 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8320 TCGv_i64 tcg_passres
;
8321 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8323 int elt
= pass
+ is_q
* 2;
8325 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8326 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8329 tcg_passres
= tcg_res
[pass
];
8331 tcg_passres
= tcg_temp_new_i64();
8335 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8336 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8338 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8339 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8341 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8342 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8344 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8345 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8347 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8348 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8349 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8351 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8352 tcg_temp_free_i64(tcg_tmp1
);
8353 tcg_temp_free_i64(tcg_tmp2
);
8356 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8357 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8358 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8359 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8361 case 9: /* SQDMLAL, SQDMLAL2 */
8362 case 11: /* SQDMLSL, SQDMLSL2 */
8363 case 13: /* SQDMULL, SQDMULL2 */
8364 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8365 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8366 tcg_passres
, tcg_passres
);
8369 g_assert_not_reached();
8372 if (opcode
== 9 || opcode
== 11) {
8373 /* saturating accumulate ops */
8375 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8377 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8378 tcg_res
[pass
], tcg_passres
);
8379 } else if (accop
> 0) {
8380 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8381 } else if (accop
< 0) {
8382 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8386 tcg_temp_free_i64(tcg_passres
);
8389 tcg_temp_free_i64(tcg_op1
);
8390 tcg_temp_free_i64(tcg_op2
);
8393 /* size 0 or 1, generally helper functions */
8394 for (pass
= 0; pass
< 2; pass
++) {
8395 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8396 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8397 TCGv_i64 tcg_passres
;
8398 int elt
= pass
+ is_q
* 2;
8400 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8401 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8404 tcg_passres
= tcg_res
[pass
];
8406 tcg_passres
= tcg_temp_new_i64();
8410 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8411 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8413 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8414 static NeonGenWidenFn
* const widenfns
[2][2] = {
8415 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8416 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8418 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8420 widenfn(tcg_op2_64
, tcg_op2
);
8421 widenfn(tcg_passres
, tcg_op1
);
8422 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8423 tcg_passres
, tcg_op2_64
);
8424 tcg_temp_free_i64(tcg_op2_64
);
8427 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8428 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8431 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8433 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8437 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8439 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8443 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8444 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8445 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8448 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8450 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8454 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8456 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8460 case 9: /* SQDMLAL, SQDMLAL2 */
8461 case 11: /* SQDMLSL, SQDMLSL2 */
8462 case 13: /* SQDMULL, SQDMULL2 */
8464 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8465 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8466 tcg_passres
, tcg_passres
);
8468 case 14: /* PMULL */
8470 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8473 g_assert_not_reached();
8475 tcg_temp_free_i32(tcg_op1
);
8476 tcg_temp_free_i32(tcg_op2
);
8479 if (opcode
== 9 || opcode
== 11) {
8480 /* saturating accumulate ops */
8482 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8484 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8488 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8489 tcg_res
[pass
], tcg_passres
);
8491 tcg_temp_free_i64(tcg_passres
);
8496 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8497 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8498 tcg_temp_free_i64(tcg_res
[0]);
8499 tcg_temp_free_i64(tcg_res
[1]);
8502 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8503 int opcode
, int rd
, int rn
, int rm
)
8505 TCGv_i64 tcg_res
[2];
8506 int part
= is_q
? 2 : 0;
8509 for (pass
= 0; pass
< 2; pass
++) {
8510 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8511 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8512 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8513 static NeonGenWidenFn
* const widenfns
[3][2] = {
8514 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8515 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8516 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8518 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8520 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8521 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8522 widenfn(tcg_op2_wide
, tcg_op2
);
8523 tcg_temp_free_i32(tcg_op2
);
8524 tcg_res
[pass
] = tcg_temp_new_i64();
8525 gen_neon_addl(size
, (opcode
== 3),
8526 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8527 tcg_temp_free_i64(tcg_op1
);
8528 tcg_temp_free_i64(tcg_op2_wide
);
8531 for (pass
= 0; pass
< 2; pass
++) {
8532 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8533 tcg_temp_free_i64(tcg_res
[pass
]);
8537 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8539 tcg_gen_shri_i64(in
, in
, 32);
8540 tcg_gen_trunc_i64_i32(res
, in
);
8543 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8545 tcg_gen_addi_i64(in
, in
, 1U << 31);
8546 do_narrow_high_u32(res
, in
);
8549 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8550 int opcode
, int rd
, int rn
, int rm
)
8552 TCGv_i32 tcg_res
[2];
8553 int part
= is_q
? 2 : 0;
8556 for (pass
= 0; pass
< 2; pass
++) {
8557 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8558 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8559 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8560 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8561 { gen_helper_neon_narrow_high_u8
,
8562 gen_helper_neon_narrow_round_high_u8
},
8563 { gen_helper_neon_narrow_high_u16
,
8564 gen_helper_neon_narrow_round_high_u16
},
8565 { do_narrow_high_u32
, do_narrow_round_high_u32
},
8567 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8569 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8570 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8572 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8574 tcg_temp_free_i64(tcg_op1
);
8575 tcg_temp_free_i64(tcg_op2
);
8577 tcg_res
[pass
] = tcg_temp_new_i32();
8578 gennarrow(tcg_res
[pass
], tcg_wideres
);
8579 tcg_temp_free_i64(tcg_wideres
);
8582 for (pass
= 0; pass
< 2; pass
++) {
8583 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8584 tcg_temp_free_i32(tcg_res
[pass
]);
8587 clear_vec_high(s
, rd
);
8591 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8593 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8594 * is the only three-reg-diff instruction which produces a
8595 * 128-bit wide result from a single operation. However since
8596 * it's possible to calculate the two halves more or less
8597 * separately we just use two helper calls.
8599 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8600 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8601 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8603 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8604 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8605 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8606 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8607 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8608 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8610 tcg_temp_free_i64(tcg_op1
);
8611 tcg_temp_free_i64(tcg_op2
);
8612 tcg_temp_free_i64(tcg_res
);
8615 /* C3.6.15 AdvSIMD three different
8616 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8617 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8618 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8619 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8621 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8623 /* Instructions in this group fall into three basic classes
8624 * (in each case with the operation working on each element in
8625 * the input vectors):
8626 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8628 * (2) wide 64 x 128 -> 128
8629 * (3) narrowing 128 x 128 -> 64
8630 * Here we do initial decode, catch unallocated cases and
8631 * dispatch to separate functions for each class.
8633 int is_q
= extract32(insn
, 30, 1);
8634 int is_u
= extract32(insn
, 29, 1);
8635 int size
= extract32(insn
, 22, 2);
8636 int opcode
= extract32(insn
, 12, 4);
8637 int rm
= extract32(insn
, 16, 5);
8638 int rn
= extract32(insn
, 5, 5);
8639 int rd
= extract32(insn
, 0, 5);
8642 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8643 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8644 /* 64 x 128 -> 128 */
8646 unallocated_encoding(s
);
8649 if (!fp_access_check(s
)) {
8652 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8654 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8655 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8656 /* 128 x 128 -> 64 */
8658 unallocated_encoding(s
);
8661 if (!fp_access_check(s
)) {
8664 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8666 case 14: /* PMULL, PMULL2 */
8667 if (is_u
|| size
== 1 || size
== 2) {
8668 unallocated_encoding(s
);
8672 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8673 unallocated_encoding(s
);
8676 if (!fp_access_check(s
)) {
8679 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8683 case 9: /* SQDMLAL, SQDMLAL2 */
8684 case 11: /* SQDMLSL, SQDMLSL2 */
8685 case 13: /* SQDMULL, SQDMULL2 */
8686 if (is_u
|| size
== 0) {
8687 unallocated_encoding(s
);
8691 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8692 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8693 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8694 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8695 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8696 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8697 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8698 /* 64 x 64 -> 128 */
8700 unallocated_encoding(s
);
8704 if (!fp_access_check(s
)) {
8708 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8711 /* opcode 15 not allocated */
8712 unallocated_encoding(s
);
8717 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8718 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8720 int rd
= extract32(insn
, 0, 5);
8721 int rn
= extract32(insn
, 5, 5);
8722 int rm
= extract32(insn
, 16, 5);
8723 int size
= extract32(insn
, 22, 2);
8724 bool is_u
= extract32(insn
, 29, 1);
8725 bool is_q
= extract32(insn
, 30, 1);
8726 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8729 if (!fp_access_check(s
)) {
8733 tcg_op1
= tcg_temp_new_i64();
8734 tcg_op2
= tcg_temp_new_i64();
8735 tcg_res
[0] = tcg_temp_new_i64();
8736 tcg_res
[1] = tcg_temp_new_i64();
8738 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8739 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8740 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8745 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8748 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8751 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8754 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8759 /* B* ops need res loaded to operate on */
8760 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8765 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8767 case 1: /* BSL bitwise select */
8768 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8769 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8770 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8772 case 2: /* BIT, bitwise insert if true */
8773 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8774 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8775 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8777 case 3: /* BIF, bitwise insert if false */
8778 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8779 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8780 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8786 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8788 tcg_gen_movi_i64(tcg_res
[1], 0);
8790 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8792 tcg_temp_free_i64(tcg_op1
);
8793 tcg_temp_free_i64(tcg_op2
);
8794 tcg_temp_free_i64(tcg_res
[0]);
8795 tcg_temp_free_i64(tcg_res
[1]);
8798 /* Helper functions for 32 bit comparisons */
8799 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8801 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8804 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8806 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8809 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8811 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8814 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8816 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8819 /* Pairwise op subgroup of C3.6.16.
8821 * This is called directly or via the handle_3same_float for float pairwise
8822 * operations where the opcode and size are calculated differently.
8824 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8825 int size
, int rn
, int rm
, int rd
)
8830 /* Floating point operations need fpst */
8831 if (opcode
>= 0x58) {
8832 fpst
= get_fpstatus_ptr();
8834 TCGV_UNUSED_PTR(fpst
);
8837 if (!fp_access_check(s
)) {
8841 /* These operations work on the concatenated rm:rn, with each pair of
8842 * adjacent elements being operated on to produce an element in the result.
8845 TCGv_i64 tcg_res
[2];
8847 for (pass
= 0; pass
< 2; pass
++) {
8848 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8849 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8850 int passreg
= (pass
== 0) ? rn
: rm
;
8852 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8853 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8854 tcg_res
[pass
] = tcg_temp_new_i64();
8857 case 0x17: /* ADDP */
8858 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8860 case 0x58: /* FMAXNMP */
8861 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8863 case 0x5a: /* FADDP */
8864 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8866 case 0x5e: /* FMAXP */
8867 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8869 case 0x78: /* FMINNMP */
8870 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8872 case 0x7e: /* FMINP */
8873 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8876 g_assert_not_reached();
8879 tcg_temp_free_i64(tcg_op1
);
8880 tcg_temp_free_i64(tcg_op2
);
8883 for (pass
= 0; pass
< 2; pass
++) {
8884 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8885 tcg_temp_free_i64(tcg_res
[pass
]);
8888 int maxpass
= is_q
? 4 : 2;
8889 TCGv_i32 tcg_res
[4];
8891 for (pass
= 0; pass
< maxpass
; pass
++) {
8892 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8893 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8894 NeonGenTwoOpFn
*genfn
= NULL
;
8895 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8896 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8898 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8899 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8900 tcg_res
[pass
] = tcg_temp_new_i32();
8903 case 0x17: /* ADDP */
8905 static NeonGenTwoOpFn
* const fns
[3] = {
8906 gen_helper_neon_padd_u8
,
8907 gen_helper_neon_padd_u16
,
8913 case 0x14: /* SMAXP, UMAXP */
8915 static NeonGenTwoOpFn
* const fns
[3][2] = {
8916 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8917 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8918 { gen_max_s32
, gen_max_u32
},
8920 genfn
= fns
[size
][u
];
8923 case 0x15: /* SMINP, UMINP */
8925 static NeonGenTwoOpFn
* const fns
[3][2] = {
8926 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8927 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8928 { gen_min_s32
, gen_min_u32
},
8930 genfn
= fns
[size
][u
];
8933 /* The FP operations are all on single floats (32 bit) */
8934 case 0x58: /* FMAXNMP */
8935 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8937 case 0x5a: /* FADDP */
8938 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8940 case 0x5e: /* FMAXP */
8941 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8943 case 0x78: /* FMINNMP */
8944 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8946 case 0x7e: /* FMINP */
8947 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8950 g_assert_not_reached();
8953 /* FP ops called directly, otherwise call now */
8955 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8958 tcg_temp_free_i32(tcg_op1
);
8959 tcg_temp_free_i32(tcg_op2
);
8962 for (pass
= 0; pass
< maxpass
; pass
++) {
8963 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8964 tcg_temp_free_i32(tcg_res
[pass
]);
8967 clear_vec_high(s
, rd
);
8971 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
8972 tcg_temp_free_ptr(fpst
);
8976 /* Floating point op subgroup of C3.6.16. */
8977 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
8979 /* For floating point ops, the U, size[1] and opcode bits
8980 * together indicate the operation. size[0] indicates single
8983 int fpopcode
= extract32(insn
, 11, 5)
8984 | (extract32(insn
, 23, 1) << 5)
8985 | (extract32(insn
, 29, 1) << 6);
8986 int is_q
= extract32(insn
, 30, 1);
8987 int size
= extract32(insn
, 22, 1);
8988 int rm
= extract32(insn
, 16, 5);
8989 int rn
= extract32(insn
, 5, 5);
8990 int rd
= extract32(insn
, 0, 5);
8992 int datasize
= is_q
? 128 : 64;
8993 int esize
= 32 << size
;
8994 int elements
= datasize
/ esize
;
8996 if (size
== 1 && !is_q
) {
8997 unallocated_encoding(s
);
9002 case 0x58: /* FMAXNMP */
9003 case 0x5a: /* FADDP */
9004 case 0x5e: /* FMAXP */
9005 case 0x78: /* FMINNMP */
9006 case 0x7e: /* FMINP */
9007 if (size
&& !is_q
) {
9008 unallocated_encoding(s
);
9011 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9014 case 0x1b: /* FMULX */
9015 case 0x1f: /* FRECPS */
9016 case 0x3f: /* FRSQRTS */
9017 case 0x5d: /* FACGE */
9018 case 0x7d: /* FACGT */
9019 case 0x19: /* FMLA */
9020 case 0x39: /* FMLS */
9021 case 0x18: /* FMAXNM */
9022 case 0x1a: /* FADD */
9023 case 0x1c: /* FCMEQ */
9024 case 0x1e: /* FMAX */
9025 case 0x38: /* FMINNM */
9026 case 0x3a: /* FSUB */
9027 case 0x3e: /* FMIN */
9028 case 0x5b: /* FMUL */
9029 case 0x5c: /* FCMGE */
9030 case 0x5f: /* FDIV */
9031 case 0x7a: /* FABD */
9032 case 0x7c: /* FCMGT */
9033 if (!fp_access_check(s
)) {
9037 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9040 unallocated_encoding(s
);
9045 /* Integer op subgroup of C3.6.16. */
9046 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9048 int is_q
= extract32(insn
, 30, 1);
9049 int u
= extract32(insn
, 29, 1);
9050 int size
= extract32(insn
, 22, 2);
9051 int opcode
= extract32(insn
, 11, 5);
9052 int rm
= extract32(insn
, 16, 5);
9053 int rn
= extract32(insn
, 5, 5);
9054 int rd
= extract32(insn
, 0, 5);
9058 case 0x13: /* MUL, PMUL */
9059 if (u
&& size
!= 0) {
9060 unallocated_encoding(s
);
9064 case 0x0: /* SHADD, UHADD */
9065 case 0x2: /* SRHADD, URHADD */
9066 case 0x4: /* SHSUB, UHSUB */
9067 case 0xc: /* SMAX, UMAX */
9068 case 0xd: /* SMIN, UMIN */
9069 case 0xe: /* SABD, UABD */
9070 case 0xf: /* SABA, UABA */
9071 case 0x12: /* MLA, MLS */
9073 unallocated_encoding(s
);
9077 case 0x16: /* SQDMULH, SQRDMULH */
9078 if (size
== 0 || size
== 3) {
9079 unallocated_encoding(s
);
9084 if (size
== 3 && !is_q
) {
9085 unallocated_encoding(s
);
9091 if (!fp_access_check(s
)) {
9097 for (pass
= 0; pass
< 2; pass
++) {
9098 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9099 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9100 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9102 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9103 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9105 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9107 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9109 tcg_temp_free_i64(tcg_res
);
9110 tcg_temp_free_i64(tcg_op1
);
9111 tcg_temp_free_i64(tcg_op2
);
9114 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9115 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9116 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9117 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9118 NeonGenTwoOpFn
*genfn
= NULL
;
9119 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9121 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9122 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9125 case 0x0: /* SHADD, UHADD */
9127 static NeonGenTwoOpFn
* const fns
[3][2] = {
9128 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9129 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9130 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9132 genfn
= fns
[size
][u
];
9135 case 0x1: /* SQADD, UQADD */
9137 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9138 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9139 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9140 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9142 genenvfn
= fns
[size
][u
];
9145 case 0x2: /* SRHADD, URHADD */
9147 static NeonGenTwoOpFn
* const fns
[3][2] = {
9148 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9149 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9150 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9152 genfn
= fns
[size
][u
];
9155 case 0x4: /* SHSUB, UHSUB */
9157 static NeonGenTwoOpFn
* const fns
[3][2] = {
9158 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9159 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9160 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9162 genfn
= fns
[size
][u
];
9165 case 0x5: /* SQSUB, UQSUB */
9167 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9168 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9169 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9170 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9172 genenvfn
= fns
[size
][u
];
9175 case 0x6: /* CMGT, CMHI */
9177 static NeonGenTwoOpFn
* const fns
[3][2] = {
9178 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9179 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9180 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9182 genfn
= fns
[size
][u
];
9185 case 0x7: /* CMGE, CMHS */
9187 static NeonGenTwoOpFn
* const fns
[3][2] = {
9188 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9189 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9190 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9192 genfn
= fns
[size
][u
];
9195 case 0x8: /* SSHL, USHL */
9197 static NeonGenTwoOpFn
* const fns
[3][2] = {
9198 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9199 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9200 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9202 genfn
= fns
[size
][u
];
9205 case 0x9: /* SQSHL, UQSHL */
9207 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9208 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9209 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9210 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9212 genenvfn
= fns
[size
][u
];
9215 case 0xa: /* SRSHL, URSHL */
9217 static NeonGenTwoOpFn
* const fns
[3][2] = {
9218 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9219 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9220 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9222 genfn
= fns
[size
][u
];
9225 case 0xb: /* SQRSHL, UQRSHL */
9227 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9228 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9229 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9230 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9232 genenvfn
= fns
[size
][u
];
9235 case 0xc: /* SMAX, UMAX */
9237 static NeonGenTwoOpFn
* const fns
[3][2] = {
9238 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9239 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9240 { gen_max_s32
, gen_max_u32
},
9242 genfn
= fns
[size
][u
];
9246 case 0xd: /* SMIN, UMIN */
9248 static NeonGenTwoOpFn
* const fns
[3][2] = {
9249 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9250 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9251 { gen_min_s32
, gen_min_u32
},
9253 genfn
= fns
[size
][u
];
9256 case 0xe: /* SABD, UABD */
9257 case 0xf: /* SABA, UABA */
9259 static NeonGenTwoOpFn
* const fns
[3][2] = {
9260 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9261 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9262 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9264 genfn
= fns
[size
][u
];
9267 case 0x10: /* ADD, SUB */
9269 static NeonGenTwoOpFn
* const fns
[3][2] = {
9270 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9271 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9272 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9274 genfn
= fns
[size
][u
];
9277 case 0x11: /* CMTST, CMEQ */
9279 static NeonGenTwoOpFn
* const fns
[3][2] = {
9280 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9281 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9282 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9284 genfn
= fns
[size
][u
];
9287 case 0x13: /* MUL, PMUL */
9291 genfn
= gen_helper_neon_mul_p8
;
9294 /* fall through : MUL */
9295 case 0x12: /* MLA, MLS */
9297 static NeonGenTwoOpFn
* const fns
[3] = {
9298 gen_helper_neon_mul_u8
,
9299 gen_helper_neon_mul_u16
,
9305 case 0x16: /* SQDMULH, SQRDMULH */
9307 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9308 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9309 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9311 assert(size
== 1 || size
== 2);
9312 genenvfn
= fns
[size
- 1][u
];
9316 g_assert_not_reached();
9320 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9322 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9325 if (opcode
== 0xf || opcode
== 0x12) {
9326 /* SABA, UABA, MLA, MLS: accumulating ops */
9327 static NeonGenTwoOpFn
* const fns
[3][2] = {
9328 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9329 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9330 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9332 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9334 genfn
= fns
[size
][is_sub
];
9335 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9336 genfn(tcg_res
, tcg_op1
, tcg_res
);
9339 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9341 tcg_temp_free_i32(tcg_res
);
9342 tcg_temp_free_i32(tcg_op1
);
9343 tcg_temp_free_i32(tcg_op2
);
9348 clear_vec_high(s
, rd
);
9352 /* C3.6.16 AdvSIMD three same
9353 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9354 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9355 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9356 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9358 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9360 int opcode
= extract32(insn
, 11, 5);
9363 case 0x3: /* logic ops */
9364 disas_simd_3same_logic(s
, insn
);
9366 case 0x17: /* ADDP */
9367 case 0x14: /* SMAXP, UMAXP */
9368 case 0x15: /* SMINP, UMINP */
9370 /* Pairwise operations */
9371 int is_q
= extract32(insn
, 30, 1);
9372 int u
= extract32(insn
, 29, 1);
9373 int size
= extract32(insn
, 22, 2);
9374 int rm
= extract32(insn
, 16, 5);
9375 int rn
= extract32(insn
, 5, 5);
9376 int rd
= extract32(insn
, 0, 5);
9377 if (opcode
== 0x17) {
9378 if (u
|| (size
== 3 && !is_q
)) {
9379 unallocated_encoding(s
);
9384 unallocated_encoding(s
);
9388 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9392 /* floating point ops, sz[1] and U are part of opcode */
9393 disas_simd_3same_float(s
, insn
);
9396 disas_simd_3same_int(s
, insn
);
9401 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9402 int size
, int rn
, int rd
)
9404 /* Handle 2-reg-misc ops which are widening (so each size element
9405 * in the source becomes a 2*size element in the destination.
9406 * The only instruction like this is FCVTL.
9411 /* 32 -> 64 bit fp conversion */
9412 TCGv_i64 tcg_res
[2];
9413 int srcelt
= is_q
? 2 : 0;
9415 for (pass
= 0; pass
< 2; pass
++) {
9416 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9417 tcg_res
[pass
] = tcg_temp_new_i64();
9419 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9420 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9421 tcg_temp_free_i32(tcg_op
);
9423 for (pass
= 0; pass
< 2; pass
++) {
9424 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9425 tcg_temp_free_i64(tcg_res
[pass
]);
9428 /* 16 -> 32 bit fp conversion */
9429 int srcelt
= is_q
? 4 : 0;
9430 TCGv_i32 tcg_res
[4];
9432 for (pass
= 0; pass
< 4; pass
++) {
9433 tcg_res
[pass
] = tcg_temp_new_i32();
9435 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9436 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9439 for (pass
= 0; pass
< 4; pass
++) {
9440 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9441 tcg_temp_free_i32(tcg_res
[pass
]);
9446 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9447 bool is_q
, int size
, int rn
, int rd
)
9449 int op
= (opcode
<< 1) | u
;
9450 int opsz
= op
+ size
;
9451 int grp_size
= 3 - opsz
;
9452 int dsize
= is_q
? 128 : 64;
9456 unallocated_encoding(s
);
9460 if (!fp_access_check(s
)) {
9465 /* Special case bytes, use bswap op on each group of elements */
9466 int groups
= dsize
/ (8 << grp_size
);
9468 for (i
= 0; i
< groups
; i
++) {
9469 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9471 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9474 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9477 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9480 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9483 g_assert_not_reached();
9485 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9486 tcg_temp_free_i64(tcg_tmp
);
9489 clear_vec_high(s
, rd
);
9492 int revmask
= (1 << grp_size
) - 1;
9493 int esize
= 8 << size
;
9494 int elements
= dsize
/ esize
;
9495 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9496 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9497 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9499 for (i
= 0; i
< elements
; i
++) {
9500 int e_rev
= (i
& 0xf) ^ revmask
;
9501 int off
= e_rev
* esize
;
9502 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9504 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9505 tcg_rn
, off
- 64, esize
);
9507 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9510 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9511 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9513 tcg_temp_free_i64(tcg_rd_hi
);
9514 tcg_temp_free_i64(tcg_rd
);
9515 tcg_temp_free_i64(tcg_rn
);
9519 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9520 bool is_q
, int size
, int rn
, int rd
)
9522 /* Implement the pairwise operations from 2-misc:
9523 * SADDLP, UADDLP, SADALP, UADALP.
9524 * These all add pairs of elements in the input to produce a
9525 * double-width result element in the output (possibly accumulating).
9527 bool accum
= (opcode
== 0x6);
9528 int maxpass
= is_q
? 2 : 1;
9530 TCGv_i64 tcg_res
[2];
9533 /* 32 + 32 -> 64 op */
9534 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9536 for (pass
= 0; pass
< maxpass
; pass
++) {
9537 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9538 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9540 tcg_res
[pass
] = tcg_temp_new_i64();
9542 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9543 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9544 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9546 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9547 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9550 tcg_temp_free_i64(tcg_op1
);
9551 tcg_temp_free_i64(tcg_op2
);
9554 for (pass
= 0; pass
< maxpass
; pass
++) {
9555 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9556 NeonGenOneOpFn
*genfn
;
9557 static NeonGenOneOpFn
* const fns
[2][2] = {
9558 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9559 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9562 genfn
= fns
[size
][u
];
9564 tcg_res
[pass
] = tcg_temp_new_i64();
9566 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9567 genfn(tcg_res
[pass
], tcg_op
);
9570 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9572 gen_helper_neon_addl_u16(tcg_res
[pass
],
9573 tcg_res
[pass
], tcg_op
);
9575 gen_helper_neon_addl_u32(tcg_res
[pass
],
9576 tcg_res
[pass
], tcg_op
);
9579 tcg_temp_free_i64(tcg_op
);
9583 tcg_res
[1] = tcg_const_i64(0);
9585 for (pass
= 0; pass
< 2; pass
++) {
9586 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9587 tcg_temp_free_i64(tcg_res
[pass
]);
9591 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9593 /* Implement SHLL and SHLL2 */
9595 int part
= is_q
? 2 : 0;
9596 TCGv_i64 tcg_res
[2];
9598 for (pass
= 0; pass
< 2; pass
++) {
9599 static NeonGenWidenFn
* const widenfns
[3] = {
9600 gen_helper_neon_widen_u8
,
9601 gen_helper_neon_widen_u16
,
9602 tcg_gen_extu_i32_i64
,
9604 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9605 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9607 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9608 tcg_res
[pass
] = tcg_temp_new_i64();
9609 widenfn(tcg_res
[pass
], tcg_op
);
9610 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9612 tcg_temp_free_i32(tcg_op
);
9615 for (pass
= 0; pass
< 2; pass
++) {
9616 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9617 tcg_temp_free_i64(tcg_res
[pass
]);
9621 /* C3.6.17 AdvSIMD two reg misc
9622 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9623 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9624 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9625 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9627 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9629 int size
= extract32(insn
, 22, 2);
9630 int opcode
= extract32(insn
, 12, 5);
9631 bool u
= extract32(insn
, 29, 1);
9632 bool is_q
= extract32(insn
, 30, 1);
9633 int rn
= extract32(insn
, 5, 5);
9634 int rd
= extract32(insn
, 0, 5);
9635 bool need_fpstatus
= false;
9636 bool need_rmode
= false;
9639 TCGv_ptr tcg_fpstatus
;
9642 case 0x0: /* REV64, REV32 */
9643 case 0x1: /* REV16 */
9644 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9646 case 0x5: /* CNT, NOT, RBIT */
9647 if (u
&& size
== 0) {
9648 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9651 } else if (u
&& size
== 1) {
9654 } else if (!u
&& size
== 0) {
9658 unallocated_encoding(s
);
9660 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9661 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9663 unallocated_encoding(s
);
9666 if (!fp_access_check(s
)) {
9670 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9672 case 0x4: /* CLS, CLZ */
9674 unallocated_encoding(s
);
9678 case 0x2: /* SADDLP, UADDLP */
9679 case 0x6: /* SADALP, UADALP */
9681 unallocated_encoding(s
);
9684 if (!fp_access_check(s
)) {
9687 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9689 case 0x13: /* SHLL, SHLL2 */
9690 if (u
== 0 || size
== 3) {
9691 unallocated_encoding(s
);
9694 if (!fp_access_check(s
)) {
9697 handle_shll(s
, is_q
, size
, rn
, rd
);
9699 case 0xa: /* CMLT */
9701 unallocated_encoding(s
);
9705 case 0x8: /* CMGT, CMGE */
9706 case 0x9: /* CMEQ, CMLE */
9707 case 0xb: /* ABS, NEG */
9708 if (size
== 3 && !is_q
) {
9709 unallocated_encoding(s
);
9713 case 0x3: /* SUQADD, USQADD */
9714 if (size
== 3 && !is_q
) {
9715 unallocated_encoding(s
);
9718 if (!fp_access_check(s
)) {
9721 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9723 case 0x7: /* SQABS, SQNEG */
9724 if (size
== 3 && !is_q
) {
9725 unallocated_encoding(s
);
9733 /* Floating point: U, size[1] and opcode indicate operation;
9734 * size[0] indicates single or double precision.
9736 int is_double
= extract32(size
, 0, 1);
9737 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9738 size
= is_double
? 3 : 2;
9740 case 0x2f: /* FABS */
9741 case 0x6f: /* FNEG */
9742 if (size
== 3 && !is_q
) {
9743 unallocated_encoding(s
);
9747 case 0x1d: /* SCVTF */
9748 case 0x5d: /* UCVTF */
9750 bool is_signed
= (opcode
== 0x1d) ? true : false;
9751 int elements
= is_double
? 2 : is_q
? 4 : 2;
9752 if (is_double
&& !is_q
) {
9753 unallocated_encoding(s
);
9756 if (!fp_access_check(s
)) {
9759 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9762 case 0x2c: /* FCMGT (zero) */
9763 case 0x2d: /* FCMEQ (zero) */
9764 case 0x2e: /* FCMLT (zero) */
9765 case 0x6c: /* FCMGE (zero) */
9766 case 0x6d: /* FCMLE (zero) */
9767 if (size
== 3 && !is_q
) {
9768 unallocated_encoding(s
);
9771 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9773 case 0x7f: /* FSQRT */
9774 if (size
== 3 && !is_q
) {
9775 unallocated_encoding(s
);
9779 case 0x1a: /* FCVTNS */
9780 case 0x1b: /* FCVTMS */
9781 case 0x3a: /* FCVTPS */
9782 case 0x3b: /* FCVTZS */
9783 case 0x5a: /* FCVTNU */
9784 case 0x5b: /* FCVTMU */
9785 case 0x7a: /* FCVTPU */
9786 case 0x7b: /* FCVTZU */
9787 need_fpstatus
= true;
9789 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9790 if (size
== 3 && !is_q
) {
9791 unallocated_encoding(s
);
9795 case 0x5c: /* FCVTAU */
9796 case 0x1c: /* FCVTAS */
9797 need_fpstatus
= true;
9799 rmode
= FPROUNDING_TIEAWAY
;
9800 if (size
== 3 && !is_q
) {
9801 unallocated_encoding(s
);
9805 case 0x3c: /* URECPE */
9807 unallocated_encoding(s
);
9811 case 0x3d: /* FRECPE */
9812 case 0x7d: /* FRSQRTE */
9813 if (size
== 3 && !is_q
) {
9814 unallocated_encoding(s
);
9817 if (!fp_access_check(s
)) {
9820 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9822 case 0x56: /* FCVTXN, FCVTXN2 */
9824 unallocated_encoding(s
);
9828 case 0x16: /* FCVTN, FCVTN2 */
9829 /* handle_2misc_narrow does a 2*size -> size operation, but these
9830 * instructions encode the source size rather than dest size.
9832 if (!fp_access_check(s
)) {
9835 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9837 case 0x17: /* FCVTL, FCVTL2 */
9838 if (!fp_access_check(s
)) {
9841 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9843 case 0x18: /* FRINTN */
9844 case 0x19: /* FRINTM */
9845 case 0x38: /* FRINTP */
9846 case 0x39: /* FRINTZ */
9848 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9850 case 0x59: /* FRINTX */
9851 case 0x79: /* FRINTI */
9852 need_fpstatus
= true;
9853 if (size
== 3 && !is_q
) {
9854 unallocated_encoding(s
);
9858 case 0x58: /* FRINTA */
9860 rmode
= FPROUNDING_TIEAWAY
;
9861 need_fpstatus
= true;
9862 if (size
== 3 && !is_q
) {
9863 unallocated_encoding(s
);
9867 case 0x7c: /* URSQRTE */
9869 unallocated_encoding(s
);
9872 need_fpstatus
= true;
9875 unallocated_encoding(s
);
9881 unallocated_encoding(s
);
9885 if (!fp_access_check(s
)) {
9889 if (need_fpstatus
) {
9890 tcg_fpstatus
= get_fpstatus_ptr();
9892 TCGV_UNUSED_PTR(tcg_fpstatus
);
9895 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9896 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9898 TCGV_UNUSED_I32(tcg_rmode
);
9902 /* All 64-bit element operations can be shared with scalar 2misc */
9905 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9906 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9907 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9909 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9911 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9912 tcg_rmode
, tcg_fpstatus
);
9914 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9916 tcg_temp_free_i64(tcg_res
);
9917 tcg_temp_free_i64(tcg_op
);
9922 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9923 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9924 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9927 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9930 /* Special cases for 32 bit elements */
9932 case 0xa: /* CMLT */
9933 /* 32 bit integer comparison against zero, result is
9934 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9939 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9940 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9942 case 0x8: /* CMGT, CMGE */
9943 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9945 case 0x9: /* CMEQ, CMLE */
9946 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9950 gen_helper_clz32(tcg_res
, tcg_op
);
9952 gen_helper_cls32(tcg_res
, tcg_op
);
9955 case 0x7: /* SQABS, SQNEG */
9957 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
9959 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
9962 case 0xb: /* ABS, NEG */
9964 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9966 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9967 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9968 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
9969 tcg_zero
, tcg_op
, tcg_res
);
9970 tcg_temp_free_i32(tcg_zero
);
9973 case 0x2f: /* FABS */
9974 gen_helper_vfp_abss(tcg_res
, tcg_op
);
9976 case 0x6f: /* FNEG */
9977 gen_helper_vfp_negs(tcg_res
, tcg_op
);
9979 case 0x7f: /* FSQRT */
9980 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
9982 case 0x1a: /* FCVTNS */
9983 case 0x1b: /* FCVTMS */
9984 case 0x1c: /* FCVTAS */
9985 case 0x3a: /* FCVTPS */
9986 case 0x3b: /* FCVTZS */
9988 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9989 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
9990 tcg_shift
, tcg_fpstatus
);
9991 tcg_temp_free_i32(tcg_shift
);
9994 case 0x5a: /* FCVTNU */
9995 case 0x5b: /* FCVTMU */
9996 case 0x5c: /* FCVTAU */
9997 case 0x7a: /* FCVTPU */
9998 case 0x7b: /* FCVTZU */
10000 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10001 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10002 tcg_shift
, tcg_fpstatus
);
10003 tcg_temp_free_i32(tcg_shift
);
10006 case 0x18: /* FRINTN */
10007 case 0x19: /* FRINTM */
10008 case 0x38: /* FRINTP */
10009 case 0x39: /* FRINTZ */
10010 case 0x58: /* FRINTA */
10011 case 0x79: /* FRINTI */
10012 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10014 case 0x59: /* FRINTX */
10015 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10017 case 0x7c: /* URSQRTE */
10018 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10021 g_assert_not_reached();
10024 /* Use helpers for 8 and 16 bit elements */
10026 case 0x5: /* CNT, RBIT */
10027 /* For these two insns size is part of the opcode specifier
10028 * (handled earlier); they always operate on byte elements.
10031 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10033 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10036 case 0x7: /* SQABS, SQNEG */
10038 NeonGenOneOpEnvFn
*genfn
;
10039 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10040 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10041 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10043 genfn
= fns
[size
][u
];
10044 genfn(tcg_res
, cpu_env
, tcg_op
);
10047 case 0x8: /* CMGT, CMGE */
10048 case 0x9: /* CMEQ, CMLE */
10049 case 0xa: /* CMLT */
10051 static NeonGenTwoOpFn
* const fns
[3][2] = {
10052 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10053 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10054 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10056 NeonGenTwoOpFn
*genfn
;
10059 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10061 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10062 comp
= (opcode
- 0x8) * 2 + u
;
10063 /* ...but LE, LT are implemented as reverse GE, GT */
10064 reverse
= (comp
> 2);
10068 genfn
= fns
[comp
][size
];
10070 genfn(tcg_res
, tcg_zero
, tcg_op
);
10072 genfn(tcg_res
, tcg_op
, tcg_zero
);
10074 tcg_temp_free_i32(tcg_zero
);
10077 case 0xb: /* ABS, NEG */
10079 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10081 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10083 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10085 tcg_temp_free_i32(tcg_zero
);
10088 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10090 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10094 case 0x4: /* CLS, CLZ */
10097 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10099 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10103 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10105 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10110 g_assert_not_reached();
10114 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10116 tcg_temp_free_i32(tcg_res
);
10117 tcg_temp_free_i32(tcg_op
);
10121 clear_vec_high(s
, rd
);
10125 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10126 tcg_temp_free_i32(tcg_rmode
);
10128 if (need_fpstatus
) {
10129 tcg_temp_free_ptr(tcg_fpstatus
);
10133 /* C3.6.13 AdvSIMD scalar x indexed element
10134 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10135 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10136 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10137 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10138 * C3.6.18 AdvSIMD vector x indexed element
10139 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10140 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10141 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10142 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10144 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10146 /* This encoding has two kinds of instruction:
10147 * normal, where we perform elt x idxelt => elt for each
10148 * element in the vector
10149 * long, where we perform elt x idxelt and generate a result of
10150 * double the width of the input element
10151 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10153 bool is_scalar
= extract32(insn
, 28, 1);
10154 bool is_q
= extract32(insn
, 30, 1);
10155 bool u
= extract32(insn
, 29, 1);
10156 int size
= extract32(insn
, 22, 2);
10157 int l
= extract32(insn
, 21, 1);
10158 int m
= extract32(insn
, 20, 1);
10159 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10160 int rm
= extract32(insn
, 16, 4);
10161 int opcode
= extract32(insn
, 12, 4);
10162 int h
= extract32(insn
, 11, 1);
10163 int rn
= extract32(insn
, 5, 5);
10164 int rd
= extract32(insn
, 0, 5);
10165 bool is_long
= false;
10166 bool is_fp
= false;
10171 case 0x0: /* MLA */
10172 case 0x4: /* MLS */
10173 if (!u
|| is_scalar
) {
10174 unallocated_encoding(s
);
10178 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10179 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10180 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10182 unallocated_encoding(s
);
10187 case 0x3: /* SQDMLAL, SQDMLAL2 */
10188 case 0x7: /* SQDMLSL, SQDMLSL2 */
10189 case 0xb: /* SQDMULL, SQDMULL2 */
10192 case 0xc: /* SQDMULH */
10193 case 0xd: /* SQRDMULH */
10195 unallocated_encoding(s
);
10199 case 0x8: /* MUL */
10200 if (u
|| is_scalar
) {
10201 unallocated_encoding(s
);
10205 case 0x1: /* FMLA */
10206 case 0x5: /* FMLS */
10208 unallocated_encoding(s
);
10212 case 0x9: /* FMUL, FMULX */
10213 if (!extract32(size
, 1, 1)) {
10214 unallocated_encoding(s
);
10220 unallocated_encoding(s
);
10225 /* low bit of size indicates single/double */
10226 size
= extract32(size
, 0, 1) ? 3 : 2;
10228 index
= h
<< 1 | l
;
10231 unallocated_encoding(s
);
10240 index
= h
<< 2 | l
<< 1 | m
;
10243 index
= h
<< 1 | l
;
10247 unallocated_encoding(s
);
10252 if (!fp_access_check(s
)) {
10257 fpst
= get_fpstatus_ptr();
10259 TCGV_UNUSED_PTR(fpst
);
10263 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10266 assert(is_fp
&& is_q
&& !is_long
);
10268 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10270 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10271 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10272 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10274 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10277 case 0x5: /* FMLS */
10278 /* As usual for ARM, separate negation for fused multiply-add */
10279 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10281 case 0x1: /* FMLA */
10282 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10283 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10285 case 0x9: /* FMUL, FMULX */
10287 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10289 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10293 g_assert_not_reached();
10296 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10297 tcg_temp_free_i64(tcg_op
);
10298 tcg_temp_free_i64(tcg_res
);
10302 clear_vec_high(s
, rd
);
10305 tcg_temp_free_i64(tcg_idx
);
10306 } else if (!is_long
) {
10307 /* 32 bit floating point, or 16 or 32 bit integer.
10308 * For the 16 bit scalar case we use the usual Neon helpers and
10309 * rely on the fact that 0 op 0 == 0 with no side effects.
10311 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10312 int pass
, maxpasses
;
10317 maxpasses
= is_q
? 4 : 2;
10320 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10322 if (size
== 1 && !is_scalar
) {
10323 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10324 * the index into both halves of the 32 bit tcg_idx and then use
10325 * the usual Neon helpers.
10327 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10330 for (pass
= 0; pass
< maxpasses
; pass
++) {
10331 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10332 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10334 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10337 case 0x0: /* MLA */
10338 case 0x4: /* MLS */
10339 case 0x8: /* MUL */
10341 static NeonGenTwoOpFn
* const fns
[2][2] = {
10342 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10343 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10345 NeonGenTwoOpFn
*genfn
;
10346 bool is_sub
= opcode
== 0x4;
10349 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10351 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10353 if (opcode
== 0x8) {
10356 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10357 genfn
= fns
[size
- 1][is_sub
];
10358 genfn(tcg_res
, tcg_op
, tcg_res
);
10361 case 0x5: /* FMLS */
10362 /* As usual for ARM, separate negation for fused multiply-add */
10363 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10365 case 0x1: /* FMLA */
10366 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10367 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10369 case 0x9: /* FMUL, FMULX */
10371 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10373 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10376 case 0xc: /* SQDMULH */
10378 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10381 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10385 case 0xd: /* SQRDMULH */
10387 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10390 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10395 g_assert_not_reached();
10399 write_fp_sreg(s
, rd
, tcg_res
);
10401 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10404 tcg_temp_free_i32(tcg_op
);
10405 tcg_temp_free_i32(tcg_res
);
10408 tcg_temp_free_i32(tcg_idx
);
10411 clear_vec_high(s
, rd
);
10414 /* long ops: 16x16->32 or 32x32->64 */
10415 TCGv_i64 tcg_res
[2];
10417 bool satop
= extract32(opcode
, 0, 1);
10418 TCGMemOp memop
= MO_32
;
10425 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10427 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10429 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10430 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10431 TCGv_i64 tcg_passres
;
10437 passelt
= pass
+ (is_q
* 2);
10440 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10442 tcg_res
[pass
] = tcg_temp_new_i64();
10444 if (opcode
== 0xa || opcode
== 0xb) {
10445 /* Non-accumulating ops */
10446 tcg_passres
= tcg_res
[pass
];
10448 tcg_passres
= tcg_temp_new_i64();
10451 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10452 tcg_temp_free_i64(tcg_op
);
10455 /* saturating, doubling */
10456 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10457 tcg_passres
, tcg_passres
);
10460 if (opcode
== 0xa || opcode
== 0xb) {
10464 /* Accumulating op: handle accumulate step */
10465 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10468 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10469 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10471 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10472 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10474 case 0x7: /* SQDMLSL, SQDMLSL2 */
10475 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10477 case 0x3: /* SQDMLAL, SQDMLAL2 */
10478 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10483 g_assert_not_reached();
10485 tcg_temp_free_i64(tcg_passres
);
10487 tcg_temp_free_i64(tcg_idx
);
10490 clear_vec_high(s
, rd
);
10493 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10496 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10499 /* The simplest way to handle the 16x16 indexed ops is to
10500 * duplicate the index into both halves of the 32 bit tcg_idx
10501 * and then use the usual Neon helpers.
10503 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10506 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10507 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10508 TCGv_i64 tcg_passres
;
10511 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10513 read_vec_element_i32(s
, tcg_op
, rn
,
10514 pass
+ (is_q
* 2), MO_32
);
10517 tcg_res
[pass
] = tcg_temp_new_i64();
10519 if (opcode
== 0xa || opcode
== 0xb) {
10520 /* Non-accumulating ops */
10521 tcg_passres
= tcg_res
[pass
];
10523 tcg_passres
= tcg_temp_new_i64();
10526 if (memop
& MO_SIGN
) {
10527 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10529 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10532 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10533 tcg_passres
, tcg_passres
);
10535 tcg_temp_free_i32(tcg_op
);
10537 if (opcode
== 0xa || opcode
== 0xb) {
10541 /* Accumulating op: handle accumulate step */
10542 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10545 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10546 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10549 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10550 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10553 case 0x7: /* SQDMLSL, SQDMLSL2 */
10554 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10556 case 0x3: /* SQDMLAL, SQDMLAL2 */
10557 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10562 g_assert_not_reached();
10564 tcg_temp_free_i64(tcg_passres
);
10566 tcg_temp_free_i32(tcg_idx
);
10569 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10574 tcg_res
[1] = tcg_const_i64(0);
10577 for (pass
= 0; pass
< 2; pass
++) {
10578 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10579 tcg_temp_free_i64(tcg_res
[pass
]);
10583 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10584 tcg_temp_free_ptr(fpst
);
10588 /* C3.6.19 Crypto AES
10589 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10590 * +-----------------+------+-----------+--------+-----+------+------+
10591 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10592 * +-----------------+------+-----------+--------+-----+------+------+
10594 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10596 int size
= extract32(insn
, 22, 2);
10597 int opcode
= extract32(insn
, 12, 5);
10598 int rn
= extract32(insn
, 5, 5);
10599 int rd
= extract32(insn
, 0, 5);
10601 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10602 CryptoThreeOpEnvFn
*genfn
;
10604 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10606 unallocated_encoding(s
);
10611 case 0x4: /* AESE */
10613 genfn
= gen_helper_crypto_aese
;
10615 case 0x6: /* AESMC */
10617 genfn
= gen_helper_crypto_aesmc
;
10619 case 0x5: /* AESD */
10621 genfn
= gen_helper_crypto_aese
;
10623 case 0x7: /* AESIMC */
10625 genfn
= gen_helper_crypto_aesmc
;
10628 unallocated_encoding(s
);
10632 /* Note that we convert the Vx register indexes into the
10633 * index within the vfp.regs[] array, so we can share the
10634 * helper with the AArch32 instructions.
10636 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10637 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10638 tcg_decrypt
= tcg_const_i32(decrypt
);
10640 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10642 tcg_temp_free_i32(tcg_rd_regno
);
10643 tcg_temp_free_i32(tcg_rn_regno
);
10644 tcg_temp_free_i32(tcg_decrypt
);
10647 /* C3.6.20 Crypto three-reg SHA
10648 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10649 * +-----------------+------+---+------+---+--------+-----+------+------+
10650 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10651 * +-----------------+------+---+------+---+--------+-----+------+------+
10653 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10655 int size
= extract32(insn
, 22, 2);
10656 int opcode
= extract32(insn
, 12, 3);
10657 int rm
= extract32(insn
, 16, 5);
10658 int rn
= extract32(insn
, 5, 5);
10659 int rd
= extract32(insn
, 0, 5);
10660 CryptoThreeOpEnvFn
*genfn
;
10661 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10662 int feature
= ARM_FEATURE_V8_SHA256
;
10665 unallocated_encoding(s
);
10670 case 0: /* SHA1C */
10671 case 1: /* SHA1P */
10672 case 2: /* SHA1M */
10673 case 3: /* SHA1SU0 */
10675 feature
= ARM_FEATURE_V8_SHA1
;
10677 case 4: /* SHA256H */
10678 genfn
= gen_helper_crypto_sha256h
;
10680 case 5: /* SHA256H2 */
10681 genfn
= gen_helper_crypto_sha256h2
;
10683 case 6: /* SHA256SU1 */
10684 genfn
= gen_helper_crypto_sha256su1
;
10687 unallocated_encoding(s
);
10691 if (!arm_dc_feature(s
, feature
)) {
10692 unallocated_encoding(s
);
10696 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10697 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10698 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
10701 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
10703 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
10705 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
10706 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
10707 tcg_temp_free_i32(tcg_opcode
);
10710 tcg_temp_free_i32(tcg_rd_regno
);
10711 tcg_temp_free_i32(tcg_rn_regno
);
10712 tcg_temp_free_i32(tcg_rm_regno
);
10715 /* C3.6.21 Crypto two-reg SHA
10716 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10717 * +-----------------+------+-----------+--------+-----+------+------+
10718 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10719 * +-----------------+------+-----------+--------+-----+------+------+
10721 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10723 int size
= extract32(insn
, 22, 2);
10724 int opcode
= extract32(insn
, 12, 5);
10725 int rn
= extract32(insn
, 5, 5);
10726 int rd
= extract32(insn
, 0, 5);
10727 CryptoTwoOpEnvFn
*genfn
;
10729 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
10732 unallocated_encoding(s
);
10737 case 0: /* SHA1H */
10738 feature
= ARM_FEATURE_V8_SHA1
;
10739 genfn
= gen_helper_crypto_sha1h
;
10741 case 1: /* SHA1SU1 */
10742 feature
= ARM_FEATURE_V8_SHA1
;
10743 genfn
= gen_helper_crypto_sha1su1
;
10745 case 2: /* SHA256SU0 */
10746 feature
= ARM_FEATURE_V8_SHA256
;
10747 genfn
= gen_helper_crypto_sha256su0
;
10750 unallocated_encoding(s
);
10754 if (!arm_dc_feature(s
, feature
)) {
10755 unallocated_encoding(s
);
10759 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10760 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10762 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
10764 tcg_temp_free_i32(tcg_rd_regno
);
10765 tcg_temp_free_i32(tcg_rn_regno
);
10768 /* C3.6 Data processing - SIMD, inc Crypto
10770 * As the decode gets a little complex we are using a table based
10771 * approach for this part of the decode.
10773 static const AArch64DecodeTable data_proc_simd
[] = {
10774 /* pattern , mask , fn */
10775 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10776 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10777 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10778 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10779 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10780 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10781 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10782 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10783 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10784 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10785 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10786 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10787 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10788 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10789 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10790 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10791 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10792 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10793 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10794 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10795 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10796 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10797 { 0x00000000, 0x00000000, NULL
}
10800 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10802 /* Note that this is called with all non-FP cases from
10803 * table C3-6 so it must UNDEF for entries not specifically
10804 * allocated to instructions in that table.
10806 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10810 unallocated_encoding(s
);
10814 /* C3.6 Data processing - SIMD and floating point */
10815 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10817 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10818 disas_data_proc_fp(s
, insn
);
10820 /* SIMD, including crypto */
10821 disas_data_proc_simd(s
, insn
);
10825 /* C3.1 A64 instruction index by encoding */
10826 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10830 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10834 s
->fp_access_checked
= false;
10836 switch (extract32(insn
, 25, 4)) {
10837 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10838 unallocated_encoding(s
);
10840 case 0x8: case 0x9: /* Data processing - immediate */
10841 disas_data_proc_imm(s
, insn
);
10843 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10844 disas_b_exc_sys(s
, insn
);
10849 case 0xe: /* Loads and stores */
10850 disas_ldst(s
, insn
);
10853 case 0xd: /* Data processing - register */
10854 disas_data_proc_reg(s
, insn
);
10857 case 0xf: /* Data processing - SIMD and floating point */
10858 disas_data_proc_simd_fp(s
, insn
);
10861 assert(FALSE
); /* all 15 cases should be handled above */
10865 /* if we allocated any temporaries, free them here */
10869 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
10870 TranslationBlock
*tb
,
10873 CPUState
*cs
= CPU(cpu
);
10874 CPUARMState
*env
= &cpu
->env
;
10875 DisasContext dc1
, *dc
= &dc1
;
10877 uint16_t *gen_opc_end
;
10879 target_ulong pc_start
;
10880 target_ulong next_page_start
;
10888 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
10890 dc
->is_jmp
= DISAS_NEXT
;
10892 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10897 dc
->bswap_code
= 0;
10898 dc
->condexec_mask
= 0;
10899 dc
->condexec_cond
= 0;
10900 #if !defined(CONFIG_USER_ONLY)
10901 dc
->user
= (ARM_TBFLAG_AA64_EL(tb
->flags
) == 0);
10903 dc
->cpacr_fpen
= ARM_TBFLAG_AA64_FPEN(tb
->flags
);
10905 dc
->vec_stride
= 0;
10906 dc
->cp_regs
= cpu
->cp_regs
;
10907 dc
->current_pl
= arm_current_pl(env
);
10908 dc
->features
= env
->features
;
10910 /* Single step state. The code-generation logic here is:
10912 * generate code with no special handling for single-stepping (except
10913 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
10914 * this happens anyway because those changes are all system register or
10916 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
10917 * emit code for one insn
10918 * emit code to clear PSTATE.SS
10919 * emit code to generate software step exception for completed step
10920 * end TB (as usual for having generated an exception)
10921 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
10922 * emit code to generate a software step exception
10925 dc
->ss_active
= ARM_TBFLAG_AA64_SS_ACTIVE(tb
->flags
);
10926 dc
->pstate_ss
= ARM_TBFLAG_AA64_PSTATE_SS(tb
->flags
);
10927 dc
->is_ldex
= false;
10928 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_pl
);
10930 init_tmp_a64_array(dc
);
10932 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10935 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10936 if (max_insns
== 0) {
10937 max_insns
= CF_COUNT_MASK
;
10942 tcg_clear_temp_count();
10945 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
10946 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
10947 if (bp
->pc
== dc
->pc
) {
10948 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
10949 /* Advance PC so that clearing the breakpoint will
10950 invalidate this TB. */
10952 goto done_generating
;
10958 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10962 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10965 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
10966 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
10967 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
10970 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
10974 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
10975 tcg_gen_debug_insn_start(dc
->pc
);
10978 if (dc
->ss_active
&& !dc
->pstate_ss
) {
10979 /* Singlestep state is Active-pending.
10980 * If we're in this state at the start of a TB then either
10981 * a) we just took an exception to an EL which is being debugged
10982 * and this is the first insn in the exception handler
10983 * b) debug exceptions were masked and we just unmasked them
10984 * without changing EL (eg by clearing PSTATE.D)
10985 * In either case we're going to take a swstep exception in the
10986 * "did not step an insn" case, and so the syndrome ISV and EX
10987 * bits should be zero.
10989 assert(num_insns
== 0);
10990 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0));
10991 dc
->is_jmp
= DISAS_EXC
;
10995 disas_a64_insn(env
, dc
);
10997 if (tcg_check_temp_count()) {
10998 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11002 /* Translation stops when a conditional branch is encountered.
11003 * Otherwise the subsequent code could get translated several times.
11004 * Also stop translation when a page boundary is reached. This
11005 * ensures prefetch aborts occur at the right place.
11008 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
11009 !cs
->singlestep_enabled
&&
11012 dc
->pc
< next_page_start
&&
11013 num_insns
< max_insns
);
11015 if (tb
->cflags
& CF_LAST_IO
) {
11019 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11020 && dc
->is_jmp
!= DISAS_EXC
) {
11021 /* Note that this means single stepping WFI doesn't halt the CPU.
11022 * For conditional branch insns this is harmless unreachable code as
11023 * gen_goto_tb() has already handled emitting the debug exception
11024 * (and thus a tb-jump is not possible when singlestepping).
11026 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11027 if (dc
->is_jmp
!= DISAS_JUMP
) {
11028 gen_a64_set_pc_im(dc
->pc
);
11030 if (cs
->singlestep_enabled
) {
11031 gen_exception_internal(EXCP_DEBUG
);
11033 gen_step_complete_exception(dc
);
11036 switch (dc
->is_jmp
) {
11038 gen_goto_tb(dc
, 1, dc
->pc
);
11042 gen_a64_set_pc_im(dc
->pc
);
11045 /* indicate that the hash table must be used to find the next TB */
11046 tcg_gen_exit_tb(0);
11048 case DISAS_TB_JUMP
:
11053 gen_a64_set_pc_im(dc
->pc
);
11054 gen_helper_wfe(cpu_env
);
11057 /* This is a special case because we don't want to just halt the CPU
11058 * if trying to debug across a WFI.
11060 gen_a64_set_pc_im(dc
->pc
);
11061 gen_helper_wfi(cpu_env
);
11067 gen_tb_end(tb
, num_insns
);
11068 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
11071 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
11072 qemu_log("----------------\n");
11073 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11074 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
11075 4 | (dc
->bswap_code
<< 1));
11080 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
11083 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
11086 tb
->size
= dc
->pc
- pc_start
;
11087 tb
->icount
= num_insns
;