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block: Add permissions to blk_new()
[qemu/ar7.git] / hw / block / fdc.c
blob74f36344f64570575bdb2f91c9e77e5904926da1
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/hw.h"
32 #include "hw/block/fdc.h"
33 #include "qapi/error.h"
34 #include "qemu/error-report.h"
35 #include "qemu/timer.h"
36 #include "hw/isa/isa.h"
37 #include "hw/sysbus.h"
38 #include "hw/block/block.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/blockdev.h"
41 #include "sysemu/sysemu.h"
42 #include "qemu/log.h"
43
44 /********************************************************/
45 /* debug Floppy devices */
46
47 #define DEBUG_FLOPPY 0
48
49 #define FLOPPY_DPRINTF(fmt, ...) \
50 do { \
51 if (DEBUG_FLOPPY) { \
52 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
53 } \
54 } while (0)
55
56
57 /********************************************************/
58 /* qdev floppy bus */
59
60 #define TYPE_FLOPPY_BUS "floppy-bus"
61 #define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
62
63 typedef struct FDCtrl FDCtrl;
64 typedef struct FDrive FDrive;
65 static FDrive *get_drv(FDCtrl *fdctrl, int unit);
66
67 typedef struct FloppyBus {
68 BusState bus;
69 FDCtrl *fdc;
70 } FloppyBus;
71
72 static const TypeInfo floppy_bus_info = {
73 .name = TYPE_FLOPPY_BUS,
74 .parent = TYPE_BUS,
75 .instance_size = sizeof(FloppyBus),
76 };
77
78 static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
79 {
80 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
81 bus->fdc = fdc;
82 }
83
84
85 /********************************************************/
86 /* Floppy drive emulation */
87
88 typedef enum FDriveRate {
89 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
90 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
91 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
92 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
93 } FDriveRate;
94
95 typedef enum FDriveSize {
96 FDRIVE_SIZE_UNKNOWN,
97 FDRIVE_SIZE_350,
98 FDRIVE_SIZE_525,
99 } FDriveSize;
100
101 typedef struct FDFormat {
102 FloppyDriveType drive;
103 uint8_t last_sect;
104 uint8_t max_track;
105 uint8_t max_head;
106 FDriveRate rate;
107 } FDFormat;
108
109 /* In many cases, the total sector size of a format is enough to uniquely
110 * identify it. However, there are some total sector collisions between
111 * formats of different physical size, and these are noted below by
112 * highlighting the total sector size for entries with collisions. */
113 static const FDFormat fd_formats[] = {
114 /* First entry is default format */
115 /* 1.44 MB 3"1/2 floppy disks */
116 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
117 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
118 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
119 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
120 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
121 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
122 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
123 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
124 /* 2.88 MB 3"1/2 floppy disks */
125 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
126 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
127 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
128 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
129 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
130 /* 720 kB 3"1/2 floppy disks */
131 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
132 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
133 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
134 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
135 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
136 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
137 /* 1.2 MB 5"1/4 floppy disks */
138 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
139 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
140 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
141 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
142 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
143 /* 720 kB 5"1/4 floppy disks */
144 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
145 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
146 /* 360 kB 5"1/4 floppy disks */
147 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
148 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
149 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
150 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
151 /* 320 kB 5"1/4 floppy disks */
152 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
153 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
154 /* 360 kB must match 5"1/4 better than 3"1/2... */
155 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
156 /* end */
157 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
158 };
159
160 static FDriveSize drive_size(FloppyDriveType drive)
161 {
162 switch (drive) {
163 case FLOPPY_DRIVE_TYPE_120:
164 return FDRIVE_SIZE_525;
165 case FLOPPY_DRIVE_TYPE_144:
166 case FLOPPY_DRIVE_TYPE_288:
167 return FDRIVE_SIZE_350;
168 default:
169 return FDRIVE_SIZE_UNKNOWN;
170 }
171 }
172
173 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
174 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
175
176 /* Will always be a fixed parameter for us */
177 #define FD_SECTOR_LEN 512
178 #define FD_SECTOR_SC 2 /* Sector size code */
179 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
180
181 /* Floppy disk drive emulation */
182 typedef enum FDiskFlags {
183 FDISK_DBL_SIDES = 0x01,
184 } FDiskFlags;
185
186 struct FDrive {
187 FDCtrl *fdctrl;
188 BlockBackend *blk;
189 /* Drive status */
190 FloppyDriveType drive; /* CMOS drive type */
191 uint8_t perpendicular; /* 2.88 MB access mode */
192 /* Position */
193 uint8_t head;
194 uint8_t track;
195 uint8_t sect;
196 /* Media */
197 FloppyDriveType disk; /* Current disk type */
198 FDiskFlags flags;
199 uint8_t last_sect; /* Nb sector per track */
200 uint8_t max_track; /* Nb of tracks */
201 uint16_t bps; /* Bytes per sector */
202 uint8_t ro; /* Is read-only */
203 uint8_t media_changed; /* Is media changed */
204 uint8_t media_rate; /* Data rate of medium */
205
206 bool media_validated; /* Have we validated the media? */
207 };
208
209
210 static FloppyDriveType get_fallback_drive_type(FDrive *drv);
211
212 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
213 * currently goes through some pains to keep seeks within the bounds
214 * established by last_sect and max_track. Correcting this is difficult,
215 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
216 *
217 * For now: allow empty drives to have large bounds so we can seek around,
218 * with the understanding that when a diskette is inserted, the bounds will
219 * properly tighten to match the geometry of that inserted medium.
220 */
221 static void fd_empty_seek_hack(FDrive *drv)
222 {
223 drv->last_sect = 0xFF;
224 drv->max_track = 0xFF;
225 }
226
227 static void fd_init(FDrive *drv)
228 {
229 /* Drive */
230 drv->perpendicular = 0;
231 /* Disk */
232 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
233 drv->last_sect = 0;
234 drv->max_track = 0;
235 drv->ro = true;
236 drv->media_changed = 1;
237 }
238
239 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
240
241 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
242 uint8_t last_sect, uint8_t num_sides)
243 {
244 return (((track * num_sides) + head) * last_sect) + sect - 1;
245 }
246
247 /* Returns current position, in sectors, for given drive */
248 static int fd_sector(FDrive *drv)
249 {
250 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
251 NUM_SIDES(drv));
252 }
253
254 /* Returns current position, in bytes, for given drive */
255 static int fd_offset(FDrive *drv)
256 {
257 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
258 return fd_sector(drv) << BDRV_SECTOR_BITS;
259 }
260
261 /* Seek to a new position:
262 * returns 0 if already on right track
263 * returns 1 if track changed
264 * returns 2 if track is invalid
265 * returns 3 if sector is invalid
266 * returns 4 if seek is disabled
267 */
268 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
269 int enable_seek)
270 {
271 uint32_t sector;
272 int ret;
273
274 if (track > drv->max_track ||
275 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
276 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
277 head, track, sect, 1,
278 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
279 drv->max_track, drv->last_sect);
280 return 2;
281 }
282 if (sect > drv->last_sect) {
283 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
284 head, track, sect, 1,
285 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
286 drv->max_track, drv->last_sect);
287 return 3;
288 }
289 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
290 ret = 0;
291 if (sector != fd_sector(drv)) {
292 #if 0
293 if (!enable_seek) {
294 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
295 " (max=%d %02x %02x)\n",
296 head, track, sect, 1, drv->max_track,
297 drv->last_sect);
298 return 4;
299 }
300 #endif
301 drv->head = head;
302 if (drv->track != track) {
303 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
304 drv->media_changed = 0;
305 }
306 ret = 1;
307 }
308 drv->track = track;
309 drv->sect = sect;
310 }
311
312 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
313 ret = 2;
314 }
315
316 return ret;
317 }
318
319 /* Set drive back to track 0 */
320 static void fd_recalibrate(FDrive *drv)
321 {
322 FLOPPY_DPRINTF("recalibrate\n");
323 fd_seek(drv, 0, 0, 1, 1);
324 }
325
326 /**
327 * Determine geometry based on inserted diskette.
328 * Will not operate on an empty drive.
329 *
330 * @return: 0 on success, -1 if the drive is empty.
331 */
332 static int pick_geometry(FDrive *drv)
333 {
334 BlockBackend *blk = drv->blk;
335 const FDFormat *parse;
336 uint64_t nb_sectors, size;
337 int i;
338 int match, size_match, type_match;
339 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
340
341 /* We can only pick a geometry if we have a diskette. */
342 if (!drv->blk || !blk_is_inserted(drv->blk) ||
343 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
344 {
345 return -1;
346 }
347
348 /* We need to determine the likely geometry of the inserted medium.
349 * In order of preference, we look for:
350 * (1) The same drive type and number of sectors,
351 * (2) The same diskette size and number of sectors,
352 * (3) The same drive type.
353 *
354 * In all cases, matches that occur higher in the drive table will take
355 * precedence over matches that occur later in the table.
356 */
357 blk_get_geometry(blk, &nb_sectors);
358 match = size_match = type_match = -1;
359 for (i = 0; ; i++) {
360 parse = &fd_formats[i];
361 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
362 break;
363 }
364 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
365 if (nb_sectors == size) {
366 if (magic || parse->drive == drv->drive) {
367 /* (1) perfect match -- nb_sectors and drive type */
368 goto out;
369 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
370 /* (2) size match -- nb_sectors and physical medium size */
371 match = (match == -1) ? i : match;
372 } else {
373 /* This is suspicious -- Did the user misconfigure? */
374 size_match = (size_match == -1) ? i : size_match;
375 }
376 } else if (type_match == -1) {
377 if ((parse->drive == drv->drive) ||
378 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
379 /* (3) type match -- nb_sectors mismatch, but matches the type
380 * specified explicitly by the user, or matches the fallback
381 * default type when using the drive autodetect mechanism */
382 type_match = i;
383 }
384 }
385 }
386
387 /* No exact match found */
388 if (match == -1) {
389 if (size_match != -1) {
390 parse = &fd_formats[size_match];
391 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
392 "but inserted medium appears to be a "
393 "%"PRId64" sector '%s' type\n",
394 FloppyDriveType_lookup[drv->drive],
395 nb_sectors,
396 FloppyDriveType_lookup[parse->drive]);
397 }
398 match = type_match;
399 }
400
401 /* No match of any kind found -- fd_format is misconfigured, abort. */
402 if (match == -1) {
403 error_setg(&error_abort, "No candidate geometries present in table "
404 " for floppy drive type '%s'",
405 FloppyDriveType_lookup[drv->drive]);
406 }
407
408 parse = &(fd_formats[match]);
409
410 out:
411 if (parse->max_head == 0) {
412 drv->flags &= ~FDISK_DBL_SIDES;
413 } else {
414 drv->flags |= FDISK_DBL_SIDES;
415 }
416 drv->max_track = parse->max_track;
417 drv->last_sect = parse->last_sect;
418 drv->disk = parse->drive;
419 drv->media_rate = parse->rate;
420 return 0;
421 }
422
423 static void pick_drive_type(FDrive *drv)
424 {
425 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
426 return;
427 }
428
429 if (pick_geometry(drv) == 0) {
430 drv->drive = drv->disk;
431 } else {
432 drv->drive = get_fallback_drive_type(drv);
433 }
434
435 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
436 }
437
438 /* Revalidate a disk drive after a disk change */
439 static void fd_revalidate(FDrive *drv)
440 {
441 int rc;
442
443 FLOPPY_DPRINTF("revalidate\n");
444 if (drv->blk != NULL) {
445 drv->ro = blk_is_read_only(drv->blk);
446 if (!blk_is_inserted(drv->blk)) {
447 FLOPPY_DPRINTF("No disk in drive\n");
448 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
449 fd_empty_seek_hack(drv);
450 } else if (!drv->media_validated) {
451 rc = pick_geometry(drv);
452 if (rc) {
453 FLOPPY_DPRINTF("Could not validate floppy drive media");
454 } else {
455 drv->media_validated = true;
456 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
457 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
458 drv->max_track, drv->last_sect,
459 drv->ro ? "ro" : "rw");
460 }
461 }
462 } else {
463 FLOPPY_DPRINTF("No drive connected\n");
464 drv->last_sect = 0;
465 drv->max_track = 0;
466 drv->flags &= ~FDISK_DBL_SIDES;
467 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
468 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
469 }
470 }
471
472 static void fd_change_cb(void *opaque, bool load)
473 {
474 FDrive *drive = opaque;
475
476 drive->media_changed = 1;
477 drive->media_validated = false;
478 fd_revalidate(drive);
479 }
480
481 static const BlockDevOps fd_block_ops = {
482 .change_media_cb = fd_change_cb,
483 };
484
485
486 #define TYPE_FLOPPY_DRIVE "floppy"
487 #define FLOPPY_DRIVE(obj) \
488 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
489
490 typedef struct FloppyDrive {
491 DeviceState qdev;
492 uint32_t unit;
493 BlockConf conf;
494 FloppyDriveType type;
495 } FloppyDrive;
496
497 static Property floppy_drive_properties[] = {
498 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
499 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf),
500 DEFINE_PROP_DEFAULT("drive-type", FloppyDrive, type,
501 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
502 FloppyDriveType),
503 DEFINE_PROP_END_OF_LIST(),
504 };
505
506 static int floppy_drive_init(DeviceState *qdev)
507 {
508 FloppyDrive *dev = FLOPPY_DRIVE(qdev);
509 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus);
510 FDrive *drive;
511 int ret;
512
513 if (dev->unit == -1) {
514 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
515 drive = get_drv(bus->fdc, dev->unit);
516 if (!drive->blk) {
517 break;
518 }
519 }
520 }
521
522 if (dev->unit >= MAX_FD) {
523 error_report("Can't create floppy unit %d, bus supports only %d units",
524 dev->unit, MAX_FD);
525 return -1;
526 }
527
528 drive = get_drv(bus->fdc, dev->unit);
529 if (drive->blk) {
530 error_report("Floppy unit %d is in use", dev->unit);
531 return -1;
532 }
533
534 if (!dev->conf.blk) {
535 /* Anonymous BlockBackend for an empty drive */
536 /* FIXME Use real permissions */
537 dev->conf.blk = blk_new(0, BLK_PERM_ALL);
538 ret = blk_attach_dev(dev->conf.blk, qdev);
539 assert(ret == 0);
540 }
541
542 blkconf_blocksizes(&dev->conf);
543 if (dev->conf.logical_block_size != 512 ||
544 dev->conf.physical_block_size != 512)
545 {
546 error_report("Physical and logical block size must be 512 for floppy");
547 return -1;
548 }
549
550 /* rerror/werror aren't supported by fdc and therefore not even registered
551 * with qdev. So set the defaults manually before they are used in
552 * blkconf_apply_backend_options(). */
553 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
554 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
555 blkconf_apply_backend_options(&dev->conf);
556
557 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
558 * for empty drives. */
559 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
560 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
561 error_report("fdc doesn't support drive option werror");
562 return -1;
563 }
564 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
565 error_report("fdc doesn't support drive option rerror");
566 return -1;
567 }
568
569 drive->blk = dev->conf.blk;
570 drive->fdctrl = bus->fdc;
571
572 fd_init(drive);
573 blk_set_dev_ops(drive->blk, &fd_block_ops, drive);
574
575 /* Keep 'type' qdev property and FDrive->drive in sync */
576 drive->drive = dev->type;
577 pick_drive_type(drive);
578 dev->type = drive->drive;
579
580 fd_revalidate(drive);
581
582 return 0;
583 }
584
585 static void floppy_drive_class_init(ObjectClass *klass, void *data)
586 {
587 DeviceClass *k = DEVICE_CLASS(klass);
588 k->init = floppy_drive_init;
589 set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
590 k->bus_type = TYPE_FLOPPY_BUS;
591 k->props = floppy_drive_properties;
592 k->desc = "virtual floppy drive";
593 }
594
595 static const TypeInfo floppy_drive_info = {
596 .name = TYPE_FLOPPY_DRIVE,
597 .parent = TYPE_DEVICE,
598 .instance_size = sizeof(FloppyDrive),
599 .class_init = floppy_drive_class_init,
600 };
601
602 /********************************************************/
603 /* Intel 82078 floppy disk controller emulation */
604
605 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
606 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
607 static int fdctrl_transfer_handler (void *opaque, int nchan,
608 int dma_pos, int dma_len);
609 static void fdctrl_raise_irq(FDCtrl *fdctrl);
610 static FDrive *get_cur_drv(FDCtrl *fdctrl);
611
612 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
613 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
614 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
615 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
616 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
617 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
618 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
619 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
620 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
621 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
622 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
623 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
624
625 enum {
626 FD_DIR_WRITE = 0,
627 FD_DIR_READ = 1,
628 FD_DIR_SCANE = 2,
629 FD_DIR_SCANL = 3,
630 FD_DIR_SCANH = 4,
631 FD_DIR_VERIFY = 5,
632 };
633
634 enum {
635 FD_STATE_MULTI = 0x01, /* multi track flag */
636 FD_STATE_FORMAT = 0x02, /* format flag */
637 };
638
639 enum {
640 FD_REG_SRA = 0x00,
641 FD_REG_SRB = 0x01,
642 FD_REG_DOR = 0x02,
643 FD_REG_TDR = 0x03,
644 FD_REG_MSR = 0x04,
645 FD_REG_DSR = 0x04,
646 FD_REG_FIFO = 0x05,
647 FD_REG_DIR = 0x07,
648 FD_REG_CCR = 0x07,
649 };
650
651 enum {
652 FD_CMD_READ_TRACK = 0x02,
653 FD_CMD_SPECIFY = 0x03,
654 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
655 FD_CMD_WRITE = 0x05,
656 FD_CMD_READ = 0x06,
657 FD_CMD_RECALIBRATE = 0x07,
658 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
659 FD_CMD_WRITE_DELETED = 0x09,
660 FD_CMD_READ_ID = 0x0a,
661 FD_CMD_READ_DELETED = 0x0c,
662 FD_CMD_FORMAT_TRACK = 0x0d,
663 FD_CMD_DUMPREG = 0x0e,
664 FD_CMD_SEEK = 0x0f,
665 FD_CMD_VERSION = 0x10,
666 FD_CMD_SCAN_EQUAL = 0x11,
667 FD_CMD_PERPENDICULAR_MODE = 0x12,
668 FD_CMD_CONFIGURE = 0x13,
669 FD_CMD_LOCK = 0x14,
670 FD_CMD_VERIFY = 0x16,
671 FD_CMD_POWERDOWN_MODE = 0x17,
672 FD_CMD_PART_ID = 0x18,
673 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
674 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
675 FD_CMD_SAVE = 0x2e,
676 FD_CMD_OPTION = 0x33,
677 FD_CMD_RESTORE = 0x4e,
678 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
679 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
680 FD_CMD_FORMAT_AND_WRITE = 0xcd,
681 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
682 };
683
684 enum {
685 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
686 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
687 FD_CONFIG_POLL = 0x10, /* Poll enabled */
688 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
689 FD_CONFIG_EIS = 0x40, /* No implied seeks */
690 };
691
692 enum {
693 FD_SR0_DS0 = 0x01,
694 FD_SR0_DS1 = 0x02,
695 FD_SR0_HEAD = 0x04,
696 FD_SR0_EQPMT = 0x10,
697 FD_SR0_SEEK = 0x20,
698 FD_SR0_ABNTERM = 0x40,
699 FD_SR0_INVCMD = 0x80,
700 FD_SR0_RDYCHG = 0xc0,
701 };
702
703 enum {
704 FD_SR1_MA = 0x01, /* Missing address mark */
705 FD_SR1_NW = 0x02, /* Not writable */
706 FD_SR1_EC = 0x80, /* End of cylinder */
707 };
708
709 enum {
710 FD_SR2_SNS = 0x04, /* Scan not satisfied */
711 FD_SR2_SEH = 0x08, /* Scan equal hit */
712 };
713
714 enum {
715 FD_SRA_DIR = 0x01,
716 FD_SRA_nWP = 0x02,
717 FD_SRA_nINDX = 0x04,
718 FD_SRA_HDSEL = 0x08,
719 FD_SRA_nTRK0 = 0x10,
720 FD_SRA_STEP = 0x20,
721 FD_SRA_nDRV2 = 0x40,
722 FD_SRA_INTPEND = 0x80,
723 };
724
725 enum {
726 FD_SRB_MTR0 = 0x01,
727 FD_SRB_MTR1 = 0x02,
728 FD_SRB_WGATE = 0x04,
729 FD_SRB_RDATA = 0x08,
730 FD_SRB_WDATA = 0x10,
731 FD_SRB_DR0 = 0x20,
732 };
733
734 enum {
735 #if MAX_FD == 4
736 FD_DOR_SELMASK = 0x03,
737 #else
738 FD_DOR_SELMASK = 0x01,
739 #endif
740 FD_DOR_nRESET = 0x04,
741 FD_DOR_DMAEN = 0x08,
742 FD_DOR_MOTEN0 = 0x10,
743 FD_DOR_MOTEN1 = 0x20,
744 FD_DOR_MOTEN2 = 0x40,
745 FD_DOR_MOTEN3 = 0x80,
746 };
747
748 enum {
749 #if MAX_FD == 4
750 FD_TDR_BOOTSEL = 0x0c,
751 #else
752 FD_TDR_BOOTSEL = 0x04,
753 #endif
754 };
755
756 enum {
757 FD_DSR_DRATEMASK= 0x03,
758 FD_DSR_PWRDOWN = 0x40,
759 FD_DSR_SWRESET = 0x80,
760 };
761
762 enum {
763 FD_MSR_DRV0BUSY = 0x01,
764 FD_MSR_DRV1BUSY = 0x02,
765 FD_MSR_DRV2BUSY = 0x04,
766 FD_MSR_DRV3BUSY = 0x08,
767 FD_MSR_CMDBUSY = 0x10,
768 FD_MSR_NONDMA = 0x20,
769 FD_MSR_DIO = 0x40,
770 FD_MSR_RQM = 0x80,
771 };
772
773 enum {
774 FD_DIR_DSKCHG = 0x80,
775 };
776
777 /*
778 * See chapter 5.0 "Controller phases" of the spec:
779 *
780 * Command phase:
781 * The host writes a command and its parameters into the FIFO. The command
782 * phase is completed when all parameters for the command have been supplied,
783 * and execution phase is entered.
784 *
785 * Execution phase:
786 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
787 * contains the payload now, otherwise it's unused. When all bytes of the
788 * required data have been transferred, the state is switched to either result
789 * phase (if the command produces status bytes) or directly back into the
790 * command phase for the next command.
791 *
792 * Result phase:
793 * The host reads out the FIFO, which contains one or more result bytes now.
794 */
795 enum {
796 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
797 FD_PHASE_RECONSTRUCT = 0,
798
799 FD_PHASE_COMMAND = 1,
800 FD_PHASE_EXECUTION = 2,
801 FD_PHASE_RESULT = 3,
802 };
803
804 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
805 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
806
807 struct FDCtrl {
808 MemoryRegion iomem;
809 qemu_irq irq;
810 /* Controller state */
811 QEMUTimer *result_timer;
812 int dma_chann;
813 uint8_t phase;
814 IsaDma *dma;
815 /* Controller's identification */
816 uint8_t version;
817 /* HW */
818 uint8_t sra;
819 uint8_t srb;
820 uint8_t dor;
821 uint8_t dor_vmstate; /* only used as temp during vmstate */
822 uint8_t tdr;
823 uint8_t dsr;
824 uint8_t msr;
825 uint8_t cur_drv;
826 uint8_t status0;
827 uint8_t status1;
828 uint8_t status2;
829 /* Command FIFO */
830 uint8_t *fifo;
831 int32_t fifo_size;
832 uint32_t data_pos;
833 uint32_t data_len;
834 uint8_t data_state;
835 uint8_t data_dir;
836 uint8_t eot; /* last wanted sector */
837 /* States kept only to be returned back */
838 /* precompensation */
839 uint8_t precomp_trk;
840 uint8_t config;
841 uint8_t lock;
842 /* Power down config (also with status regB access mode */
843 uint8_t pwrd;
844 /* Floppy drives */
845 FloppyBus bus;
846 uint8_t num_floppies;
847 FDrive drives[MAX_FD];
848 struct {
849 BlockBackend *blk;
850 FloppyDriveType type;
851 } qdev_for_drives[MAX_FD];
852 int reset_sensei;
853 uint32_t check_media_rate;
854 FloppyDriveType fallback; /* type=auto failure fallback */
855 /* Timers state */
856 uint8_t timer0;
857 uint8_t timer1;
858 PortioList portio_list;
859 };
860
861 static FloppyDriveType get_fallback_drive_type(FDrive *drv)
862 {
863 return drv->fdctrl->fallback;
864 }
865
866 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
867 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
868
869 typedef struct FDCtrlSysBus {
870 /*< private >*/
871 SysBusDevice parent_obj;
872 /*< public >*/
873
874 struct FDCtrl state;
875 } FDCtrlSysBus;
876
877 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
878
879 typedef struct FDCtrlISABus {
880 ISADevice parent_obj;
881
882 uint32_t iobase;
883 uint32_t irq;
884 uint32_t dma;
885 struct FDCtrl state;
886 int32_t bootindexA;
887 int32_t bootindexB;
888 } FDCtrlISABus;
889
890 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
891 {
892 FDCtrl *fdctrl = opaque;
893 uint32_t retval;
894
895 reg &= 7;
896 switch (reg) {
897 case FD_REG_SRA:
898 retval = fdctrl_read_statusA(fdctrl);
899 break;
900 case FD_REG_SRB:
901 retval = fdctrl_read_statusB(fdctrl);
902 break;
903 case FD_REG_DOR:
904 retval = fdctrl_read_dor(fdctrl);
905 break;
906 case FD_REG_TDR:
907 retval = fdctrl_read_tape(fdctrl);
908 break;
909 case FD_REG_MSR:
910 retval = fdctrl_read_main_status(fdctrl);
911 break;
912 case FD_REG_FIFO:
913 retval = fdctrl_read_data(fdctrl);
914 break;
915 case FD_REG_DIR:
916 retval = fdctrl_read_dir(fdctrl);
917 break;
918 default:
919 retval = (uint32_t)(-1);
920 break;
921 }
922 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
923
924 return retval;
925 }
926
927 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
928 {
929 FDCtrl *fdctrl = opaque;
930
931 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
932
933 reg &= 7;
934 switch (reg) {
935 case FD_REG_DOR:
936 fdctrl_write_dor(fdctrl, value);
937 break;
938 case FD_REG_TDR:
939 fdctrl_write_tape(fdctrl, value);
940 break;
941 case FD_REG_DSR:
942 fdctrl_write_rate(fdctrl, value);
943 break;
944 case FD_REG_FIFO:
945 fdctrl_write_data(fdctrl, value);
946 break;
947 case FD_REG_CCR:
948 fdctrl_write_ccr(fdctrl, value);
949 break;
950 default:
951 break;
952 }
953 }
954
955 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
956 unsigned ize)
957 {
958 return fdctrl_read(opaque, (uint32_t)reg);
959 }
960
961 static void fdctrl_write_mem (void *opaque, hwaddr reg,
962 uint64_t value, unsigned size)
963 {
964 fdctrl_write(opaque, (uint32_t)reg, value);
965 }
966
967 static const MemoryRegionOps fdctrl_mem_ops = {
968 .read = fdctrl_read_mem,
969 .write = fdctrl_write_mem,
970 .endianness = DEVICE_NATIVE_ENDIAN,
971 };
972
973 static const MemoryRegionOps fdctrl_mem_strict_ops = {
974 .read = fdctrl_read_mem,
975 .write = fdctrl_write_mem,
976 .endianness = DEVICE_NATIVE_ENDIAN,
977 .valid = {
978 .min_access_size = 1,
979 .max_access_size = 1,
980 },
981 };
982
983 static bool fdrive_media_changed_needed(void *opaque)
984 {
985 FDrive *drive = opaque;
986
987 return (drive->blk != NULL && drive->media_changed != 1);
988 }
989
990 static const VMStateDescription vmstate_fdrive_media_changed = {
991 .name = "fdrive/media_changed",
992 .version_id = 1,
993 .minimum_version_id = 1,
994 .needed = fdrive_media_changed_needed,
995 .fields = (VMStateField[]) {
996 VMSTATE_UINT8(media_changed, FDrive),
997 VMSTATE_END_OF_LIST()
998 }
999 };
1000
1001 static bool fdrive_media_rate_needed(void *opaque)
1002 {
1003 FDrive *drive = opaque;
1004
1005 return drive->fdctrl->check_media_rate;
1006 }
1007
1008 static const VMStateDescription vmstate_fdrive_media_rate = {
1009 .name = "fdrive/media_rate",
1010 .version_id = 1,
1011 .minimum_version_id = 1,
1012 .needed = fdrive_media_rate_needed,
1013 .fields = (VMStateField[]) {
1014 VMSTATE_UINT8(media_rate, FDrive),
1015 VMSTATE_END_OF_LIST()
1016 }
1017 };
1018
1019 static bool fdrive_perpendicular_needed(void *opaque)
1020 {
1021 FDrive *drive = opaque;
1022
1023 return drive->perpendicular != 0;
1024 }
1025
1026 static const VMStateDescription vmstate_fdrive_perpendicular = {
1027 .name = "fdrive/perpendicular",
1028 .version_id = 1,
1029 .minimum_version_id = 1,
1030 .needed = fdrive_perpendicular_needed,
1031 .fields = (VMStateField[]) {
1032 VMSTATE_UINT8(perpendicular, FDrive),
1033 VMSTATE_END_OF_LIST()
1034 }
1035 };
1036
1037 static int fdrive_post_load(void *opaque, int version_id)
1038 {
1039 fd_revalidate(opaque);
1040 return 0;
1041 }
1042
1043 static const VMStateDescription vmstate_fdrive = {
1044 .name = "fdrive",
1045 .version_id = 1,
1046 .minimum_version_id = 1,
1047 .post_load = fdrive_post_load,
1048 .fields = (VMStateField[]) {
1049 VMSTATE_UINT8(head, FDrive),
1050 VMSTATE_UINT8(track, FDrive),
1051 VMSTATE_UINT8(sect, FDrive),
1052 VMSTATE_END_OF_LIST()
1053 },
1054 .subsections = (const VMStateDescription*[]) {
1055 &vmstate_fdrive_media_changed,
1056 &vmstate_fdrive_media_rate,
1057 &vmstate_fdrive_perpendicular,
1058 NULL
1059 }
1060 };
1061
1062 /*
1063 * Reconstructs the phase from register values according to the logic that was
1064 * implemented in qemu 2.3. This is the default value that is used if the phase
1065 * subsection is not present on migration.
1066 *
1067 * Don't change this function to reflect newer qemu versions, it is part of
1068 * the migration ABI.
1069 */
1070 static int reconstruct_phase(FDCtrl *fdctrl)
1071 {
1072 if (fdctrl->msr & FD_MSR_NONDMA) {
1073 return FD_PHASE_EXECUTION;
1074 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
1075 /* qemu 2.3 disabled RQM only during DMA transfers */
1076 return FD_PHASE_EXECUTION;
1077 } else if (fdctrl->msr & FD_MSR_DIO) {
1078 return FD_PHASE_RESULT;
1079 } else {
1080 return FD_PHASE_COMMAND;
1081 }
1082 }
1083
1084 static void fdc_pre_save(void *opaque)
1085 {
1086 FDCtrl *s = opaque;
1087
1088 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
1089 }
1090
1091 static int fdc_pre_load(void *opaque)
1092 {
1093 FDCtrl *s = opaque;
1094 s->phase = FD_PHASE_RECONSTRUCT;
1095 return 0;
1096 }
1097
1098 static int fdc_post_load(void *opaque, int version_id)
1099 {
1100 FDCtrl *s = opaque;
1101
1102 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
1103 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
1104
1105 if (s->phase == FD_PHASE_RECONSTRUCT) {
1106 s->phase = reconstruct_phase(s);
1107 }
1108
1109 return 0;
1110 }
1111
1112 static bool fdc_reset_sensei_needed(void *opaque)
1113 {
1114 FDCtrl *s = opaque;
1115
1116 return s->reset_sensei != 0;
1117 }
1118
1119 static const VMStateDescription vmstate_fdc_reset_sensei = {
1120 .name = "fdc/reset_sensei",
1121 .version_id = 1,
1122 .minimum_version_id = 1,
1123 .needed = fdc_reset_sensei_needed,
1124 .fields = (VMStateField[]) {
1125 VMSTATE_INT32(reset_sensei, FDCtrl),
1126 VMSTATE_END_OF_LIST()
1127 }
1128 };
1129
1130 static bool fdc_result_timer_needed(void *opaque)
1131 {
1132 FDCtrl *s = opaque;
1133
1134 return timer_pending(s->result_timer);
1135 }
1136
1137 static const VMStateDescription vmstate_fdc_result_timer = {
1138 .name = "fdc/result_timer",
1139 .version_id = 1,
1140 .minimum_version_id = 1,
1141 .needed = fdc_result_timer_needed,
1142 .fields = (VMStateField[]) {
1143 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
1144 VMSTATE_END_OF_LIST()
1145 }
1146 };
1147
1148 static bool fdc_phase_needed(void *opaque)
1149 {
1150 FDCtrl *fdctrl = opaque;
1151
1152 return reconstruct_phase(fdctrl) != fdctrl->phase;
1153 }
1154
1155 static const VMStateDescription vmstate_fdc_phase = {
1156 .name = "fdc/phase",
1157 .version_id = 1,
1158 .minimum_version_id = 1,
1159 .needed = fdc_phase_needed,
1160 .fields = (VMStateField[]) {
1161 VMSTATE_UINT8(phase, FDCtrl),
1162 VMSTATE_END_OF_LIST()
1163 }
1164 };
1165
1166 static const VMStateDescription vmstate_fdc = {
1167 .name = "fdc",
1168 .version_id = 2,
1169 .minimum_version_id = 2,
1170 .pre_save = fdc_pre_save,
1171 .pre_load = fdc_pre_load,
1172 .post_load = fdc_post_load,
1173 .fields = (VMStateField[]) {
1174 /* Controller State */
1175 VMSTATE_UINT8(sra, FDCtrl),
1176 VMSTATE_UINT8(srb, FDCtrl),
1177 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1178 VMSTATE_UINT8(tdr, FDCtrl),
1179 VMSTATE_UINT8(dsr, FDCtrl),
1180 VMSTATE_UINT8(msr, FDCtrl),
1181 VMSTATE_UINT8(status0, FDCtrl),
1182 VMSTATE_UINT8(status1, FDCtrl),
1183 VMSTATE_UINT8(status2, FDCtrl),
1184 /* Command FIFO */
1185 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1186 uint8_t),
1187 VMSTATE_UINT32(data_pos, FDCtrl),
1188 VMSTATE_UINT32(data_len, FDCtrl),
1189 VMSTATE_UINT8(data_state, FDCtrl),
1190 VMSTATE_UINT8(data_dir, FDCtrl),
1191 VMSTATE_UINT8(eot, FDCtrl),
1192 /* States kept only to be returned back */
1193 VMSTATE_UINT8(timer0, FDCtrl),
1194 VMSTATE_UINT8(timer1, FDCtrl),
1195 VMSTATE_UINT8(precomp_trk, FDCtrl),
1196 VMSTATE_UINT8(config, FDCtrl),
1197 VMSTATE_UINT8(lock, FDCtrl),
1198 VMSTATE_UINT8(pwrd, FDCtrl),
1199 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
1200 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1201 vmstate_fdrive, FDrive),
1202 VMSTATE_END_OF_LIST()
1203 },
1204 .subsections = (const VMStateDescription*[]) {
1205 &vmstate_fdc_reset_sensei,
1206 &vmstate_fdc_result_timer,
1207 &vmstate_fdc_phase,
1208 NULL
1209 }
1210 };
1211
1212 static void fdctrl_external_reset_sysbus(DeviceState *d)
1213 {
1214 FDCtrlSysBus *sys = SYSBUS_FDC(d);
1215 FDCtrl *s = &sys->state;
1216
1217 fdctrl_reset(s, 0);
1218 }
1219
1220 static void fdctrl_external_reset_isa(DeviceState *d)
1221 {
1222 FDCtrlISABus *isa = ISA_FDC(d);
1223 FDCtrl *s = &isa->state;
1224
1225 fdctrl_reset(s, 0);
1226 }
1227
1228 static void fdctrl_handle_tc(void *opaque, int irq, int level)
1229 {
1230 //FDCtrl *s = opaque;
1231
1232 if (level) {
1233 // XXX
1234 FLOPPY_DPRINTF("TC pulsed\n");
1235 }
1236 }
1237
1238 /* Change IRQ state */
1239 static void fdctrl_reset_irq(FDCtrl *fdctrl)
1240 {
1241 fdctrl->status0 = 0;
1242 if (!(fdctrl->sra & FD_SRA_INTPEND))
1243 return;
1244 FLOPPY_DPRINTF("Reset interrupt\n");
1245 qemu_set_irq(fdctrl->irq, 0);
1246 fdctrl->sra &= ~FD_SRA_INTPEND;
1247 }
1248
1249 static void fdctrl_raise_irq(FDCtrl *fdctrl)
1250 {
1251 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1252 qemu_set_irq(fdctrl->irq, 1);
1253 fdctrl->sra |= FD_SRA_INTPEND;
1254 }
1255
1256 fdctrl->reset_sensei = 0;
1257 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
1258 }
1259
1260 /* Reset controller */
1261 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
1262 {
1263 int i;
1264
1265 FLOPPY_DPRINTF("reset controller\n");
1266 fdctrl_reset_irq(fdctrl);
1267 /* Initialise controller */
1268 fdctrl->sra = 0;
1269 fdctrl->srb = 0xc0;
1270 if (!fdctrl->drives[1].blk) {
1271 fdctrl->sra |= FD_SRA_nDRV2;
1272 }
1273 fdctrl->cur_drv = 0;
1274 fdctrl->dor = FD_DOR_nRESET;
1275 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
1276 fdctrl->msr = FD_MSR_RQM;
1277 fdctrl->reset_sensei = 0;
1278 timer_del(fdctrl->result_timer);
1279 /* FIFO state */
1280 fdctrl->data_pos = 0;
1281 fdctrl->data_len = 0;
1282 fdctrl->data_state = 0;
1283 fdctrl->data_dir = FD_DIR_WRITE;
1284 for (i = 0; i < MAX_FD; i++)
1285 fd_recalibrate(&fdctrl->drives[i]);
1286 fdctrl_to_command_phase(fdctrl);
1287 if (do_irq) {
1288 fdctrl->status0 |= FD_SR0_RDYCHG;
1289 fdctrl_raise_irq(fdctrl);
1290 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
1291 }
1292 }
1293
1294 static inline FDrive *drv0(FDCtrl *fdctrl)
1295 {
1296 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1297 }
1298
1299 static inline FDrive *drv1(FDCtrl *fdctrl)
1300 {
1301 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1302 return &fdctrl->drives[1];
1303 else
1304 return &fdctrl->drives[0];
1305 }
1306
1307 #if MAX_FD == 4
1308 static inline FDrive *drv2(FDCtrl *fdctrl)
1309 {
1310 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1311 return &fdctrl->drives[2];
1312 else
1313 return &fdctrl->drives[1];
1314 }
1315
1316 static inline FDrive *drv3(FDCtrl *fdctrl)
1317 {
1318 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1319 return &fdctrl->drives[3];
1320 else
1321 return &fdctrl->drives[2];
1322 }
1323 #endif
1324
1325 static FDrive *get_drv(FDCtrl *fdctrl, int unit)
1326 {
1327 switch (unit) {
1328 case 0: return drv0(fdctrl);
1329 case 1: return drv1(fdctrl);
1330 #if MAX_FD == 4
1331 case 2: return drv2(fdctrl);
1332 case 3: return drv3(fdctrl);
1333 #endif
1334 default: return NULL;
1335 }
1336 }
1337
1338 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1339 {
1340 return get_drv(fdctrl, fdctrl->cur_drv);
1341 }
1342
1343 /* Status A register : 0x00 (read-only) */
1344 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1345 {
1346 uint32_t retval = fdctrl->sra;
1347
1348 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1349
1350 return retval;
1351 }
1352
1353 /* Status B register : 0x01 (read-only) */
1354 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1355 {
1356 uint32_t retval = fdctrl->srb;
1357
1358 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1359
1360 return retval;
1361 }
1362
1363 /* Digital output register : 0x02 */
1364 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1365 {
1366 uint32_t retval = fdctrl->dor;
1367
1368 /* Selected drive */
1369 retval |= fdctrl->cur_drv;
1370 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1371
1372 return retval;
1373 }
1374
1375 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1376 {
1377 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1378
1379 /* Motors */
1380 if (value & FD_DOR_MOTEN0)
1381 fdctrl->srb |= FD_SRB_MTR0;
1382 else
1383 fdctrl->srb &= ~FD_SRB_MTR0;
1384 if (value & FD_DOR_MOTEN1)
1385 fdctrl->srb |= FD_SRB_MTR1;
1386 else
1387 fdctrl->srb &= ~FD_SRB_MTR1;
1388
1389 /* Drive */
1390 if (value & 1)
1391 fdctrl->srb |= FD_SRB_DR0;
1392 else
1393 fdctrl->srb &= ~FD_SRB_DR0;
1394
1395 /* Reset */
1396 if (!(value & FD_DOR_nRESET)) {
1397 if (fdctrl->dor & FD_DOR_nRESET) {
1398 FLOPPY_DPRINTF("controller enter RESET state\n");
1399 }
1400 } else {
1401 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1402 FLOPPY_DPRINTF("controller out of RESET state\n");
1403 fdctrl_reset(fdctrl, 1);
1404 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1405 }
1406 }
1407 /* Selected drive */
1408 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1409
1410 fdctrl->dor = value;
1411 }
1412
1413 /* Tape drive register : 0x03 */
1414 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1415 {
1416 uint32_t retval = fdctrl->tdr;
1417
1418 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1419
1420 return retval;
1421 }
1422
1423 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1424 {
1425 /* Reset mode */
1426 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1427 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1428 return;
1429 }
1430 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1431 /* Disk boot selection indicator */
1432 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1433 /* Tape indicators: never allow */
1434 }
1435
1436 /* Main status register : 0x04 (read) */
1437 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1438 {
1439 uint32_t retval = fdctrl->msr;
1440
1441 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1442 fdctrl->dor |= FD_DOR_nRESET;
1443
1444 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1445
1446 return retval;
1447 }
1448
1449 /* Data select rate register : 0x04 (write) */
1450 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1451 {
1452 /* Reset mode */
1453 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1454 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1455 return;
1456 }
1457 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1458 /* Reset: autoclear */
1459 if (value & FD_DSR_SWRESET) {
1460 fdctrl->dor &= ~FD_DOR_nRESET;
1461 fdctrl_reset(fdctrl, 1);
1462 fdctrl->dor |= FD_DOR_nRESET;
1463 }
1464 if (value & FD_DSR_PWRDOWN) {
1465 fdctrl_reset(fdctrl, 1);
1466 }
1467 fdctrl->dsr = value;
1468 }
1469
1470 /* Configuration control register: 0x07 (write) */
1471 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1472 {
1473 /* Reset mode */
1474 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1475 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1476 return;
1477 }
1478 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1479
1480 /* Only the rate selection bits used in AT mode, and we
1481 * store those in the DSR.
1482 */
1483 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1484 (value & FD_DSR_DRATEMASK);
1485 }
1486
1487 static int fdctrl_media_changed(FDrive *drv)
1488 {
1489 return drv->media_changed;
1490 }
1491
1492 /* Digital input register : 0x07 (read-only) */
1493 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1494 {
1495 uint32_t retval = 0;
1496
1497 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1498 retval |= FD_DIR_DSKCHG;
1499 }
1500 if (retval != 0) {
1501 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1502 }
1503
1504 return retval;
1505 }
1506
1507 /* Clear the FIFO and update the state for receiving the next command */
1508 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1509 {
1510 fdctrl->phase = FD_PHASE_COMMAND;
1511 fdctrl->data_dir = FD_DIR_WRITE;
1512 fdctrl->data_pos = 0;
1513 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1514 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1515 fdctrl->msr |= FD_MSR_RQM;
1516 }
1517
1518 /* Update the state to allow the guest to read out the command status.
1519 * @fifo_len is the number of result bytes to be read out. */
1520 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1521 {
1522 fdctrl->phase = FD_PHASE_RESULT;
1523 fdctrl->data_dir = FD_DIR_READ;
1524 fdctrl->data_len = fifo_len;
1525 fdctrl->data_pos = 0;
1526 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1527 }
1528
1529 /* Set an error: unimplemented/unknown command */
1530 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1531 {
1532 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1533 fdctrl->fifo[0]);
1534 fdctrl->fifo[0] = FD_SR0_INVCMD;
1535 fdctrl_to_result_phase(fdctrl, 1);
1536 }
1537
1538 /* Seek to next sector
1539 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1540 * otherwise returns 1
1541 */
1542 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1543 {
1544 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1545 cur_drv->head, cur_drv->track, cur_drv->sect,
1546 fd_sector(cur_drv));
1547 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1548 error in fact */
1549 uint8_t new_head = cur_drv->head;
1550 uint8_t new_track = cur_drv->track;
1551 uint8_t new_sect = cur_drv->sect;
1552
1553 int ret = 1;
1554
1555 if (new_sect >= cur_drv->last_sect ||
1556 new_sect == fdctrl->eot) {
1557 new_sect = 1;
1558 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1559 if (new_head == 0 &&
1560 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1561 new_head = 1;
1562 } else {
1563 new_head = 0;
1564 new_track++;
1565 fdctrl->status0 |= FD_SR0_SEEK;
1566 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1567 ret = 0;
1568 }
1569 }
1570 } else {
1571 fdctrl->status0 |= FD_SR0_SEEK;
1572 new_track++;
1573 ret = 0;
1574 }
1575 if (ret == 1) {
1576 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1577 new_head, new_track, new_sect, fd_sector(cur_drv));
1578 }
1579 } else {
1580 new_sect++;
1581 }
1582 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1583 return ret;
1584 }
1585
1586 /* Callback for transfer end (stop or abort) */
1587 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1588 uint8_t status1, uint8_t status2)
1589 {
1590 FDrive *cur_drv;
1591 cur_drv = get_cur_drv(fdctrl);
1592
1593 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1594 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1595 if (cur_drv->head) {
1596 fdctrl->status0 |= FD_SR0_HEAD;
1597 }
1598 fdctrl->status0 |= status0;
1599
1600 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1601 status0, status1, status2, fdctrl->status0);
1602 fdctrl->fifo[0] = fdctrl->status0;
1603 fdctrl->fifo[1] = status1;
1604 fdctrl->fifo[2] = status2;
1605 fdctrl->fifo[3] = cur_drv->track;
1606 fdctrl->fifo[4] = cur_drv->head;
1607 fdctrl->fifo[5] = cur_drv->sect;
1608 fdctrl->fifo[6] = FD_SECTOR_SC;
1609 fdctrl->data_dir = FD_DIR_READ;
1610 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1611 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1612 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
1613 }
1614 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1615 fdctrl->msr &= ~FD_MSR_NONDMA;
1616
1617 fdctrl_to_result_phase(fdctrl, 7);
1618 fdctrl_raise_irq(fdctrl);
1619 }
1620
1621 /* Prepare a data transfer (either DMA or FIFO) */
1622 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1623 {
1624 FDrive *cur_drv;
1625 uint8_t kh, kt, ks;
1626
1627 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1628 cur_drv = get_cur_drv(fdctrl);
1629 kt = fdctrl->fifo[2];
1630 kh = fdctrl->fifo[3];
1631 ks = fdctrl->fifo[4];
1632 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1633 GET_CUR_DRV(fdctrl), kh, kt, ks,
1634 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1635 NUM_SIDES(cur_drv)));
1636 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1637 case 2:
1638 /* sect too big */
1639 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1640 fdctrl->fifo[3] = kt;
1641 fdctrl->fifo[4] = kh;
1642 fdctrl->fifo[5] = ks;
1643 return;
1644 case 3:
1645 /* track too big */
1646 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1647 fdctrl->fifo[3] = kt;
1648 fdctrl->fifo[4] = kh;
1649 fdctrl->fifo[5] = ks;
1650 return;
1651 case 4:
1652 /* No seek enabled */
1653 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1654 fdctrl->fifo[3] = kt;
1655 fdctrl->fifo[4] = kh;
1656 fdctrl->fifo[5] = ks;
1657 return;
1658 case 1:
1659 fdctrl->status0 |= FD_SR0_SEEK;
1660 break;
1661 default:
1662 break;
1663 }
1664
1665 /* Check the data rate. If the programmed data rate does not match
1666 * the currently inserted medium, the operation has to fail. */
1667 if (fdctrl->check_media_rate &&
1668 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1669 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1670 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1671 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1672 fdctrl->fifo[3] = kt;
1673 fdctrl->fifo[4] = kh;
1674 fdctrl->fifo[5] = ks;
1675 return;
1676 }
1677
1678 /* Set the FIFO state */
1679 fdctrl->data_dir = direction;
1680 fdctrl->data_pos = 0;
1681 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1682 if (fdctrl->fifo[0] & 0x80)
1683 fdctrl->data_state |= FD_STATE_MULTI;
1684 else
1685 fdctrl->data_state &= ~FD_STATE_MULTI;
1686 if (fdctrl->fifo[5] == 0) {
1687 fdctrl->data_len = fdctrl->fifo[8];
1688 } else {
1689 int tmp;
1690 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1691 tmp = (fdctrl->fifo[6] - ks + 1);
1692 if (fdctrl->fifo[0] & 0x80)
1693 tmp += fdctrl->fifo[6];
1694 fdctrl->data_len *= tmp;
1695 }
1696 fdctrl->eot = fdctrl->fifo[6];
1697 if (fdctrl->dor & FD_DOR_DMAEN) {
1698 IsaDmaTransferMode dma_mode;
1699 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1700 bool dma_mode_ok;
1701 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1702 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
1703 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1704 dma_mode, direction,
1705 (128 << fdctrl->fifo[5]) *
1706 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1707 switch (direction) {
1708 case FD_DIR_SCANE:
1709 case FD_DIR_SCANL:
1710 case FD_DIR_SCANH:
1711 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1712 break;
1713 case FD_DIR_WRITE:
1714 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1715 break;
1716 case FD_DIR_READ:
1717 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1718 break;
1719 case FD_DIR_VERIFY:
1720 dma_mode_ok = true;
1721 break;
1722 default:
1723 dma_mode_ok = false;
1724 break;
1725 }
1726 if (dma_mode_ok) {
1727 /* No access is allowed until DMA transfer has completed */
1728 fdctrl->msr &= ~FD_MSR_RQM;
1729 if (direction != FD_DIR_VERIFY) {
1730 /* Now, we just have to wait for the DMA controller to
1731 * recall us...
1732 */
1733 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1734 k->schedule(fdctrl->dma);
1735 } else {
1736 /* Start transfer */
1737 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1738 fdctrl->data_len);
1739 }
1740 return;
1741 } else {
1742 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1743 direction);
1744 }
1745 }
1746 FLOPPY_DPRINTF("start non-DMA transfer\n");
1747 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1748 if (direction != FD_DIR_WRITE)
1749 fdctrl->msr |= FD_MSR_DIO;
1750 /* IO based transfer: calculate len */
1751 fdctrl_raise_irq(fdctrl);
1752 }
1753
1754 /* Prepare a transfer of deleted data */
1755 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1756 {
1757 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1758
1759 /* We don't handle deleted data,
1760 * so we don't return *ANYTHING*
1761 */
1762 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1763 }
1764
1765 /* handlers for DMA transfers */
1766 static int fdctrl_transfer_handler (void *opaque, int nchan,
1767 int dma_pos, int dma_len)
1768 {
1769 FDCtrl *fdctrl;
1770 FDrive *cur_drv;
1771 int len, start_pos, rel_pos;
1772 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1773 IsaDmaClass *k;
1774
1775 fdctrl = opaque;
1776 if (fdctrl->msr & FD_MSR_RQM) {
1777 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1778 return 0;
1779 }
1780 k = ISADMA_GET_CLASS(fdctrl->dma);
1781 cur_drv = get_cur_drv(fdctrl);
1782 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1783 fdctrl->data_dir == FD_DIR_SCANH)
1784 status2 = FD_SR2_SNS;
1785 if (dma_len > fdctrl->data_len)
1786 dma_len = fdctrl->data_len;
1787 if (cur_drv->blk == NULL) {
1788 if (fdctrl->data_dir == FD_DIR_WRITE)
1789 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1790 else
1791 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1792 len = 0;
1793 goto transfer_error;
1794 }
1795 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1796 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1797 len = dma_len - fdctrl->data_pos;
1798 if (len + rel_pos > FD_SECTOR_LEN)
1799 len = FD_SECTOR_LEN - rel_pos;
1800 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1801 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1802 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1803 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1804 fd_sector(cur_drv) * FD_SECTOR_LEN);
1805 if (fdctrl->data_dir != FD_DIR_WRITE ||
1806 len < FD_SECTOR_LEN || rel_pos != 0) {
1807 /* READ & SCAN commands and realign to a sector for WRITE */
1808 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1809 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
1810 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1811 fd_sector(cur_drv));
1812 /* Sure, image size is too small... */
1813 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1814 }
1815 }
1816 switch (fdctrl->data_dir) {
1817 case FD_DIR_READ:
1818 /* READ commands */
1819 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1820 fdctrl->data_pos, len);
1821 break;
1822 case FD_DIR_WRITE:
1823 /* WRITE commands */
1824 if (cur_drv->ro) {
1825 /* Handle readonly medium early, no need to do DMA, touch the
1826 * LED or attempt any writes. A real floppy doesn't attempt
1827 * to write to readonly media either. */
1828 fdctrl_stop_transfer(fdctrl,
1829 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1830 0x00);
1831 goto transfer_error;
1832 }
1833
1834 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1835 fdctrl->data_pos, len);
1836 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1837 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
1838 FLOPPY_DPRINTF("error writing sector %d\n",
1839 fd_sector(cur_drv));
1840 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1841 goto transfer_error;
1842 }
1843 break;
1844 case FD_DIR_VERIFY:
1845 /* VERIFY commands */
1846 break;
1847 default:
1848 /* SCAN commands */
1849 {
1850 uint8_t tmpbuf[FD_SECTOR_LEN];
1851 int ret;
1852 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1853 len);
1854 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1855 if (ret == 0) {
1856 status2 = FD_SR2_SEH;
1857 goto end_transfer;
1858 }
1859 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1860 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1861 status2 = 0x00;
1862 goto end_transfer;
1863 }
1864 }
1865 break;
1866 }
1867 fdctrl->data_pos += len;
1868 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1869 if (rel_pos == 0) {
1870 /* Seek to next sector */
1871 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1872 break;
1873 }
1874 }
1875 end_transfer:
1876 len = fdctrl->data_pos - start_pos;
1877 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1878 fdctrl->data_pos, len, fdctrl->data_len);
1879 if (fdctrl->data_dir == FD_DIR_SCANE ||
1880 fdctrl->data_dir == FD_DIR_SCANL ||
1881 fdctrl->data_dir == FD_DIR_SCANH)
1882 status2 = FD_SR2_SEH;
1883 fdctrl->data_len -= len;
1884 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1885 transfer_error:
1886
1887 return len;
1888 }
1889
1890 /* Data register : 0x05 */
1891 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1892 {
1893 FDrive *cur_drv;
1894 uint32_t retval = 0;
1895 uint32_t pos;
1896
1897 cur_drv = get_cur_drv(fdctrl);
1898 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1899 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1900 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1901 return 0;
1902 }
1903
1904 /* If data_len spans multiple sectors, the current position in the FIFO
1905 * wraps around while fdctrl->data_pos is the real position in the whole
1906 * request. */
1907 pos = fdctrl->data_pos;
1908 pos %= FD_SECTOR_LEN;
1909
1910 switch (fdctrl->phase) {
1911 case FD_PHASE_EXECUTION:
1912 assert(fdctrl->msr & FD_MSR_NONDMA);
1913 if (pos == 0) {
1914 if (fdctrl->data_pos != 0)
1915 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1916 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1917 fd_sector(cur_drv));
1918 return 0;
1919 }
1920 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1921 BDRV_SECTOR_SIZE)
1922 < 0) {
1923 FLOPPY_DPRINTF("error getting sector %d\n",
1924 fd_sector(cur_drv));
1925 /* Sure, image size is too small... */
1926 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1927 }
1928 }
1929
1930 if (++fdctrl->data_pos == fdctrl->data_len) {
1931 fdctrl->msr &= ~FD_MSR_RQM;
1932 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1933 }
1934 break;
1935
1936 case FD_PHASE_RESULT:
1937 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1938 if (++fdctrl->data_pos == fdctrl->data_len) {
1939 fdctrl->msr &= ~FD_MSR_RQM;
1940 fdctrl_to_command_phase(fdctrl);
1941 fdctrl_reset_irq(fdctrl);
1942 }
1943 break;
1944
1945 case FD_PHASE_COMMAND:
1946 default:
1947 abort();
1948 }
1949
1950 retval = fdctrl->fifo[pos];
1951 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1952
1953 return retval;
1954 }
1955
1956 static void fdctrl_format_sector(FDCtrl *fdctrl)
1957 {
1958 FDrive *cur_drv;
1959 uint8_t kh, kt, ks;
1960
1961 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1962 cur_drv = get_cur_drv(fdctrl);
1963 kt = fdctrl->fifo[6];
1964 kh = fdctrl->fifo[7];
1965 ks = fdctrl->fifo[8];
1966 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1967 GET_CUR_DRV(fdctrl), kh, kt, ks,
1968 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1969 NUM_SIDES(cur_drv)));
1970 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1971 case 2:
1972 /* sect too big */
1973 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1974 fdctrl->fifo[3] = kt;
1975 fdctrl->fifo[4] = kh;
1976 fdctrl->fifo[5] = ks;
1977 return;
1978 case 3:
1979 /* track too big */
1980 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1981 fdctrl->fifo[3] = kt;
1982 fdctrl->fifo[4] = kh;
1983 fdctrl->fifo[5] = ks;
1984 return;
1985 case 4:
1986 /* No seek enabled */
1987 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1988 fdctrl->fifo[3] = kt;
1989 fdctrl->fifo[4] = kh;
1990 fdctrl->fifo[5] = ks;
1991 return;
1992 case 1:
1993 fdctrl->status0 |= FD_SR0_SEEK;
1994 break;
1995 default:
1996 break;
1997 }
1998 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1999 if (cur_drv->blk == NULL ||
2000 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2001 BDRV_SECTOR_SIZE, 0) < 0) {
2002 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
2003 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
2004 } else {
2005 if (cur_drv->sect == cur_drv->last_sect) {
2006 fdctrl->data_state &= ~FD_STATE_FORMAT;
2007 /* Last sector done */
2008 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2009 } else {
2010 /* More to do */
2011 fdctrl->data_pos = 0;
2012 fdctrl->data_len = 4;
2013 }
2014 }
2015 }
2016
2017 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
2018 {
2019 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
2020 fdctrl->fifo[0] = fdctrl->lock << 4;
2021 fdctrl_to_result_phase(fdctrl, 1);
2022 }
2023
2024 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
2025 {
2026 FDrive *cur_drv = get_cur_drv(fdctrl);
2027
2028 /* Drives position */
2029 fdctrl->fifo[0] = drv0(fdctrl)->track;
2030 fdctrl->fifo[1] = drv1(fdctrl)->track;
2031 #if MAX_FD == 4
2032 fdctrl->fifo[2] = drv2(fdctrl)->track;
2033 fdctrl->fifo[3] = drv3(fdctrl)->track;
2034 #else
2035 fdctrl->fifo[2] = 0;
2036 fdctrl->fifo[3] = 0;
2037 #endif
2038 /* timers */
2039 fdctrl->fifo[4] = fdctrl->timer0;
2040 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
2041 fdctrl->fifo[6] = cur_drv->last_sect;
2042 fdctrl->fifo[7] = (fdctrl->lock << 7) |
2043 (cur_drv->perpendicular << 2);
2044 fdctrl->fifo[8] = fdctrl->config;
2045 fdctrl->fifo[9] = fdctrl->precomp_trk;
2046 fdctrl_to_result_phase(fdctrl, 10);
2047 }
2048
2049 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
2050 {
2051 /* Controller's version */
2052 fdctrl->fifo[0] = fdctrl->version;
2053 fdctrl_to_result_phase(fdctrl, 1);
2054 }
2055
2056 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
2057 {
2058 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
2059 fdctrl_to_result_phase(fdctrl, 1);
2060 }
2061
2062 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
2063 {
2064 FDrive *cur_drv = get_cur_drv(fdctrl);
2065
2066 /* Drives position */
2067 drv0(fdctrl)->track = fdctrl->fifo[3];
2068 drv1(fdctrl)->track = fdctrl->fifo[4];
2069 #if MAX_FD == 4
2070 drv2(fdctrl)->track = fdctrl->fifo[5];
2071 drv3(fdctrl)->track = fdctrl->fifo[6];
2072 #endif
2073 /* timers */
2074 fdctrl->timer0 = fdctrl->fifo[7];
2075 fdctrl->timer1 = fdctrl->fifo[8];
2076 cur_drv->last_sect = fdctrl->fifo[9];
2077 fdctrl->lock = fdctrl->fifo[10] >> 7;
2078 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
2079 fdctrl->config = fdctrl->fifo[11];
2080 fdctrl->precomp_trk = fdctrl->fifo[12];
2081 fdctrl->pwrd = fdctrl->fifo[13];
2082 fdctrl_to_command_phase(fdctrl);
2083 }
2084
2085 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
2086 {
2087 FDrive *cur_drv = get_cur_drv(fdctrl);
2088
2089 fdctrl->fifo[0] = 0;
2090 fdctrl->fifo[1] = 0;
2091 /* Drives position */
2092 fdctrl->fifo[2] = drv0(fdctrl)->track;
2093 fdctrl->fifo[3] = drv1(fdctrl)->track;
2094 #if MAX_FD == 4
2095 fdctrl->fifo[4] = drv2(fdctrl)->track;
2096 fdctrl->fifo[5] = drv3(fdctrl)->track;
2097 #else
2098 fdctrl->fifo[4] = 0;
2099 fdctrl->fifo[5] = 0;
2100 #endif
2101 /* timers */
2102 fdctrl->fifo[6] = fdctrl->timer0;
2103 fdctrl->fifo[7] = fdctrl->timer1;
2104 fdctrl->fifo[8] = cur_drv->last_sect;
2105 fdctrl->fifo[9] = (fdctrl->lock << 7) |
2106 (cur_drv->perpendicular << 2);
2107 fdctrl->fifo[10] = fdctrl->config;
2108 fdctrl->fifo[11] = fdctrl->precomp_trk;
2109 fdctrl->fifo[12] = fdctrl->pwrd;
2110 fdctrl->fifo[13] = 0;
2111 fdctrl->fifo[14] = 0;
2112 fdctrl_to_result_phase(fdctrl, 15);
2113 }
2114
2115 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
2116 {
2117 FDrive *cur_drv = get_cur_drv(fdctrl);
2118
2119 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2120 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2121 (NANOSECONDS_PER_SECOND / 50));
2122 }
2123
2124 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
2125 {
2126 FDrive *cur_drv;
2127
2128 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2129 cur_drv = get_cur_drv(fdctrl);
2130 fdctrl->data_state |= FD_STATE_FORMAT;
2131 if (fdctrl->fifo[0] & 0x80)
2132 fdctrl->data_state |= FD_STATE_MULTI;
2133 else
2134 fdctrl->data_state &= ~FD_STATE_MULTI;
2135 cur_drv->bps =
2136 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
2137 #if 0
2138 cur_drv->last_sect =
2139 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
2140 fdctrl->fifo[3] / 2;
2141 #else
2142 cur_drv->last_sect = fdctrl->fifo[3];
2143 #endif
2144 /* TODO: implement format using DMA expected by the Bochs BIOS
2145 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2146 * the sector with the specified fill byte
2147 */
2148 fdctrl->data_state &= ~FD_STATE_FORMAT;
2149 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2150 }
2151
2152 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
2153 {
2154 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2155 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
2156 if (fdctrl->fifo[2] & 1)
2157 fdctrl->dor &= ~FD_DOR_DMAEN;
2158 else
2159 fdctrl->dor |= FD_DOR_DMAEN;
2160 /* No result back */
2161 fdctrl_to_command_phase(fdctrl);
2162 }
2163
2164 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
2165 {
2166 FDrive *cur_drv;
2167
2168 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2169 cur_drv = get_cur_drv(fdctrl);
2170 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2171 /* 1 Byte status back */
2172 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2173 (cur_drv->track == 0 ? 0x10 : 0x00) |
2174 (cur_drv->head << 2) |
2175 GET_CUR_DRV(fdctrl) |
2176 0x28;
2177 fdctrl_to_result_phase(fdctrl, 1);
2178 }
2179
2180 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
2181 {
2182 FDrive *cur_drv;
2183
2184 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2185 cur_drv = get_cur_drv(fdctrl);
2186 fd_recalibrate(cur_drv);
2187 fdctrl_to_command_phase(fdctrl);
2188 /* Raise Interrupt */
2189 fdctrl->status0 |= FD_SR0_SEEK;
2190 fdctrl_raise_irq(fdctrl);
2191 }
2192
2193 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
2194 {
2195 FDrive *cur_drv = get_cur_drv(fdctrl);
2196
2197 if (fdctrl->reset_sensei > 0) {
2198 fdctrl->fifo[0] =
2199 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2200 fdctrl->reset_sensei--;
2201 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2202 fdctrl->fifo[0] = FD_SR0_INVCMD;
2203 fdctrl_to_result_phase(fdctrl, 1);
2204 return;
2205 } else {
2206 fdctrl->fifo[0] =
2207 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2208 | GET_CUR_DRV(fdctrl);
2209 }
2210
2211 fdctrl->fifo[1] = cur_drv->track;
2212 fdctrl_to_result_phase(fdctrl, 2);
2213 fdctrl_reset_irq(fdctrl);
2214 fdctrl->status0 = FD_SR0_RDYCHG;
2215 }
2216
2217 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
2218 {
2219 FDrive *cur_drv;
2220
2221 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2222 cur_drv = get_cur_drv(fdctrl);
2223 fdctrl_to_command_phase(fdctrl);
2224 /* The seek command just sends step pulses to the drive and doesn't care if
2225 * there is a medium inserted of if it's banging the head against the drive.
2226 */
2227 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
2228 /* Raise Interrupt */
2229 fdctrl->status0 |= FD_SR0_SEEK;
2230 fdctrl_raise_irq(fdctrl);
2231 }
2232
2233 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
2234 {
2235 FDrive *cur_drv = get_cur_drv(fdctrl);
2236
2237 if (fdctrl->fifo[1] & 0x80)
2238 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2239 /* No result back */
2240 fdctrl_to_command_phase(fdctrl);
2241 }
2242
2243 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
2244 {
2245 fdctrl->config = fdctrl->fifo[2];
2246 fdctrl->precomp_trk = fdctrl->fifo[3];
2247 /* No result back */
2248 fdctrl_to_command_phase(fdctrl);
2249 }
2250
2251 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
2252 {
2253 fdctrl->pwrd = fdctrl->fifo[1];
2254 fdctrl->fifo[0] = fdctrl->fifo[1];
2255 fdctrl_to_result_phase(fdctrl, 1);
2256 }
2257
2258 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
2259 {
2260 /* No result back */
2261 fdctrl_to_command_phase(fdctrl);
2262 }
2263
2264 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
2265 {
2266 FDrive *cur_drv = get_cur_drv(fdctrl);
2267 uint32_t pos;
2268
2269 pos = fdctrl->data_pos - 1;
2270 pos %= FD_SECTOR_LEN;
2271 if (fdctrl->fifo[pos] & 0x80) {
2272 /* Command parameters done */
2273 if (fdctrl->fifo[pos] & 0x40) {
2274 fdctrl->fifo[0] = fdctrl->fifo[1];
2275 fdctrl->fifo[2] = 0;
2276 fdctrl->fifo[3] = 0;
2277 fdctrl_to_result_phase(fdctrl, 4);
2278 } else {
2279 fdctrl_to_command_phase(fdctrl);
2280 }
2281 } else if (fdctrl->data_len > 7) {
2282 /* ERROR */
2283 fdctrl->fifo[0] = 0x80 |
2284 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
2285 fdctrl_to_result_phase(fdctrl, 1);
2286 }
2287 }
2288
2289 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
2290 {
2291 FDrive *cur_drv;
2292
2293 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2294 cur_drv = get_cur_drv(fdctrl);
2295 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
2296 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2297 cur_drv->sect, 1);
2298 } else {
2299 fd_seek(cur_drv, cur_drv->head,
2300 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
2301 }
2302 fdctrl_to_command_phase(fdctrl);
2303 /* Raise Interrupt */
2304 fdctrl->status0 |= FD_SR0_SEEK;
2305 fdctrl_raise_irq(fdctrl);
2306 }
2307
2308 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
2309 {
2310 FDrive *cur_drv;
2311
2312 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2313 cur_drv = get_cur_drv(fdctrl);
2314 if (fdctrl->fifo[2] > cur_drv->track) {
2315 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
2316 } else {
2317 fd_seek(cur_drv, cur_drv->head,
2318 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
2319 }
2320 fdctrl_to_command_phase(fdctrl);
2321 /* Raise Interrupt */
2322 fdctrl->status0 |= FD_SR0_SEEK;
2323 fdctrl_raise_irq(fdctrl);
2324 }
2325
2326 /*
2327 * Handlers for the execution phase of each command
2328 */
2329 typedef struct FDCtrlCommand {
2330 uint8_t value;
2331 uint8_t mask;
2332 const char* name;
2333 int parameters;
2334 void (*handler)(FDCtrl *fdctrl, int direction);
2335 int direction;
2336 } FDCtrlCommand;
2337
2338 static const FDCtrlCommand handlers[] = {
2339 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2340 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2341 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2342 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2343 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2344 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2345 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2346 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2347 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2348 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2349 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2350 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2351 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2352 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2353 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2354 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2355 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2356 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2357 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2358 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2359 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2360 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2361 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2362 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2363 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2364 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2365 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2366 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2367 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2368 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2369 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2370 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2371 };
2372 /* Associate command to an index in the 'handlers' array */
2373 static uint8_t command_to_handler[256];
2374
2375 static const FDCtrlCommand *get_command(uint8_t cmd)
2376 {
2377 int idx;
2378
2379 idx = command_to_handler[cmd];
2380 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2381 return &handlers[idx];
2382 }
2383
2384 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2385 {
2386 FDrive *cur_drv;
2387 const FDCtrlCommand *cmd;
2388 uint32_t pos;
2389
2390 /* Reset mode */
2391 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2392 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2393 return;
2394 }
2395 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2396 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2397 return;
2398 }
2399 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2400
2401 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2402
2403 /* If data_len spans multiple sectors, the current position in the FIFO
2404 * wraps around while fdctrl->data_pos is the real position in the whole
2405 * request. */
2406 pos = fdctrl->data_pos++;
2407 pos %= FD_SECTOR_LEN;
2408 fdctrl->fifo[pos] = value;
2409
2410 if (fdctrl->data_pos == fdctrl->data_len) {
2411 fdctrl->msr &= ~FD_MSR_RQM;
2412 }
2413
2414 switch (fdctrl->phase) {
2415 case FD_PHASE_EXECUTION:
2416 /* For DMA requests, RQM should be cleared during execution phase, so
2417 * we would have errored out above. */
2418 assert(fdctrl->msr & FD_MSR_NONDMA);
2419
2420 /* FIFO data write */
2421 if (pos == FD_SECTOR_LEN - 1 ||
2422 fdctrl->data_pos == fdctrl->data_len) {
2423 cur_drv = get_cur_drv(fdctrl);
2424 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2425 BDRV_SECTOR_SIZE, 0) < 0) {
2426 FLOPPY_DPRINTF("error writing sector %d\n",
2427 fd_sector(cur_drv));
2428 break;
2429 }
2430 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2431 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2432 fd_sector(cur_drv));
2433 break;
2434 }
2435 }
2436
2437 /* Switch to result phase when done with the transfer */
2438 if (fdctrl->data_pos == fdctrl->data_len) {
2439 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2440 }
2441 break;
2442
2443 case FD_PHASE_COMMAND:
2444 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2445 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2446
2447 if (pos == 0) {
2448 /* The first byte specifies the command. Now we start reading
2449 * as many parameters as this command requires. */
2450 cmd = get_command(value);
2451 fdctrl->data_len = cmd->parameters + 1;
2452 if (cmd->parameters) {
2453 fdctrl->msr |= FD_MSR_RQM;
2454 }
2455 fdctrl->msr |= FD_MSR_CMDBUSY;
2456 }
2457
2458 if (fdctrl->data_pos == fdctrl->data_len) {
2459 /* We have all parameters now, execute the command */
2460 fdctrl->phase = FD_PHASE_EXECUTION;
2461
2462 if (fdctrl->data_state & FD_STATE_FORMAT) {
2463 fdctrl_format_sector(fdctrl);
2464 break;
2465 }
2466
2467 cmd = get_command(fdctrl->fifo[0]);
2468 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2469 cmd->handler(fdctrl, cmd->direction);
2470 }
2471 break;
2472
2473 case FD_PHASE_RESULT:
2474 default:
2475 abort();
2476 }
2477 }
2478
2479 static void fdctrl_result_timer(void *opaque)
2480 {
2481 FDCtrl *fdctrl = opaque;
2482 FDrive *cur_drv = get_cur_drv(fdctrl);
2483
2484 /* Pretend we are spinning.
2485 * This is needed for Coherent, which uses READ ID to check for
2486 * sector interleaving.
2487 */
2488 if (cur_drv->last_sect != 0) {
2489 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2490 }
2491 /* READ_ID can't automatically succeed! */
2492 if (fdctrl->check_media_rate &&
2493 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2494 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2495 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2496 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2497 } else {
2498 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2499 }
2500 }
2501
2502 /* Init functions */
2503 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp,
2504 DeviceState *fdc_dev)
2505 {
2506 unsigned int i;
2507 FDrive *drive;
2508 DeviceState *dev;
2509 BlockBackend *blk;
2510 Error *local_err = NULL;
2511
2512 for (i = 0; i < MAX_FD; i++) {
2513 drive = &fdctrl->drives[i];
2514 drive->fdctrl = fdctrl;
2515
2516 /* If the drive is not present, we skip creating the qdev device, but
2517 * still have to initialise the controller. */
2518 blk = fdctrl->qdev_for_drives[i].blk;
2519 if (!blk) {
2520 fd_init(drive);
2521 fd_revalidate(drive);
2522 continue;
2523 }
2524
2525 dev = qdev_create(&fdctrl->bus.bus, "floppy");
2526 qdev_prop_set_uint32(dev, "unit", i);
2527 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
2528
2529 blk_ref(blk);
2530 blk_detach_dev(blk, fdc_dev);
2531 fdctrl->qdev_for_drives[i].blk = NULL;
2532 qdev_prop_set_drive(dev, "drive", blk, &local_err);
2533 blk_unref(blk);
2534
2535 if (local_err) {
2536 error_propagate(errp, local_err);
2537 return;
2538 }
2539
2540 object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
2541 if (local_err) {
2542 error_propagate(errp, local_err);
2543 return;
2544 }
2545 }
2546 }
2547
2548 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2549 {
2550 DeviceState *dev;
2551 ISADevice *isadev;
2552
2553 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2554 if (!isadev) {
2555 return NULL;
2556 }
2557 dev = DEVICE(isadev);
2558
2559 if (fds[0]) {
2560 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2561 &error_fatal);
2562 }
2563 if (fds[1]) {
2564 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2565 &error_fatal);
2566 }
2567 qdev_init_nofail(dev);
2568
2569 return isadev;
2570 }
2571
2572 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2573 hwaddr mmio_base, DriveInfo **fds)
2574 {
2575 FDCtrl *fdctrl;
2576 DeviceState *dev;
2577 SysBusDevice *sbd;
2578 FDCtrlSysBus *sys;
2579
2580 dev = qdev_create(NULL, "sysbus-fdc");
2581 sys = SYSBUS_FDC(dev);
2582 fdctrl = &sys->state;
2583 fdctrl->dma_chann = dma_chann; /* FIXME */
2584 if (fds[0]) {
2585 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2586 &error_fatal);
2587 }
2588 if (fds[1]) {
2589 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2590 &error_fatal);
2591 }
2592 qdev_init_nofail(dev);
2593 sbd = SYS_BUS_DEVICE(dev);
2594 sysbus_connect_irq(sbd, 0, irq);
2595 sysbus_mmio_map(sbd, 0, mmio_base);
2596 }
2597
2598 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2599 DriveInfo **fds, qemu_irq *fdc_tc)
2600 {
2601 DeviceState *dev;
2602 FDCtrlSysBus *sys;
2603
2604 dev = qdev_create(NULL, "SUNW,fdtwo");
2605 if (fds[0]) {
2606 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2607 &error_fatal);
2608 }
2609 qdev_init_nofail(dev);
2610 sys = SYSBUS_FDC(dev);
2611 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2612 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2613 *fdc_tc = qdev_get_gpio_in(dev, 0);
2614 }
2615
2616 static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2617 Error **errp)
2618 {
2619 int i, j;
2620 static int command_tables_inited = 0;
2621
2622 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2623 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2624 }
2625
2626 /* Fill 'command_to_handler' lookup table */
2627 if (!command_tables_inited) {
2628 command_tables_inited = 1;
2629 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2630 for (j = 0; j < sizeof(command_to_handler); j++) {
2631 if ((j & handlers[i].mask) == handlers[i].value) {
2632 command_to_handler[j] = i;
2633 }
2634 }
2635 }
2636 }
2637
2638 FLOPPY_DPRINTF("init controller\n");
2639 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2640 fdctrl->fifo_size = 512;
2641 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2642 fdctrl_result_timer, fdctrl);
2643
2644 fdctrl->version = 0x90; /* Intel 82078 controller */
2645 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2646 fdctrl->num_floppies = MAX_FD;
2647
2648 if (fdctrl->dma_chann != -1) {
2649 IsaDmaClass *k;
2650 assert(fdctrl->dma);
2651 k = ISADMA_GET_CLASS(fdctrl->dma);
2652 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2653 &fdctrl_transfer_handler, fdctrl);
2654 }
2655
2656 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
2657 fdctrl_connect_drives(fdctrl, errp, dev);
2658 }
2659
2660 static const MemoryRegionPortio fdc_portio_list[] = {
2661 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2662 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2663 PORTIO_END_OF_LIST(),
2664 };
2665
2666 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2667 {
2668 ISADevice *isadev = ISA_DEVICE(dev);
2669 FDCtrlISABus *isa = ISA_FDC(dev);
2670 FDCtrl *fdctrl = &isa->state;
2671 Error *err = NULL;
2672
2673 isa_register_portio_list(isadev, &fdctrl->portio_list,
2674 isa->iobase, fdc_portio_list, fdctrl,
2675 "fdc");
2676
2677 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2678 fdctrl->dma_chann = isa->dma;
2679 if (fdctrl->dma_chann != -1) {
2680 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
2681 assert(fdctrl->dma);
2682 }
2683
2684 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2685 fdctrl_realize_common(dev, fdctrl, &err);
2686 if (err != NULL) {
2687 error_propagate(errp, err);
2688 return;
2689 }
2690 }
2691
2692 static void sysbus_fdc_initfn(Object *obj)
2693 {
2694 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2695 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2696 FDCtrl *fdctrl = &sys->state;
2697
2698 fdctrl->dma_chann = -1;
2699
2700 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2701 "fdc", 0x08);
2702 sysbus_init_mmio(sbd, &fdctrl->iomem);
2703 }
2704
2705 static void sun4m_fdc_initfn(Object *obj)
2706 {
2707 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2708 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2709 FDCtrl *fdctrl = &sys->state;
2710
2711 fdctrl->dma_chann = -1;
2712
2713 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2714 fdctrl, "fdctrl", 0x08);
2715 sysbus_init_mmio(sbd, &fdctrl->iomem);
2716 }
2717
2718 static void sysbus_fdc_common_initfn(Object *obj)
2719 {
2720 DeviceState *dev = DEVICE(obj);
2721 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2722 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2723 FDCtrl *fdctrl = &sys->state;
2724
2725 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2726
2727 sysbus_init_irq(sbd, &fdctrl->irq);
2728 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2729 }
2730
2731 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2732 {
2733 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2734 FDCtrl *fdctrl = &sys->state;
2735
2736 fdctrl_realize_common(dev, fdctrl, errp);
2737 }
2738
2739 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2740 {
2741 FDCtrlISABus *isa = ISA_FDC(fdc);
2742
2743 return isa->state.drives[i].drive;
2744 }
2745
2746 void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2747 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2748 {
2749 const FDFormat *fdf;
2750
2751 *maxc = *maxh = *maxs = 0;
2752 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2753 if (fdf->drive != type) {
2754 continue;
2755 }
2756 if (*maxc < fdf->max_track) {
2757 *maxc = fdf->max_track;
2758 }
2759 if (*maxh < fdf->max_head) {
2760 *maxh = fdf->max_head;
2761 }
2762 if (*maxs < fdf->last_sect) {
2763 *maxs = fdf->last_sect;
2764 }
2765 }
2766 (*maxc)--;
2767 }
2768
2769 static const VMStateDescription vmstate_isa_fdc ={
2770 .name = "fdc",
2771 .version_id = 2,
2772 .minimum_version_id = 2,
2773 .fields = (VMStateField[]) {
2774 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2775 VMSTATE_END_OF_LIST()
2776 }
2777 };
2778
2779 static Property isa_fdc_properties[] = {
2780 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2781 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2782 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2783 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk),
2784 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk),
2785 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2786 0, true),
2787 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
2788 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2789 FloppyDriveType),
2790 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
2791 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2792 FloppyDriveType),
2793 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2794 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
2795 FloppyDriveType),
2796 DEFINE_PROP_END_OF_LIST(),
2797 };
2798
2799 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2800 {
2801 DeviceClass *dc = DEVICE_CLASS(klass);
2802
2803 dc->realize = isabus_fdc_realize;
2804 dc->fw_name = "fdc";
2805 dc->reset = fdctrl_external_reset_isa;
2806 dc->vmsd = &vmstate_isa_fdc;
2807 dc->props = isa_fdc_properties;
2808 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2809 }
2810
2811 static void isabus_fdc_instance_init(Object *obj)
2812 {
2813 FDCtrlISABus *isa = ISA_FDC(obj);
2814
2815 device_add_bootindex_property(obj, &isa->bootindexA,
2816 "bootindexA", "/floppy@0",
2817 DEVICE(obj), NULL);
2818 device_add_bootindex_property(obj, &isa->bootindexB,
2819 "bootindexB", "/floppy@1",
2820 DEVICE(obj), NULL);
2821 }
2822
2823 static const TypeInfo isa_fdc_info = {
2824 .name = TYPE_ISA_FDC,
2825 .parent = TYPE_ISA_DEVICE,
2826 .instance_size = sizeof(FDCtrlISABus),
2827 .class_init = isabus_fdc_class_init,
2828 .instance_init = isabus_fdc_instance_init,
2829 };
2830
2831 static const VMStateDescription vmstate_sysbus_fdc ={
2832 .name = "fdc",
2833 .version_id = 2,
2834 .minimum_version_id = 2,
2835 .fields = (VMStateField[]) {
2836 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2837 VMSTATE_END_OF_LIST()
2838 }
2839 };
2840
2841 static Property sysbus_fdc_properties[] = {
2842 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2843 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk),
2844 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type,
2845 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2846 FloppyDriveType),
2847 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type,
2848 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2849 FloppyDriveType),
2850 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2851 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2852 FloppyDriveType),
2853 DEFINE_PROP_END_OF_LIST(),
2854 };
2855
2856 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2857 {
2858 DeviceClass *dc = DEVICE_CLASS(klass);
2859
2860 dc->props = sysbus_fdc_properties;
2861 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2862 }
2863
2864 static const TypeInfo sysbus_fdc_info = {
2865 .name = "sysbus-fdc",
2866 .parent = TYPE_SYSBUS_FDC,
2867 .instance_init = sysbus_fdc_initfn,
2868 .class_init = sysbus_fdc_class_init,
2869 };
2870
2871 static Property sun4m_fdc_properties[] = {
2872 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2873 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type,
2874 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2875 FloppyDriveType),
2876 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2877 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2878 FloppyDriveType),
2879 DEFINE_PROP_END_OF_LIST(),
2880 };
2881
2882 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2883 {
2884 DeviceClass *dc = DEVICE_CLASS(klass);
2885
2886 dc->props = sun4m_fdc_properties;
2887 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2888 }
2889
2890 static const TypeInfo sun4m_fdc_info = {
2891 .name = "SUNW,fdtwo",
2892 .parent = TYPE_SYSBUS_FDC,
2893 .instance_init = sun4m_fdc_initfn,
2894 .class_init = sun4m_fdc_class_init,
2895 };
2896
2897 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2898 {
2899 DeviceClass *dc = DEVICE_CLASS(klass);
2900
2901 dc->realize = sysbus_fdc_common_realize;
2902 dc->reset = fdctrl_external_reset_sysbus;
2903 dc->vmsd = &vmstate_sysbus_fdc;
2904 }
2905
2906 static const TypeInfo sysbus_fdc_type_info = {
2907 .name = TYPE_SYSBUS_FDC,
2908 .parent = TYPE_SYS_BUS_DEVICE,
2909 .instance_size = sizeof(FDCtrlSysBus),
2910 .instance_init = sysbus_fdc_common_initfn,
2911 .abstract = true,
2912 .class_init = sysbus_fdc_common_class_init,
2913 };
2914
2915 static void fdc_register_types(void)
2916 {
2917 type_register_static(&isa_fdc_info);
2918 type_register_static(&sysbus_fdc_type_info);
2919 type_register_static(&sysbus_fdc_info);
2920 type_register_static(&sun4m_fdc_info);
2921 type_register_static(&floppy_bus_info);
2922 type_register_static(&floppy_drive_info);
2923 }
2924
2925 type_init(fdc_register_types)
AR7 emulation for QEMU