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1 # AArch64 SVE instruction descriptions
2 #
3 # Copyright (c) 2017 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
19 # This file is processed by scripts/decodetree.py
20 #
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
25 %imm4_16_p1 16:4 !function=plus1
26 %imm6_22_5 22:1 5:5
27 %imm7_22_16 22:2 16:5
28 %imm8_16_10 16:5 10:3
29 %imm9_16_10 16:s6 10:3
30 %size_23 23:2
31 %dtype_23_13 23:2 13:2
32 %index3_22_19 22:1 19:2
34 # A combination of tsz:imm3 -- extract esize.
35 %tszimm_esz 22:2 5:5 !function=tszimm_esz
36 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
37 %tszimm_shr 22:2 5:5 !function=tszimm_shr
38 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
39 %tszimm_shl 22:2 5:5 !function=tszimm_shl
41 # Similarly for the tszh/tszl pair at 22/16 for zzi
42 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
43 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
44 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
46 # Signed 8-bit immediate, optionally shifted left by 8.
47 %sh8_i8s 5:9 !function=expand_imm_sh8s
48 # Unsigned 8-bit immediate, optionally shifted left by 8.
49 %sh8_i8u 5:9 !function=expand_imm_sh8u
51 # Unsigned load of msz into esz=2, represented as a dtype.
52 %msz_dtype 23:2 !function=msz_dtype
54 # Either a copy of rd (at bit 0), or a different source
55 # as propagated via the MOVPRFX instruction.
56 %reg_movprfx 0:5
58 ###########################################################################
59 # Named attribute sets. These are used to make nice(er) names
60 # when creating helpers common to those for the individual
61 # instruction patterns.
63 &rr_esz rd rn esz
64 &rri rd rn imm
65 &rr_dbm rd rn dbm
66 &rrri rd rn rm imm
67 &rri_esz rd rn imm esz
68 &rrr_esz rd rn rm esz
69 &rpr_esz rd pg rn esz
70 &rpr_s rd pg rn s
71 &rprr_s rd pg rn rm s
72 &rprr_esz rd pg rn rm esz
73 &rprrr_esz rd pg rn rm ra esz
74 &rpri_esz rd pg rn imm esz
75 &ptrue rd esz pat s
76 &incdec_cnt rd pat esz imm d u
77 &incdec2_cnt rd rn pat esz imm d u
78 &incdec_pred rd pg esz d u
79 &incdec2_pred rd rn pg esz d u
80 &rprr_load rd pg rn rm dtype nreg
81 &rpri_load rd pg rn imm dtype nreg
82 &rprr_store rd pg rn rm msz esz nreg
83 &rpri_store rd pg rn imm msz esz nreg
84 &rprr_gather_load rd pg rn rm esz msz u ff xs scale
85 &rpri_gather_load rd pg rn imm esz msz u ff
86 &rprr_scatter_store rd pg rn rm esz msz xs scale
87 &rpri_scatter_store rd pg rn imm esz msz
89 ###########################################################################
90 # Named instruction formats. These are generally used to
91 # reduce the amount of duplication between instruction patterns.
93 # Two operand with unused vector element size
94 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
96 # Two operand
97 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
98 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
100 # Two operand with governing predicate, flags setting
101 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
102 @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0
104 # Three operand with unused vector element size
105 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
107 # Three predicate operand, with governing predicate, flag setting
108 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
110 # Three operand, vector element size
111 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
112 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
113 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
114 &rrr_esz rn=%reg_movprfx
115 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
116 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
117 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
118 &rri_esz rn=%reg_movprfx
119 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
120 &rri_esz rn=%reg_movprfx
122 # Three operand with "memory" size, aka immediate left shift
123 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
125 # Two register operand, with governing predicate, vector element size
126 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
127 &rprr_esz rn=%reg_movprfx
128 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
129 &rprr_esz rm=%reg_movprfx
130 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
131 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
133 # Three register operand, with governing predicate, vector element size
134 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
135 &rprrr_esz ra=%reg_movprfx
136 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
137 &rprrr_esz rn=%reg_movprfx
138 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
139 &rprrr_esz rn=%reg_movprfx
141 # One register operand, with governing predicate, vector element size
142 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
143 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
144 @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz
146 # One register operand, with governing predicate, no vector element size
147 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
149 # Two register operands with a 6-bit signed immediate.
150 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
152 # Two register operand, one immediate operand, with predicate,
153 # element size encoded as TSZHL. User must fill in imm.
154 @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
155 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
157 # Similarly without predicate.
158 @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
159 &rri_esz esz=%tszimm16_esz
161 # Two register operand, one immediate operand, with 4-bit predicate.
162 # User must fill in imm.
163 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
164 &rpri_esz rn=%reg_movprfx
166 # Two register operand, one one-bit floating-point operand.
167 @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
168 &rpri_esz rn=%reg_movprfx
170 # Two register operand, one encoded bitmask.
171 @rdn_dbm ........ .. .... dbm:13 rd:5 \
172 &rr_dbm rn=%reg_movprfx
174 # Predicate output, vector and immediate input,
175 # controlling predicate, element size.
176 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
177 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
179 # Basic Load/Store with 9-bit immediate offset
180 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
181 &rri imm=%imm9_16_10
182 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
183 &rri imm=%imm9_16_10
185 # One register, pattern, and uint4+1.
186 # User must fill in U and D.
187 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
188 &incdec_cnt imm=%imm4_16_p1
189 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
190 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
192 # One register, predicate.
193 # User must fill in U and D.
194 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
195 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
196 &incdec2_pred rn=%reg_movprfx
198 # Loads; user must fill in NREG.
199 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
200 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
202 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
203 &rprr_load dtype=%msz_dtype
204 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
205 &rpri_load dtype=%msz_dtype
207 # Gather Loads.
208 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
209 &rprr_gather_load xs=2
210 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
211 &rprr_gather_load
212 @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
213 &rprr_gather_load
214 @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
215 &rprr_gather_load
216 @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
217 &rprr_gather_load xs=2
218 @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
219 &rprr_gather_load xs=2
220 @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
221 &rpri_gather_load
223 # Stores; user must fill in ESZ, MSZ, NREG as needed.
224 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
225 @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
226 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
227 &rprr_store nreg=0
228 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
229 &rprr_scatter_store
230 @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
231 &rpri_scatter_store
233 ###########################################################################
234 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
236 ### SVE Integer Arithmetic - Binary Predicated Group
238 # SVE bitwise logical vector operations (predicated)
239 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
240 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
241 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
242 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
244 # SVE integer add/subtract vectors (predicated)
245 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
246 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
247 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
249 # SVE integer min/max/difference (predicated)
250 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
251 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
252 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
253 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
254 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
255 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
257 # SVE integer multiply/divide (predicated)
258 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
259 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
260 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
261 # Note that divide requires size >= 2; below 2 is unallocated.
262 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
263 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
264 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
265 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
267 ### SVE Integer Reduction Group
269 # SVE bitwise logical reduction (predicated)
270 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
271 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
272 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
274 # SVE constructive prefix (predicated)
275 MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn
276 MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn
278 # SVE integer add reduction (predicated)
279 # Note that saddv requires size != 3.
280 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
281 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
283 # SVE integer min/max reduction (predicated)
284 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
285 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
286 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
287 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
289 ### SVE Shift by Immediate - Predicated Group
291 # SVE bitwise shift by immediate (predicated)
292 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
293 @rdn_pg_tszimm imm=%tszimm_shr
294 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
295 @rdn_pg_tszimm imm=%tszimm_shr
296 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
297 @rdn_pg_tszimm imm=%tszimm_shl
298 ASRD 00000100 .. 000 100 100 ... .. ... ..... \
299 @rdn_pg_tszimm imm=%tszimm_shr
301 # SVE bitwise shift by vector (predicated)
302 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
303 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
304 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
305 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
306 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
307 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
309 # SVE bitwise shift by wide elements (predicated)
310 # Note these require size != 3.
311 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
312 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
313 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
315 ### SVE Integer Arithmetic - Unary Predicated Group
317 # SVE unary bit operations (predicated)
318 # Note esz != 0 for FABS and FNEG.
319 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
320 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
321 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
322 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
323 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
324 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
325 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
327 # SVE integer unary operations (predicated)
328 # Note esz > original size for extensions.
329 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
330 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
331 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
332 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
333 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
334 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
335 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
336 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
338 ### SVE Floating Point Compare - Vectors Group
340 # SVE floating-point compare vectors
341 FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
342 FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
343 FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
344 FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
345 FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
346 FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
347 FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
349 ### SVE Integer Multiply-Add Group
351 # SVE integer multiply-add writing addend (predicated)
352 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
353 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
355 # SVE integer multiply-add writing multiplicand (predicated)
356 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
357 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
359 ### SVE Integer Arithmetic - Unpredicated Group
361 # SVE integer add/subtract vectors (unpredicated)
362 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
363 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
364 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
365 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
366 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
367 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
369 ### SVE Logical - Unpredicated Group
371 # SVE bitwise logical operations (unpredicated)
372 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
373 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
374 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
375 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
377 ### SVE Index Generation Group
379 # SVE index generation (immediate start, immediate increment)
380 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
382 # SVE index generation (immediate start, register increment)
383 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
385 # SVE index generation (register start, immediate increment)
386 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
388 # SVE index generation (register start, register increment)
389 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
391 ### SVE Stack Allocation Group
393 # SVE stack frame adjustment
394 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
395 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
397 # SVE stack frame size
398 RDVL 00000100 101 11111 01010 imm:s6 rd:5
400 ### SVE Bitwise Shift - Unpredicated Group
402 # SVE bitwise shift by immediate (unpredicated)
403 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
404 @rd_rn_tszimm imm=%tszimm16_shr
405 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
406 @rd_rn_tszimm imm=%tszimm16_shr
407 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
408 @rd_rn_tszimm imm=%tszimm16_shl
410 # SVE bitwise shift by wide elements (unpredicated)
411 # Note esz != 3
412 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
413 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
414 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
416 ### SVE Compute Vector Address Group
418 # SVE vector address generation
419 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
420 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
421 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
422 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
424 ### SVE Integer Misc - Unpredicated Group
426 # SVE constructive prefix (unpredicated)
427 MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5
429 # SVE floating-point exponential accelerator
430 # Note esz != 0
431 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
433 # SVE floating-point trig select coefficient
434 # Note esz != 0
435 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
437 ### SVE Element Count Group
439 # SVE element count
440 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
442 # SVE inc/dec register by element count
443 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
445 # SVE saturating inc/dec register by element count
446 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
447 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
449 # SVE inc/dec vector by element count
450 # Note this requires esz != 0.
451 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
453 # SVE saturating inc/dec vector by element count
454 # Note these require esz != 0.
455 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
457 ### SVE Bitwise Immediate Group
459 # SVE bitwise logical with immediate (unpredicated)
460 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
461 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
462 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
464 # SVE broadcast bitmask immediate
465 DUPM 00000101 11 0000 dbm:13 rd:5
467 ### SVE Integer Wide Immediate - Predicated Group
469 # SVE copy floating-point immediate (predicated)
470 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
472 # SVE copy integer immediate (predicated)
473 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
474 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
476 ### SVE Permute - Extract Group
478 # SVE extract vector (immediate offset)
479 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
480 &rrri rn=%reg_movprfx imm=%imm8_16_10
482 ### SVE Permute - Unpredicated Group
484 # SVE broadcast general register
485 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
487 # SVE broadcast indexed element
488 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
489 &rri imm=%imm7_22_16
491 # SVE insert SIMD&FP scalar register
492 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
494 # SVE insert general register
495 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
497 # SVE reverse vector elements
498 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
500 # SVE vector table lookup
501 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
503 # SVE unpack vector elements
504 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
506 ### SVE Permute - Predicates Group
508 # SVE permute predicate elements
509 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
510 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
511 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
512 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
513 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
514 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
516 # SVE reverse predicate elements
517 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
519 # SVE unpack predicate elements
520 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
521 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
523 ### SVE Permute - Interleaving Group
525 # SVE permute vector elements
526 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
527 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
528 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
529 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
530 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
531 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
533 ### SVE Permute - Predicated Group
535 # SVE compress active elements
536 # Note esz >= 2
537 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
539 # SVE conditionally broadcast element to vector
540 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
541 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
543 # SVE conditionally copy element to SIMD&FP scalar
544 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
545 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
547 # SVE conditionally copy element to general register
548 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
549 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
551 # SVE copy element to SIMD&FP scalar register
552 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
553 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
555 # SVE copy element to general register
556 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
557 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
559 # SVE copy element from SIMD&FP scalar register
560 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
562 # SVE copy element from general register to vector (predicated)
563 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
565 # SVE reverse within elements
566 # Note esz >= operation size
567 REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
568 REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
569 REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
570 RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
572 # SVE vector splice (predicated)
573 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
575 ### SVE Select Vectors Group
577 # SVE select vector elements (predicated)
578 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
580 ### SVE Integer Compare - Vectors Group
582 # SVE integer compare_vectors
583 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
584 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
585 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
586 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
587 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
588 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
590 # SVE integer compare with wide elements
591 # Note these require esz != 3.
592 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
593 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
594 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
595 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
596 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
597 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
598 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
599 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
600 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
601 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
603 ### SVE Integer Compare - Unsigned Immediate Group
605 # SVE integer compare with unsigned immediate
606 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
607 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
608 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
609 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
611 ### SVE Integer Compare - Signed Immediate Group
613 # SVE integer compare with signed immediate
614 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
615 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
616 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
617 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
618 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
619 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
621 ### SVE Predicate Logical Operations Group
623 # SVE predicate logical operations
624 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
625 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
626 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
627 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
628 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
629 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
630 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
631 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
633 ### SVE Predicate Misc Group
635 # SVE predicate test
636 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
638 # SVE predicate initialize
639 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
641 # SVE initialize FFR
642 SETFFR 00100101 0010 1100 1001 0000 0000 0000
644 # SVE zero predicate register
645 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
647 # SVE predicate read from FFR (predicated)
648 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
650 # SVE predicate read from FFR (unpredicated)
651 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
653 # SVE FFR write from predicate (WRFFR)
654 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
656 # SVE predicate first active
657 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
659 # SVE predicate next active
660 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
662 ### SVE Partition Break Group
664 # SVE propagate break from previous partition
665 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
666 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
668 # SVE partition break condition
669 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
670 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
671 BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
672 BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
674 # SVE propagate break to next partition
675 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
677 ### SVE Predicate Count Group
679 # SVE predicate count
680 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
682 # SVE inc/dec register by predicate count
683 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
685 # SVE inc/dec vector by predicate count
686 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
688 # SVE saturating inc/dec register by predicate count
689 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
690 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
692 # SVE saturating inc/dec vector by predicate count
693 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
695 ### SVE Integer Compare - Scalars Group
697 # SVE conditionally terminate scalars
698 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
700 # SVE integer compare scalar count and limit
701 WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
703 ### SVE Integer Wide Immediate - Unpredicated Group
705 # SVE broadcast floating-point immediate (unpredicated)
706 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
708 # SVE broadcast integer immediate (unpredicated)
709 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
711 # SVE integer add/subtract immediate (unpredicated)
712 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
713 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
714 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
715 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
716 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
717 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
718 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
720 # SVE integer min/max immediate (unpredicated)
721 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
722 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
723 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
724 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
726 # SVE integer multiply immediate (unpredicated)
727 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
729 # SVE integer dot product (unpredicated)
730 DOT_zzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 ra=%reg_movprfx
732 # SVE integer dot product (indexed)
733 DOT_zzx 01000100 101 index:2 rm:3 00000 u:1 rn:5 rd:5 \
734 sz=0 ra=%reg_movprfx
735 DOT_zzx 01000100 111 index:1 rm:4 00000 u:1 rn:5 rd:5 \
736 sz=1 ra=%reg_movprfx
738 # SVE floating-point complex add (predicated)
739 FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \
740 rn=%reg_movprfx
742 # SVE floating-point complex multiply-add (predicated)
743 FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \
744 ra=%reg_movprfx
746 # SVE floating-point complex multiply-add (indexed)
747 FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \
748 ra=%reg_movprfx esz=1
749 FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \
750 ra=%reg_movprfx esz=2
752 ### SVE FP Multiply-Add Indexed Group
754 # SVE floating-point multiply-add (indexed)
755 FMLA_zzxz 01100100 0.1 .. rm:3 00000 sub:1 rn:5 rd:5 \
756 ra=%reg_movprfx index=%index3_22_19 esz=1
757 FMLA_zzxz 01100100 101 index:2 rm:3 00000 sub:1 rn:5 rd:5 \
758 ra=%reg_movprfx esz=2
759 FMLA_zzxz 01100100 111 index:1 rm:4 00000 sub:1 rn:5 rd:5 \
760 ra=%reg_movprfx esz=3
762 ### SVE FP Multiply Indexed Group
764 # SVE floating-point multiply (indexed)
765 FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \
766 index=%index3_22_19 esz=1
767 FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2
768 FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3
770 ### SVE FP Fast Reduction Group
772 FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn
773 FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn
774 FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn
775 FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn
776 FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
778 ## SVE Floating Point Unary Operations - Unpredicated Group
780 FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
781 FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
783 ### SVE FP Compare with Zero Group
785 FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn
786 FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn
787 FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn
788 FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn
789 FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn
790 FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn
792 ### SVE FP Accumulating Reduction Group
794 # SVE floating-point serial reduction (predicated)
795 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
797 ### SVE Floating Point Arithmetic - Unpredicated Group
799 # SVE floating-point arithmetic (unpredicated)
800 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
801 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
802 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
803 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
804 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
805 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
807 ### SVE FP Arithmetic Predicated Group
809 # SVE floating-point arithmetic (predicated)
810 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
811 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
812 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
813 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
814 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
815 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
816 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
817 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
818 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
819 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
820 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
821 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
822 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
824 # SVE floating-point arithmetic with immediate (predicated)
825 FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
826 FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1
827 FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1
828 FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1
829 FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1
830 FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1
831 FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
832 FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
834 # SVE floating-point trig multiply-add coefficient
835 FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx
837 ### SVE FP Multiply-Add Group
839 # SVE floating-point multiply-accumulate writing addend
840 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
841 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
842 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
843 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
845 # SVE floating-point multiply-accumulate writing multiplicand
846 # Alter the operand extraction order and reuse the helpers from above.
847 # FMAD, FMSB, FNMAD, FNMS
848 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
849 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
850 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
851 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
853 ### SVE FP Unary Operations Predicated Group
855 # SVE floating-point convert precision
856 FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
857 FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
858 FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0
859 FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
860 FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
861 FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
863 # SVE floating-point convert to integer
864 FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
865 FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
866 FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
867 FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
868 FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
869 FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
870 FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
871 FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
872 FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0
873 FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0
874 FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
875 FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
876 FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
877 FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
879 # SVE floating-point round to integral value
880 FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
881 FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
882 FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
883 FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
884 FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
885 FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
886 FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
888 # SVE floating-point unary operations
889 FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
890 FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
892 # SVE integer convert to floating-point
893 SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
894 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
895 SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
896 SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
897 SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
898 SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
899 SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
901 UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
902 UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
903 UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
904 UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
905 UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
906 UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
907 UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
909 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
911 # SVE load predicate register
912 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
914 # SVE load vector register
915 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
917 # SVE load and broadcast element
918 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
919 &rpri_load dtype=%dtype_23_13 nreg=0
921 # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
922 # SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
923 LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
924 @rprr_g_load_xs_u esz=2 msz=0 scale=0
925 LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
926 @rprr_g_load_xs_u_sc esz=2 msz=1
927 LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
928 @rprr_g_load_xs_sc esz=2 msz=2 u=1
930 # SVE 32-bit gather load (vector plus immediate)
931 LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
932 @rpri_g_load esz=2
934 ### SVE Memory Contiguous Load Group
936 # SVE contiguous load (scalar plus scalar)
937 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
939 # SVE contiguous first-fault load (scalar plus scalar)
940 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
942 # SVE contiguous load (scalar plus immediate)
943 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
945 # SVE contiguous non-fault load (scalar plus immediate)
946 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
948 # SVE contiguous non-temporal load (scalar plus scalar)
949 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
950 # SVE load multiple structures (scalar plus scalar)
951 # LD2B, LD2H, LD2W, LD2D; etc.
952 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
954 # SVE contiguous non-temporal load (scalar plus immediate)
955 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
956 # SVE load multiple structures (scalar plus immediate)
957 # LD2B, LD2H, LD2W, LD2D; etc.
958 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
960 # SVE load and broadcast quadword (scalar plus scalar)
961 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
962 @rprr_load_msz nreg=0
964 # SVE load and broadcast quadword (scalar plus immediate)
965 # LD1RQB, LD1RQH, LD1RQS, LD1RQD
966 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
967 @rpri_load_msz nreg=0
969 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
970 PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
972 # SVE 32-bit gather prefetch (vector plus immediate)
973 PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
975 # SVE contiguous prefetch (scalar plus immediate)
976 PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
978 # SVE contiguous prefetch (scalar plus scalar)
979 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
981 ### SVE Memory 64-bit Gather Group
983 # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
984 # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
985 LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
986 @rprr_g_load_xs_u esz=3 msz=0 scale=0
987 LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
988 @rprr_g_load_xs_u_sc esz=3 msz=1
989 LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
990 @rprr_g_load_xs_u_sc esz=3 msz=2
991 LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
992 @rprr_g_load_xs_sc esz=3 msz=3 u=1
994 # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
995 # SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
996 LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
997 @rprr_g_load_u esz=3 msz=0 scale=0
998 LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
999 @rprr_g_load_u_sc esz=3 msz=1
1000 LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
1001 @rprr_g_load_u_sc esz=3 msz=2
1002 LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
1003 @rprr_g_load_sc esz=3 msz=3 u=1
1005 # SVE 64-bit gather load (vector plus immediate)
1006 LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
1007 @rpri_g_load esz=3
1009 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
1010 PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
1012 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
1013 PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
1015 # SVE 64-bit gather prefetch (vector plus immediate)
1016 PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
1018 ### SVE Memory Store Group
1020 # SVE store predicate register
1021 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
1023 # SVE store vector register
1024 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
1026 # SVE contiguous store (scalar plus immediate)
1027 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1028 ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \
1029 @rpri_store_msz nreg=0
1031 # SVE contiguous store (scalar plus scalar)
1032 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1033 # Enumerate msz lest we conflict with STR_zri.
1034 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
1035 @rprr_store_esz_n0 msz=0
1036 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
1037 @rprr_store_esz_n0 msz=1
1038 ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \
1039 @rprr_store_esz_n0 msz=2
1040 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
1041 @rprr_store msz=3 esz=3 nreg=0
1043 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
1044 # SVE store multiple structures (scalar plus immediate) (nreg != 0)
1045 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
1046 @rpri_store_msz esz=%size_23
1048 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
1049 # SVE store multiple structures (scalar plus scalar) (nreg != 0)
1050 ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
1051 @rprr_store esz=%size_23
1053 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
1054 # Require msz > 0 && msz <= esz.
1055 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
1056 @rprr_scatter_store xs=0 esz=2 scale=1
1057 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
1058 @rprr_scatter_store xs=1 esz=2 scale=1
1060 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
1061 # Require msz <= esz.
1062 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
1063 @rprr_scatter_store xs=0 esz=2 scale=0
1064 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
1065 @rprr_scatter_store xs=1 esz=2 scale=0
1067 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
1068 # Require msz > 0
1069 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
1070 @rprr_scatter_store xs=2 esz=3 scale=1
1072 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
1073 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
1074 @rprr_scatter_store xs=2 esz=3 scale=0
1076 # SVE 64-bit scatter store (vector plus immediate)
1077 ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
1078 @rpri_scatter_store esz=3
1080 # SVE 32-bit scatter store (vector plus immediate)
1081 ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
1082 @rpri_scatter_store esz=2
1084 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
1085 # Require msz > 0
1086 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
1087 @rprr_scatter_store xs=0 esz=3 scale=1
1088 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
1089 @rprr_scatter_store xs=1 esz=3 scale=1
1091 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
1092 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
1093 @rprr_scatter_store xs=0 esz=3 scale=0
1094 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
1095 @rprr_scatter_store xs=1 esz=3 scale=0