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[qemu/ar7.git] / hw / riscv / spike.c
blobd0c48437125f21778744b3647d2f0a6e39b71fd4
1 /*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/log.h"
28 #include "qemu/error-report.h"
29 #include "qapi/error.h"
30 #include "hw/boards.h"
31 #include "hw/loader.h"
32 #include "hw/sysbus.h"
33 #include "target/riscv/cpu.h"
34 #include "hw/riscv/riscv_htif.h"
35 #include "hw/riscv/riscv_hart.h"
36 #include "hw/riscv/sifive_clint.h"
37 #include "hw/riscv/spike.h"
38 #include "hw/riscv/boot.h"
39 #include "chardev/char.h"
40 #include "sysemu/arch_init.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/qtest.h"
43 #include "sysemu/sysemu.h"
44 #include "exec/address-spaces.h"
45
46 #include <libfdt.h>
47
48 #if defined(TARGET_RISCV32)
49 # define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
50 #else
51 # define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
52 #endif
53
54 static const struct MemmapEntry {
55 hwaddr base;
56 hwaddr size;
57 } spike_memmap[] = {
58 [SPIKE_MROM] = { 0x1000, 0x11000 },
59 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
60 [SPIKE_DRAM] = { 0x80000000, 0x0 },
61 };
62
63 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
64 uint64_t mem_size, const char *cmdline)
65 {
66 void *fdt;
67 int cpu;
68 uint32_t *cells;
69 char *nodename;
70
71 fdt = s->fdt = create_device_tree(&s->fdt_size);
72 if (!fdt) {
73 error_report("create_device_tree() failed");
74 exit(1);
75 }
76
77 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
78 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
79 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
80 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
81
82 qemu_fdt_add_subnode(fdt, "/htif");
83 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
84
85 qemu_fdt_add_subnode(fdt, "/soc");
86 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
87 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
88 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
89 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
90
91 nodename = g_strdup_printf("/memory@%lx",
92 (long)memmap[SPIKE_DRAM].base);
93 qemu_fdt_add_subnode(fdt, nodename);
94 qemu_fdt_setprop_cells(fdt, nodename, "reg",
95 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
96 mem_size >> 32, mem_size);
97 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
98 g_free(nodename);
99
100 qemu_fdt_add_subnode(fdt, "/cpus");
101 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
102 SIFIVE_CLINT_TIMEBASE_FREQ);
103 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
104 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
105
106 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
107 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
108 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
109 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
110 qemu_fdt_add_subnode(fdt, nodename);
111 #if defined(TARGET_RISCV32)
112 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
113 #else
114 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
115 #endif
116 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
117 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
118 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
119 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
120 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
121 qemu_fdt_add_subnode(fdt, intc);
122 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
123 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
124 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
125 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
126 g_free(isa);
127 g_free(intc);
128 g_free(nodename);
129 }
130
131 cells = g_new0(uint32_t, s->soc.num_harts * 4);
132 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
133 nodename =
134 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
135 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
136 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
137 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
138 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
139 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
140 g_free(nodename);
141 }
142 nodename = g_strdup_printf("/soc/clint@%lx",
143 (long)memmap[SPIKE_CLINT].base);
144 qemu_fdt_add_subnode(fdt, nodename);
145 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
146 qemu_fdt_setprop_cells(fdt, nodename, "reg",
147 0x0, memmap[SPIKE_CLINT].base,
148 0x0, memmap[SPIKE_CLINT].size);
149 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
150 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
151 g_free(cells);
152 g_free(nodename);
153
154 if (cmdline) {
155 qemu_fdt_add_subnode(fdt, "/chosen");
156 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
157 }
158 }
159
160 static void spike_board_init(MachineState *machine)
161 {
162 const struct MemmapEntry *memmap = spike_memmap;
163
164 SpikeState *s = g_new0(SpikeState, 1);
165 MemoryRegion *system_memory = get_system_memory();
166 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
167 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
168 int i;
169 unsigned int smp_cpus = machine->smp.cpus;
170
171 /* Initialize SOC */
172 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
173 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
174 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
175 &error_abort);
176 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
177 &error_abort);
178 object_property_set_bool(OBJECT(&s->soc), true, "realized",
179 &error_abort);
180
181 /* register system main memory (actual RAM) */
182 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
183 machine->ram_size, &error_fatal);
184 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
185 main_mem);
186
187 /* create device tree */
188 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
189
190 /* boot rom */
191 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
192 memmap[SPIKE_MROM].size, &error_fatal);
193 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
194 mask_rom);
195
196 riscv_find_and_load_firmware(machine, BIOS_FILENAME,
197 memmap[SPIKE_DRAM].base,
198 htif_symbol_callback);
199
200 if (machine->kernel_filename) {
201 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
202 htif_symbol_callback);
203
204 if (machine->initrd_filename) {
205 hwaddr start;
206 hwaddr end = riscv_load_initrd(machine->initrd_filename,
207 machine->ram_size, kernel_entry,
208 &start);
209 qemu_fdt_setprop_cell(s->fdt, "/chosen",
210 "linux,initrd-start", start);
211 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
212 end);
213 }
214 }
215
216 /* reset vector */
217 uint32_t reset_vec[8] = {
218 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
219 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
220 0xf1402573, /* csrr a0, mhartid */
221 #if defined(TARGET_RISCV32)
222 0x0182a283, /* lw t0, 24(t0) */
223 #elif defined(TARGET_RISCV64)
224 0x0182b283, /* ld t0, 24(t0) */
225 #endif
226 0x00028067, /* jr t0 */
227 0x00000000,
228 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
229 0x00000000,
230 /* dtb: */
231 };
232
233 /* copy in the reset vector in little_endian byte order */
234 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
235 reset_vec[i] = cpu_to_le32(reset_vec[i]);
236 }
237 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
238 memmap[SPIKE_MROM].base, &address_space_memory);
239
240 /* copy in the device tree */
241 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
242 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
243 error_report("not enough space to store device-tree");
244 exit(1);
245 }
246 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
247 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
248 memmap[SPIKE_MROM].base + sizeof(reset_vec),
249 &address_space_memory);
250
251 /* initialize HTIF using symbols found in load_kernel */
252 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
253
254 /* Core Local Interruptor (timer and IPI) */
255 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
256 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
257 false);
258 }
259
260 static void spike_v1_10_0_board_init(MachineState *machine)
261 {
262 const struct MemmapEntry *memmap = spike_memmap;
263
264 SpikeState *s = g_new0(SpikeState, 1);
265 MemoryRegion *system_memory = get_system_memory();
266 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
267 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
268 int i;
269 unsigned int smp_cpus = machine->smp.cpus;
270
271 if (!qtest_enabled()) {
272 info_report("The Spike v1.10.0 machine has been deprecated. "
273 "Please use the generic spike machine and specify the ISA "
274 "versions using -cpu.");
275 }
276
277 /* Initialize SOC */
278 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
279 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
280 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
281 &error_abort);
282 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
283 &error_abort);
284 object_property_set_bool(OBJECT(&s->soc), true, "realized",
285 &error_abort);
286
287 /* register system main memory (actual RAM) */
288 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
289 machine->ram_size, &error_fatal);
290 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
291 main_mem);
292
293 /* create device tree */
294 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
295
296 /* boot rom */
297 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
298 memmap[SPIKE_MROM].size, &error_fatal);
299 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
300 mask_rom);
301
302 if (machine->kernel_filename) {
303 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
304 }
305
306 /* reset vector */
307 uint32_t reset_vec[8] = {
308 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
309 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
310 0xf1402573, /* csrr a0, mhartid */
311 #if defined(TARGET_RISCV32)
312 0x0182a283, /* lw t0, 24(t0) */
313 #elif defined(TARGET_RISCV64)
314 0x0182b283, /* ld t0, 24(t0) */
315 #endif
316 0x00028067, /* jr t0 */
317 0x00000000,
318 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
319 0x00000000,
320 /* dtb: */
321 };
322
323 /* copy in the reset vector in little_endian byte order */
324 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
325 reset_vec[i] = cpu_to_le32(reset_vec[i]);
326 }
327 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
328 memmap[SPIKE_MROM].base, &address_space_memory);
329
330 /* copy in the device tree */
331 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
332 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
333 error_report("not enough space to store device-tree");
334 exit(1);
335 }
336 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
337 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
338 memmap[SPIKE_MROM].base + sizeof(reset_vec),
339 &address_space_memory);
340
341 /* initialize HTIF using symbols found in load_kernel */
342 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
343
344 /* Core Local Interruptor (timer and IPI) */
345 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
346 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
347 false);
348 }
349
350 static void spike_v1_09_1_board_init(MachineState *machine)
351 {
352 const struct MemmapEntry *memmap = spike_memmap;
353
354 SpikeState *s = g_new0(SpikeState, 1);
355 MemoryRegion *system_memory = get_system_memory();
356 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
357 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
358 int i;
359 unsigned int smp_cpus = machine->smp.cpus;
360
361 if (!qtest_enabled()) {
362 info_report("The Spike v1.09.1 machine has been deprecated. "
363 "Please use the generic spike machine and specify the ISA "
364 "versions using -cpu.");
365 }
366
367 /* Initialize SOC */
368 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
369 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
370 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
371 &error_abort);
372 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
373 &error_abort);
374 object_property_set_bool(OBJECT(&s->soc), true, "realized",
375 &error_abort);
376
377 /* register system main memory (actual RAM) */
378 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
379 machine->ram_size, &error_fatal);
380 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
381 main_mem);
382
383 /* boot rom */
384 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
385 memmap[SPIKE_MROM].size, &error_fatal);
386 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
387 mask_rom);
388
389 if (machine->kernel_filename) {
390 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
391 }
392
393 /* reset vector */
394 uint32_t reset_vec[8] = {
395 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
396 0x00028067, /* jump to DRAM_BASE */
397 0x00000000, /* reserved */
398 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
399 0, 0, 0, 0 /* trap vector */
400 };
401
402 /* part one of config string - before memory size specified */
403 const char *config_string_tmpl =
404 "platform {\n"
405 " vendor ucb;\n"
406 " arch spike;\n"
407 "};\n"
408 "rtc {\n"
409 " addr 0x%" PRIx64 "x;\n"
410 "};\n"
411 "ram {\n"
412 " 0 {\n"
413 " addr 0x%" PRIx64 "x;\n"
414 " size 0x%" PRIx64 "x;\n"
415 " };\n"
416 "};\n"
417 "core {\n"
418 " 0" " {\n"
419 " " "0 {\n"
420 " isa %s;\n"
421 " timecmp 0x%" PRIx64 "x;\n"
422 " ipi 0x%" PRIx64 "x;\n"
423 " };\n"
424 " };\n"
425 "};\n";
426
427 /* build config string with supplied memory size */
428 char *isa = riscv_isa_string(&s->soc.harts[0]);
429 char *config_string = g_strdup_printf(config_string_tmpl,
430 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
431 (uint64_t)memmap[SPIKE_DRAM].base,
432 (uint64_t)ram_size, isa,
433 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
434 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
435 g_free(isa);
436 size_t config_string_len = strlen(config_string);
437
438 /* copy in the reset vector in little_endian byte order */
439 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
440 reset_vec[i] = cpu_to_le32(reset_vec[i]);
441 }
442 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
443 memmap[SPIKE_MROM].base, &address_space_memory);
444
445 /* copy in the config string */
446 rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
447 memmap[SPIKE_MROM].base + sizeof(reset_vec),
448 &address_space_memory);
449
450 /* initialize HTIF using symbols found in load_kernel */
451 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
452
453 /* Core Local Interruptor (timer and IPI) */
454 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
455 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
456 false);
457
458 g_free(config_string);
459 }
460
461 static void spike_v1_09_1_machine_init(MachineClass *mc)
462 {
463 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
464 mc->init = spike_v1_09_1_board_init;
465 mc->max_cpus = 1;
466 }
467
468 static void spike_v1_10_0_machine_init(MachineClass *mc)
469 {
470 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
471 mc->init = spike_v1_10_0_board_init;
472 mc->max_cpus = 1;
473 }
474
475 static void spike_machine_init(MachineClass *mc)
476 {
477 mc->desc = "RISC-V Spike Board";
478 mc->init = spike_board_init;
479 mc->max_cpus = 8;
480 mc->is_default = true;
481 mc->default_cpu_type = SPIKE_V1_10_0_CPU;
482 }
483
484 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
485 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
486 DEFINE_MACHINE("spike", spike_machine_init)
AR7 emulation for QEMU