hw/riscv/sifive_plic.c

   1 /*
   2  * SiFive PLIC (Platform Level Interrupt Controller)
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This provides a parameterizable interrupt controller based on SiFive's PLIC.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24 #include "qemu/error-report.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/pci/msi.h"
  27 #include "hw/boards.h"
  28 #include "hw/qdev-properties.h"
  29 #include "target/riscv/cpu.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/riscv/sifive_plic.h"
  32
  33 #define RISCV_DEBUG_PLIC 0
  34
  35 static PLICMode char_to_mode(char c)
  36 {
  37     switch (c) {
  38     case 'U': return PLICMode_U;
  39     case 'S': return PLICMode_S;
  40     case 'H': return PLICMode_H;
  41     case 'M': return PLICMode_M;
  42     default:
  43         error_report("plic: invalid mode '%c'", c);
  44         exit(1);
  45     }
  46 }
  47
  48 static char mode_to_char(PLICMode m)
  49 {
  50     switch (m) {
  51     case PLICMode_U: return 'U';
  52     case PLICMode_S: return 'S';
  53     case PLICMode_H: return 'H';
  54     case PLICMode_M: return 'M';
  55     default: return '?';
  56     }
  57 }
  58
  59 static void sifive_plic_print_state(SiFivePLICState *plic)
  60 {
  61     int i;
  62     int addrid;
  63
  64     /* pending */
  65     qemu_log("pending       : ");
  66     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  67         qemu_log("%08x", plic->pending[i]);
  68     }
  69     qemu_log("\n");
  70
  71     /* pending */
  72     qemu_log("claimed       : ");
  73     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  74         qemu_log("%08x", plic->claimed[i]);
  75     }
  76     qemu_log("\n");
  77
  78     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
  79         qemu_log("hart%d-%c enable: ",
  80             plic->addr_config[addrid].hartid,
  81             mode_to_char(plic->addr_config[addrid].mode));
  82         for (i = plic->bitfield_words - 1; i >= 0; i--) {
  83             qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
  84         }
  85         qemu_log("\n");
  86     }
  87 }
  88
  89 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
  90 {
  91     uint32_t old, new, cmp = atomic_read(a);
  92
  93     do {
  94         old = cmp;
  95         new = (old & ~mask) | (value & mask);
  96         cmp = atomic_cmpxchg(a, old, new);
  97     } while (old != cmp);
  98
  99     return old;
 100 }
 101
 102 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
 103 {
 104     atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
 105 }
 106
 107 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
 108 {
 109     atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
 110 }
 111
 112 static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
 113 {
 114     int i, j;
 115     for (i = 0; i < plic->bitfield_words; i++) {
 116         uint32_t pending_enabled_not_claimed =
 117             (plic->pending[i] & ~plic->claimed[i]) &
 118             plic->enable[addrid * plic->bitfield_words + i];
 119         if (!pending_enabled_not_claimed) {
 120             continue;
 121         }
 122         for (j = 0; j < 32; j++) {
 123             int irq = (i << 5) + j;
 124             uint32_t prio = plic->source_priority[irq];
 125             int enabled = pending_enabled_not_claimed & (1 << j);
 126             if (enabled && prio > plic->target_priority[addrid]) {
 127                 return 1;
 128             }
 129         }
 130     }
 131     return 0;
 132 }
 133
 134 static void sifive_plic_update(SiFivePLICState *plic)
 135 {
 136     int addrid;
 137
 138     /* raise irq on harts where this irq is enabled */
 139     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
 140         uint32_t hartid = plic->addr_config[addrid].hartid;
 141         PLICMode mode = plic->addr_config[addrid].mode;
 142         CPUState *cpu = qemu_get_cpu(hartid);
 143         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 144         if (!env) {
 145             continue;
 146         }
 147         int level = sifive_plic_irqs_pending(plic, addrid);
 148         switch (mode) {
 149         case PLICMode_M:
 150             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 151             break;
 152         case PLICMode_S:
 153             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
 154             break;
 155         default:
 156             break;
 157         }
 158     }
 159
 160     if (RISCV_DEBUG_PLIC) {
 161         sifive_plic_print_state(plic);
 162     }
 163 }
 164
 165 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 166 {
 167     int i, j;
 168     for (i = 0; i < plic->bitfield_words; i++) {
 169         uint32_t pending_enabled_not_claimed =
 170             (plic->pending[i] & ~plic->claimed[i]) &
 171             plic->enable[addrid * plic->bitfield_words + i];
 172         if (!pending_enabled_not_claimed) {
 173             continue;
 174         }
 175         for (j = 0; j < 32; j++) {
 176             int irq = (i << 5) + j;
 177             uint32_t prio = plic->source_priority[irq];
 178             int enabled = pending_enabled_not_claimed & (1 << j);
 179             if (enabled && prio > plic->target_priority[addrid]) {
 180                 sifive_plic_set_pending(plic, irq, false);
 181                 sifive_plic_set_claimed(plic, irq, true);
 182                 return irq;
 183             }
 184         }
 185     }
 186     return 0;
 187 }
 188
 189 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
 190 {
 191     SiFivePLICState *plic = opaque;
 192
 193     /* writes must be 4 byte words */
 194     if ((addr & 0x3) != 0) {
 195         goto err;
 196     }
 197
 198     if (addr >= plic->priority_base && /* 4 bytes per source */
 199         addr < plic->priority_base + (plic->num_sources << 2))
 200     {
 201         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 202         if (RISCV_DEBUG_PLIC) {
 203             qemu_log("plic: read priority: irq=%d priority=%d\n",
 204                 irq, plic->source_priority[irq]);
 205         }
 206         return plic->source_priority[irq];
 207     } else if (addr >= plic->pending_base && /* 1 bit per source */
 208                addr < plic->pending_base + (plic->num_sources >> 3))
 209     {
 210         uint32_t word = (addr - plic->pending_base) >> 2;
 211         if (RISCV_DEBUG_PLIC) {
 212             qemu_log("plic: read pending: word=%d value=%d\n",
 213                 word, plic->pending[word]);
 214         }
 215         return plic->pending[word];
 216     } else if (addr >= plic->enable_base && /* 1 bit per source */
 217              addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 218     {
 219         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 220         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 221         if (wordid < plic->bitfield_words) {
 222             if (RISCV_DEBUG_PLIC) {
 223                 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
 224                     plic->addr_config[addrid].hartid,
 225                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 226                     plic->enable[addrid * plic->bitfield_words + wordid]);
 227             }
 228             return plic->enable[addrid * plic->bitfield_words + wordid];
 229         }
 230     } else if (addr >= plic->context_base && /* 1 bit per source */
 231              addr < plic->context_base + plic->num_addrs * plic->context_stride)
 232     {
 233         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 234         uint32_t contextid = (addr & (plic->context_stride - 1));
 235         if (contextid == 0) {
 236             if (RISCV_DEBUG_PLIC) {
 237                 qemu_log("plic: read priority: hart%d-%c priority=%x\n",
 238                     plic->addr_config[addrid].hartid,
 239                     mode_to_char(plic->addr_config[addrid].mode),
 240                     plic->target_priority[addrid]);
 241             }
 242             return plic->target_priority[addrid];
 243         } else if (contextid == 4) {
 244             uint32_t value = sifive_plic_claim(plic, addrid);
 245             if (RISCV_DEBUG_PLIC) {
 246                 qemu_log("plic: read claim: hart%d-%c irq=%x\n",
 247                     plic->addr_config[addrid].hartid,
 248                     mode_to_char(plic->addr_config[addrid].mode),
 249                     value);
 250                 sifive_plic_print_state(plic);
 251             }
 252             return value;
 253         }
 254     }
 255
 256 err:
 257     qemu_log_mask(LOG_GUEST_ERROR,
 258                   "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
 259                   __func__, addr);
 260     return 0;
 261 }
 262
 263 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 264         unsigned size)
 265 {
 266     SiFivePLICState *plic = opaque;
 267
 268     /* writes must be 4 byte words */
 269     if ((addr & 0x3) != 0) {
 270         goto err;
 271     }
 272
 273     if (addr >= plic->priority_base && /* 4 bytes per source */
 274         addr < plic->priority_base + (plic->num_sources << 2))
 275     {
 276         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 277         plic->source_priority[irq] = value & 7;
 278         if (RISCV_DEBUG_PLIC) {
 279             qemu_log("plic: write priority: irq=%d priority=%d\n",
 280                 irq, plic->source_priority[irq]);
 281         }
 282         return;
 283     } else if (addr >= plic->pending_base && /* 1 bit per source */
 284                addr < plic->pending_base + (plic->num_sources >> 3))
 285     {
 286         qemu_log_mask(LOG_GUEST_ERROR,
 287                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
 288                       __func__, addr);
 289         return;
 290     } else if (addr >= plic->enable_base && /* 1 bit per source */
 291         addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 292     {
 293         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 294         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 295         if (wordid < plic->bitfield_words) {
 296             plic->enable[addrid * plic->bitfield_words + wordid] = value;
 297             if (RISCV_DEBUG_PLIC) {
 298                 qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
 299                     plic->addr_config[addrid].hartid,
 300                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 301                     plic->enable[addrid * plic->bitfield_words + wordid]);
 302             }
 303             return;
 304         }
 305     } else if (addr >= plic->context_base && /* 4 bytes per reg */
 306         addr < plic->context_base + plic->num_addrs * plic->context_stride)
 307     {
 308         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 309         uint32_t contextid = (addr & (plic->context_stride - 1));
 310         if (contextid == 0) {
 311             if (RISCV_DEBUG_PLIC) {
 312                 qemu_log("plic: write priority: hart%d-%c priority=%x\n",
 313                     plic->addr_config[addrid].hartid,
 314                     mode_to_char(plic->addr_config[addrid].mode),
 315                     plic->target_priority[addrid]);
 316             }
 317             if (value <= plic->num_priorities) {
 318                 plic->target_priority[addrid] = value;
 319                 sifive_plic_update(plic);
 320             }
 321             return;
 322         } else if (contextid == 4) {
 323             if (RISCV_DEBUG_PLIC) {
 324                 qemu_log("plic: write claim: hart%d-%c irq=%x\n",
 325                     plic->addr_config[addrid].hartid,
 326                     mode_to_char(plic->addr_config[addrid].mode),
 327                     (uint32_t)value);
 328             }
 329             if (value < plic->num_sources) {
 330                 sifive_plic_set_claimed(plic, value, false);
 331                 sifive_plic_update(plic);
 332             }
 333             return;
 334         }
 335     }
 336
 337 err:
 338     qemu_log_mask(LOG_GUEST_ERROR,
 339                   "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
 340                   __func__, addr);
 341 }
 342
 343 static const MemoryRegionOps sifive_plic_ops = {
 344     .read = sifive_plic_read,
 345     .write = sifive_plic_write,
 346     .endianness = DEVICE_LITTLE_ENDIAN,
 347     .valid = {
 348         .min_access_size = 4,
 349         .max_access_size = 4
 350     }
 351 };
 352
 353 static Property sifive_plic_properties[] = {
 354     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
 355     DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
 356     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
 357     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
 358     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 359     DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 360     DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
 361     DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
 362     DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
 363     DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
 364     DEFINE_PROP_END_OF_LIST(),
 365 };
 366
 367 /*
 368  * parse PLIC hart/mode address offset config
 369  *
 370  * "M"              1 hart with M mode
 371  * "MS,MS"          2 harts, 0-1 with M and S mode
 372  * "M,MS,MS,MS,MS"  5 harts, 0 with M mode, 1-5 with M and S mode
 373  */
 374 static void parse_hart_config(SiFivePLICState *plic)
 375 {
 376     int addrid, hartid, modes;
 377     const char *p;
 378     char c;
 379
 380     /* count and validate hart/mode combinations */
 381     addrid = 0, hartid = 0, modes = 0;
 382     p = plic->hart_config;
 383     while ((c = *p++)) {
 384         if (c == ',') {
 385             addrid += ctpop8(modes);
 386             modes = 0;
 387             hartid++;
 388         } else {
 389             int m = 1 << char_to_mode(c);
 390             if (modes == (modes | m)) {
 391                 error_report("plic: duplicate mode '%c' in config: %s",
 392                              c, plic->hart_config);
 393                 exit(1);
 394             }
 395             modes |= m;
 396         }
 397     }
 398     if (modes) {
 399         addrid += ctpop8(modes);
 400     }
 401     hartid++;
 402
 403     /* store hart/mode combinations */
 404     plic->num_addrs = addrid;
 405     plic->addr_config = g_new(PLICAddr, plic->num_addrs);
 406     addrid = 0, hartid = 0;
 407     p = plic->hart_config;
 408     while ((c = *p++)) {
 409         if (c == ',') {
 410             hartid++;
 411         } else {
 412             plic->addr_config[addrid].addrid = addrid;
 413             plic->addr_config[addrid].hartid = hartid;
 414             plic->addr_config[addrid].mode = char_to_mode(c);
 415             addrid++;
 416         }
 417     }
 418 }
 419
 420 static void sifive_plic_irq_request(void *opaque, int irq, int level)
 421 {
 422     SiFivePLICState *plic = opaque;
 423     if (RISCV_DEBUG_PLIC) {
 424         qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
 425     }
 426     sifive_plic_set_pending(plic, irq, level > 0);
 427     sifive_plic_update(plic);
 428 }
 429
 430 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 431 {
 432     MachineState *ms = MACHINE(qdev_get_machine());
 433     unsigned int smp_cpus = ms->smp.cpus;
 434     SiFivePLICState *plic = SIFIVE_PLIC(dev);
 435     int i;
 436
 437     memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
 438                           TYPE_SIFIVE_PLIC, plic->aperture_size);
 439     parse_hart_config(plic);
 440     plic->bitfield_words = (plic->num_sources + 31) >> 5;
 441     plic->source_priority = g_new0(uint32_t, plic->num_sources);
 442     plic->target_priority = g_new(uint32_t, plic->num_addrs);
 443     plic->pending = g_new0(uint32_t, plic->bitfield_words);
 444     plic->claimed = g_new0(uint32_t, plic->bitfield_words);
 445     plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 446     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
 447     qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
 448
 449     /* We can't allow the supervisor to control SEIP as this would allow the
 450      * supervisor to clear a pending external interrupt which will result in
 451      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
 452      * hardware controlled when a PLIC is attached.
 453      */
 454     for (i = 0; i < smp_cpus; i++) {
 455         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 456         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 457             error_report("SEIP already claimed");
 458             exit(1);
 459         }
 460     }
 461
 462     msi_nonbroken = true;
 463 }
 464
 465 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 466 {
 467     DeviceClass *dc = DEVICE_CLASS(klass);
 468
 469     device_class_set_props(dc, sifive_plic_properties);
 470     dc->realize = sifive_plic_realize;
 471 }
 472
 473 static const TypeInfo sifive_plic_info = {
 474     .name          = TYPE_SIFIVE_PLIC,
 475     .parent        = TYPE_SYS_BUS_DEVICE,
 476     .instance_size = sizeof(SiFivePLICState),
 477     .class_init    = sifive_plic_class_init,
 478 };
 479
 480 static void sifive_plic_register_types(void)
 481 {
 482     type_register_static(&sifive_plic_info);
 483 }
 484
 485 type_init(sifive_plic_register_types)
 486
 487 /*
 488  * Create PLIC device.
 489  */
 490 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 491     uint32_t num_sources, uint32_t num_priorities,
 492     uint32_t priority_base, uint32_t pending_base,
 493     uint32_t enable_base, uint32_t enable_stride,
 494     uint32_t context_base, uint32_t context_stride,
 495     uint32_t aperture_size)
 496 {
 497     DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC);
 498     assert(enable_stride == (enable_stride & -enable_stride));
 499     assert(context_stride == (context_stride & -context_stride));
 500     qdev_prop_set_string(dev, "hart-config", hart_config);
 501     qdev_prop_set_uint32(dev, "num-sources", num_sources);
 502     qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
 503     qdev_prop_set_uint32(dev, "priority-base", priority_base);
 504     qdev_prop_set_uint32(dev, "pending-base", pending_base);
 505     qdev_prop_set_uint32(dev, "enable-base", enable_base);
 506     qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
 507     qdev_prop_set_uint32(dev, "context-base", context_base);
 508     qdev_prop_set_uint32(dev, "context-stride", context_stride);
 509     qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
 510     qdev_init_nofail(dev);
 511     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 512     return dev;
 513 }