target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #include "config.h"
  23
  24 #if defined(TARGET_AARCH64)
  25   /* AArch64 definitions */
  26 #  define TARGET_LONG_BITS 64
  27 #  define ELF_MACHINE EM_AARCH64
  28 #else
  29 #  define TARGET_LONG_BITS 32
  30 #  define ELF_MACHINE EM_ARM
  31 #endif
  32
  33 #define CPUArchState struct CPUARMState
  34
  35 #include "qemu-common.h"
  36 #include "exec/cpu-defs.h"
  37
  38 #include "fpu/softfloat.h"
  39
  40 #define TARGET_HAS_ICE 1
  41
  42 #define EXCP_UDEF            1   /* undefined instruction */
  43 #define EXCP_SWI             2   /* software interrupt */
  44 #define EXCP_PREFETCH_ABORT  3
  45 #define EXCP_DATA_ABORT      4
  46 #define EXCP_IRQ             5
  47 #define EXCP_FIQ             6
  48 #define EXCP_BKPT            7
  49 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  50 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  51 #define EXCP_STREX          10
  52
  53 #define ARMV7M_EXCP_RESET   1
  54 #define ARMV7M_EXCP_NMI     2
  55 #define ARMV7M_EXCP_HARD    3
  56 #define ARMV7M_EXCP_MEM     4
  57 #define ARMV7M_EXCP_BUS     5
  58 #define ARMV7M_EXCP_USAGE   6
  59 #define ARMV7M_EXCP_SVC     11
  60 #define ARMV7M_EXCP_DEBUG   12
  61 #define ARMV7M_EXCP_PENDSV  14
  62 #define ARMV7M_EXCP_SYSTICK 15
  63
  64 /* ARM-specific interrupt pending bits.  */
  65 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  66
  67 /* Meanings of the ARMCPU object's two inbound GPIO lines */
  68 #define ARM_CPU_IRQ 0
  69 #define ARM_CPU_FIQ 1
  70
  71 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  72                             int srcreg, int operand, uint32_t value);
  73 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  74                                int dstreg, int operand);
  75
  76 struct arm_boot_info;
  77
  78 #define NB_MMU_MODES 2
  79
  80 /* We currently assume float and double are IEEE single and double
  81    precision respectively.
  82    Doing runtime conversions is tricky because VFP registers may contain
  83    integer values (eg. as the result of a FTOSI instruction).
  84    s<2n> maps to the least significant half of d<n>
  85    s<2n+1> maps to the most significant half of d<n>
  86  */
  87
  88 /* CPU state for each instance of a generic timer (in cp15 c14) */
  89 typedef struct ARMGenericTimer {
  90     uint64_t cval; /* Timer CompareValue register */
  91     uint32_t ctl; /* Timer Control register */
  92 } ARMGenericTimer;
  93
  94 #define GTIMER_PHYS 0
  95 #define GTIMER_VIRT 1
  96 #define NUM_GTIMERS 2
  97
  98 /* Scale factor for generic timers, ie number of ns per tick.
  99  * This gives a 62.5MHz timer.
 100  */
 101 #define GTIMER_SCALE 16
 102
 103 typedef struct CPUARMState {
 104     /* Regs for current mode.  */
 105     uint32_t regs[16];
 106
 107     /* 32/64 switch only happens when taking and returning from
 108      * exceptions so the overlap semantics are taken care of then
 109      * instead of having a complicated union.
 110      */
 111     /* Regs for A64 mode.  */
 112     uint64_t xregs[32];
 113     uint64_t pc;
 114     /* TODO: pstate doesn't correspond to an architectural register;
 115      * it would be better modelled as the underlying fields.
 116      */
 117     uint32_t pstate;
 118     uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
 119
 120     /* Frequently accessed CPSR bits are stored separately for efficiency.
 121        This contains all the other bits.  Use cpsr_{read,write} to access
 122        the whole CPSR.  */
 123     uint32_t uncached_cpsr;
 124     uint32_t spsr;
 125
 126     /* Banked registers.  */
 127     uint32_t banked_spsr[6];
 128     uint32_t banked_r13[6];
 129     uint32_t banked_r14[6];
 130
 131     /* These hold r8-r12.  */
 132     uint32_t usr_regs[5];
 133     uint32_t fiq_regs[5];
 134
 135     /* cpsr flag cache for faster execution */
 136     uint32_t CF; /* 0 or 1 */
 137     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 138     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 139     uint32_t ZF; /* Z set if zero.  */
 140     uint32_t QF; /* 0 or 1 */
 141     uint32_t GE; /* cpsr[19:16] */
 142     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 143     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 144
 145     /* System control coprocessor (cp15) */
 146     struct {
 147         uint32_t c0_cpuid;
 148         uint32_t c0_cssel; /* Cache size selection.  */
 149         uint32_t c1_sys; /* System control register.  */
 150         uint32_t c1_coproc; /* Coprocessor access register.  */
 151         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 152         uint32_t c1_scr; /* secure config register.  */
 153         uint32_t c2_base0; /* MMU translation table base 0.  */
 154         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 155         uint32_t c2_base1; /* MMU translation table base 0.  */
 156         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 157         uint32_t c2_control; /* MMU translation table base control.  */
 158         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 159         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 160         uint32_t c2_data; /* MPU data cachable bits.  */
 161         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 162         uint32_t c3; /* MMU domain access control register
 163                         MPU write buffer control.  */
 164         uint32_t c5_insn; /* Fault status registers.  */
 165         uint32_t c5_data;
 166         uint32_t c6_region[8]; /* MPU base/size registers.  */
 167         uint32_t c6_insn; /* Fault address registers.  */
 168         uint32_t c6_data;
 169         uint32_t c7_par;  /* Translation result. */
 170         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 171         uint32_t c9_insn; /* Cache lockdown registers.  */
 172         uint32_t c9_data;
 173         uint32_t c9_pmcr; /* performance monitor control register */
 174         uint32_t c9_pmcnten; /* perf monitor counter enables */
 175         uint32_t c9_pmovsr; /* perf monitor overflow status */
 176         uint32_t c9_pmxevtyper; /* perf monitor event type */
 177         uint32_t c9_pmuserenr; /* perf monitor user enable */
 178         uint32_t c9_pminten; /* perf monitor interrupt enables */
 179         uint32_t c13_fcse; /* FCSE PID.  */
 180         uint32_t c13_context; /* Context ID.  */
 181         uint32_t c13_tls1; /* User RW Thread register.  */
 182         uint32_t c13_tls2; /* User RO Thread register.  */
 183         uint32_t c13_tls3; /* Privileged Thread register.  */
 184         uint32_t c14_cntfrq; /* Counter Frequency register */
 185         uint32_t c14_cntkctl; /* Timer Control register */
 186         ARMGenericTimer c14_timer[NUM_GTIMERS];
 187         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 188         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 189         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 190         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 191         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 192         uint32_t c15_config_base_address; /* SCU base address.  */
 193         uint32_t c15_diagnostic; /* diagnostic register */
 194         uint32_t c15_power_diagnostic;
 195         uint32_t c15_power_control; /* power control */
 196     } cp15;
 197
 198     /* System registers (AArch64) */
 199     struct {
 200         uint64_t tpidr_el0;
 201     } sr;
 202
 203     struct {
 204         uint32_t other_sp;
 205         uint32_t vecbase;
 206         uint32_t basepri;
 207         uint32_t control;
 208         int current_sp;
 209         int exception;
 210         int pending_exception;
 211     } v7m;
 212
 213     /* Thumb-2 EE state.  */
 214     uint32_t teecr;
 215     uint32_t teehbr;
 216
 217     /* VFP coprocessor state.  */
 218     struct {
 219         /* VFP/Neon register state. Note that the mapping between S, D and Q
 220          * views of the register bank differs between AArch64 and AArch32:
 221          * In AArch32:
 222          *  Qn = regs[2n+1]:regs[2n]
 223          *  Dn = regs[n]
 224          *  Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
 225          * (and regs[32] to regs[63] are inaccessible)
 226          * In AArch64:
 227          *  Qn = regs[2n+1]:regs[2n]
 228          *  Dn = regs[2n]
 229          *  Sn = regs[2n] bits 31..0
 230          * This corresponds to the architecturally defined mapping between
 231          * the two execution states, and means we do not need to explicitly
 232          * map these registers when changing states.
 233          */
 234         float64 regs[64];
 235
 236         uint32_t xregs[16];
 237         /* We store these fpcsr fields separately for convenience.  */
 238         int vec_len;
 239         int vec_stride;
 240
 241         /* scratch space when Tn are not sufficient.  */
 242         uint32_t scratch[8];
 243
 244         /* fp_status is the "normal" fp status. standard_fp_status retains
 245          * values corresponding to the ARM "Standard FPSCR Value", ie
 246          * default-NaN, flush-to-zero, round-to-nearest and is used by
 247          * any operations (generally Neon) which the architecture defines
 248          * as controlled by the standard FPSCR value rather than the FPSCR.
 249          *
 250          * To avoid having to transfer exception bits around, we simply
 251          * say that the FPSCR cumulative exception flags are the logical
 252          * OR of the flags in the two fp statuses. This relies on the
 253          * only thing which needs to read the exception flags being
 254          * an explicit FPSCR read.
 255          */
 256         float_status fp_status;
 257         float_status standard_fp_status;
 258     } vfp;
 259     uint32_t exclusive_addr;
 260     uint32_t exclusive_val;
 261     uint32_t exclusive_high;
 262 #if defined(CONFIG_USER_ONLY)
 263     uint32_t exclusive_test;
 264     uint32_t exclusive_info;
 265 #endif
 266
 267     /* iwMMXt coprocessor state.  */
 268     struct {
 269         uint64_t regs[16];
 270         uint64_t val;
 271
 272         uint32_t cregs[16];
 273     } iwmmxt;
 274
 275     /* For mixed endian mode.  */
 276     bool bswap_code;
 277
 278 #if defined(CONFIG_USER_ONLY)
 279     /* For usermode syscall translation.  */
 280     int eabi;
 281 #endif
 282
 283     CPU_COMMON
 284
 285     /* These fields after the common ones so they are preserved on reset.  */
 286
 287     /* Internal CPU feature flags.  */
 288     uint64_t features;
 289
 290     void *nvic;
 291     const struct arm_boot_info *boot_info;
 292 } CPUARMState;
 293
 294 #include "cpu-qom.h"
 295
 296 ARMCPU *cpu_arm_init(const char *cpu_model);
 297 void arm_translate_init(void);
 298 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 299 int cpu_arm_exec(CPUARMState *s);
 300 int bank_number(int mode);
 301 void switch_mode(CPUARMState *, int);
 302 uint32_t do_arm_semihosting(CPUARMState *env);
 303
 304 static inline bool is_a64(CPUARMState *env)
 305 {
 306     return env->aarch64;
 307 }
 308
 309 #define PSTATE_N_SHIFT 3
 310 #define PSTATE_N  (1 << PSTATE_N_SHIFT)
 311 #define PSTATE_Z_SHIFT 2
 312 #define PSTATE_Z  (1 << PSTATE_Z_SHIFT)
 313 #define PSTATE_C_SHIFT 1
 314 #define PSTATE_C  (1 << PSTATE_C_SHIFT)
 315 #define PSTATE_V_SHIFT 0
 316 #define PSTATE_V  (1 << PSTATE_V_SHIFT)
 317
 318 /* you can call this signal handler from your SIGBUS and SIGSEGV
 319    signal handlers to inform the virtual CPU of exceptions. non zero
 320    is returned if the signal was handled by the virtual CPU.  */
 321 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 322                            void *puc);
 323 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 324                               int mmu_idx);
 325 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 326
 327 #define CPSR_M (0x1fU)
 328 #define CPSR_T (1U << 5)
 329 #define CPSR_F (1U << 6)
 330 #define CPSR_I (1U << 7)
 331 #define CPSR_A (1U << 8)
 332 #define CPSR_E (1U << 9)
 333 #define CPSR_IT_2_7 (0xfc00U)
 334 #define CPSR_GE (0xfU << 16)
 335 #define CPSR_RESERVED (0xfU << 20)
 336 #define CPSR_J (1U << 24)
 337 #define CPSR_IT_0_1 (3U << 25)
 338 #define CPSR_Q (1U << 27)
 339 #define CPSR_V (1U << 28)
 340 #define CPSR_C (1U << 29)
 341 #define CPSR_Z (1U << 30)
 342 #define CPSR_N (1U << 31)
 343 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 344
 345 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 346 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 347 /* Bits writable in user mode.  */
 348 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 349 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 350 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 351
 352 /* Return the current CPSR value.  */
 353 uint32_t cpsr_read(CPUARMState *env);
 354 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 355 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 356
 357 /* Return the current xPSR value.  */
 358 static inline uint32_t xpsr_read(CPUARMState *env)
 359 {
 360     int ZF;
 361     ZF = (env->ZF == 0);
 362     return (env->NF & 0x80000000) | (ZF << 30)
 363         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 364         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 365         | ((env->condexec_bits & 0xfc) << 8)
 366         | env->v7m.exception;
 367 }
 368
 369 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 370 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 371 {
 372     if (mask & CPSR_NZCV) {
 373         env->ZF = (~val) & CPSR_Z;
 374         env->NF = val;
 375         env->CF = (val >> 29) & 1;
 376         env->VF = (val << 3) & 0x80000000;
 377     }
 378     if (mask & CPSR_Q)
 379         env->QF = ((val & CPSR_Q) != 0);
 380     if (mask & (1 << 24))
 381         env->thumb = ((val & (1 << 24)) != 0);
 382     if (mask & CPSR_IT_0_1) {
 383         env->condexec_bits &= ~3;
 384         env->condexec_bits |= (val >> 25) & 3;
 385     }
 386     if (mask & CPSR_IT_2_7) {
 387         env->condexec_bits &= 3;
 388         env->condexec_bits |= (val >> 8) & 0xfc;
 389     }
 390     if (mask & 0x1ff) {
 391         env->v7m.exception = val & 0x1ff;
 392     }
 393 }
 394
 395 /* Return the current FPSCR value.  */
 396 uint32_t vfp_get_fpscr(CPUARMState *env);
 397 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 398
 399 enum arm_cpu_mode {
 400   ARM_CPU_MODE_USR = 0x10,
 401   ARM_CPU_MODE_FIQ = 0x11,
 402   ARM_CPU_MODE_IRQ = 0x12,
 403   ARM_CPU_MODE_SVC = 0x13,
 404   ARM_CPU_MODE_ABT = 0x17,
 405   ARM_CPU_MODE_UND = 0x1b,
 406   ARM_CPU_MODE_SYS = 0x1f
 407 };
 408
 409 /* VFP system registers.  */
 410 #define ARM_VFP_FPSID   0
 411 #define ARM_VFP_FPSCR   1
 412 #define ARM_VFP_MVFR1   6
 413 #define ARM_VFP_MVFR0   7
 414 #define ARM_VFP_FPEXC   8
 415 #define ARM_VFP_FPINST  9
 416 #define ARM_VFP_FPINST2 10
 417
 418 /* iwMMXt coprocessor control registers.  */
 419 #define ARM_IWMMXT_wCID         0
 420 #define ARM_IWMMXT_wCon         1
 421 #define ARM_IWMMXT_wCSSF        2
 422 #define ARM_IWMMXT_wCASF        3
 423 #define ARM_IWMMXT_wCGR0        8
 424 #define ARM_IWMMXT_wCGR1        9
 425 #define ARM_IWMMXT_wCGR2        10
 426 #define ARM_IWMMXT_wCGR3        11
 427
 428 /* If adding a feature bit which corresponds to a Linux ELF
 429  * HWCAP bit, remember to update the feature-bit-to-hwcap
 430  * mapping in linux-user/elfload.c:get_elf_hwcap().
 431  */
 432 enum arm_features {
 433     ARM_FEATURE_VFP,
 434     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 435     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 436     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 437     ARM_FEATURE_V6,
 438     ARM_FEATURE_V6K,
 439     ARM_FEATURE_V7,
 440     ARM_FEATURE_THUMB2,
 441     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 442     ARM_FEATURE_VFP3,
 443     ARM_FEATURE_VFP_FP16,
 444     ARM_FEATURE_NEON,
 445     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 446     ARM_FEATURE_M, /* Microcontroller profile.  */
 447     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 448     ARM_FEATURE_THUMB2EE,
 449     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 450     ARM_FEATURE_V4T,
 451     ARM_FEATURE_V5,
 452     ARM_FEATURE_STRONGARM,
 453     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 454     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 455     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 456     ARM_FEATURE_GENERIC_TIMER,
 457     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 458     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 459     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 460     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 461     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 462     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 463     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 464     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 465     ARM_FEATURE_V8,
 466     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
 467 };
 468
 469 static inline int arm_feature(CPUARMState *env, int feature)
 470 {
 471     return (env->features & (1ULL << feature)) != 0;
 472 }
 473
 474 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 475
 476 /* Interface between CPU and Interrupt controller.  */
 477 void armv7m_nvic_set_pending(void *opaque, int irq);
 478 int armv7m_nvic_acknowledge_irq(void *opaque);
 479 void armv7m_nvic_complete_irq(void *opaque, int irq);
 480
 481 /* Interface for defining coprocessor registers.
 482  * Registers are defined in tables of arm_cp_reginfo structs
 483  * which are passed to define_arm_cp_regs().
 484  */
 485
 486 /* When looking up a coprocessor register we look for it
 487  * via an integer which encodes all of:
 488  *  coprocessor number
 489  *  Crn, Crm, opc1, opc2 fields
 490  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 491  *    or via MRRC/MCRR?)
 492  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 493  * (In this case crn and opc2 should be zero.)
 494  */
 495 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 496     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 497      ((crm) << 7) | ((opc1) << 3) | (opc2))
 498
 499 /* Note that these must line up with the KVM/ARM register
 500  * ID field definitions (kvm.c will check this, but we
 501  * can't just use the KVM defines here as the kvm headers
 502  * are unavailable to non-KVM-specific files)
 503  */
 504 #define CP_REG_SIZE_SHIFT 52
 505 #define CP_REG_SIZE_MASK       0x00f0000000000000ULL
 506 #define CP_REG_SIZE_U32        0x0020000000000000ULL
 507 #define CP_REG_SIZE_U64        0x0030000000000000ULL
 508 #define CP_REG_ARM             0x4000000000000000ULL
 509
 510 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
 511  * version used as a key for the coprocessor register hashtable
 512  */
 513 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 514 {
 515     uint32_t cpregid = kvmid;
 516     if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 517         cpregid |= (1 << 15);
 518     }
 519     return cpregid;
 520 }
 521
 522 /* Convert a truncated 32 bit hashtable key into the full
 523  * 64 bit KVM register ID.
 524  */
 525 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 526 {
 527     uint64_t kvmid = cpregid & ~(1 << 15);
 528     if (cpregid & (1 << 15)) {
 529         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 530     } else {
 531         kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 532     }
 533     return kvmid;
 534 }
 535
 536 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 537  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 538  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 539  * TCG can assume the value to be constant (ie load at translate time)
 540  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 541  * indicates that the TB should not be ended after a write to this register
 542  * (the default is that the TB ends after cp writes). OVERRIDE permits
 543  * a register definition to override a previous definition for the
 544  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 545  * old must have the OVERRIDE bit set.
 546  * NO_MIGRATE indicates that this register should be ignored for migration;
 547  * (eg because any state is accessed via some other coprocessor register).
 548  * IO indicates that this register does I/O and therefore its accesses
 549  * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
 550  * registers which implement clocks or timers require this.
 551  */
 552 #define ARM_CP_SPECIAL 1
 553 #define ARM_CP_CONST 2
 554 #define ARM_CP_64BIT 4
 555 #define ARM_CP_SUPPRESS_TB_END 8
 556 #define ARM_CP_OVERRIDE 16
 557 #define ARM_CP_NO_MIGRATE 32
 558 #define ARM_CP_IO 64
 559 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 560 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 561 #define ARM_LAST_SPECIAL ARM_CP_WFI
 562 /* Used only as a terminator for ARMCPRegInfo lists */
 563 #define ARM_CP_SENTINEL 0xffff
 564 /* Mask of only the flag bits in a type field */
 565 #define ARM_CP_FLAG_MASK 0x7f
 566
 567 /* Return true if cptype is a valid type field. This is used to try to
 568  * catch errors where the sentinel has been accidentally left off the end
 569  * of a list of registers.
 570  */
 571 static inline bool cptype_valid(int cptype)
 572 {
 573     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 574         || ((cptype & ARM_CP_SPECIAL) &&
 575             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 576 }
 577
 578 /* Access rights:
 579  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 580  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 581  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 582  * (ie any of the privileged modes in Secure state, or Monitor mode).
 583  * If a register is accessible in one privilege level it's always accessible
 584  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 585  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 586  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 587  * terminology a little and call this PL3.
 588  *
 589  * If access permissions for a register are more complex than can be
 590  * described with these bits, then use a laxer set of restrictions, and
 591  * do the more restrictive/complex check inside a helper function.
 592  */
 593 #define PL3_R 0x80
 594 #define PL3_W 0x40
 595 #define PL2_R (0x20 | PL3_R)
 596 #define PL2_W (0x10 | PL3_W)
 597 #define PL1_R (0x08 | PL2_R)
 598 #define PL1_W (0x04 | PL2_W)
 599 #define PL0_R (0x02 | PL1_R)
 600 #define PL0_W (0x01 | PL1_W)
 601
 602 #define PL3_RW (PL3_R | PL3_W)
 603 #define PL2_RW (PL2_R | PL2_W)
 604 #define PL1_RW (PL1_R | PL1_W)
 605 #define PL0_RW (PL0_R | PL0_W)
 606
 607 static inline int arm_current_pl(CPUARMState *env)
 608 {
 609     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 610         return 0;
 611     }
 612     /* We don't currently implement the Virtualization or TrustZone
 613      * extensions, so PL2 and PL3 don't exist for us.
 614      */
 615     return 1;
 616 }
 617
 618 typedef struct ARMCPRegInfo ARMCPRegInfo;
 619
 620 /* Access functions for coprocessor registers. These should return
 621  * 0 on success, or one of the EXCP_* constants if access should cause
 622  * an exception (in which case *value is not written).
 623  */
 624 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 625                      uint64_t *value);
 626 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 627                       uint64_t value);
 628 /* Hook function for register reset */
 629 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 630
 631 #define CP_ANY 0xff
 632
 633 /* Definition of an ARM coprocessor register */
 634 struct ARMCPRegInfo {
 635     /* Name of register (useful mainly for debugging, need not be unique) */
 636     const char *name;
 637     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 638      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 639      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 640      * will be decoded to this register. The register read and write
 641      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 642      * used by the program, so it is possible to register a wildcard and
 643      * then behave differently on read/write if necessary.
 644      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 645      * must both be zero.
 646      */
 647     uint8_t cp;
 648     uint8_t crn;
 649     uint8_t crm;
 650     uint8_t opc1;
 651     uint8_t opc2;
 652     /* Register type: ARM_CP_* bits/values */
 653     int type;
 654     /* Access rights: PL*_[RW] */
 655     int access;
 656     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 657      * this register was defined: can be used to hand data through to the
 658      * register read/write functions, since they are passed the ARMCPRegInfo*.
 659      */
 660     void *opaque;
 661     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 662      * fieldoffset is non-zero, the reset value of the register.
 663      */
 664     uint64_t resetvalue;
 665     /* Offset of the field in CPUARMState for this register. This is not
 666      * needed if either:
 667      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 668      *  2. both readfn and writefn are specified
 669      */
 670     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 671     /* Function for handling reads of this register. If NULL, then reads
 672      * will be done by loading from the offset into CPUARMState specified
 673      * by fieldoffset.
 674      */
 675     CPReadFn *readfn;
 676     /* Function for handling writes of this register. If NULL, then writes
 677      * will be done by writing to the offset into CPUARMState specified
 678      * by fieldoffset.
 679      */
 680     CPWriteFn *writefn;
 681     /* Function for doing a "raw" read; used when we need to copy
 682      * coprocessor state to the kernel for KVM or out for
 683      * migration. This only needs to be provided if there is also a
 684      * readfn and it makes an access permission check.
 685      */
 686     CPReadFn *raw_readfn;
 687     /* Function for doing a "raw" write; used when we need to copy KVM
 688      * kernel coprocessor state into userspace, or for inbound
 689      * migration. This only needs to be provided if there is also a
 690      * writefn and it makes an access permission check or masks out
 691      * "unwritable" bits or has write-one-to-clear or similar behaviour.
 692      */
 693     CPWriteFn *raw_writefn;
 694     /* Function for resetting the register. If NULL, then reset will be done
 695      * by writing resetvalue to the field specified in fieldoffset. If
 696      * fieldoffset is 0 then no reset will be done.
 697      */
 698     CPResetFn *resetfn;
 699 };
 700
 701 /* Macros which are lvalues for the field in CPUARMState for the
 702  * ARMCPRegInfo *ri.
 703  */
 704 #define CPREG_FIELD32(env, ri) \
 705     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 706 #define CPREG_FIELD64(env, ri) \
 707     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 708
 709 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 710
 711 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 712                                     const ARMCPRegInfo *regs, void *opaque);
 713 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 714                                        const ARMCPRegInfo *regs, void *opaque);
 715 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 716 {
 717     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 718 }
 719 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 720 {
 721     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 722 }
 723 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 724
 725 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 726 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 727                         uint64_t value);
 728 /* CPReadFn that can be used for read-as-zero behaviour */
 729 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 730
 731 static inline bool cp_access_ok(CPUARMState *env,
 732                                 const ARMCPRegInfo *ri, int isread)
 733 {
 734     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 735 }
 736
 737 /**
 738  * write_list_to_cpustate
 739  * @cpu: ARMCPU
 740  *
 741  * For each register listed in the ARMCPU cpreg_indexes list, write
 742  * its value from the cpreg_values list into the ARMCPUState structure.
 743  * This updates TCG's working data structures from KVM data or
 744  * from incoming migration state.
 745  *
 746  * Returns: true if all register values were updated correctly,
 747  * false if some register was unknown or could not be written.
 748  * Note that we do not stop early on failure -- we will attempt
 749  * writing all registers in the list.
 750  */
 751 bool write_list_to_cpustate(ARMCPU *cpu);
 752
 753 /**
 754  * write_cpustate_to_list:
 755  * @cpu: ARMCPU
 756  *
 757  * For each register listed in the ARMCPU cpreg_indexes list, write
 758  * its value from the ARMCPUState structure into the cpreg_values list.
 759  * This is used to copy info from TCG's working data structures into
 760  * KVM or for outbound migration.
 761  *
 762  * Returns: true if all register values were read correctly,
 763  * false if some register was unknown or could not be read.
 764  * Note that we do not stop early on failure -- we will attempt
 765  * reading all registers in the list.
 766  */
 767 bool write_cpustate_to_list(ARMCPU *cpu);
 768
 769 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 770    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 771    conventional cores (ie. Application or Realtime profile).  */
 772
 773 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 774
 775 #define ARM_CPUID_TI915T      0x54029152
 776 #define ARM_CPUID_TI925T      0x54029252
 777
 778 #if defined(CONFIG_USER_ONLY)
 779 #define TARGET_PAGE_BITS 12
 780 #else
 781 /* The ARM MMU allows 1k pages.  */
 782 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 783    architecture revisions.  Maybe a configure option to disable them.  */
 784 #define TARGET_PAGE_BITS 10
 785 #endif
 786
 787 #if defined(TARGET_AARCH64)
 788 #  define TARGET_PHYS_ADDR_SPACE_BITS 48
 789 #  define TARGET_VIRT_ADDR_SPACE_BITS 64
 790 #else
 791 #  define TARGET_PHYS_ADDR_SPACE_BITS 40
 792 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 793 #endif
 794
 795 static inline CPUARMState *cpu_init(const char *cpu_model)
 796 {
 797     ARMCPU *cpu = cpu_arm_init(cpu_model);
 798     if (cpu) {
 799         return &cpu->env;
 800     }
 801     return NULL;
 802 }
 803
 804 #define cpu_exec cpu_arm_exec
 805 #define cpu_gen_code cpu_arm_gen_code
 806 #define cpu_signal_handler cpu_arm_signal_handler
 807 #define cpu_list arm_cpu_list
 808
 809 /* MMU modes definitions */
 810 #define MMU_MODE0_SUFFIX _kernel
 811 #define MMU_MODE1_SUFFIX _user
 812 #define MMU_USER_IDX 1
 813 static inline int cpu_mmu_index (CPUARMState *env)
 814 {
 815     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 816 }
 817
 818 #include "exec/cpu-all.h"
 819
 820 /* Bit usage in the TB flags field: bit 31 indicates whether we are
 821  * in 32 or 64 bit mode. The meaning of the other bits depends on that.
 822  */
 823 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
 824 #define ARM_TBFLAG_AARCH64_STATE_MASK  (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
 825
 826 /* Bit usage when in AArch32 state: */
 827 #define ARM_TBFLAG_THUMB_SHIFT      0
 828 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 829 #define ARM_TBFLAG_VECLEN_SHIFT     1
 830 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 831 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 832 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 833 #define ARM_TBFLAG_PRIV_SHIFT       6
 834 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 835 #define ARM_TBFLAG_VFPEN_SHIFT      7
 836 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 837 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 838 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 839 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 840 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 841
 842 /* Bit usage when in AArch64 state: currently no bits defined */
 843
 844 /* some convenience accessor macros */
 845 #define ARM_TBFLAG_AARCH64_STATE(F) \
 846     (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
 847 #define ARM_TBFLAG_THUMB(F) \
 848     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 849 #define ARM_TBFLAG_VECLEN(F) \
 850     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 851 #define ARM_TBFLAG_VECSTRIDE(F) \
 852     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 853 #define ARM_TBFLAG_PRIV(F) \
 854     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 855 #define ARM_TBFLAG_VFPEN(F) \
 856     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 857 #define ARM_TBFLAG_CONDEXEC(F) \
 858     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 859 #define ARM_TBFLAG_BSWAP_CODE(F) \
 860     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 861
 862 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 863                                         target_ulong *cs_base, int *flags)
 864 {
 865     if (is_a64(env)) {
 866         *pc = env->pc;
 867         *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
 868     } else {
 869         int privmode;
 870         *pc = env->regs[15];
 871         *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 872             | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 873             | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 874             | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 875             | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 876         if (arm_feature(env, ARM_FEATURE_M)) {
 877             privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 878         } else {
 879             privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 880         }
 881         if (privmode) {
 882             *flags |= ARM_TBFLAG_PRIV_MASK;
 883         }
 884         if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 885             *flags |= ARM_TBFLAG_VFPEN_MASK;
 886         }
 887     }
 888
 889     *cs_base = 0;
 890 }
 891
 892 static inline bool cpu_has_work(CPUState *cpu)
 893 {
 894     return cpu->interrupt_request &
 895         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 896 }
 897
 898 #include "exec/exec-all.h"
 899
 900 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 901 {
 902     if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
 903         env->pc = tb->pc;
 904     } else {
 905         env->regs[15] = tb->pc;
 906     }
 907 }
 908
 909 /* Load an instruction and return it in the standard little-endian order */
 910 static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
 911                                     bool do_swap)
 912 {
 913     uint32_t insn = cpu_ldl_code(env, addr);
 914     if (do_swap) {
 915         return bswap32(insn);
 916     }
 917     return insn;
 918 }
 919
 920 /* Ditto, for a halfword (Thumb) instruction */
 921 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
 922                                      bool do_swap)
 923 {
 924     uint16_t insn = cpu_lduw_code(env, addr);
 925     if (do_swap) {
 926         return bswap16(insn);
 927     }
 928     return insn;
 929 }
 930
 931 #endif