target-mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "kvm_mips.h"
  23 #include "qemu-common.h"
  24 #include "sysemu/kvm.h"
  25
  26
  27 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  28 {
  29     MIPSCPU *cpu = MIPS_CPU(cs);
  30     CPUMIPSState *env = &cpu->env;
  31
  32     env->active_tc.PC = value & ~(target_ulong)1;
  33     if (value & 1) {
  34         env->hflags |= MIPS_HFLAG_M16;
  35     } else {
  36         env->hflags &= ~(MIPS_HFLAG_M16);
  37     }
  38 }
  39
  40 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  41 {
  42     MIPSCPU *cpu = MIPS_CPU(cs);
  43     CPUMIPSState *env = &cpu->env;
  44
  45     env->active_tc.PC = tb->pc;
  46     env->hflags &= ~MIPS_HFLAG_BMASK;
  47     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  48 }
  49
  50 static bool mips_cpu_has_work(CPUState *cs)
  51 {
  52     MIPSCPU *cpu = MIPS_CPU(cs);
  53     CPUMIPSState *env = &cpu->env;
  54     bool has_work = false;
  55
  56     /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
  57        interrupts wake-up the CPU, however most of the implementations only
  58        check for interrupts that can be taken. */
  59     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  60         cpu_mips_hw_interrupts_pending(env)) {
  61         if (cpu_mips_hw_interrupts_enabled(env) ||
  62             (env->insn_flags & ISA_MIPS32R6)) {
  63             has_work = true;
  64         }
  65     }
  66
  67     /* MIPS-MT has the ability to halt the CPU.  */
  68     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  69         /* The QEMU model will issue an _WAKE request whenever the CPUs
  70            should be woken up.  */
  71         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  72             has_work = true;
  73         }
  74
  75         if (!mips_vpe_active(env)) {
  76             has_work = false;
  77         }
  78     }
  79     return has_work;
  80 }
  81
  82 /* CPUClass::reset() */
  83 static void mips_cpu_reset(CPUState *s)
  84 {
  85     MIPSCPU *cpu = MIPS_CPU(s);
  86     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
  87     CPUMIPSState *env = &cpu->env;
  88
  89     mcc->parent_reset(s);
  90
  91     memset(env, 0, offsetof(CPUMIPSState, mvp));
  92     tlb_flush(s, 1);
  93
  94     cpu_state_reset(env);
  95
  96 #ifndef CONFIG_USER_ONLY
  97     if (kvm_enabled()) {
  98         kvm_mips_reset_vcpu(cpu);
  99     }
 100 #endif
 101 }
 102
 103 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
 104 #ifdef TARGET_WORDS_BIGENDIAN
 105     info->print_insn = print_insn_big_mips;
 106 #else
 107     info->print_insn = print_insn_little_mips;
 108 #endif
 109 }
 110
 111 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 112 {
 113     CPUState *cs = CPU(dev);
 114     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 115
 116     cpu_reset(cs);
 117     qemu_init_vcpu(cs);
 118
 119     mcc->parent_realize(dev, errp);
 120 }
 121
 122 static void mips_cpu_initfn(Object *obj)
 123 {
 124     CPUState *cs = CPU(obj);
 125     MIPSCPU *cpu = MIPS_CPU(obj);
 126     CPUMIPSState *env = &cpu->env;
 127
 128     cs->env_ptr = env;
 129     cpu_exec_init(cs, &error_abort);
 130
 131     if (tcg_enabled()) {
 132         mips_tcg_init();
 133     }
 134 }
 135
 136 static void mips_cpu_class_init(ObjectClass *c, void *data)
 137 {
 138     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 139     CPUClass *cc = CPU_CLASS(c);
 140     DeviceClass *dc = DEVICE_CLASS(c);
 141
 142     mcc->parent_realize = dc->realize;
 143     dc->realize = mips_cpu_realizefn;
 144
 145     mcc->parent_reset = cc->reset;
 146     cc->reset = mips_cpu_reset;
 147
 148     cc->has_work = mips_cpu_has_work;
 149     cc->do_interrupt = mips_cpu_do_interrupt;
 150     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 151     cc->dump_state = mips_cpu_dump_state;
 152     cc->set_pc = mips_cpu_set_pc;
 153     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 154     cc->gdb_read_register = mips_cpu_gdb_read_register;
 155     cc->gdb_write_register = mips_cpu_gdb_write_register;
 156 #ifdef CONFIG_USER_ONLY
 157     cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
 158 #else
 159     cc->do_unassigned_access = mips_cpu_unassigned_access;
 160     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 161     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 162     cc->vmsd = &vmstate_mips_cpu;
 163 #endif
 164     cc->disas_set_info = mips_cpu_disas_set_info;
 165
 166     cc->gdb_num_core_regs = 73;
 167     cc->gdb_stop_before_watchpoint = true;
 168
 169     /*
 170      * Reason: mips_cpu_initfn() calls cpu_exec_init(), which saves
 171      * the object in cpus -> dangling pointer after final
 172      * object_unref().
 173      */
 174     dc->cannot_destroy_with_object_finalize_yet = true;
 175 }
 176
 177 static const TypeInfo mips_cpu_type_info = {
 178     .name = TYPE_MIPS_CPU,
 179     .parent = TYPE_CPU,
 180     .instance_size = sizeof(MIPSCPU),
 181     .instance_init = mips_cpu_initfn,
 182     .abstract = false,
 183     .class_size = sizeof(MIPSCPUClass),
 184     .class_init = mips_cpu_class_init,
 185 };
 186
 187 static void mips_cpu_register_types(void)
 188 {
 189     type_register_static(&mips_cpu_type_info);
 190 }
 191
 192 type_init(mips_cpu_register_types)