target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13 #include "exec/semihost.h"
  14
  15 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  16
  17 #ifndef CONFIG_USER_ONLY
  18 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  19                           int access_type, ARMMMUIdx mmu_idx,
  20                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  21                           target_ulong *page_size, uint32_t *fsr,
  22                           ARMMMUFaultInfo *fi);
  23
  24 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  25                                int access_type, ARMMMUIdx mmu_idx,
  26                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  27                                target_ulong *page_size_ptr, uint32_t *fsr,
  28                                ARMMMUFaultInfo *fi);
  29
  30 /* Definitions for the PMCCNTR and PMCR registers */
  31 #define PMCRD   0x8
  32 #define PMCRC   0x4
  33 #define PMCRE   0x1
  34 #endif
  35
  36 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  37 {
  38     int nregs;
  39
  40     /* VFP data registers are always little-endian.  */
  41     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  42     if (reg < nregs) {
  43         stfq_le_p(buf, env->vfp.regs[reg]);
  44         return 8;
  45     }
  46     if (arm_feature(env, ARM_FEATURE_NEON)) {
  47         /* Aliases for Q regs.  */
  48         nregs += 16;
  49         if (reg < nregs) {
  50             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  51             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  52             return 16;
  53         }
  54     }
  55     switch (reg - nregs) {
  56     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  57     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  58     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  59     }
  60     return 0;
  61 }
  62
  63 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  64 {
  65     int nregs;
  66
  67     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  68     if (reg < nregs) {
  69         env->vfp.regs[reg] = ldfq_le_p(buf);
  70         return 8;
  71     }
  72     if (arm_feature(env, ARM_FEATURE_NEON)) {
  73         nregs += 16;
  74         if (reg < nregs) {
  75             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  76             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  77             return 16;
  78         }
  79     }
  80     switch (reg - nregs) {
  81     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  82     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  83     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  84     }
  85     return 0;
  86 }
  87
  88 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  89 {
  90     switch (reg) {
  91     case 0 ... 31:
  92         /* 128 bit FP register */
  93         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  94         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  95         return 16;
  96     case 32:
  97         /* FPSR */
  98         stl_p(buf, vfp_get_fpsr(env));
  99         return 4;
 100     case 33:
 101         /* FPCR */
 102         stl_p(buf, vfp_get_fpcr(env));
 103         return 4;
 104     default:
 105         return 0;
 106     }
 107 }
 108
 109 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 110 {
 111     switch (reg) {
 112     case 0 ... 31:
 113         /* 128 bit FP register */
 114         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 115         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 116         return 16;
 117     case 32:
 118         /* FPSR */
 119         vfp_set_fpsr(env, ldl_p(buf));
 120         return 4;
 121     case 33:
 122         /* FPCR */
 123         vfp_set_fpcr(env, ldl_p(buf));
 124         return 4;
 125     default:
 126         return 0;
 127     }
 128 }
 129
 130 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 131 {
 132     assert(ri->fieldoffset);
 133     if (cpreg_field_is_64bit(ri)) {
 134         return CPREG_FIELD64(env, ri);
 135     } else {
 136         return CPREG_FIELD32(env, ri);
 137     }
 138 }
 139
 140 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 141                       uint64_t value)
 142 {
 143     assert(ri->fieldoffset);
 144     if (cpreg_field_is_64bit(ri)) {
 145         CPREG_FIELD64(env, ri) = value;
 146     } else {
 147         CPREG_FIELD32(env, ri) = value;
 148     }
 149 }
 150
 151 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 152 {
 153     return (char *)env + ri->fieldoffset;
 154 }
 155
 156 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 157 {
 158     /* Raw read of a coprocessor register (as needed for migration, etc). */
 159     if (ri->type & ARM_CP_CONST) {
 160         return ri->resetvalue;
 161     } else if (ri->raw_readfn) {
 162         return ri->raw_readfn(env, ri);
 163     } else if (ri->readfn) {
 164         return ri->readfn(env, ri);
 165     } else {
 166         return raw_read(env, ri);
 167     }
 168 }
 169
 170 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 171                              uint64_t v)
 172 {
 173     /* Raw write of a coprocessor register (as needed for migration, etc).
 174      * Note that constant registers are treated as write-ignored; the
 175      * caller should check for success by whether a readback gives the
 176      * value written.
 177      */
 178     if (ri->type & ARM_CP_CONST) {
 179         return;
 180     } else if (ri->raw_writefn) {
 181         ri->raw_writefn(env, ri, v);
 182     } else if (ri->writefn) {
 183         ri->writefn(env, ri, v);
 184     } else {
 185         raw_write(env, ri, v);
 186     }
 187 }
 188
 189 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 190 {
 191    /* Return true if the regdef would cause an assertion if you called
 192     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 193     * program bug for it not to have the NO_RAW flag).
 194     * NB that returning false here doesn't necessarily mean that calling
 195     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 196     * read/write access functions which are safe for raw use" from "has
 197     * read/write access functions which have side effects but has forgotten
 198     * to provide raw access functions".
 199     * The tests here line up with the conditions in read/write_raw_cp_reg()
 200     * and assertions in raw_read()/raw_write().
 201     */
 202     if ((ri->type & ARM_CP_CONST) ||
 203         ri->fieldoffset ||
 204         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 205         return false;
 206     }
 207     return true;
 208 }
 209
 210 bool write_cpustate_to_list(ARMCPU *cpu)
 211 {
 212     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 213     int i;
 214     bool ok = true;
 215
 216     for (i = 0; i < cpu->cpreg_array_len; i++) {
 217         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 218         const ARMCPRegInfo *ri;
 219
 220         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 221         if (!ri) {
 222             ok = false;
 223             continue;
 224         }
 225         if (ri->type & ARM_CP_NO_RAW) {
 226             continue;
 227         }
 228         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 229     }
 230     return ok;
 231 }
 232
 233 bool write_list_to_cpustate(ARMCPU *cpu)
 234 {
 235     int i;
 236     bool ok = true;
 237
 238     for (i = 0; i < cpu->cpreg_array_len; i++) {
 239         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 240         uint64_t v = cpu->cpreg_values[i];
 241         const ARMCPRegInfo *ri;
 242
 243         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 244         if (!ri) {
 245             ok = false;
 246             continue;
 247         }
 248         if (ri->type & ARM_CP_NO_RAW) {
 249             continue;
 250         }
 251         /* Write value and confirm it reads back as written
 252          * (to catch read-only registers and partially read-only
 253          * registers where the incoming migration value doesn't match)
 254          */
 255         write_raw_cp_reg(&cpu->env, ri, v);
 256         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 257             ok = false;
 258         }
 259     }
 260     return ok;
 261 }
 262
 263 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 264 {
 265     ARMCPU *cpu = opaque;
 266     uint64_t regidx;
 267     const ARMCPRegInfo *ri;
 268
 269     regidx = *(uint32_t *)key;
 270     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 271
 272     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 273         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 274         /* The value array need not be initialized at this point */
 275         cpu->cpreg_array_len++;
 276     }
 277 }
 278
 279 static void count_cpreg(gpointer key, gpointer opaque)
 280 {
 281     ARMCPU *cpu = opaque;
 282     uint64_t regidx;
 283     const ARMCPRegInfo *ri;
 284
 285     regidx = *(uint32_t *)key;
 286     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 287
 288     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 289         cpu->cpreg_array_len++;
 290     }
 291 }
 292
 293 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 294 {
 295     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 296     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 297
 298     if (aidx > bidx) {
 299         return 1;
 300     }
 301     if (aidx < bidx) {
 302         return -1;
 303     }
 304     return 0;
 305 }
 306
 307 void init_cpreg_list(ARMCPU *cpu)
 308 {
 309     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 310      * Note that we require cpreg_tuples[] to be sorted by key ID.
 311      */
 312     GList *keys;
 313     int arraylen;
 314
 315     keys = g_hash_table_get_keys(cpu->cp_regs);
 316     keys = g_list_sort(keys, cpreg_key_compare);
 317
 318     cpu->cpreg_array_len = 0;
 319
 320     g_list_foreach(keys, count_cpreg, cpu);
 321
 322     arraylen = cpu->cpreg_array_len;
 323     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 324     cpu->cpreg_values = g_new(uint64_t, arraylen);
 325     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 328     cpu->cpreg_array_len = 0;
 329
 330     g_list_foreach(keys, add_cpreg_to_list, cpu);
 331
 332     assert(cpu->cpreg_array_len == arraylen);
 333
 334     g_list_free(keys);
 335 }
 336
 337 /*
 338  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 339  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 340  *
 341  * access_el3_aa32ns: Used to check AArch32 register views.
 342  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 343  */
 344 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 345                                         const ARMCPRegInfo *ri)
 346 {
 347     bool secure = arm_is_secure_below_el3(env);
 348
 349     assert(!arm_el_is_aa64(env, 3));
 350     if (secure) {
 351         return CP_ACCESS_TRAP_UNCATEGORIZED;
 352     }
 353     return CP_ACCESS_OK;
 354 }
 355
 356 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 357                                                 const ARMCPRegInfo *ri)
 358 {
 359     if (!arm_el_is_aa64(env, 3)) {
 360         return access_el3_aa32ns(env, ri);
 361     }
 362     return CP_ACCESS_OK;
 363 }
 364
 365 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 366 {
 367     ARMCPU *cpu = arm_env_get_cpu(env);
 368
 369     raw_write(env, ri, value);
 370     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 371 }
 372
 373 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 374 {
 375     ARMCPU *cpu = arm_env_get_cpu(env);
 376
 377     if (raw_read(env, ri) != value) {
 378         /* Unlike real hardware the qemu TLB uses virtual addresses,
 379          * not modified virtual addresses, so this causes a TLB flush.
 380          */
 381         tlb_flush(CPU(cpu), 1);
 382         raw_write(env, ri, value);
 383     }
 384 }
 385
 386 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 387                              uint64_t value)
 388 {
 389     ARMCPU *cpu = arm_env_get_cpu(env);
 390
 391     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 392         && !extended_addresses_enabled(env)) {
 393         /* For VMSA (when not using the LPAE long descriptor page table
 394          * format) this register includes the ASID, so do a TLB flush.
 395          * For PMSA it is purely a process ID and no action is needed.
 396          */
 397         tlb_flush(CPU(cpu), 1);
 398     }
 399     raw_write(env, ri, value);
 400 }
 401
 402 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 403                           uint64_t value)
 404 {
 405     /* Invalidate all (TLBIALL) */
 406     ARMCPU *cpu = arm_env_get_cpu(env);
 407
 408     tlb_flush(CPU(cpu), 1);
 409 }
 410
 411 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 412                           uint64_t value)
 413 {
 414     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 415     ARMCPU *cpu = arm_env_get_cpu(env);
 416
 417     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 418 }
 419
 420 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 421                            uint64_t value)
 422 {
 423     /* Invalidate by ASID (TLBIASID) */
 424     ARMCPU *cpu = arm_env_get_cpu(env);
 425
 426     tlb_flush(CPU(cpu), value == 0);
 427 }
 428
 429 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 430                            uint64_t value)
 431 {
 432     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 433     ARMCPU *cpu = arm_env_get_cpu(env);
 434
 435     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 436 }
 437
 438 /* IS variants of TLB operations must affect all cores */
 439 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 440                              uint64_t value)
 441 {
 442     CPUState *other_cs;
 443
 444     CPU_FOREACH(other_cs) {
 445         tlb_flush(other_cs, 1);
 446     }
 447 }
 448
 449 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 450                              uint64_t value)
 451 {
 452     CPUState *other_cs;
 453
 454     CPU_FOREACH(other_cs) {
 455         tlb_flush(other_cs, value == 0);
 456     }
 457 }
 458
 459 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 460                              uint64_t value)
 461 {
 462     CPUState *other_cs;
 463
 464     CPU_FOREACH(other_cs) {
 465         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 466     }
 467 }
 468
 469 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 470                              uint64_t value)
 471 {
 472     CPUState *other_cs;
 473
 474     CPU_FOREACH(other_cs) {
 475         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 476     }
 477 }
 478
 479 static const ARMCPRegInfo cp_reginfo[] = {
 480     /* Define the secure and non-secure FCSE identifier CP registers
 481      * separately because there is no secure bank in V8 (no _EL3).  This allows
 482      * the secure register to be properly reset and migrated. There is also no
 483      * v8 EL1 version of the register so the non-secure instance stands alone.
 484      */
 485     { .name = "FCSEIDR(NS)",
 486       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 487       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 488       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 489       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 490     { .name = "FCSEIDR(S)",
 491       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 492       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 493       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 494       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 495     /* Define the secure and non-secure context identifier CP registers
 496      * separately because there is no secure bank in V8 (no _EL3).  This allows
 497      * the secure register to be properly reset and migrated.  In the
 498      * non-secure case, the 32-bit register will have reset and migration
 499      * disabled during registration as it is handled by the 64-bit instance.
 500      */
 501     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 502       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 503       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 504       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 505       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 506     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 507       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 508       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 509       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 510       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 511     REGINFO_SENTINEL
 512 };
 513
 514 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 515     /* NB: Some of these registers exist in v8 but with more precise
 516      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 517      */
 518     /* MMU Domain access control / MPU write buffer control */
 519     { .name = "DACR",
 520       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 521       .access = PL1_RW, .resetvalue = 0,
 522       .writefn = dacr_write, .raw_writefn = raw_write,
 523       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 524                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 525     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 526      * For v6 and v5, these mappings are overly broad.
 527      */
 528     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 529       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 530     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 531       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 532     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 533       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 534     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 535       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 536     /* Cache maintenance ops; some of this space may be overridden later. */
 537     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 538       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 539       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 540     REGINFO_SENTINEL
 541 };
 542
 543 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 544     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 545      * over-broad.
 546      */
 547     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 548       .access = PL1_W, .type = ARM_CP_WFI },
 549     REGINFO_SENTINEL
 550 };
 551
 552 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 553     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 554      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 555      */
 556     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 557       .access = PL1_W, .type = ARM_CP_WFI },
 558     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 559      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 560      * OMAPCP will override this space.
 561      */
 562     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 563       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 564       .resetvalue = 0 },
 565     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 566       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 567       .resetvalue = 0 },
 568     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 569     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 570       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 571       .resetvalue = 0 },
 572     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 573      * implementing it as RAZ means the "debug architecture version" bits
 574      * will read as a reserved value, which should cause Linux to not try
 575      * to use the debug hardware.
 576      */
 577     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 578       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 579     /* MMU TLB control. Note that the wildcarding means we cover not just
 580      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 581      */
 582     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 583       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 584       .type = ARM_CP_NO_RAW },
 585     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 586       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 587       .type = ARM_CP_NO_RAW },
 588     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 589       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 590       .type = ARM_CP_NO_RAW },
 591     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 592       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 593       .type = ARM_CP_NO_RAW },
 594     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 595       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 596     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 597       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 598     REGINFO_SENTINEL
 599 };
 600
 601 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 602                         uint64_t value)
 603 {
 604     uint32_t mask = 0;
 605
 606     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 607     if (!arm_feature(env, ARM_FEATURE_V8)) {
 608         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 609          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 610          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 611          */
 612         if (arm_feature(env, ARM_FEATURE_VFP)) {
 613             /* VFP coprocessor: cp10 & cp11 [23:20] */
 614             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 615
 616             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 617                 /* ASEDIS [31] bit is RAO/WI */
 618                 value |= (1 << 31);
 619             }
 620
 621             /* VFPv3 and upwards with NEON implement 32 double precision
 622              * registers (D0-D31).
 623              */
 624             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 625                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 626                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 627                 value |= (1 << 30);
 628             }
 629         }
 630         value &= mask;
 631     }
 632     env->cp15.cpacr_el1 = value;
 633 }
 634
 635 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 636 {
 637     if (arm_feature(env, ARM_FEATURE_V8)) {
 638         /* Check if CPACR accesses are to be trapped to EL2 */
 639         if (arm_current_el(env) == 1 &&
 640             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 641             return CP_ACCESS_TRAP_EL2;
 642         /* Check if CPACR accesses are to be trapped to EL3 */
 643         } else if (arm_current_el(env) < 3 &&
 644                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 645             return CP_ACCESS_TRAP_EL3;
 646         }
 647     }
 648
 649     return CP_ACCESS_OK;
 650 }
 651
 652 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 653 {
 654     /* Check if CPTR accesses are set to trap to EL3 */
 655     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 656         return CP_ACCESS_TRAP_EL3;
 657     }
 658
 659     return CP_ACCESS_OK;
 660 }
 661
 662 static const ARMCPRegInfo v6_cp_reginfo[] = {
 663     /* prefetch by MVA in v6, NOP in v7 */
 664     { .name = "MVA_prefetch",
 665       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 666       .access = PL1_W, .type = ARM_CP_NOP },
 667     /* We need to break the TB after ISB to execute self-modifying code
 668      * correctly and also to take any pending interrupts immediately.
 669      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 670      */
 671     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 672       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 673     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 674       .access = PL0_W, .type = ARM_CP_NOP },
 675     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 676       .access = PL0_W, .type = ARM_CP_NOP },
 677     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 678       .access = PL1_RW,
 679       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 680                              offsetof(CPUARMState, cp15.ifar_ns) },
 681       .resetvalue = 0, },
 682     /* Watchpoint Fault Address Register : should actually only be present
 683      * for 1136, 1176, 11MPCore.
 684      */
 685     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 686       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 687     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 688       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 689       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 690       .resetvalue = 0, .writefn = cpacr_write },
 691     REGINFO_SENTINEL
 692 };
 693
 694 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 695 {
 696     /* Performance monitor registers user accessibility is controlled
 697      * by PMUSERENR.
 698      */
 699     if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
 700         return CP_ACCESS_TRAP;
 701     }
 702     return CP_ACCESS_OK;
 703 }
 704
 705 #ifndef CONFIG_USER_ONLY
 706
 707 static inline bool arm_ccnt_enabled(CPUARMState *env)
 708 {
 709     /* This does not support checking PMCCFILTR_EL0 register */
 710
 711     if (!(env->cp15.c9_pmcr & PMCRE)) {
 712         return false;
 713     }
 714
 715     return true;
 716 }
 717
 718 void pmccntr_sync(CPUARMState *env)
 719 {
 720     uint64_t temp_ticks;
 721
 722     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 723                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 724
 725     if (env->cp15.c9_pmcr & PMCRD) {
 726         /* Increment once every 64 processor clock cycles */
 727         temp_ticks /= 64;
 728     }
 729
 730     if (arm_ccnt_enabled(env)) {
 731         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 732     }
 733 }
 734
 735 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 736                        uint64_t value)
 737 {
 738     pmccntr_sync(env);
 739
 740     if (value & PMCRC) {
 741         /* The counter has been reset */
 742         env->cp15.c15_ccnt = 0;
 743     }
 744
 745     /* only the DP, X, D and E bits are writable */
 746     env->cp15.c9_pmcr &= ~0x39;
 747     env->cp15.c9_pmcr |= (value & 0x39);
 748
 749     pmccntr_sync(env);
 750 }
 751
 752 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 753 {
 754     uint64_t total_ticks;
 755
 756     if (!arm_ccnt_enabled(env)) {
 757         /* Counter is disabled, do not change value */
 758         return env->cp15.c15_ccnt;
 759     }
 760
 761     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 762                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 763
 764     if (env->cp15.c9_pmcr & PMCRD) {
 765         /* Increment once every 64 processor clock cycles */
 766         total_ticks /= 64;
 767     }
 768     return total_ticks - env->cp15.c15_ccnt;
 769 }
 770
 771 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 772                         uint64_t value)
 773 {
 774     uint64_t total_ticks;
 775
 776     if (!arm_ccnt_enabled(env)) {
 777         /* Counter is disabled, set the absolute value */
 778         env->cp15.c15_ccnt = value;
 779         return;
 780     }
 781
 782     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 783                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 784
 785     if (env->cp15.c9_pmcr & PMCRD) {
 786         /* Increment once every 64 processor clock cycles */
 787         total_ticks /= 64;
 788     }
 789     env->cp15.c15_ccnt = total_ticks - value;
 790 }
 791
 792 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 793                             uint64_t value)
 794 {
 795     uint64_t cur_val = pmccntr_read(env, NULL);
 796
 797     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 798 }
 799
 800 #else /* CONFIG_USER_ONLY */
 801
 802 void pmccntr_sync(CPUARMState *env)
 803 {
 804 }
 805
 806 #endif
 807
 808 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 809                             uint64_t value)
 810 {
 811     pmccntr_sync(env);
 812     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 813     pmccntr_sync(env);
 814 }
 815
 816 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 817                             uint64_t value)
 818 {
 819     value &= (1 << 31);
 820     env->cp15.c9_pmcnten |= value;
 821 }
 822
 823 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 824                              uint64_t value)
 825 {
 826     value &= (1 << 31);
 827     env->cp15.c9_pmcnten &= ~value;
 828 }
 829
 830 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 831                          uint64_t value)
 832 {
 833     env->cp15.c9_pmovsr &= ~value;
 834 }
 835
 836 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 837                              uint64_t value)
 838 {
 839     env->cp15.c9_pmxevtyper = value & 0xff;
 840 }
 841
 842 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 843                             uint64_t value)
 844 {
 845     env->cp15.c9_pmuserenr = value & 1;
 846 }
 847
 848 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 849                              uint64_t value)
 850 {
 851     /* We have no event counters so only the C bit can be changed */
 852     value &= (1 << 31);
 853     env->cp15.c9_pminten |= value;
 854 }
 855
 856 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 857                              uint64_t value)
 858 {
 859     value &= (1 << 31);
 860     env->cp15.c9_pminten &= ~value;
 861 }
 862
 863 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 864                        uint64_t value)
 865 {
 866     /* Note that even though the AArch64 view of this register has bits
 867      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 868      * architectural requirements for bits which are RES0 only in some
 869      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 870      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 871      */
 872     raw_write(env, ri, value & ~0x1FULL);
 873 }
 874
 875 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 876 {
 877     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 878      * For bits that vary between AArch32/64, code needs to check the
 879      * current execution mode before directly using the feature bit.
 880      */
 881     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 882
 883     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 884         valid_mask &= ~SCR_HCE;
 885
 886         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 887          * supported if EL2 exists. The bit is UNK/SBZP when
 888          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 889          * when EL2 is unavailable.
 890          * On ARMv8, this bit is always available.
 891          */
 892         if (arm_feature(env, ARM_FEATURE_V7) &&
 893             !arm_feature(env, ARM_FEATURE_V8)) {
 894             valid_mask &= ~SCR_SMD;
 895         }
 896     }
 897
 898     /* Clear all-context RES0 bits.  */
 899     value &= valid_mask;
 900     raw_write(env, ri, value);
 901 }
 902
 903 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 904 {
 905     ARMCPU *cpu = arm_env_get_cpu(env);
 906
 907     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
 908      * bank
 909      */
 910     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 911                                         ri->secure & ARM_CP_SECSTATE_S);
 912
 913     return cpu->ccsidr[index];
 914 }
 915
 916 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 917                          uint64_t value)
 918 {
 919     raw_write(env, ri, value & 0xf);
 920 }
 921
 922 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 923 {
 924     CPUState *cs = ENV_GET_CPU(env);
 925     uint64_t ret = 0;
 926
 927     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 928         ret |= CPSR_I;
 929     }
 930     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 931         ret |= CPSR_F;
 932     }
 933     /* External aborts are not possible in QEMU so A bit is always clear */
 934     return ret;
 935 }
 936
 937 static const ARMCPRegInfo v7_cp_reginfo[] = {
 938     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 939     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 940       .access = PL1_W, .type = ARM_CP_NOP },
 941     /* Performance monitors are implementation defined in v7,
 942      * but with an ARM recommended set of registers, which we
 943      * follow (although we don't actually implement any counters)
 944      *
 945      * Performance registers fall into three categories:
 946      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 947      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 948      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 949      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 950      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 951      */
 952     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 953       .access = PL0_RW, .type = ARM_CP_ALIAS,
 954       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 955       .writefn = pmcntenset_write,
 956       .accessfn = pmreg_access,
 957       .raw_writefn = raw_write },
 958     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 959       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 960       .access = PL0_RW, .accessfn = pmreg_access,
 961       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 962       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 963     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 964       .access = PL0_RW,
 965       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 966       .accessfn = pmreg_access,
 967       .writefn = pmcntenclr_write,
 968       .type = ARM_CP_ALIAS },
 969     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 970       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 971       .access = PL0_RW, .accessfn = pmreg_access,
 972       .type = ARM_CP_ALIAS,
 973       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 974       .writefn = pmcntenclr_write },
 975     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 976       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 977       .accessfn = pmreg_access,
 978       .writefn = pmovsr_write,
 979       .raw_writefn = raw_write },
 980     /* Unimplemented so WI. */
 981     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 982       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 983     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 984      * We choose to RAZ/WI.
 985      */
 986     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 987       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 988       .accessfn = pmreg_access },
 989 #ifndef CONFIG_USER_ONLY
 990     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 991       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 992       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 993       .accessfn = pmreg_access },
 994     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 995       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 996       .access = PL0_RW, .accessfn = pmreg_access,
 997       .type = ARM_CP_IO,
 998       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 999 #endif
1000     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1001       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1002       .writefn = pmccfiltr_write,
1003       .access = PL0_RW, .accessfn = pmreg_access,
1004       .type = ARM_CP_IO,
1005       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1006       .resetvalue = 0, },
1007     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1008       .access = PL0_RW,
1009       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1010       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1011       .raw_writefn = raw_write },
1012     /* Unimplemented, RAZ/WI. */
1013     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1014       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1015       .accessfn = pmreg_access },
1016     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1017       .access = PL0_R | PL1_RW,
1018       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1019       .resetvalue = 0,
1020       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1021     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1022       .access = PL1_RW,
1023       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1024       .resetvalue = 0,
1025       .writefn = pmintenset_write, .raw_writefn = raw_write },
1026     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1027       .access = PL1_RW, .type = ARM_CP_ALIAS,
1028       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1029       .writefn = pmintenclr_write, },
1030     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1031       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1032       .access = PL1_RW, .writefn = vbar_write,
1033       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1034                              offsetof(CPUARMState, cp15.vbar_ns) },
1035       .resetvalue = 0 },
1036     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1037       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1038       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1039     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1040       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1041       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1042       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1043                              offsetof(CPUARMState, cp15.csselr_ns) } },
1044     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1045      * just RAZ for all cores:
1046      */
1047     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1048       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1049       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1050     /* Auxiliary fault status registers: these also are IMPDEF, and we
1051      * choose to RAZ/WI for all cores.
1052      */
1053     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1054       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1055       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1056     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1057       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1058       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1059     /* MAIR can just read-as-written because we don't implement caches
1060      * and so don't need to care about memory attributes.
1061      */
1062     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1063       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1064       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1065       .resetvalue = 0 },
1066     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1067       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1068       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1069       .resetvalue = 0 },
1070     /* For non-long-descriptor page tables these are PRRR and NMRR;
1071      * regardless they still act as reads-as-written for QEMU.
1072      */
1073      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1074       * allows them to assign the correct fieldoffset based on the endianness
1075       * handled in the field definitions.
1076       */
1077     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1078       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1079       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1080                              offsetof(CPUARMState, cp15.mair0_ns) },
1081       .resetfn = arm_cp_reset_ignore },
1082     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1083       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1084       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1085                              offsetof(CPUARMState, cp15.mair1_ns) },
1086       .resetfn = arm_cp_reset_ignore },
1087     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1088       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1089       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1090     /* 32 bit ITLB invalidates */
1091     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1092       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1093     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1094       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1095     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1096       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1097     /* 32 bit DTLB invalidates */
1098     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1099       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1100     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1101       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1102     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1103       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1104     /* 32 bit TLB invalidates */
1105     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1106       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1107     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1108       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1109     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1110       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1111     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1112       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1113     REGINFO_SENTINEL
1114 };
1115
1116 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1117     /* 32 bit TLB invalidates, Inner Shareable */
1118     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1119       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1120     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1121       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1122     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1123       .type = ARM_CP_NO_RAW, .access = PL1_W,
1124       .writefn = tlbiasid_is_write },
1125     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1126       .type = ARM_CP_NO_RAW, .access = PL1_W,
1127       .writefn = tlbimvaa_is_write },
1128     REGINFO_SENTINEL
1129 };
1130
1131 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1132                         uint64_t value)
1133 {
1134     value &= 1;
1135     env->teecr = value;
1136 }
1137
1138 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1139 {
1140     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1141         return CP_ACCESS_TRAP;
1142     }
1143     return CP_ACCESS_OK;
1144 }
1145
1146 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1147     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1148       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1149       .resetvalue = 0,
1150       .writefn = teecr_write },
1151     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1152       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1153       .accessfn = teehbr_access, .resetvalue = 0 },
1154     REGINFO_SENTINEL
1155 };
1156
1157 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1158     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1159       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1160       .access = PL0_RW,
1161       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1162     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1163       .access = PL0_RW,
1164       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1165                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1166       .resetfn = arm_cp_reset_ignore },
1167     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1168       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1169       .access = PL0_R|PL1_W,
1170       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1171       .resetvalue = 0},
1172     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1173       .access = PL0_R|PL1_W,
1174       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1175                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1176       .resetfn = arm_cp_reset_ignore },
1177     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1178       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1179       .access = PL1_RW,
1180       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1181     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1182       .access = PL1_RW,
1183       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1184                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1185       .resetvalue = 0 },
1186     REGINFO_SENTINEL
1187 };
1188
1189 #ifndef CONFIG_USER_ONLY
1190
1191 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1192 {
1193     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1194     if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1195         return CP_ACCESS_TRAP;
1196     }
1197     return CP_ACCESS_OK;
1198 }
1199
1200 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1201 {
1202     unsigned int cur_el = arm_current_el(env);
1203     bool secure = arm_is_secure(env);
1204
1205     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1206     if (cur_el == 0 &&
1207         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1208         return CP_ACCESS_TRAP;
1209     }
1210
1211     if (arm_feature(env, ARM_FEATURE_EL2) &&
1212         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1213         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1214         return CP_ACCESS_TRAP_EL2;
1215     }
1216     return CP_ACCESS_OK;
1217 }
1218
1219 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1220 {
1221     unsigned int cur_el = arm_current_el(env);
1222     bool secure = arm_is_secure(env);
1223
1224     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1225      * EL0[PV]TEN is zero.
1226      */
1227     if (cur_el == 0 &&
1228         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1229         return CP_ACCESS_TRAP;
1230     }
1231
1232     if (arm_feature(env, ARM_FEATURE_EL2) &&
1233         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1234         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1235         return CP_ACCESS_TRAP_EL2;
1236     }
1237     return CP_ACCESS_OK;
1238 }
1239
1240 static CPAccessResult gt_pct_access(CPUARMState *env,
1241                                          const ARMCPRegInfo *ri)
1242 {
1243     return gt_counter_access(env, GTIMER_PHYS);
1244 }
1245
1246 static CPAccessResult gt_vct_access(CPUARMState *env,
1247                                          const ARMCPRegInfo *ri)
1248 {
1249     return gt_counter_access(env, GTIMER_VIRT);
1250 }
1251
1252 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1253 {
1254     return gt_timer_access(env, GTIMER_PHYS);
1255 }
1256
1257 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1258 {
1259     return gt_timer_access(env, GTIMER_VIRT);
1260 }
1261
1262 static CPAccessResult gt_stimer_access(CPUARMState *env,
1263                                        const ARMCPRegInfo *ri)
1264 {
1265     /* The AArch64 register view of the secure physical timer is
1266      * always accessible from EL3, and configurably accessible from
1267      * Secure EL1.
1268      */
1269     switch (arm_current_el(env)) {
1270     case 1:
1271         if (!arm_is_secure(env)) {
1272             return CP_ACCESS_TRAP;
1273         }
1274         if (!(env->cp15.scr_el3 & SCR_ST)) {
1275             return CP_ACCESS_TRAP_EL3;
1276         }
1277         return CP_ACCESS_OK;
1278     case 0:
1279     case 2:
1280         return CP_ACCESS_TRAP;
1281     case 3:
1282         return CP_ACCESS_OK;
1283     default:
1284         g_assert_not_reached();
1285     }
1286 }
1287
1288 static uint64_t gt_get_countervalue(CPUARMState *env)
1289 {
1290     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1291 }
1292
1293 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1294 {
1295     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1296
1297     if (gt->ctl & 1) {
1298         /* Timer enabled: calculate and set current ISTATUS, irq, and
1299          * reset timer to when ISTATUS next has to change
1300          */
1301         uint64_t offset = timeridx == GTIMER_VIRT ?
1302                                       cpu->env.cp15.cntvoff_el2 : 0;
1303         uint64_t count = gt_get_countervalue(&cpu->env);
1304         /* Note that this must be unsigned 64 bit arithmetic: */
1305         int istatus = count - offset >= gt->cval;
1306         uint64_t nexttick;
1307
1308         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1309         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1310                      (istatus && !(gt->ctl & 2)));
1311         if (istatus) {
1312             /* Next transition is when count rolls back over to zero */
1313             nexttick = UINT64_MAX;
1314         } else {
1315             /* Next transition is when we hit cval */
1316             nexttick = gt->cval + offset;
1317         }
1318         /* Note that the desired next expiry time might be beyond the
1319          * signed-64-bit range of a QEMUTimer -- in this case we just
1320          * set the timer for as far in the future as possible. When the
1321          * timer expires we will reset the timer for any remaining period.
1322          */
1323         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1324             nexttick = INT64_MAX / GTIMER_SCALE;
1325         }
1326         timer_mod(cpu->gt_timer[timeridx], nexttick);
1327     } else {
1328         /* Timer disabled: ISTATUS and timer output always clear */
1329         gt->ctl &= ~4;
1330         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1331         timer_del(cpu->gt_timer[timeridx]);
1332     }
1333 }
1334
1335 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1336                            int timeridx)
1337 {
1338     ARMCPU *cpu = arm_env_get_cpu(env);
1339
1340     timer_del(cpu->gt_timer[timeridx]);
1341 }
1342
1343 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1344 {
1345     return gt_get_countervalue(env);
1346 }
1347
1348 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1349 {
1350     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1351 }
1352
1353 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1354                           int timeridx,
1355                           uint64_t value)
1356 {
1357     env->cp15.c14_timer[timeridx].cval = value;
1358     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1359 }
1360
1361 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1362                              int timeridx)
1363 {
1364     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1365
1366     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1367                       (gt_get_countervalue(env) - offset));
1368 }
1369
1370 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1371                           int timeridx,
1372                           uint64_t value)
1373 {
1374     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1375
1376     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1377                                          sextract64(value, 0, 32);
1378     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1379 }
1380
1381 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1382                          int timeridx,
1383                          uint64_t value)
1384 {
1385     ARMCPU *cpu = arm_env_get_cpu(env);
1386     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1387
1388     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1389     if ((oldval ^ value) & 1) {
1390         /* Enable toggled */
1391         gt_recalc_timer(cpu, timeridx);
1392     } else if ((oldval ^ value) & 2) {
1393         /* IMASK toggled: don't need to recalculate,
1394          * just set the interrupt line based on ISTATUS
1395          */
1396         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1397                      (oldval & 4) && !(value & 2));
1398     }
1399 }
1400
1401 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1402 {
1403     gt_timer_reset(env, ri, GTIMER_PHYS);
1404 }
1405
1406 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1407                                uint64_t value)
1408 {
1409     gt_cval_write(env, ri, GTIMER_PHYS, value);
1410 }
1411
1412 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1413 {
1414     return gt_tval_read(env, ri, GTIMER_PHYS);
1415 }
1416
1417 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1418                                uint64_t value)
1419 {
1420     gt_tval_write(env, ri, GTIMER_PHYS, value);
1421 }
1422
1423 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1424                               uint64_t value)
1425 {
1426     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1427 }
1428
1429 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1430 {
1431     gt_timer_reset(env, ri, GTIMER_VIRT);
1432 }
1433
1434 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1435                                uint64_t value)
1436 {
1437     gt_cval_write(env, ri, GTIMER_VIRT, value);
1438 }
1439
1440 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1441 {
1442     return gt_tval_read(env, ri, GTIMER_VIRT);
1443 }
1444
1445 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1446                                uint64_t value)
1447 {
1448     gt_tval_write(env, ri, GTIMER_VIRT, value);
1449 }
1450
1451 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1452                               uint64_t value)
1453 {
1454     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1455 }
1456
1457 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1458                               uint64_t value)
1459 {
1460     ARMCPU *cpu = arm_env_get_cpu(env);
1461
1462     raw_write(env, ri, value);
1463     gt_recalc_timer(cpu, GTIMER_VIRT);
1464 }
1465
1466 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1467 {
1468     gt_timer_reset(env, ri, GTIMER_HYP);
1469 }
1470
1471 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1472                               uint64_t value)
1473 {
1474     gt_cval_write(env, ri, GTIMER_HYP, value);
1475 }
1476
1477 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1478 {
1479     return gt_tval_read(env, ri, GTIMER_HYP);
1480 }
1481
1482 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1483                               uint64_t value)
1484 {
1485     gt_tval_write(env, ri, GTIMER_HYP, value);
1486 }
1487
1488 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1489                               uint64_t value)
1490 {
1491     gt_ctl_write(env, ri, GTIMER_HYP, value);
1492 }
1493
1494 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1495 {
1496     gt_timer_reset(env, ri, GTIMER_SEC);
1497 }
1498
1499 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1500                               uint64_t value)
1501 {
1502     gt_cval_write(env, ri, GTIMER_SEC, value);
1503 }
1504
1505 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1506 {
1507     return gt_tval_read(env, ri, GTIMER_SEC);
1508 }
1509
1510 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1511                               uint64_t value)
1512 {
1513     gt_tval_write(env, ri, GTIMER_SEC, value);
1514 }
1515
1516 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1517                               uint64_t value)
1518 {
1519     gt_ctl_write(env, ri, GTIMER_SEC, value);
1520 }
1521
1522 void arm_gt_ptimer_cb(void *opaque)
1523 {
1524     ARMCPU *cpu = opaque;
1525
1526     gt_recalc_timer(cpu, GTIMER_PHYS);
1527 }
1528
1529 void arm_gt_vtimer_cb(void *opaque)
1530 {
1531     ARMCPU *cpu = opaque;
1532
1533     gt_recalc_timer(cpu, GTIMER_VIRT);
1534 }
1535
1536 void arm_gt_htimer_cb(void *opaque)
1537 {
1538     ARMCPU *cpu = opaque;
1539
1540     gt_recalc_timer(cpu, GTIMER_HYP);
1541 }
1542
1543 void arm_gt_stimer_cb(void *opaque)
1544 {
1545     ARMCPU *cpu = opaque;
1546
1547     gt_recalc_timer(cpu, GTIMER_SEC);
1548 }
1549
1550 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1551     /* Note that CNTFRQ is purely reads-as-written for the benefit
1552      * of software; writing it doesn't actually change the timer frequency.
1553      * Our reset value matches the fixed frequency we implement the timer at.
1554      */
1555     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1556       .type = ARM_CP_ALIAS,
1557       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1558       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1559     },
1560     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1561       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1562       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1563       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1564       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1565     },
1566     /* overall control: mostly access permissions */
1567     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1568       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1569       .access = PL1_RW,
1570       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1571       .resetvalue = 0,
1572     },
1573     /* per-timer control */
1574     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1575       .secure = ARM_CP_SECSTATE_NS,
1576       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1577       .accessfn = gt_ptimer_access,
1578       .fieldoffset = offsetoflow32(CPUARMState,
1579                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1580       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1581     },
1582     { .name = "CNTP_CTL(S)",
1583       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1584       .secure = ARM_CP_SECSTATE_S,
1585       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1586       .accessfn = gt_ptimer_access,
1587       .fieldoffset = offsetoflow32(CPUARMState,
1588                                    cp15.c14_timer[GTIMER_SEC].ctl),
1589       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1590     },
1591     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1592       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1593       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1594       .accessfn = gt_ptimer_access,
1595       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1596       .resetvalue = 0,
1597       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1598     },
1599     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1600       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1601       .accessfn = gt_vtimer_access,
1602       .fieldoffset = offsetoflow32(CPUARMState,
1603                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1604       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1605     },
1606     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1607       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1608       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1609       .accessfn = gt_vtimer_access,
1610       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1611       .resetvalue = 0,
1612       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1613     },
1614     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1615     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1616       .secure = ARM_CP_SECSTATE_NS,
1617       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1618       .accessfn = gt_ptimer_access,
1619       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1620     },
1621     { .name = "CNTP_TVAL(S)",
1622       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1623       .secure = ARM_CP_SECSTATE_S,
1624       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1625       .accessfn = gt_ptimer_access,
1626       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1627     },
1628     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1629       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1630       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1631       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1632       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1633     },
1634     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1635       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1636       .accessfn = gt_vtimer_access,
1637       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1638     },
1639     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1640       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1641       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1642       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1643       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1644     },
1645     /* The counter itself */
1646     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1647       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1648       .accessfn = gt_pct_access,
1649       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1650     },
1651     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1652       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1653       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1654       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1655     },
1656     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1657       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1658       .accessfn = gt_vct_access,
1659       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1660     },
1661     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1662       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1663       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1664       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1665     },
1666     /* Comparison value, indicating when the timer goes off */
1667     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1668       .secure = ARM_CP_SECSTATE_NS,
1669       .access = PL1_RW | PL0_R,
1670       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1671       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1672       .accessfn = gt_ptimer_access,
1673       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1674     },
1675     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1676       .secure = ARM_CP_SECSTATE_S,
1677       .access = PL1_RW | PL0_R,
1678       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1679       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1680       .accessfn = gt_ptimer_access,
1681       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1682     },
1683     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1684       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1685       .access = PL1_RW | PL0_R,
1686       .type = ARM_CP_IO,
1687       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1688       .resetvalue = 0, .accessfn = gt_ptimer_access,
1689       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1690     },
1691     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1692       .access = PL1_RW | PL0_R,
1693       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1694       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1695       .accessfn = gt_vtimer_access,
1696       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1697     },
1698     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1699       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1700       .access = PL1_RW | PL0_R,
1701       .type = ARM_CP_IO,
1702       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1703       .resetvalue = 0, .accessfn = gt_vtimer_access,
1704       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1705     },
1706     /* Secure timer -- this is actually restricted to only EL3
1707      * and configurably Secure-EL1 via the accessfn.
1708      */
1709     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1710       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1711       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1712       .accessfn = gt_stimer_access,
1713       .readfn = gt_sec_tval_read,
1714       .writefn = gt_sec_tval_write,
1715       .resetfn = gt_sec_timer_reset,
1716     },
1717     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1718       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1719       .type = ARM_CP_IO, .access = PL1_RW,
1720       .accessfn = gt_stimer_access,
1721       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1722       .resetvalue = 0,
1723       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1724     },
1725     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1726       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1727       .type = ARM_CP_IO, .access = PL1_RW,
1728       .accessfn = gt_stimer_access,
1729       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1730       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1731     },
1732     REGINFO_SENTINEL
1733 };
1734
1735 #else
1736 /* In user-mode none of the generic timer registers are accessible,
1737  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1738  * so instead just don't register any of them.
1739  */
1740 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1741     REGINFO_SENTINEL
1742 };
1743
1744 #endif
1745
1746 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1747 {
1748     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1749         raw_write(env, ri, value);
1750     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1751         raw_write(env, ri, value & 0xfffff6ff);
1752     } else {
1753         raw_write(env, ri, value & 0xfffff1ff);
1754     }
1755 }
1756
1757 #ifndef CONFIG_USER_ONLY
1758 /* get_phys_addr() isn't present for user-mode-only targets */
1759
1760 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1761 {
1762     if (ri->opc2 & 4) {
1763         /* The ATS12NSO* operations must trap to EL3 if executed in
1764          * Secure EL1 (which can only happen if EL3 is AArch64).
1765          * They are simply UNDEF if executed from NS EL1.
1766          * They function normally from EL2 or EL3.
1767          */
1768         if (arm_current_el(env) == 1) {
1769             if (arm_is_secure_below_el3(env)) {
1770                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1771             }
1772             return CP_ACCESS_TRAP_UNCATEGORIZED;
1773         }
1774     }
1775     return CP_ACCESS_OK;
1776 }
1777
1778 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1779                              int access_type, ARMMMUIdx mmu_idx)
1780 {
1781     hwaddr phys_addr;
1782     target_ulong page_size;
1783     int prot;
1784     uint32_t fsr;
1785     bool ret;
1786     uint64_t par64;
1787     MemTxAttrs attrs = {};
1788     ARMMMUFaultInfo fi = {};
1789
1790     ret = get_phys_addr(env, value, access_type, mmu_idx,
1791                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1792     if (extended_addresses_enabled(env)) {
1793         /* fsr is a DFSR/IFSR value for the long descriptor
1794          * translation table format, but with WnR always clear.
1795          * Convert it to a 64-bit PAR.
1796          */
1797         par64 = (1 << 11); /* LPAE bit always set */
1798         if (!ret) {
1799             par64 |= phys_addr & ~0xfffULL;
1800             if (!attrs.secure) {
1801                 par64 |= (1 << 9); /* NS */
1802             }
1803             /* We don't set the ATTR or SH fields in the PAR. */
1804         } else {
1805             par64 |= 1; /* F */
1806             par64 |= (fsr & 0x3f) << 1; /* FS */
1807             /* Note that S2WLK and FSTAGE are always zero, because we don't
1808              * implement virtualization and therefore there can't be a stage 2
1809              * fault.
1810              */
1811         }
1812     } else {
1813         /* fsr is a DFSR/IFSR value for the short descriptor
1814          * translation table format (with WnR always clear).
1815          * Convert it to a 32-bit PAR.
1816          */
1817         if (!ret) {
1818             /* We do not set any attribute bits in the PAR */
1819             if (page_size == (1 << 24)
1820                 && arm_feature(env, ARM_FEATURE_V7)) {
1821                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1822             } else {
1823                 par64 = phys_addr & 0xfffff000;
1824             }
1825             if (!attrs.secure) {
1826                 par64 |= (1 << 9); /* NS */
1827             }
1828         } else {
1829             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1830                     ((fsr & 0xf) << 1) | 1;
1831         }
1832     }
1833     return par64;
1834 }
1835
1836 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1837 {
1838     int access_type = ri->opc2 & 1;
1839     uint64_t par64;
1840     ARMMMUIdx mmu_idx;
1841     int el = arm_current_el(env);
1842     bool secure = arm_is_secure_below_el3(env);
1843
1844     switch (ri->opc2 & 6) {
1845     case 0:
1846         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1847         switch (el) {
1848         case 3:
1849             mmu_idx = ARMMMUIdx_S1E3;
1850             break;
1851         case 2:
1852             mmu_idx = ARMMMUIdx_S1NSE1;
1853             break;
1854         case 1:
1855             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1856             break;
1857         default:
1858             g_assert_not_reached();
1859         }
1860         break;
1861     case 2:
1862         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1863         switch (el) {
1864         case 3:
1865             mmu_idx = ARMMMUIdx_S1SE0;
1866             break;
1867         case 2:
1868             mmu_idx = ARMMMUIdx_S1NSE0;
1869             break;
1870         case 1:
1871             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1872             break;
1873         default:
1874             g_assert_not_reached();
1875         }
1876         break;
1877     case 4:
1878         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1879         mmu_idx = ARMMMUIdx_S12NSE1;
1880         break;
1881     case 6:
1882         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1883         mmu_idx = ARMMMUIdx_S12NSE0;
1884         break;
1885     default:
1886         g_assert_not_reached();
1887     }
1888
1889     par64 = do_ats_write(env, value, access_type, mmu_idx);
1890
1891     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1892 }
1893
1894 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
1895                         uint64_t value)
1896 {
1897     int access_type = ri->opc2 & 1;
1898     uint64_t par64;
1899
1900     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
1901
1902     A32_BANKED_CURRENT_REG_SET(env, par, par64);
1903 }
1904
1905 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
1906 {
1907     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
1908         return CP_ACCESS_TRAP;
1909     }
1910     return CP_ACCESS_OK;
1911 }
1912
1913 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1914                         uint64_t value)
1915 {
1916     int access_type = ri->opc2 & 1;
1917     ARMMMUIdx mmu_idx;
1918     int secure = arm_is_secure_below_el3(env);
1919
1920     switch (ri->opc2 & 6) {
1921     case 0:
1922         switch (ri->opc1) {
1923         case 0: /* AT S1E1R, AT S1E1W */
1924             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1925             break;
1926         case 4: /* AT S1E2R, AT S1E2W */
1927             mmu_idx = ARMMMUIdx_S1E2;
1928             break;
1929         case 6: /* AT S1E3R, AT S1E3W */
1930             mmu_idx = ARMMMUIdx_S1E3;
1931             break;
1932         default:
1933             g_assert_not_reached();
1934         }
1935         break;
1936     case 2: /* AT S1E0R, AT S1E0W */
1937         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1938         break;
1939     case 4: /* AT S12E1R, AT S12E1W */
1940         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
1941         break;
1942     case 6: /* AT S12E0R, AT S12E0W */
1943         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
1944         break;
1945     default:
1946         g_assert_not_reached();
1947     }
1948
1949     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1950 }
1951 #endif
1952
1953 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1954     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1955       .access = PL1_RW, .resetvalue = 0,
1956       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1957                              offsetoflow32(CPUARMState, cp15.par_ns) },
1958       .writefn = par_write },
1959 #ifndef CONFIG_USER_ONLY
1960     /* This underdecoding is safe because the reginfo is NO_RAW. */
1961     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1962       .access = PL1_W, .accessfn = ats_access,
1963       .writefn = ats_write, .type = ARM_CP_NO_RAW },
1964 #endif
1965     REGINFO_SENTINEL
1966 };
1967
1968 /* Return basic MPU access permission bits.  */
1969 static uint32_t simple_mpu_ap_bits(uint32_t val)
1970 {
1971     uint32_t ret;
1972     uint32_t mask;
1973     int i;
1974     ret = 0;
1975     mask = 3;
1976     for (i = 0; i < 16; i += 2) {
1977         ret |= (val >> i) & mask;
1978         mask <<= 2;
1979     }
1980     return ret;
1981 }
1982
1983 /* Pad basic MPU access permission bits to extended format.  */
1984 static uint32_t extended_mpu_ap_bits(uint32_t val)
1985 {
1986     uint32_t ret;
1987     uint32_t mask;
1988     int i;
1989     ret = 0;
1990     mask = 3;
1991     for (i = 0; i < 16; i += 2) {
1992         ret |= (val & mask) << i;
1993         mask <<= 2;
1994     }
1995     return ret;
1996 }
1997
1998 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1999                                  uint64_t value)
2000 {
2001     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2002 }
2003
2004 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2005 {
2006     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2007 }
2008
2009 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2010                                  uint64_t value)
2011 {
2012     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2013 }
2014
2015 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2016 {
2017     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2018 }
2019
2020 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2021 {
2022     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2023
2024     if (!u32p) {
2025         return 0;
2026     }
2027
2028     u32p += env->cp15.c6_rgnr;
2029     return *u32p;
2030 }
2031
2032 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2033                          uint64_t value)
2034 {
2035     ARMCPU *cpu = arm_env_get_cpu(env);
2036     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2037
2038     if (!u32p) {
2039         return;
2040     }
2041
2042     u32p += env->cp15.c6_rgnr;
2043     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2044     *u32p = value;
2045 }
2046
2047 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2048 {
2049     ARMCPU *cpu = arm_env_get_cpu(env);
2050     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2051
2052     if (!u32p) {
2053         return;
2054     }
2055
2056     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2057 }
2058
2059 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2060                               uint64_t value)
2061 {
2062     ARMCPU *cpu = arm_env_get_cpu(env);
2063     uint32_t nrgs = cpu->pmsav7_dregion;
2064
2065     if (value >= nrgs) {
2066         qemu_log_mask(LOG_GUEST_ERROR,
2067                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2068                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2069         return;
2070     }
2071
2072     raw_write(env, ri, value);
2073 }
2074
2075 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2076     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2077       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2078       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2079       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2080     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2081       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2082       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2083       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2084     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2085       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2086       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2087       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2088     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2089       .access = PL1_RW,
2090       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2091       .writefn = pmsav7_rgnr_write },
2092     REGINFO_SENTINEL
2093 };
2094
2095 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2096     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2097       .access = PL1_RW, .type = ARM_CP_ALIAS,
2098       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2099       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2100     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2101       .access = PL1_RW, .type = ARM_CP_ALIAS,
2102       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2103       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2104     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2105       .access = PL1_RW,
2106       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2107       .resetvalue = 0, },
2108     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2109       .access = PL1_RW,
2110       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2111       .resetvalue = 0, },
2112     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2113       .access = PL1_RW,
2114       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2115     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2116       .access = PL1_RW,
2117       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2118     /* Protection region base and size registers */
2119     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2120       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2121       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2122     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2123       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2124       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2125     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2126       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2127       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2128     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2129       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2130       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2131     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2132       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2133       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2134     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2135       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2136       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2137     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2138       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2139       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2140     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2141       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2142       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2143     REGINFO_SENTINEL
2144 };
2145
2146 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2147                                  uint64_t value)
2148 {
2149     TCR *tcr = raw_ptr(env, ri);
2150     int maskshift = extract32(value, 0, 3);
2151
2152     if (!arm_feature(env, ARM_FEATURE_V8)) {
2153         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2154             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2155              * using Long-desciptor translation table format */
2156             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2157         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2158             /* In an implementation that includes the Security Extensions
2159              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2160              * Short-descriptor translation table format.
2161              */
2162             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2163         } else {
2164             value &= TTBCR_N;
2165         }
2166     }
2167
2168     /* Update the masks corresponding to the TCR bank being written
2169      * Note that we always calculate mask and base_mask, but
2170      * they are only used for short-descriptor tables (ie if EAE is 0);
2171      * for long-descriptor tables the TCR fields are used differently
2172      * and the mask and base_mask values are meaningless.
2173      */
2174     tcr->raw_tcr = value;
2175     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2176     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2177 }
2178
2179 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2180                              uint64_t value)
2181 {
2182     ARMCPU *cpu = arm_env_get_cpu(env);
2183
2184     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2185         /* With LPAE the TTBCR could result in a change of ASID
2186          * via the TTBCR.A1 bit, so do a TLB flush.
2187          */
2188         tlb_flush(CPU(cpu), 1);
2189     }
2190     vmsa_ttbcr_raw_write(env, ri, value);
2191 }
2192
2193 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2194 {
2195     TCR *tcr = raw_ptr(env, ri);
2196
2197     /* Reset both the TCR as well as the masks corresponding to the bank of
2198      * the TCR being reset.
2199      */
2200     tcr->raw_tcr = 0;
2201     tcr->mask = 0;
2202     tcr->base_mask = 0xffffc000u;
2203 }
2204
2205 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2206                                uint64_t value)
2207 {
2208     ARMCPU *cpu = arm_env_get_cpu(env);
2209     TCR *tcr = raw_ptr(env, ri);
2210
2211     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2212     tlb_flush(CPU(cpu), 1);
2213     tcr->raw_tcr = value;
2214 }
2215
2216 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2217                             uint64_t value)
2218 {
2219     /* 64 bit accesses to the TTBRs can change the ASID and so we
2220      * must flush the TLB.
2221      */
2222     if (cpreg_field_is_64bit(ri)) {
2223         ARMCPU *cpu = arm_env_get_cpu(env);
2224
2225         tlb_flush(CPU(cpu), 1);
2226     }
2227     raw_write(env, ri, value);
2228 }
2229
2230 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2231                         uint64_t value)
2232 {
2233     ARMCPU *cpu = arm_env_get_cpu(env);
2234     CPUState *cs = CPU(cpu);
2235
2236     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2237     if (raw_read(env, ri) != value) {
2238         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2239                             ARMMMUIdx_S2NS, -1);
2240         raw_write(env, ri, value);
2241     }
2242 }
2243
2244 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2245     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2246       .access = PL1_RW, .type = ARM_CP_ALIAS,
2247       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2248                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2249     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2250       .access = PL1_RW, .resetvalue = 0,
2251       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2252                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2253     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2254       .access = PL1_RW, .resetvalue = 0,
2255       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2256                              offsetof(CPUARMState, cp15.dfar_ns) } },
2257     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2258       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2259       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2260       .resetvalue = 0, },
2261     REGINFO_SENTINEL
2262 };
2263
2264 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2265     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2266       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2267       .access = PL1_RW,
2268       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2269     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2270       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2271       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2272       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2273                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2274     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2275       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2276       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2277       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2278                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2279     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2280       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2281       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2282       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2283       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2284     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2285       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2286       .raw_writefn = vmsa_ttbcr_raw_write,
2287       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2288                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2289     REGINFO_SENTINEL
2290 };
2291
2292 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2293                                 uint64_t value)
2294 {
2295     env->cp15.c15_ticonfig = value & 0xe7;
2296     /* The OS_TYPE bit in this register changes the reported CPUID! */
2297     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2298         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2299 }
2300
2301 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2302                                 uint64_t value)
2303 {
2304     env->cp15.c15_threadid = value & 0xffff;
2305 }
2306
2307 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2308                            uint64_t value)
2309 {
2310     /* Wait-for-interrupt (deprecated) */
2311     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2312 }
2313
2314 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2315                                   uint64_t value)
2316 {
2317     /* On OMAP there are registers indicating the max/min index of dcache lines
2318      * containing a dirty line; cache flush operations have to reset these.
2319      */
2320     env->cp15.c15_i_max = 0x000;
2321     env->cp15.c15_i_min = 0xff0;
2322 }
2323
2324 static const ARMCPRegInfo omap_cp_reginfo[] = {
2325     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2326       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2327       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2328       .resetvalue = 0, },
2329     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2330       .access = PL1_RW, .type = ARM_CP_NOP },
2331     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2332       .access = PL1_RW,
2333       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2334       .writefn = omap_ticonfig_write },
2335     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2336       .access = PL1_RW,
2337       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2338     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2339       .access = PL1_RW, .resetvalue = 0xff0,
2340       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2341     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2342       .access = PL1_RW,
2343       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2344       .writefn = omap_threadid_write },
2345     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2346       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2347       .type = ARM_CP_NO_RAW,
2348       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2349     /* TODO: Peripheral port remap register:
2350      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2351      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2352      * when MMU is off.
2353      */
2354     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2355       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2356       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2357       .writefn = omap_cachemaint_write },
2358     { .name = "C9", .cp = 15, .crn = 9,
2359       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2360       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2361     REGINFO_SENTINEL
2362 };
2363
2364 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2365                               uint64_t value)
2366 {
2367     env->cp15.c15_cpar = value & 0x3fff;
2368 }
2369
2370 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2371     { .name = "XSCALE_CPAR",
2372       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2373       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2374       .writefn = xscale_cpar_write, },
2375     { .name = "XSCALE_AUXCR",
2376       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2377       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2378       .resetvalue = 0, },
2379     /* XScale specific cache-lockdown: since we have no cache we NOP these
2380      * and hope the guest does not really rely on cache behaviour.
2381      */
2382     { .name = "XSCALE_LOCK_ICACHE_LINE",
2383       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2384       .access = PL1_W, .type = ARM_CP_NOP },
2385     { .name = "XSCALE_UNLOCK_ICACHE",
2386       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2387       .access = PL1_W, .type = ARM_CP_NOP },
2388     { .name = "XSCALE_DCACHE_LOCK",
2389       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2390       .access = PL1_RW, .type = ARM_CP_NOP },
2391     { .name = "XSCALE_UNLOCK_DCACHE",
2392       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2393       .access = PL1_W, .type = ARM_CP_NOP },
2394     REGINFO_SENTINEL
2395 };
2396
2397 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2398     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2399      * implementation of this implementation-defined space.
2400      * Ideally this should eventually disappear in favour of actually
2401      * implementing the correct behaviour for all cores.
2402      */
2403     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2404       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2405       .access = PL1_RW,
2406       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2407       .resetvalue = 0 },
2408     REGINFO_SENTINEL
2409 };
2410
2411 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2412     /* Cache status: RAZ because we have no cache so it's always clean */
2413     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2414       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2415       .resetvalue = 0 },
2416     REGINFO_SENTINEL
2417 };
2418
2419 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2420     /* We never have a a block transfer operation in progress */
2421     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2422       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2423       .resetvalue = 0 },
2424     /* The cache ops themselves: these all NOP for QEMU */
2425     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2426       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2427     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2428       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2429     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2430       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2431     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2432       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2433     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2434       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2435     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2436       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2437     REGINFO_SENTINEL
2438 };
2439
2440 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2441     /* The cache test-and-clean instructions always return (1 << 30)
2442      * to indicate that there are no dirty cache lines.
2443      */
2444     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2445       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2446       .resetvalue = (1 << 30) },
2447     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2448       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2449       .resetvalue = (1 << 30) },
2450     REGINFO_SENTINEL
2451 };
2452
2453 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2454     /* Ignore ReadBuffer accesses */
2455     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2456       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2457       .access = PL1_RW, .resetvalue = 0,
2458       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2459     REGINFO_SENTINEL
2460 };
2461
2462 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2463 {
2464     ARMCPU *cpu = arm_env_get_cpu(env);
2465     unsigned int cur_el = arm_current_el(env);
2466     bool secure = arm_is_secure(env);
2467
2468     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2469         return env->cp15.vpidr_el2;
2470     }
2471     return raw_read(env, ri);
2472 }
2473
2474 static uint64_t mpidr_read_val(CPUARMState *env)
2475 {
2476     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2477     uint64_t mpidr = cpu->mp_affinity;
2478
2479     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2480         mpidr |= (1U << 31);
2481         /* Cores which are uniprocessor (non-coherent)
2482          * but still implement the MP extensions set
2483          * bit 30. (For instance, Cortex-R5).
2484          */
2485         if (cpu->mp_is_up) {
2486             mpidr |= (1u << 30);
2487         }
2488     }
2489     return mpidr;
2490 }
2491
2492 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2493 {
2494     unsigned int cur_el = arm_current_el(env);
2495     bool secure = arm_is_secure(env);
2496
2497     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2498         return env->cp15.vmpidr_el2;
2499     }
2500     return mpidr_read_val(env);
2501 }
2502
2503 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2504     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2505       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2506       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2507     REGINFO_SENTINEL
2508 };
2509
2510 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2511     /* NOP AMAIR0/1 */
2512     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2513       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2514       .access = PL1_RW, .type = ARM_CP_CONST,
2515       .resetvalue = 0 },
2516     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2517     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2518       .access = PL1_RW, .type = ARM_CP_CONST,
2519       .resetvalue = 0 },
2520     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2521       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2522       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2523                              offsetof(CPUARMState, cp15.par_ns)} },
2524     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2525       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2526       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2527                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2528       .writefn = vmsa_ttbr_write, },
2529     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2530       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2531       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2532                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2533       .writefn = vmsa_ttbr_write, },
2534     REGINFO_SENTINEL
2535 };
2536
2537 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2538 {
2539     return vfp_get_fpcr(env);
2540 }
2541
2542 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2543                             uint64_t value)
2544 {
2545     vfp_set_fpcr(env, value);
2546 }
2547
2548 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2549 {
2550     return vfp_get_fpsr(env);
2551 }
2552
2553 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2554                             uint64_t value)
2555 {
2556     vfp_set_fpsr(env, value);
2557 }
2558
2559 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2560 {
2561     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2562         return CP_ACCESS_TRAP;
2563     }
2564     return CP_ACCESS_OK;
2565 }
2566
2567 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2568                             uint64_t value)
2569 {
2570     env->daif = value & PSTATE_DAIF;
2571 }
2572
2573 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2574                                           const ARMCPRegInfo *ri)
2575 {
2576     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2577      * SCTLR_EL1.UCI is set.
2578      */
2579     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2580         return CP_ACCESS_TRAP;
2581     }
2582     return CP_ACCESS_OK;
2583 }
2584
2585 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2586  * Page D4-1736 (DDI0487A.b)
2587  */
2588
2589 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2590                                     uint64_t value)
2591 {
2592     ARMCPU *cpu = arm_env_get_cpu(env);
2593     CPUState *cs = CPU(cpu);
2594
2595     if (arm_is_secure_below_el3(env)) {
2596         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2597     } else {
2598         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2599     }
2600 }
2601
2602 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2603                                       uint64_t value)
2604 {
2605     bool sec = arm_is_secure_below_el3(env);
2606     CPUState *other_cs;
2607
2608     CPU_FOREACH(other_cs) {
2609         if (sec) {
2610             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2611         } else {
2612             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2613                                 ARMMMUIdx_S12NSE0, -1);
2614         }
2615     }
2616 }
2617
2618 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2619                                   uint64_t value)
2620 {
2621     /* Note that the 'ALL' scope must invalidate both stage 1 and
2622      * stage 2 translations, whereas most other scopes only invalidate
2623      * stage 1 translations.
2624      */
2625     ARMCPU *cpu = arm_env_get_cpu(env);
2626     CPUState *cs = CPU(cpu);
2627
2628     if (arm_is_secure_below_el3(env)) {
2629         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2630     } else {
2631         if (arm_feature(env, ARM_FEATURE_EL2)) {
2632             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2633                                 ARMMMUIdx_S2NS, -1);
2634         } else {
2635             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2636         }
2637     }
2638 }
2639
2640 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2641                                   uint64_t value)
2642 {
2643     ARMCPU *cpu = arm_env_get_cpu(env);
2644     CPUState *cs = CPU(cpu);
2645
2646     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2647 }
2648
2649 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2650                                   uint64_t value)
2651 {
2652     ARMCPU *cpu = arm_env_get_cpu(env);
2653     CPUState *cs = CPU(cpu);
2654
2655     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2656 }
2657
2658 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2659                                     uint64_t value)
2660 {
2661     /* Note that the 'ALL' scope must invalidate both stage 1 and
2662      * stage 2 translations, whereas most other scopes only invalidate
2663      * stage 1 translations.
2664      */
2665     bool sec = arm_is_secure_below_el3(env);
2666     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2667     CPUState *other_cs;
2668
2669     CPU_FOREACH(other_cs) {
2670         if (sec) {
2671             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2672         } else if (has_el2) {
2673             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2674                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2675         } else {
2676             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2677                                 ARMMMUIdx_S12NSE0, -1);
2678         }
2679     }
2680 }
2681
2682 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2683                                     uint64_t value)
2684 {
2685     CPUState *other_cs;
2686
2687     CPU_FOREACH(other_cs) {
2688         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2689     }
2690 }
2691
2692 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2693                                     uint64_t value)
2694 {
2695     CPUState *other_cs;
2696
2697     CPU_FOREACH(other_cs) {
2698         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2699     }
2700 }
2701
2702 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2703                                  uint64_t value)
2704 {
2705     /* Invalidate by VA, EL1&0 (AArch64 version).
2706      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2707      * since we don't support flush-for-specific-ASID-only or
2708      * flush-last-level-only.
2709      */
2710     ARMCPU *cpu = arm_env_get_cpu(env);
2711     CPUState *cs = CPU(cpu);
2712     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2713
2714     if (arm_is_secure_below_el3(env)) {
2715         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2716                                  ARMMMUIdx_S1SE0, -1);
2717     } else {
2718         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2719                                  ARMMMUIdx_S12NSE0, -1);
2720     }
2721 }
2722
2723 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2724                                  uint64_t value)
2725 {
2726     /* Invalidate by VA, EL2
2727      * Currently handles both VAE2 and VALE2, since we don't support
2728      * flush-last-level-only.
2729      */
2730     ARMCPU *cpu = arm_env_get_cpu(env);
2731     CPUState *cs = CPU(cpu);
2732     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2733
2734     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2735 }
2736
2737 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2738                                  uint64_t value)
2739 {
2740     /* Invalidate by VA, EL3
2741      * Currently handles both VAE3 and VALE3, since we don't support
2742      * flush-last-level-only.
2743      */
2744     ARMCPU *cpu = arm_env_get_cpu(env);
2745     CPUState *cs = CPU(cpu);
2746     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2747
2748     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2749 }
2750
2751 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2752                                    uint64_t value)
2753 {
2754     bool sec = arm_is_secure_below_el3(env);
2755     CPUState *other_cs;
2756     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2757
2758     CPU_FOREACH(other_cs) {
2759         if (sec) {
2760             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2761                                      ARMMMUIdx_S1SE0, -1);
2762         } else {
2763             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2764                                      ARMMMUIdx_S12NSE0, -1);
2765         }
2766     }
2767 }
2768
2769 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2770                                    uint64_t value)
2771 {
2772     CPUState *other_cs;
2773     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2774
2775     CPU_FOREACH(other_cs) {
2776         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2777     }
2778 }
2779
2780 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2781                                    uint64_t value)
2782 {
2783     CPUState *other_cs;
2784     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2785
2786     CPU_FOREACH(other_cs) {
2787         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2788     }
2789 }
2790
2791 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2792                                     uint64_t value)
2793 {
2794     /* Invalidate by IPA. This has to invalidate any structures that
2795      * contain only stage 2 translation information, but does not need
2796      * to apply to structures that contain combined stage 1 and stage 2
2797      * translation information.
2798      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2799      */
2800     ARMCPU *cpu = arm_env_get_cpu(env);
2801     CPUState *cs = CPU(cpu);
2802     uint64_t pageaddr;
2803
2804     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2805         return;
2806     }
2807
2808     pageaddr = sextract64(value << 12, 0, 48);
2809
2810     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2811 }
2812
2813 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2814                                       uint64_t value)
2815 {
2816     CPUState *other_cs;
2817     uint64_t pageaddr;
2818
2819     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2820         return;
2821     }
2822
2823     pageaddr = sextract64(value << 12, 0, 48);
2824
2825     CPU_FOREACH(other_cs) {
2826         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2827     }
2828 }
2829
2830 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2831 {
2832     /* We don't implement EL2, so the only control on DC ZVA is the
2833      * bit in the SCTLR which can prohibit access for EL0.
2834      */
2835     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2836         return CP_ACCESS_TRAP;
2837     }
2838     return CP_ACCESS_OK;
2839 }
2840
2841 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2842 {
2843     ARMCPU *cpu = arm_env_get_cpu(env);
2844     int dzp_bit = 1 << 4;
2845
2846     /* DZP indicates whether DC ZVA access is allowed */
2847     if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2848         dzp_bit = 0;
2849     }
2850     return cpu->dcz_blocksize | dzp_bit;
2851 }
2852
2853 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2854 {
2855     if (!(env->pstate & PSTATE_SP)) {
2856         /* Access to SP_EL0 is undefined if it's being used as
2857          * the stack pointer.
2858          */
2859         return CP_ACCESS_TRAP_UNCATEGORIZED;
2860     }
2861     return CP_ACCESS_OK;
2862 }
2863
2864 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2865 {
2866     return env->pstate & PSTATE_SP;
2867 }
2868
2869 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2870 {
2871     update_spsel(env, val);
2872 }
2873
2874 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2875                         uint64_t value)
2876 {
2877     ARMCPU *cpu = arm_env_get_cpu(env);
2878
2879     if (raw_read(env, ri) == value) {
2880         /* Skip the TLB flush if nothing actually changed; Linux likes
2881          * to do a lot of pointless SCTLR writes.
2882          */
2883         return;
2884     }
2885
2886     raw_write(env, ri, value);
2887     /* ??? Lots of these bits are not implemented.  */
2888     /* This may enable/disable the MMU, so do a TLB flush.  */
2889     tlb_flush(CPU(cpu), 1);
2890 }
2891
2892 static const ARMCPRegInfo v8_cp_reginfo[] = {
2893     /* Minimal set of EL0-visible registers. This will need to be expanded
2894      * significantly for system emulation of AArch64 CPUs.
2895      */
2896     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2897       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2898       .access = PL0_RW, .type = ARM_CP_NZCV },
2899     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2900       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2901       .type = ARM_CP_NO_RAW,
2902       .access = PL0_RW, .accessfn = aa64_daif_access,
2903       .fieldoffset = offsetof(CPUARMState, daif),
2904       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2905     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2906       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2907       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2908     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2909       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2910       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2911     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2912       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2913       .access = PL0_R, .type = ARM_CP_NO_RAW,
2914       .readfn = aa64_dczid_read },
2915     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2916       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2917       .access = PL0_W, .type = ARM_CP_DC_ZVA,
2918 #ifndef CONFIG_USER_ONLY
2919       /* Avoid overhead of an access check that always passes in user-mode */
2920       .accessfn = aa64_zva_access,
2921 #endif
2922     },
2923     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2924       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2925       .access = PL1_R, .type = ARM_CP_CURRENTEL },
2926     /* Cache ops: all NOPs since we don't emulate caches */
2927     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2928       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2929       .access = PL1_W, .type = ARM_CP_NOP },
2930     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2931       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2932       .access = PL1_W, .type = ARM_CP_NOP },
2933     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2934       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2935       .access = PL0_W, .type = ARM_CP_NOP,
2936       .accessfn = aa64_cacheop_access },
2937     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2938       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2939       .access = PL1_W, .type = ARM_CP_NOP },
2940     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2941       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2942       .access = PL1_W, .type = ARM_CP_NOP },
2943     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2944       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2945       .access = PL0_W, .type = ARM_CP_NOP,
2946       .accessfn = aa64_cacheop_access },
2947     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2948       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2949       .access = PL1_W, .type = ARM_CP_NOP },
2950     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2951       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2952       .access = PL0_W, .type = ARM_CP_NOP,
2953       .accessfn = aa64_cacheop_access },
2954     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2955       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2956       .access = PL0_W, .type = ARM_CP_NOP,
2957       .accessfn = aa64_cacheop_access },
2958     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2959       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2960       .access = PL1_W, .type = ARM_CP_NOP },
2961     /* TLBI operations */
2962     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2963       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2964       .access = PL1_W, .type = ARM_CP_NO_RAW,
2965       .writefn = tlbi_aa64_vmalle1is_write },
2966     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2967       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2968       .access = PL1_W, .type = ARM_CP_NO_RAW,
2969       .writefn = tlbi_aa64_vae1is_write },
2970     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2971       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2972       .access = PL1_W, .type = ARM_CP_NO_RAW,
2973       .writefn = tlbi_aa64_vmalle1is_write },
2974     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2975       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2976       .access = PL1_W, .type = ARM_CP_NO_RAW,
2977       .writefn = tlbi_aa64_vae1is_write },
2978     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2979       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2980       .access = PL1_W, .type = ARM_CP_NO_RAW,
2981       .writefn = tlbi_aa64_vae1is_write },
2982     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2983       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2984       .access = PL1_W, .type = ARM_CP_NO_RAW,
2985       .writefn = tlbi_aa64_vae1is_write },
2986     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2987       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2988       .access = PL1_W, .type = ARM_CP_NO_RAW,
2989       .writefn = tlbi_aa64_vmalle1_write },
2990     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2991       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2992       .access = PL1_W, .type = ARM_CP_NO_RAW,
2993       .writefn = tlbi_aa64_vae1_write },
2994     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2995       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2996       .access = PL1_W, .type = ARM_CP_NO_RAW,
2997       .writefn = tlbi_aa64_vmalle1_write },
2998     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2999       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3000       .access = PL1_W, .type = ARM_CP_NO_RAW,
3001       .writefn = tlbi_aa64_vae1_write },
3002     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3003       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3004       .access = PL1_W, .type = ARM_CP_NO_RAW,
3005       .writefn = tlbi_aa64_vae1_write },
3006     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3007       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3008       .access = PL1_W, .type = ARM_CP_NO_RAW,
3009       .writefn = tlbi_aa64_vae1_write },
3010     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3011       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3012       .access = PL2_W, .type = ARM_CP_NO_RAW,
3013       .writefn = tlbi_aa64_ipas2e1is_write },
3014     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3015       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3016       .access = PL2_W, .type = ARM_CP_NO_RAW,
3017       .writefn = tlbi_aa64_ipas2e1is_write },
3018     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3019       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3020       .access = PL2_W, .type = ARM_CP_NO_RAW,
3021       .writefn = tlbi_aa64_alle1is_write },
3022     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3023       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3024       .access = PL2_W, .type = ARM_CP_NO_RAW,
3025       .writefn = tlbi_aa64_alle1is_write },
3026     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3027       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3028       .access = PL2_W, .type = ARM_CP_NO_RAW,
3029       .writefn = tlbi_aa64_ipas2e1_write },
3030     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3031       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3032       .access = PL2_W, .type = ARM_CP_NO_RAW,
3033       .writefn = tlbi_aa64_ipas2e1_write },
3034     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3035       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3036       .access = PL2_W, .type = ARM_CP_NO_RAW,
3037       .writefn = tlbi_aa64_alle1_write },
3038     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3039       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3040       .access = PL2_W, .type = ARM_CP_NO_RAW,
3041       .writefn = tlbi_aa64_alle1is_write },
3042 #ifndef CONFIG_USER_ONLY
3043     /* 64 bit address translation operations */
3044     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3045       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3046       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3047     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3048       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3049       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3050     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3051       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3052       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3053     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3054       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3055       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3056     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3057       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3058       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3059     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3060       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3061       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3062     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3063       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3064       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3065     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3066       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3067       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3068     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3069     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3070       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3071       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3072     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3073       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3074       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3075     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3076       .type = ARM_CP_ALIAS,
3077       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3078       .access = PL1_RW, .resetvalue = 0,
3079       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3080       .writefn = par_write },
3081 #endif
3082     /* TLB invalidate last level of translation table walk */
3083     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3084       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3085     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3086       .type = ARM_CP_NO_RAW, .access = PL1_W,
3087       .writefn = tlbimvaa_is_write },
3088     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3089       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3090     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3091       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3092     /* 32 bit cache operations */
3093     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3094       .type = ARM_CP_NOP, .access = PL1_W },
3095     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3096       .type = ARM_CP_NOP, .access = PL1_W },
3097     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3098       .type = ARM_CP_NOP, .access = PL1_W },
3099     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3100       .type = ARM_CP_NOP, .access = PL1_W },
3101     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3102       .type = ARM_CP_NOP, .access = PL1_W },
3103     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3104       .type = ARM_CP_NOP, .access = PL1_W },
3105     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3106       .type = ARM_CP_NOP, .access = PL1_W },
3107     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3108       .type = ARM_CP_NOP, .access = PL1_W },
3109     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3110       .type = ARM_CP_NOP, .access = PL1_W },
3111     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3112       .type = ARM_CP_NOP, .access = PL1_W },
3113     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3114       .type = ARM_CP_NOP, .access = PL1_W },
3115     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3116       .type = ARM_CP_NOP, .access = PL1_W },
3117     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3118       .type = ARM_CP_NOP, .access = PL1_W },
3119     /* MMU Domain access control / MPU write buffer control */
3120     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3121       .access = PL1_RW, .resetvalue = 0,
3122       .writefn = dacr_write, .raw_writefn = raw_write,
3123       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3124                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3125     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3126       .type = ARM_CP_ALIAS,
3127       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3128       .access = PL1_RW,
3129       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3130     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3131       .type = ARM_CP_ALIAS,
3132       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3133       .access = PL1_RW,
3134       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3135     /* We rely on the access checks not allowing the guest to write to the
3136      * state field when SPSel indicates that it's being used as the stack
3137      * pointer.
3138      */
3139     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3140       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3141       .access = PL1_RW, .accessfn = sp_el0_access,
3142       .type = ARM_CP_ALIAS,
3143       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3144     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3145       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3146       .access = PL2_RW, .type = ARM_CP_ALIAS,
3147       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3148     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3149       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3150       .type = ARM_CP_NO_RAW,
3151       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3152     REGINFO_SENTINEL
3153 };
3154
3155 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3156 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3157     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3158       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3159       .access = PL2_RW,
3160       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3161     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3162       .type = ARM_CP_NO_RAW,
3163       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3164       .access = PL2_RW,
3165       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3166     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3167       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3168       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3169     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3170       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3171       .access = PL2_RW, .type = ARM_CP_CONST,
3172       .resetvalue = 0 },
3173     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3174       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3175       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3176     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3177       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3178       .access = PL2_RW, .type = ARM_CP_CONST,
3179       .resetvalue = 0 },
3180     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3181       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3182       .access = PL2_RW, .type = ARM_CP_CONST,
3183       .resetvalue = 0 },
3184     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3185       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3186       .access = PL2_RW, .type = ARM_CP_CONST,
3187       .resetvalue = 0 },
3188     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3189       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3190       .access = PL2_RW, .type = ARM_CP_CONST,
3191       .resetvalue = 0 },
3192     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3193       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3194       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3195     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3196       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3197       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3198       .type = ARM_CP_CONST, .resetvalue = 0 },
3199     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3200       .cp = 15, .opc1 = 6, .crm = 2,
3201       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3202       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3203     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3204       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3205       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3206     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3207       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3208       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3209     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3210       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3211       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3212     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3213       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3214       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3215     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3216       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3217       .resetvalue = 0 },
3218     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3219       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3220       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3221     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3222       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3223       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3224     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3225       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3226       .resetvalue = 0 },
3227     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3228       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3229       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3230     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3231       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3232       .resetvalue = 0 },
3233     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3234       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3235       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3236     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3237       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3238       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3239     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3240       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3241       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3242     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3243       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3244       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3245       .type = ARM_CP_CONST, .resetvalue = 0 },
3246     REGINFO_SENTINEL
3247 };
3248
3249 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3250 {
3251     ARMCPU *cpu = arm_env_get_cpu(env);
3252     uint64_t valid_mask = HCR_MASK;
3253
3254     if (arm_feature(env, ARM_FEATURE_EL3)) {
3255         valid_mask &= ~HCR_HCD;
3256     } else {
3257         valid_mask &= ~HCR_TSC;
3258     }
3259
3260     /* Clear RES0 bits.  */
3261     value &= valid_mask;
3262
3263     /* These bits change the MMU setup:
3264      * HCR_VM enables stage 2 translation
3265      * HCR_PTW forbids certain page-table setups
3266      * HCR_DC Disables stage1 and enables stage2 translation
3267      */
3268     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3269         tlb_flush(CPU(cpu), 1);
3270     }
3271     raw_write(env, ri, value);
3272 }
3273
3274 static const ARMCPRegInfo el2_cp_reginfo[] = {
3275     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3276       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3277       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3278       .writefn = hcr_write },
3279     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3280       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3281       .access = PL2_RW, .resetvalue = 0,
3282       .writefn = dacr_write, .raw_writefn = raw_write,
3283       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3284     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3285       .type = ARM_CP_ALIAS,
3286       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3287       .access = PL2_RW,
3288       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3289     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3290       .type = ARM_CP_ALIAS,
3291       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3292       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3293     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3294       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3295       .access = PL2_RW, .resetvalue = 0,
3296       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3297     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3298       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3299       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3300     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3301       .type = ARM_CP_ALIAS,
3302       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3303       .access = PL2_RW,
3304       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3305     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3306       .type = ARM_CP_ALIAS,
3307       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3308       .access = PL2_RW,
3309       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3310     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3311       .type = ARM_CP_ALIAS,
3312       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3313       .access = PL2_RW,
3314       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3315     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3316       .type = ARM_CP_ALIAS,
3317       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3318       .access = PL2_RW,
3319       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3320     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3321       .type = ARM_CP_ALIAS,
3322       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3323       .access = PL2_RW,
3324       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3325     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3326       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3327       .access = PL2_RW, .writefn = vbar_write,
3328       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3329       .resetvalue = 0 },
3330     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3331       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3332       .access = PL3_RW, .type = ARM_CP_ALIAS,
3333       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3334     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3335       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3336       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3337       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3338     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3339       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3340       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3341       .resetvalue = 0 },
3342     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3343       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3344       .access = PL2_RW, .type = ARM_CP_ALIAS,
3345       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3346     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3347       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3348       .access = PL2_RW, .type = ARM_CP_CONST,
3349       .resetvalue = 0 },
3350     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3351     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3352       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3353       .access = PL2_RW, .type = ARM_CP_CONST,
3354       .resetvalue = 0 },
3355     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3356       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3357       .access = PL2_RW, .type = ARM_CP_CONST,
3358       .resetvalue = 0 },
3359     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3360       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3361       .access = PL2_RW, .type = ARM_CP_CONST,
3362       .resetvalue = 0 },
3363     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3364       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3365       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3366       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3367       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3368     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3369       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3370       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3371       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3372     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3373       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3374       .access = PL2_RW, .type = ARM_CP_ALIAS,
3375       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3376     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3377       .cp = 15, .opc1 = 6, .crm = 2,
3378       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3379       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3380       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3381       .writefn = vttbr_write },
3382     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3383       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3384       .access = PL2_RW, .writefn = vttbr_write,
3385       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3386     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3387       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3388       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3389       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3390     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3391       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3392       .access = PL2_RW, .resetvalue = 0,
3393       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3394     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3395       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3396       .access = PL2_RW, .resetvalue = 0,
3397       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3398     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3399       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3400       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3401     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3402       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3403       .type = ARM_CP_NO_RAW, .access = PL2_W,
3404       .writefn = tlbi_aa64_alle2_write },
3405     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3406       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3407       .type = ARM_CP_NO_RAW, .access = PL2_W,
3408       .writefn = tlbi_aa64_vae2_write },
3409     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3410       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3411       .access = PL2_W, .type = ARM_CP_NO_RAW,
3412       .writefn = tlbi_aa64_vae2_write },
3413     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3414       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3415       .access = PL2_W, .type = ARM_CP_NO_RAW,
3416       .writefn = tlbi_aa64_alle2is_write },
3417     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3418       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3419       .type = ARM_CP_NO_RAW, .access = PL2_W,
3420       .writefn = tlbi_aa64_vae2is_write },
3421     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3422       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3423       .access = PL2_W, .type = ARM_CP_NO_RAW,
3424       .writefn = tlbi_aa64_vae2is_write },
3425 #ifndef CONFIG_USER_ONLY
3426     /* Unlike the other EL2-related AT operations, these must
3427      * UNDEF from EL3 if EL2 is not implemented, which is why we
3428      * define them here rather than with the rest of the AT ops.
3429      */
3430     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3431       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3432       .access = PL2_W, .accessfn = at_s1e2_access,
3433       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3434     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3435       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3436       .access = PL2_W, .accessfn = at_s1e2_access,
3437       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3438     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3439      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3440      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3441      * to behave as if SCR.NS was 1.
3442      */
3443     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3444       .access = PL2_W,
3445       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3446     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3447       .access = PL2_W,
3448       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3449     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3450       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3451       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3452        * reset values as IMPDEF. We choose to reset to 3 to comply with
3453        * both ARMv7 and ARMv8.
3454        */
3455       .access = PL2_RW, .resetvalue = 3,
3456       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3457     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3458       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3459       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3460       .writefn = gt_cntvoff_write,
3461       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3462     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3463       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3464       .writefn = gt_cntvoff_write,
3465       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3466     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3467       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3468       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3469       .type = ARM_CP_IO, .access = PL2_RW,
3470       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3471     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3472       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3473       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3474       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3475     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3476       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3477       .type = ARM_CP_IO, .access = PL2_RW,
3478       .resetfn = gt_hyp_timer_reset,
3479       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3480     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3481       .type = ARM_CP_IO,
3482       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3483       .access = PL2_RW,
3484       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3485       .resetvalue = 0,
3486       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3487 #endif
3488     /* The only field of MDCR_EL2 that has a defined architectural reset value
3489      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3490      * don't impelment any PMU event counters, so using zero as a reset
3491      * value for MDCR_EL2 is okay
3492      */
3493     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3494       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3495       .access = PL2_RW, .resetvalue = 0,
3496       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3497     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3498       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3499       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3500       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3501     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3502       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3503       .access = PL2_RW,
3504       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3505     REGINFO_SENTINEL
3506 };
3507
3508 static const ARMCPRegInfo el3_cp_reginfo[] = {
3509     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3510       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3511       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3512       .resetvalue = 0, .writefn = scr_write },
3513     { .name = "SCR",  .type = ARM_CP_ALIAS,
3514       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3515       .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3516       .writefn = scr_write },
3517     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3518       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3519       .access = PL3_RW, .resetvalue = 0,
3520       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3521     { .name = "SDER",
3522       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3523       .access = PL3_RW, .resetvalue = 0,
3524       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3525       /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3526     { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
3527       .access = PL3_W | PL1_R, .resetvalue = 0,
3528       .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
3529     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3530       .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
3531       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3532     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3533       .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3534       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3535       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3536       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3537     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3538       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3539       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3540       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3541     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3542       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3543       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3544       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3545       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3546     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3547       .type = ARM_CP_ALIAS,
3548       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3549       .access = PL3_RW,
3550       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3551     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3552       .type = ARM_CP_ALIAS,
3553       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3554       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3555     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3556       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3557       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3558     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3559       .type = ARM_CP_ALIAS,
3560       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3561       .access = PL3_RW,
3562       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3563     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3564       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3565       .access = PL3_RW, .writefn = vbar_write,
3566       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3567       .resetvalue = 0 },
3568     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3569       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3570       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3571       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3572     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3573       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3574       .access = PL3_RW, .resetvalue = 0,
3575       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3576     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3577       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3578       .access = PL3_RW, .type = ARM_CP_CONST,
3579       .resetvalue = 0 },
3580     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3581       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3582       .access = PL3_RW, .type = ARM_CP_CONST,
3583       .resetvalue = 0 },
3584     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3585       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3586       .access = PL3_RW, .type = ARM_CP_CONST,
3587       .resetvalue = 0 },
3588     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3589       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3590       .access = PL3_W, .type = ARM_CP_NO_RAW,
3591       .writefn = tlbi_aa64_alle3is_write },
3592     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3593       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3594       .access = PL3_W, .type = ARM_CP_NO_RAW,
3595       .writefn = tlbi_aa64_vae3is_write },
3596     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3597       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3598       .access = PL3_W, .type = ARM_CP_NO_RAW,
3599       .writefn = tlbi_aa64_vae3is_write },
3600     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3601       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3602       .access = PL3_W, .type = ARM_CP_NO_RAW,
3603       .writefn = tlbi_aa64_alle3_write },
3604     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3605       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3606       .access = PL3_W, .type = ARM_CP_NO_RAW,
3607       .writefn = tlbi_aa64_vae3_write },
3608     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3609       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3610       .access = PL3_W, .type = ARM_CP_NO_RAW,
3611       .writefn = tlbi_aa64_vae3_write },
3612     REGINFO_SENTINEL
3613 };
3614
3615 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
3616 {
3617     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3618      * but the AArch32 CTR has its own reginfo struct)
3619      */
3620     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3621         return CP_ACCESS_TRAP;
3622     }
3623     return CP_ACCESS_OK;
3624 }
3625
3626 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3627                         uint64_t value)
3628 {
3629     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3630      * read via a bit in OSLSR_EL1.
3631      */
3632     int oslock;
3633
3634     if (ri->state == ARM_CP_STATE_AA32) {
3635         oslock = (value == 0xC5ACCE55);
3636     } else {
3637         oslock = value & 1;
3638     }
3639
3640     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3641 }
3642
3643 static const ARMCPRegInfo debug_cp_reginfo[] = {
3644     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3645      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3646      * unlike DBGDRAR it is never accessible from EL0.
3647      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3648      * accessor.
3649      */
3650     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3651       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3652     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3653       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3654       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3655     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3656       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3657     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3658     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3659       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3660       .access = PL1_RW,
3661       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3662       .resetvalue = 0 },
3663     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3664      * We don't implement the configurable EL0 access.
3665      */
3666     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3667       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3668       .type = ARM_CP_ALIAS,
3669       .access = PL1_R,
3670       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3671     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3672       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3673       .access = PL1_W, .type = ARM_CP_NO_RAW,
3674       .writefn = oslar_write },
3675     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3676       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3677       .access = PL1_R, .resetvalue = 10,
3678       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3679     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3680     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3681       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3682       .access = PL1_RW, .type = ARM_CP_NOP },
3683     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3684      * implement vector catch debug events yet.
3685      */
3686     { .name = "DBGVCR",
3687       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3688       .access = PL1_RW, .type = ARM_CP_NOP },
3689     REGINFO_SENTINEL
3690 };
3691
3692 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3693     /* 64 bit access versions of the (dummy) debug registers */
3694     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3695       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3696     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3697       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3698     REGINFO_SENTINEL
3699 };
3700
3701 void hw_watchpoint_update(ARMCPU *cpu, int n)
3702 {
3703     CPUARMState *env = &cpu->env;
3704     vaddr len = 0;
3705     vaddr wvr = env->cp15.dbgwvr[n];
3706     uint64_t wcr = env->cp15.dbgwcr[n];
3707     int mask;
3708     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3709
3710     if (env->cpu_watchpoint[n]) {
3711         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3712         env->cpu_watchpoint[n] = NULL;
3713     }
3714
3715     if (!extract64(wcr, 0, 1)) {
3716         /* E bit clear : watchpoint disabled */
3717         return;
3718     }
3719
3720     switch (extract64(wcr, 3, 2)) {
3721     case 0:
3722         /* LSC 00 is reserved and must behave as if the wp is disabled */
3723         return;
3724     case 1:
3725         flags |= BP_MEM_READ;
3726         break;
3727     case 2:
3728         flags |= BP_MEM_WRITE;
3729         break;
3730     case 3:
3731         flags |= BP_MEM_ACCESS;
3732         break;
3733     }
3734
3735     /* Attempts to use both MASK and BAS fields simultaneously are
3736      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3737      * thus generating a watchpoint for every byte in the masked region.
3738      */
3739     mask = extract64(wcr, 24, 4);
3740     if (mask == 1 || mask == 2) {
3741         /* Reserved values of MASK; we must act as if the mask value was
3742          * some non-reserved value, or as if the watchpoint were disabled.
3743          * We choose the latter.
3744          */
3745         return;
3746     } else if (mask) {
3747         /* Watchpoint covers an aligned area up to 2GB in size */
3748         len = 1ULL << mask;
3749         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3750          * whether the watchpoint fires when the unmasked bits match; we opt
3751          * to generate the exceptions.
3752          */
3753         wvr &= ~(len - 1);
3754     } else {
3755         /* Watchpoint covers bytes defined by the byte address select bits */
3756         int bas = extract64(wcr, 5, 8);
3757         int basstart;
3758
3759         if (bas == 0) {
3760             /* This must act as if the watchpoint is disabled */
3761             return;
3762         }
3763
3764         if (extract64(wvr, 2, 1)) {
3765             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3766              * ignored, and BAS[3:0] define which bytes to watch.
3767              */
3768             bas &= 0xf;
3769         }
3770         /* The BAS bits are supposed to be programmed to indicate a contiguous
3771          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3772          * we fire for each byte in the word/doubleword addressed by the WVR.
3773          * We choose to ignore any non-zero bits after the first range of 1s.
3774          */
3775         basstart = ctz32(bas);
3776         len = cto32(bas >> basstart);
3777         wvr += basstart;
3778     }
3779
3780     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3781                           &env->cpu_watchpoint[n]);
3782 }
3783
3784 void hw_watchpoint_update_all(ARMCPU *cpu)
3785 {
3786     int i;
3787     CPUARMState *env = &cpu->env;
3788
3789     /* Completely clear out existing QEMU watchpoints and our array, to
3790      * avoid possible stale entries following migration load.
3791      */
3792     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
3793     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
3794
3795     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
3796         hw_watchpoint_update(cpu, i);
3797     }
3798 }
3799
3800 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3801                          uint64_t value)
3802 {
3803     ARMCPU *cpu = arm_env_get_cpu(env);
3804     int i = ri->crm;
3805
3806     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3807      * register reads and behaves as if values written are sign extended.
3808      * Bits [1:0] are RES0.
3809      */
3810     value = sextract64(value, 0, 49) & ~3ULL;
3811
3812     raw_write(env, ri, value);
3813     hw_watchpoint_update(cpu, i);
3814 }
3815
3816 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3817                          uint64_t value)
3818 {
3819     ARMCPU *cpu = arm_env_get_cpu(env);
3820     int i = ri->crm;
3821
3822     raw_write(env, ri, value);
3823     hw_watchpoint_update(cpu, i);
3824 }
3825
3826 void hw_breakpoint_update(ARMCPU *cpu, int n)
3827 {
3828     CPUARMState *env = &cpu->env;
3829     uint64_t bvr = env->cp15.dbgbvr[n];
3830     uint64_t bcr = env->cp15.dbgbcr[n];
3831     vaddr addr;
3832     int bt;
3833     int flags = BP_CPU;
3834
3835     if (env->cpu_breakpoint[n]) {
3836         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
3837         env->cpu_breakpoint[n] = NULL;
3838     }
3839
3840     if (!extract64(bcr, 0, 1)) {
3841         /* E bit clear : watchpoint disabled */
3842         return;
3843     }
3844
3845     bt = extract64(bcr, 20, 4);
3846
3847     switch (bt) {
3848     case 4: /* unlinked address mismatch (reserved if AArch64) */
3849     case 5: /* linked address mismatch (reserved if AArch64) */
3850         qemu_log_mask(LOG_UNIMP,
3851                       "arm: address mismatch breakpoint types not implemented");
3852         return;
3853     case 0: /* unlinked address match */
3854     case 1: /* linked address match */
3855     {
3856         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3857          * we behave as if the register was sign extended. Bits [1:0] are
3858          * RES0. The BAS field is used to allow setting breakpoints on 16
3859          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3860          * a bp will fire if the addresses covered by the bp and the addresses
3861          * covered by the insn overlap but the insn doesn't start at the
3862          * start of the bp address range. We choose to require the insn and
3863          * the bp to have the same address. The constraints on writing to
3864          * BAS enforced in dbgbcr_write mean we have only four cases:
3865          *  0b0000  => no breakpoint
3866          *  0b0011  => breakpoint on addr
3867          *  0b1100  => breakpoint on addr + 2
3868          *  0b1111  => breakpoint on addr
3869          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3870          */
3871         int bas = extract64(bcr, 5, 4);
3872         addr = sextract64(bvr, 0, 49) & ~3ULL;
3873         if (bas == 0) {
3874             return;
3875         }
3876         if (bas == 0xc) {
3877             addr += 2;
3878         }
3879         break;
3880     }
3881     case 2: /* unlinked context ID match */
3882     case 8: /* unlinked VMID match (reserved if no EL2) */
3883     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3884         qemu_log_mask(LOG_UNIMP,
3885                       "arm: unlinked context breakpoint types not implemented");
3886         return;
3887     case 9: /* linked VMID match (reserved if no EL2) */
3888     case 11: /* linked context ID and VMID match (reserved if no EL2) */
3889     case 3: /* linked context ID match */
3890     default:
3891         /* We must generate no events for Linked context matches (unless
3892          * they are linked to by some other bp/wp, which is handled in
3893          * updates for the linking bp/wp). We choose to also generate no events
3894          * for reserved values.
3895          */
3896         return;
3897     }
3898
3899     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
3900 }
3901
3902 void hw_breakpoint_update_all(ARMCPU *cpu)
3903 {
3904     int i;
3905     CPUARMState *env = &cpu->env;
3906
3907     /* Completely clear out existing QEMU breakpoints and our array, to
3908      * avoid possible stale entries following migration load.
3909      */
3910     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3911     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3912
3913     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3914         hw_breakpoint_update(cpu, i);
3915     }
3916 }
3917
3918 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3919                          uint64_t value)
3920 {
3921     ARMCPU *cpu = arm_env_get_cpu(env);
3922     int i = ri->crm;
3923
3924     raw_write(env, ri, value);
3925     hw_breakpoint_update(cpu, i);
3926 }
3927
3928 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3929                          uint64_t value)
3930 {
3931     ARMCPU *cpu = arm_env_get_cpu(env);
3932     int i = ri->crm;
3933
3934     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3935      * copy of BAS[0].
3936      */
3937     value = deposit64(value, 6, 1, extract64(value, 5, 1));
3938     value = deposit64(value, 8, 1, extract64(value, 7, 1));
3939
3940     raw_write(env, ri, value);
3941     hw_breakpoint_update(cpu, i);
3942 }
3943
3944 static void define_debug_regs(ARMCPU *cpu)
3945 {
3946     /* Define v7 and v8 architectural debug registers.
3947      * These are just dummy implementations for now.
3948      */
3949     int i;
3950     int wrps, brps, ctx_cmps;
3951     ARMCPRegInfo dbgdidr = {
3952         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
3953         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
3954     };
3955
3956     /* Note that all these register fields hold "number of Xs minus 1". */
3957     brps = extract32(cpu->dbgdidr, 24, 4);
3958     wrps = extract32(cpu->dbgdidr, 28, 4);
3959     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
3960
3961     assert(ctx_cmps <= brps);
3962
3963     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3964      * of the debug registers such as number of breakpoints;
3965      * check that if they both exist then they agree.
3966      */
3967     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
3968         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
3969         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
3970         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
3971     }
3972
3973     define_one_arm_cp_reg(cpu, &dbgdidr);
3974     define_arm_cp_regs(cpu, debug_cp_reginfo);
3975
3976     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
3977         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
3978     }
3979
3980     for (i = 0; i < brps + 1; i++) {
3981         ARMCPRegInfo dbgregs[] = {
3982             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
3983               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
3984               .access = PL1_RW,
3985               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
3986               .writefn = dbgbvr_write, .raw_writefn = raw_write
3987             },
3988             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
3989               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
3990               .access = PL1_RW,
3991               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
3992               .writefn = dbgbcr_write, .raw_writefn = raw_write
3993             },
3994             REGINFO_SENTINEL
3995         };
3996         define_arm_cp_regs(cpu, dbgregs);
3997     }
3998
3999     for (i = 0; i < wrps + 1; i++) {
4000         ARMCPRegInfo dbgregs[] = {
4001             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4002               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4003               .access = PL1_RW,
4004               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4005               .writefn = dbgwvr_write, .raw_writefn = raw_write
4006             },
4007             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4008               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4009               .access = PL1_RW,
4010               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4011               .writefn = dbgwcr_write, .raw_writefn = raw_write
4012             },
4013             REGINFO_SENTINEL
4014         };
4015         define_arm_cp_regs(cpu, dbgregs);
4016     }
4017 }
4018
4019 void register_cp_regs_for_features(ARMCPU *cpu)
4020 {
4021     /* Register all the coprocessor registers based on feature bits */
4022     CPUARMState *env = &cpu->env;
4023     if (arm_feature(env, ARM_FEATURE_M)) {
4024         /* M profile has no coprocessor registers */
4025         return;
4026     }
4027
4028     define_arm_cp_regs(cpu, cp_reginfo);
4029     if (!arm_feature(env, ARM_FEATURE_V8)) {
4030         /* Must go early as it is full of wildcards that may be
4031          * overridden by later definitions.
4032          */
4033         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4034     }
4035
4036     if (arm_feature(env, ARM_FEATURE_V6)) {
4037         /* The ID registers all have impdef reset values */
4038         ARMCPRegInfo v6_idregs[] = {
4039             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4040               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4041               .access = PL1_R, .type = ARM_CP_CONST,
4042               .resetvalue = cpu->id_pfr0 },
4043             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4044               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4045               .access = PL1_R, .type = ARM_CP_CONST,
4046               .resetvalue = cpu->id_pfr1 },
4047             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4048               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4049               .access = PL1_R, .type = ARM_CP_CONST,
4050               .resetvalue = cpu->id_dfr0 },
4051             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4052               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4053               .access = PL1_R, .type = ARM_CP_CONST,
4054               .resetvalue = cpu->id_afr0 },
4055             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4056               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4057               .access = PL1_R, .type = ARM_CP_CONST,
4058               .resetvalue = cpu->id_mmfr0 },
4059             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4060               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4061               .access = PL1_R, .type = ARM_CP_CONST,
4062               .resetvalue = cpu->id_mmfr1 },
4063             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4064               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4065               .access = PL1_R, .type = ARM_CP_CONST,
4066               .resetvalue = cpu->id_mmfr2 },
4067             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4068               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4069               .access = PL1_R, .type = ARM_CP_CONST,
4070               .resetvalue = cpu->id_mmfr3 },
4071             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4072               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4073               .access = PL1_R, .type = ARM_CP_CONST,
4074               .resetvalue = cpu->id_isar0 },
4075             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4076               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4077               .access = PL1_R, .type = ARM_CP_CONST,
4078               .resetvalue = cpu->id_isar1 },
4079             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4080               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4081               .access = PL1_R, .type = ARM_CP_CONST,
4082               .resetvalue = cpu->id_isar2 },
4083             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4084               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4085               .access = PL1_R, .type = ARM_CP_CONST,
4086               .resetvalue = cpu->id_isar3 },
4087             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4088               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4089               .access = PL1_R, .type = ARM_CP_CONST,
4090               .resetvalue = cpu->id_isar4 },
4091             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4092               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4093               .access = PL1_R, .type = ARM_CP_CONST,
4094               .resetvalue = cpu->id_isar5 },
4095             /* 6..7 are as yet unallocated and must RAZ */
4096             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
4097               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
4098               .resetvalue = 0 },
4099             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
4100               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
4101               .resetvalue = 0 },
4102             REGINFO_SENTINEL
4103         };
4104         define_arm_cp_regs(cpu, v6_idregs);
4105         define_arm_cp_regs(cpu, v6_cp_reginfo);
4106     } else {
4107         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4108     }
4109     if (arm_feature(env, ARM_FEATURE_V6K)) {
4110         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4111     }
4112     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4113         !arm_feature(env, ARM_FEATURE_MPU)) {
4114         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4115     }
4116     if (arm_feature(env, ARM_FEATURE_V7)) {
4117         /* v7 performance monitor control register: same implementor
4118          * field as main ID register, and we implement only the cycle
4119          * count register.
4120          */
4121 #ifndef CONFIG_USER_ONLY
4122         ARMCPRegInfo pmcr = {
4123             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4124             .access = PL0_RW,
4125             .type = ARM_CP_IO | ARM_CP_ALIAS,
4126             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4127             .accessfn = pmreg_access, .writefn = pmcr_write,
4128             .raw_writefn = raw_write,
4129         };
4130         ARMCPRegInfo pmcr64 = {
4131             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4132             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4133             .access = PL0_RW, .accessfn = pmreg_access,
4134             .type = ARM_CP_IO,
4135             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4136             .resetvalue = cpu->midr & 0xff000000,
4137             .writefn = pmcr_write, .raw_writefn = raw_write,
4138         };
4139         define_one_arm_cp_reg(cpu, &pmcr);
4140         define_one_arm_cp_reg(cpu, &pmcr64);
4141 #endif
4142         ARMCPRegInfo clidr = {
4143             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4144             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4145             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4146         };
4147         define_one_arm_cp_reg(cpu, &clidr);
4148         define_arm_cp_regs(cpu, v7_cp_reginfo);
4149         define_debug_regs(cpu);
4150     } else {
4151         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4152     }
4153     if (arm_feature(env, ARM_FEATURE_V8)) {
4154         /* AArch64 ID registers, which all have impdef reset values */
4155         ARMCPRegInfo v8_idregs[] = {
4156             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4157               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4158               .access = PL1_R, .type = ARM_CP_CONST,
4159               .resetvalue = cpu->id_aa64pfr0 },
4160             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4161               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4162               .access = PL1_R, .type = ARM_CP_CONST,
4163               .resetvalue = cpu->id_aa64pfr1},
4164             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4165               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4166               .access = PL1_R, .type = ARM_CP_CONST,
4167               /* We mask out the PMUVer field, because we don't currently
4168                * implement the PMU. Not advertising it prevents the guest
4169                * from trying to use it and getting UNDEFs on registers we
4170                * don't implement.
4171                */
4172               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4173             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4174               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4175               .access = PL1_R, .type = ARM_CP_CONST,
4176               .resetvalue = cpu->id_aa64dfr1 },
4177             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4178               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4179               .access = PL1_R, .type = ARM_CP_CONST,
4180               .resetvalue = cpu->id_aa64afr0 },
4181             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4182               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4183               .access = PL1_R, .type = ARM_CP_CONST,
4184               .resetvalue = cpu->id_aa64afr1 },
4185             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4186               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4187               .access = PL1_R, .type = ARM_CP_CONST,
4188               .resetvalue = cpu->id_aa64isar0 },
4189             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4190               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4191               .access = PL1_R, .type = ARM_CP_CONST,
4192               .resetvalue = cpu->id_aa64isar1 },
4193             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4194               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4195               .access = PL1_R, .type = ARM_CP_CONST,
4196               .resetvalue = cpu->id_aa64mmfr0 },
4197             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4198               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4199               .access = PL1_R, .type = ARM_CP_CONST,
4200               .resetvalue = cpu->id_aa64mmfr1 },
4201             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4202               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4203               .access = PL1_R, .type = ARM_CP_CONST,
4204               .resetvalue = cpu->mvfr0 },
4205             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4206               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4207               .access = PL1_R, .type = ARM_CP_CONST,
4208               .resetvalue = cpu->mvfr1 },
4209             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4210               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4211               .access = PL1_R, .type = ARM_CP_CONST,
4212               .resetvalue = cpu->mvfr2 },
4213             REGINFO_SENTINEL
4214         };
4215         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4216         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4217             !arm_feature(env, ARM_FEATURE_EL2)) {
4218             ARMCPRegInfo rvbar = {
4219                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4220                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4221                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4222             };
4223             define_one_arm_cp_reg(cpu, &rvbar);
4224         }
4225         define_arm_cp_regs(cpu, v8_idregs);
4226         define_arm_cp_regs(cpu, v8_cp_reginfo);
4227     }
4228     if (arm_feature(env, ARM_FEATURE_EL2)) {
4229         uint64_t vmpidr_def = mpidr_read_val(env);
4230         ARMCPRegInfo vpidr_regs[] = {
4231             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4232               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4233               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4234               .resetvalue = cpu->midr,
4235               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4236             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4237               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4238               .access = PL2_RW, .resetvalue = cpu->midr,
4239               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4240             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4241               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4242               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4243               .resetvalue = vmpidr_def,
4244               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4245             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4246               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4247               .access = PL2_RW,
4248               .resetvalue = vmpidr_def,
4249               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4250             REGINFO_SENTINEL
4251         };
4252         define_arm_cp_regs(cpu, vpidr_regs);
4253         define_arm_cp_regs(cpu, el2_cp_reginfo);
4254         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4255         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4256             ARMCPRegInfo rvbar = {
4257                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4258                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4259                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4260             };
4261             define_one_arm_cp_reg(cpu, &rvbar);
4262         }
4263     } else {
4264         /* If EL2 is missing but higher ELs are enabled, we need to
4265          * register the no_el2 reginfos.
4266          */
4267         if (arm_feature(env, ARM_FEATURE_EL3)) {
4268             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4269              * of MIDR_EL1 and MPIDR_EL1.
4270              */
4271             ARMCPRegInfo vpidr_regs[] = {
4272                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4273                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4274                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4275                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4276                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4277                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4278                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4279                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4280                   .type = ARM_CP_NO_RAW,
4281                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4282                 REGINFO_SENTINEL
4283             };
4284             define_arm_cp_regs(cpu, vpidr_regs);
4285             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4286         }
4287     }
4288     if (arm_feature(env, ARM_FEATURE_EL3)) {
4289         define_arm_cp_regs(cpu, el3_cp_reginfo);
4290         ARMCPRegInfo rvbar = {
4291             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4292             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4293             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4294         };
4295         define_one_arm_cp_reg(cpu, &rvbar);
4296     }
4297     if (arm_feature(env, ARM_FEATURE_MPU)) {
4298         if (arm_feature(env, ARM_FEATURE_V6)) {
4299             /* PMSAv6 not implemented */
4300             assert(arm_feature(env, ARM_FEATURE_V7));
4301             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4302             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4303         } else {
4304             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4305         }
4306     } else {
4307         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4308         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4309     }
4310     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4311         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4312     }
4313     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4314         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4315     }
4316     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4317         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4318     }
4319     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4320         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4321     }
4322     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4323         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4324     }
4325     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4326         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4327     }
4328     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4329         define_arm_cp_regs(cpu, omap_cp_reginfo);
4330     }
4331     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4332         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4333     }
4334     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4335         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4336     }
4337     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4338         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4339     }
4340     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4341         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4342     }
4343     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4344      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4345      * be read-only (ie write causes UNDEF exception).
4346      */
4347     {
4348         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4349             /* Pre-v8 MIDR space.
4350              * Note that the MIDR isn't a simple constant register because
4351              * of the TI925 behaviour where writes to another register can
4352              * cause the MIDR value to change.
4353              *
4354              * Unimplemented registers in the c15 0 0 0 space default to
4355              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4356              * and friends override accordingly.
4357              */
4358             { .name = "MIDR",
4359               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4360               .access = PL1_R, .resetvalue = cpu->midr,
4361               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4362               .readfn = midr_read,
4363               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4364               .type = ARM_CP_OVERRIDE },
4365             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4366             { .name = "DUMMY",
4367               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4368               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4369             { .name = "DUMMY",
4370               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4371               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4372             { .name = "DUMMY",
4373               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4374               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4375             { .name = "DUMMY",
4376               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4377               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4378             { .name = "DUMMY",
4379               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4380               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4381             REGINFO_SENTINEL
4382         };
4383         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4384             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4385               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4386               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4387               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4388               .readfn = midr_read },
4389             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4390             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4391               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4392               .access = PL1_R, .resetvalue = cpu->midr },
4393             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4394               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4395               .access = PL1_R, .resetvalue = cpu->midr },
4396             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4397               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4398               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4399             REGINFO_SENTINEL
4400         };
4401         ARMCPRegInfo id_cp_reginfo[] = {
4402             /* These are common to v8 and pre-v8 */
4403             { .name = "CTR",
4404               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4405               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4406             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4407               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4408               .access = PL0_R, .accessfn = ctr_el0_access,
4409               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4410             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4411             { .name = "TCMTR",
4412               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4413               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4414             REGINFO_SENTINEL
4415         };
4416         /* TLBTR is specific to VMSA */
4417         ARMCPRegInfo id_tlbtr_reginfo = {
4418               .name = "TLBTR",
4419               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4420               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4421         };
4422         /* MPUIR is specific to PMSA V6+ */
4423         ARMCPRegInfo id_mpuir_reginfo = {
4424               .name = "MPUIR",
4425               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4426               .access = PL1_R, .type = ARM_CP_CONST,
4427               .resetvalue = cpu->pmsav7_dregion << 8
4428         };
4429         ARMCPRegInfo crn0_wi_reginfo = {
4430             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4431             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4432             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4433         };
4434         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4435             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4436             ARMCPRegInfo *r;
4437             /* Register the blanket "writes ignored" value first to cover the
4438              * whole space. Then update the specific ID registers to allow write
4439              * access, so that they ignore writes rather than causing them to
4440              * UNDEF.
4441              */
4442             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4443             for (r = id_pre_v8_midr_cp_reginfo;
4444                  r->type != ARM_CP_SENTINEL; r++) {
4445                 r->access = PL1_RW;
4446             }
4447             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4448                 r->access = PL1_RW;
4449             }
4450             id_tlbtr_reginfo.access = PL1_RW;
4451             id_tlbtr_reginfo.access = PL1_RW;
4452         }
4453         if (arm_feature(env, ARM_FEATURE_V8)) {
4454             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4455         } else {
4456             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4457         }
4458         define_arm_cp_regs(cpu, id_cp_reginfo);
4459         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4460             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4461         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4462             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4463         }
4464     }
4465
4466     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4467         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4468     }
4469
4470     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4471         ARMCPRegInfo auxcr_reginfo[] = {
4472             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4473               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4474               .access = PL1_RW, .type = ARM_CP_CONST,
4475               .resetvalue = cpu->reset_auxcr },
4476             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4477               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4478               .access = PL2_RW, .type = ARM_CP_CONST,
4479               .resetvalue = 0 },
4480             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4481               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4482               .access = PL3_RW, .type = ARM_CP_CONST,
4483               .resetvalue = 0 },
4484             REGINFO_SENTINEL
4485         };
4486         define_arm_cp_regs(cpu, auxcr_reginfo);
4487     }
4488
4489     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4490         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4491             /* 32 bit view is [31:18] 0...0 [43:32]. */
4492             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4493                 | extract64(cpu->reset_cbar, 32, 12);
4494             ARMCPRegInfo cbar_reginfo[] = {
4495                 { .name = "CBAR",
4496                   .type = ARM_CP_CONST,
4497                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4498                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4499                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4500                   .type = ARM_CP_CONST,
4501                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4502                   .access = PL1_R, .resetvalue = cbar32 },
4503                 REGINFO_SENTINEL
4504             };
4505             /* We don't implement a r/w 64 bit CBAR currently */
4506             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4507             define_arm_cp_regs(cpu, cbar_reginfo);
4508         } else {
4509             ARMCPRegInfo cbar = {
4510                 .name = "CBAR",
4511                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4512                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4513                 .fieldoffset = offsetof(CPUARMState,
4514                                         cp15.c15_config_base_address)
4515             };
4516             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4517                 cbar.access = PL1_R;
4518                 cbar.fieldoffset = 0;
4519                 cbar.type = ARM_CP_CONST;
4520             }
4521             define_one_arm_cp_reg(cpu, &cbar);
4522         }
4523     }
4524
4525     /* Generic registers whose values depend on the implementation */
4526     {
4527         ARMCPRegInfo sctlr = {
4528             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4529             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4530             .access = PL1_RW,
4531             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4532                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4533             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4534             .raw_writefn = raw_write,
4535         };
4536         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4537             /* Normally we would always end the TB on an SCTLR write, but Linux
4538              * arch/arm/mach-pxa/sleep.S expects two instructions following
4539              * an MMU enable to execute from cache.  Imitate this behaviour.
4540              */
4541             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4542         }
4543         define_one_arm_cp_reg(cpu, &sctlr);
4544     }
4545 }
4546
4547 ARMCPU *cpu_arm_init(const char *cpu_model)
4548 {
4549     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4550 }
4551
4552 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4553 {
4554     CPUState *cs = CPU(cpu);
4555     CPUARMState *env = &cpu->env;
4556
4557     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4558         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4559                                  aarch64_fpu_gdb_set_reg,
4560                                  34, "aarch64-fpu.xml", 0);
4561     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4562         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4563                                  51, "arm-neon.xml", 0);
4564     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4565         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4566                                  35, "arm-vfp3.xml", 0);
4567     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4568         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4569                                  19, "arm-vfp.xml", 0);
4570     }
4571 }
4572
4573 /* Sort alphabetically by type name, except for "any". */
4574 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4575 {
4576     ObjectClass *class_a = (ObjectClass *)a;
4577     ObjectClass *class_b = (ObjectClass *)b;
4578     const char *name_a, *name_b;
4579
4580     name_a = object_class_get_name(class_a);
4581     name_b = object_class_get_name(class_b);
4582     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4583         return 1;
4584     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4585         return -1;
4586     } else {
4587         return strcmp(name_a, name_b);
4588     }
4589 }
4590
4591 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4592 {
4593     ObjectClass *oc = data;
4594     CPUListState *s = user_data;
4595     const char *typename;
4596     char *name;
4597
4598     typename = object_class_get_name(oc);
4599     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4600     (*s->cpu_fprintf)(s->file, "  %s\n",
4601                       name);
4602     g_free(name);
4603 }
4604
4605 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4606 {
4607     CPUListState s = {
4608         .file = f,
4609         .cpu_fprintf = cpu_fprintf,
4610     };
4611     GSList *list;
4612
4613     list = object_class_get_list(TYPE_ARM_CPU, false);
4614     list = g_slist_sort(list, arm_cpu_list_compare);
4615     (*cpu_fprintf)(f, "Available CPUs:\n");
4616     g_slist_foreach(list, arm_cpu_list_entry, &s);
4617     g_slist_free(list);
4618 #ifdef CONFIG_KVM
4619     /* The 'host' CPU type is dynamically registered only if KVM is
4620      * enabled, so we have to special-case it here:
4621      */
4622     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
4623 #endif
4624 }
4625
4626 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
4627 {
4628     ObjectClass *oc = data;
4629     CpuDefinitionInfoList **cpu_list = user_data;
4630     CpuDefinitionInfoList *entry;
4631     CpuDefinitionInfo *info;
4632     const char *typename;
4633
4634     typename = object_class_get_name(oc);
4635     info = g_malloc0(sizeof(*info));
4636     info->name = g_strndup(typename,
4637                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
4638
4639     entry = g_malloc0(sizeof(*entry));
4640     entry->value = info;
4641     entry->next = *cpu_list;
4642     *cpu_list = entry;
4643 }
4644
4645 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
4646 {
4647     CpuDefinitionInfoList *cpu_list = NULL;
4648     GSList *list;
4649
4650     list = object_class_get_list(TYPE_ARM_CPU, false);
4651     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
4652     g_slist_free(list);
4653
4654     return cpu_list;
4655 }
4656
4657 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
4658                                    void *opaque, int state, int secstate,
4659                                    int crm, int opc1, int opc2)
4660 {
4661     /* Private utility function for define_one_arm_cp_reg_with_opaque():
4662      * add a single reginfo struct to the hash table.
4663      */
4664     uint32_t *key = g_new(uint32_t, 1);
4665     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
4666     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
4667     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
4668
4669     /* Reset the secure state to the specific incoming state.  This is
4670      * necessary as the register may have been defined with both states.
4671      */
4672     r2->secure = secstate;
4673
4674     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4675         /* Register is banked (using both entries in array).
4676          * Overwriting fieldoffset as the array is only used to define
4677          * banked registers but later only fieldoffset is used.
4678          */
4679         r2->fieldoffset = r->bank_fieldoffsets[ns];
4680     }
4681
4682     if (state == ARM_CP_STATE_AA32) {
4683         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
4684             /* If the register is banked then we don't need to migrate or
4685              * reset the 32-bit instance in certain cases:
4686              *
4687              * 1) If the register has both 32-bit and 64-bit instances then we
4688              *    can count on the 64-bit instance taking care of the
4689              *    non-secure bank.
4690              * 2) If ARMv8 is enabled then we can count on a 64-bit version
4691              *    taking care of the secure bank.  This requires that separate
4692              *    32 and 64-bit definitions are provided.
4693              */
4694             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
4695                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
4696                 r2->type |= ARM_CP_ALIAS;
4697             }
4698         } else if ((secstate != r->secure) && !ns) {
4699             /* The register is not banked so we only want to allow migration of
4700              * the non-secure instance.
4701              */
4702             r2->type |= ARM_CP_ALIAS;
4703         }
4704
4705         if (r->state == ARM_CP_STATE_BOTH) {
4706             /* We assume it is a cp15 register if the .cp field is left unset.
4707              */
4708             if (r2->cp == 0) {
4709                 r2->cp = 15;
4710             }
4711
4712 #ifdef HOST_WORDS_BIGENDIAN
4713             if (r2->fieldoffset) {
4714                 r2->fieldoffset += sizeof(uint32_t);
4715             }
4716 #endif
4717         }
4718     }
4719     if (state == ARM_CP_STATE_AA64) {
4720         /* To allow abbreviation of ARMCPRegInfo
4721          * definitions, we treat cp == 0 as equivalent to
4722          * the value for "standard guest-visible sysreg".
4723          * STATE_BOTH definitions are also always "standard
4724          * sysreg" in their AArch64 view (the .cp value may
4725          * be non-zero for the benefit of the AArch32 view).
4726          */
4727         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
4728             r2->cp = CP_REG_ARM64_SYSREG_CP;
4729         }
4730         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
4731                                   r2->opc0, opc1, opc2);
4732     } else {
4733         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
4734     }
4735     if (opaque) {
4736         r2->opaque = opaque;
4737     }
4738     /* reginfo passed to helpers is correct for the actual access,
4739      * and is never ARM_CP_STATE_BOTH:
4740      */
4741     r2->state = state;
4742     /* Make sure reginfo passed to helpers for wildcarded regs
4743      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4744      */
4745     r2->crm = crm;
4746     r2->opc1 = opc1;
4747     r2->opc2 = opc2;
4748     /* By convention, for wildcarded registers only the first
4749      * entry is used for migration; the others are marked as
4750      * ALIAS so we don't try to transfer the register
4751      * multiple times. Special registers (ie NOP/WFI) are
4752      * never migratable and not even raw-accessible.
4753      */
4754     if ((r->type & ARM_CP_SPECIAL)) {
4755         r2->type |= ARM_CP_NO_RAW;
4756     }
4757     if (((r->crm == CP_ANY) && crm != 0) ||
4758         ((r->opc1 == CP_ANY) && opc1 != 0) ||
4759         ((r->opc2 == CP_ANY) && opc2 != 0)) {
4760         r2->type |= ARM_CP_ALIAS;
4761     }
4762
4763     /* Check that raw accesses are either forbidden or handled. Note that
4764      * we can't assert this earlier because the setup of fieldoffset for
4765      * banked registers has to be done first.
4766      */
4767     if (!(r2->type & ARM_CP_NO_RAW)) {
4768         assert(!raw_accessors_invalid(r2));
4769     }
4770
4771     /* Overriding of an existing definition must be explicitly
4772      * requested.
4773      */
4774     if (!(r->type & ARM_CP_OVERRIDE)) {
4775         ARMCPRegInfo *oldreg;
4776         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
4777         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
4778             fprintf(stderr, "Register redefined: cp=%d %d bit "
4779                     "crn=%d crm=%d opc1=%d opc2=%d, "
4780                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
4781                     r2->crn, r2->crm, r2->opc1, r2->opc2,
4782                     oldreg->name, r2->name);
4783             g_assert_not_reached();
4784         }
4785     }
4786     g_hash_table_insert(cpu->cp_regs, key, r2);
4787 }
4788
4789
4790 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
4791                                        const ARMCPRegInfo *r, void *opaque)
4792 {
4793     /* Define implementations of coprocessor registers.
4794      * We store these in a hashtable because typically
4795      * there are less than 150 registers in a space which
4796      * is 16*16*16*8*8 = 262144 in size.
4797      * Wildcarding is supported for the crm, opc1 and opc2 fields.
4798      * If a register is defined twice then the second definition is
4799      * used, so this can be used to define some generic registers and
4800      * then override them with implementation specific variations.
4801      * At least one of the original and the second definition should
4802      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4803      * against accidental use.
4804      *
4805      * The state field defines whether the register is to be
4806      * visible in the AArch32 or AArch64 execution state. If the
4807      * state is set to ARM_CP_STATE_BOTH then we synthesise a
4808      * reginfo structure for the AArch32 view, which sees the lower
4809      * 32 bits of the 64 bit register.
4810      *
4811      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4812      * be wildcarded. AArch64 registers are always considered to be 64
4813      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4814      * the register, if any.
4815      */
4816     int crm, opc1, opc2, state;
4817     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
4818     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
4819     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
4820     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
4821     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
4822     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
4823     /* 64 bit registers have only CRm and Opc1 fields */
4824     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
4825     /* op0 only exists in the AArch64 encodings */
4826     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
4827     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4828     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
4829     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4830      * encodes a minimum access level for the register. We roll this
4831      * runtime check into our general permission check code, so check
4832      * here that the reginfo's specified permissions are strict enough
4833      * to encompass the generic architectural permission check.
4834      */
4835     if (r->state != ARM_CP_STATE_AA32) {
4836         int mask = 0;
4837         switch (r->opc1) {
4838         case 0: case 1: case 2:
4839             /* min_EL EL1 */
4840             mask = PL1_RW;
4841             break;
4842         case 3:
4843             /* min_EL EL0 */
4844             mask = PL0_RW;
4845             break;
4846         case 4:
4847             /* min_EL EL2 */
4848             mask = PL2_RW;
4849             break;
4850         case 5:
4851             /* unallocated encoding, so not possible */
4852             assert(false);
4853             break;
4854         case 6:
4855             /* min_EL EL3 */
4856             mask = PL3_RW;
4857             break;
4858         case 7:
4859             /* min_EL EL1, secure mode only (we don't check the latter) */
4860             mask = PL1_RW;
4861             break;
4862         default:
4863             /* broken reginfo with out-of-range opc1 */
4864             assert(false);
4865             break;
4866         }
4867         /* assert our permissions are not too lax (stricter is fine) */
4868         assert((r->access & ~mask) == 0);
4869     }
4870
4871     /* Check that the register definition has enough info to handle
4872      * reads and writes if they are permitted.
4873      */
4874     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
4875         if (r->access & PL3_R) {
4876             assert((r->fieldoffset ||
4877                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4878                    r->readfn);
4879         }
4880         if (r->access & PL3_W) {
4881             assert((r->fieldoffset ||
4882                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
4883                    r->writefn);
4884         }
4885     }
4886     /* Bad type field probably means missing sentinel at end of reg list */
4887     assert(cptype_valid(r->type));
4888     for (crm = crmmin; crm <= crmmax; crm++) {
4889         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
4890             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
4891                 for (state = ARM_CP_STATE_AA32;
4892                      state <= ARM_CP_STATE_AA64; state++) {
4893                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
4894                         continue;
4895                     }
4896                     if (state == ARM_CP_STATE_AA32) {
4897                         /* Under AArch32 CP registers can be common
4898                          * (same for secure and non-secure world) or banked.
4899                          */
4900                         switch (r->secure) {
4901                         case ARM_CP_SECSTATE_S:
4902                         case ARM_CP_SECSTATE_NS:
4903                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4904                                                    r->secure, crm, opc1, opc2);
4905                             break;
4906                         default:
4907                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4908                                                    ARM_CP_SECSTATE_S,
4909                                                    crm, opc1, opc2);
4910                             add_cpreg_to_hashtable(cpu, r, opaque, state,
4911                                                    ARM_CP_SECSTATE_NS,
4912                                                    crm, opc1, opc2);
4913                             break;
4914                         }
4915                     } else {
4916                         /* AArch64 registers get mapped to non-secure instance
4917                          * of AArch32 */
4918                         add_cpreg_to_hashtable(cpu, r, opaque, state,
4919                                                ARM_CP_SECSTATE_NS,
4920                                                crm, opc1, opc2);
4921                     }
4922                 }
4923             }
4924         }
4925     }
4926 }
4927
4928 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
4929                                     const ARMCPRegInfo *regs, void *opaque)
4930 {
4931     /* Define a whole list of registers */
4932     const ARMCPRegInfo *r;
4933     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
4934         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
4935     }
4936 }
4937
4938 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4939 {
4940     return g_hash_table_lookup(cpregs, &encoded_cp);
4941 }
4942
4943 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
4944                          uint64_t value)
4945 {
4946     /* Helper coprocessor write function for write-ignore registers */
4947 }
4948
4949 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
4950 {
4951     /* Helper coprocessor write function for read-as-zero registers */
4952     return 0;
4953 }
4954
4955 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
4956 {
4957     /* Helper coprocessor reset function for do-nothing-on-reset registers */
4958 }
4959
4960 static int bad_mode_switch(CPUARMState *env, int mode)
4961 {
4962     /* Return true if it is not valid for us to switch to
4963      * this CPU mode (ie all the UNPREDICTABLE cases in
4964      * the ARM ARM CPSRWriteByInstr pseudocode).
4965      */
4966     switch (mode) {
4967     case ARM_CPU_MODE_USR:
4968     case ARM_CPU_MODE_SYS:
4969     case ARM_CPU_MODE_SVC:
4970     case ARM_CPU_MODE_ABT:
4971     case ARM_CPU_MODE_UND:
4972     case ARM_CPU_MODE_IRQ:
4973     case ARM_CPU_MODE_FIQ:
4974         return 0;
4975     case ARM_CPU_MODE_MON:
4976         return !arm_is_secure(env);
4977     default:
4978         return 1;
4979     }
4980 }
4981
4982 uint32_t cpsr_read(CPUARMState *env)
4983 {
4984     int ZF;
4985     ZF = (env->ZF == 0);
4986     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
4987         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
4988         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
4989         | ((env->condexec_bits & 0xfc) << 8)
4990         | (env->GE << 16) | (env->daif & CPSR_AIF);
4991 }
4992
4993 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
4994 {
4995     uint32_t changed_daif;
4996
4997     if (mask & CPSR_NZCV) {
4998         env->ZF = (~val) & CPSR_Z;
4999         env->NF = val;
5000         env->CF = (val >> 29) & 1;
5001         env->VF = (val << 3) & 0x80000000;
5002     }
5003     if (mask & CPSR_Q)
5004         env->QF = ((val & CPSR_Q) != 0);
5005     if (mask & CPSR_T)
5006         env->thumb = ((val & CPSR_T) != 0);
5007     if (mask & CPSR_IT_0_1) {
5008         env->condexec_bits &= ~3;
5009         env->condexec_bits |= (val >> 25) & 3;
5010     }
5011     if (mask & CPSR_IT_2_7) {
5012         env->condexec_bits &= 3;
5013         env->condexec_bits |= (val >> 8) & 0xfc;
5014     }
5015     if (mask & CPSR_GE) {
5016         env->GE = (val >> 16) & 0xf;
5017     }
5018
5019     /* In a V7 implementation that includes the security extensions but does
5020      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5021      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5022      * bits respectively.
5023      *
5024      * In a V8 implementation, it is permitted for privileged software to
5025      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5026      */
5027     if (!arm_feature(env, ARM_FEATURE_V8) &&
5028         arm_feature(env, ARM_FEATURE_EL3) &&
5029         !arm_feature(env, ARM_FEATURE_EL2) &&
5030         !arm_is_secure(env)) {
5031
5032         changed_daif = (env->daif ^ val) & mask;
5033
5034         if (changed_daif & CPSR_A) {
5035             /* Check to see if we are allowed to change the masking of async
5036              * abort exceptions from a non-secure state.
5037              */
5038             if (!(env->cp15.scr_el3 & SCR_AW)) {
5039                 qemu_log_mask(LOG_GUEST_ERROR,
5040                               "Ignoring attempt to switch CPSR_A flag from "
5041                               "non-secure world with SCR.AW bit clear\n");
5042                 mask &= ~CPSR_A;
5043             }
5044         }
5045
5046         if (changed_daif & CPSR_F) {
5047             /* Check to see if we are allowed to change the masking of FIQ
5048              * exceptions from a non-secure state.
5049              */
5050             if (!(env->cp15.scr_el3 & SCR_FW)) {
5051                 qemu_log_mask(LOG_GUEST_ERROR,
5052                               "Ignoring attempt to switch CPSR_F flag from "
5053                               "non-secure world with SCR.FW bit clear\n");
5054                 mask &= ~CPSR_F;
5055             }
5056
5057             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5058              * If this bit is set software is not allowed to mask
5059              * FIQs, but is allowed to set CPSR_F to 0.
5060              */
5061             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5062                 (val & CPSR_F)) {
5063                 qemu_log_mask(LOG_GUEST_ERROR,
5064                               "Ignoring attempt to enable CPSR_F flag "
5065                               "(non-maskable FIQ [NMFI] support enabled)\n");
5066                 mask &= ~CPSR_F;
5067             }
5068         }
5069     }
5070
5071     env->daif &= ~(CPSR_AIF & mask);
5072     env->daif |= val & CPSR_AIF & mask;
5073
5074     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
5075         if (bad_mode_switch(env, val & CPSR_M)) {
5076             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
5077              * We choose to ignore the attempt and leave the CPSR M field
5078              * untouched.
5079              */
5080             mask &= ~CPSR_M;
5081         } else {
5082             switch_mode(env, val & CPSR_M);
5083         }
5084     }
5085     mask &= ~CACHED_CPSR_BITS;
5086     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5087 }
5088
5089 /* Sign/zero extend */
5090 uint32_t HELPER(sxtb16)(uint32_t x)
5091 {
5092     uint32_t res;
5093     res = (uint16_t)(int8_t)x;
5094     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5095     return res;
5096 }
5097
5098 uint32_t HELPER(uxtb16)(uint32_t x)
5099 {
5100     uint32_t res;
5101     res = (uint16_t)(uint8_t)x;
5102     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5103     return res;
5104 }
5105
5106 uint32_t HELPER(clz)(uint32_t x)
5107 {
5108     return clz32(x);
5109 }
5110
5111 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5112 {
5113     if (den == 0)
5114       return 0;
5115     if (num == INT_MIN && den == -1)
5116       return INT_MIN;
5117     return num / den;
5118 }
5119
5120 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5121 {
5122     if (den == 0)
5123       return 0;
5124     return num / den;
5125 }
5126
5127 uint32_t HELPER(rbit)(uint32_t x)
5128 {
5129     return revbit32(x);
5130 }
5131
5132 #if defined(CONFIG_USER_ONLY)
5133
5134 /* These should probably raise undefined insn exceptions.  */
5135 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5136 {
5137     ARMCPU *cpu = arm_env_get_cpu(env);
5138
5139     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5140 }
5141
5142 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5143 {
5144     ARMCPU *cpu = arm_env_get_cpu(env);
5145
5146     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5147     return 0;
5148 }
5149
5150 void switch_mode(CPUARMState *env, int mode)
5151 {
5152     ARMCPU *cpu = arm_env_get_cpu(env);
5153
5154     if (mode != ARM_CPU_MODE_USR) {
5155         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5156     }
5157 }
5158
5159 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5160 {
5161     ARMCPU *cpu = arm_env_get_cpu(env);
5162
5163     cpu_abort(CPU(cpu), "banked r13 write\n");
5164 }
5165
5166 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5167 {
5168     ARMCPU *cpu = arm_env_get_cpu(env);
5169
5170     cpu_abort(CPU(cpu), "banked r13 read\n");
5171     return 0;
5172 }
5173
5174 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5175                                  uint32_t cur_el, bool secure)
5176 {
5177     return 1;
5178 }
5179
5180 void aarch64_sync_64_to_32(CPUARMState *env)
5181 {
5182     g_assert_not_reached();
5183 }
5184
5185 #else
5186
5187 /* Map CPU modes onto saved register banks.  */
5188 int bank_number(int mode)
5189 {
5190     switch (mode) {
5191     case ARM_CPU_MODE_USR:
5192     case ARM_CPU_MODE_SYS:
5193         return BANK_USRSYS;
5194     case ARM_CPU_MODE_SVC:
5195         return BANK_SVC;
5196     case ARM_CPU_MODE_ABT:
5197         return BANK_ABT;
5198     case ARM_CPU_MODE_UND:
5199         return BANK_UND;
5200     case ARM_CPU_MODE_IRQ:
5201         return BANK_IRQ;
5202     case ARM_CPU_MODE_FIQ:
5203         return BANK_FIQ;
5204     case ARM_CPU_MODE_HYP:
5205         return BANK_HYP;
5206     case ARM_CPU_MODE_MON:
5207         return BANK_MON;
5208     }
5209     g_assert_not_reached();
5210 }
5211
5212 void switch_mode(CPUARMState *env, int mode)
5213 {
5214     int old_mode;
5215     int i;
5216
5217     old_mode = env->uncached_cpsr & CPSR_M;
5218     if (mode == old_mode)
5219         return;
5220
5221     if (old_mode == ARM_CPU_MODE_FIQ) {
5222         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5223         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5224     } else if (mode == ARM_CPU_MODE_FIQ) {
5225         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5226         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5227     }
5228
5229     i = bank_number(old_mode);
5230     env->banked_r13[i] = env->regs[13];
5231     env->banked_r14[i] = env->regs[14];
5232     env->banked_spsr[i] = env->spsr;
5233
5234     i = bank_number(mode);
5235     env->regs[13] = env->banked_r13[i];
5236     env->regs[14] = env->banked_r14[i];
5237     env->spsr = env->banked_spsr[i];
5238 }
5239
5240 /* Physical Interrupt Target EL Lookup Table
5241  *
5242  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5243  *
5244  * The below multi-dimensional table is used for looking up the target
5245  * exception level given numerous condition criteria.  Specifically, the
5246  * target EL is based on SCR and HCR routing controls as well as the
5247  * currently executing EL and secure state.
5248  *
5249  *    Dimensions:
5250  *    target_el_table[2][2][2][2][2][4]
5251  *                    |  |  |  |  |  +--- Current EL
5252  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5253  *                    |  |  |  +--------- HCR mask override
5254  *                    |  |  +------------ SCR exec state control
5255  *                    |  +--------------- SCR mask override
5256  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5257  *
5258  *    The table values are as such:
5259  *    0-3 = EL0-EL3
5260  *     -1 = Cannot occur
5261  *
5262  * The ARM ARM target EL table includes entries indicating that an "exception
5263  * is not taken".  The two cases where this is applicable are:
5264  *    1) An exception is taken from EL3 but the SCR does not have the exception
5265  *    routed to EL3.
5266  *    2) An exception is taken from EL2 but the HCR does not have the exception
5267  *    routed to EL2.
5268  * In these two cases, the below table contain a target of EL1.  This value is
5269  * returned as it is expected that the consumer of the table data will check
5270  * for "target EL >= current EL" to ensure the exception is not taken.
5271  *
5272  *            SCR     HCR
5273  *         64  EA     AMO                 From
5274  *        BIT IRQ     IMO      Non-secure         Secure
5275  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5276  */
5277 static const int8_t target_el_table[2][2][2][2][2][4] = {
5278     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5279        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5280       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5281        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5282      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5283        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5284       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5285        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5286     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5287        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5288       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5289        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5290      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5291        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5292       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5293        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5294 };
5295
5296 /*
5297  * Determine the target EL for physical exceptions
5298  */
5299 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5300                                  uint32_t cur_el, bool secure)
5301 {
5302     CPUARMState *env = cs->env_ptr;
5303     int rw;
5304     int scr;
5305     int hcr;
5306     int target_el;
5307     /* Is the highest EL AArch64? */
5308     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5309
5310     if (arm_feature(env, ARM_FEATURE_EL3)) {
5311         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5312     } else {
5313         /* Either EL2 is the highest EL (and so the EL2 register width
5314          * is given by is64); or there is no EL2 or EL3, in which case
5315          * the value of 'rw' does not affect the table lookup anyway.
5316          */
5317         rw = is64;
5318     }
5319
5320     switch (excp_idx) {
5321     case EXCP_IRQ:
5322         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5323         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5324         break;
5325     case EXCP_FIQ:
5326         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5327         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5328         break;
5329     default:
5330         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5331         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5332         break;
5333     };
5334
5335     /* If HCR.TGE is set then HCR is treated as being 1 */
5336     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5337
5338     /* Perform a table-lookup for the target EL given the current state */
5339     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5340
5341     assert(target_el > 0);
5342
5343     return target_el;
5344 }
5345
5346 static void v7m_push(CPUARMState *env, uint32_t val)
5347 {
5348     CPUState *cs = CPU(arm_env_get_cpu(env));
5349
5350     env->regs[13] -= 4;
5351     stl_phys(cs->as, env->regs[13], val);
5352 }
5353
5354 static uint32_t v7m_pop(CPUARMState *env)
5355 {
5356     CPUState *cs = CPU(arm_env_get_cpu(env));
5357     uint32_t val;
5358
5359     val = ldl_phys(cs->as, env->regs[13]);
5360     env->regs[13] += 4;
5361     return val;
5362 }
5363
5364 /* Switch to V7M main or process stack pointer.  */
5365 static void switch_v7m_sp(CPUARMState *env, int process)
5366 {
5367     uint32_t tmp;
5368     if (env->v7m.current_sp != process) {
5369         tmp = env->v7m.other_sp;
5370         env->v7m.other_sp = env->regs[13];
5371         env->regs[13] = tmp;
5372         env->v7m.current_sp = process;
5373     }
5374 }
5375
5376 static void do_v7m_exception_exit(CPUARMState *env)
5377 {
5378     uint32_t type;
5379     uint32_t xpsr;
5380
5381     type = env->regs[15];
5382     if (env->v7m.exception != 0)
5383         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5384
5385     /* Switch to the target stack.  */
5386     switch_v7m_sp(env, (type & 4) != 0);
5387     /* Pop registers.  */
5388     env->regs[0] = v7m_pop(env);
5389     env->regs[1] = v7m_pop(env);
5390     env->regs[2] = v7m_pop(env);
5391     env->regs[3] = v7m_pop(env);
5392     env->regs[12] = v7m_pop(env);
5393     env->regs[14] = v7m_pop(env);
5394     env->regs[15] = v7m_pop(env);
5395     if (env->regs[15] & 1) {
5396         qemu_log_mask(LOG_GUEST_ERROR,
5397                       "M profile return from interrupt with misaligned "
5398                       "PC is UNPREDICTABLE\n");
5399         /* Actual hardware seems to ignore the lsbit, and there are several
5400          * RTOSes out there which incorrectly assume the r15 in the stack
5401          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5402          */
5403         env->regs[15] &= ~1U;
5404     }
5405     xpsr = v7m_pop(env);
5406     xpsr_write(env, xpsr, 0xfffffdff);
5407     /* Undo stack alignment.  */
5408     if (xpsr & 0x200)
5409         env->regs[13] |= 4;
5410     /* ??? The exception return type specifies Thread/Handler mode.  However
5411        this is also implied by the xPSR value. Not sure what to do
5412        if there is a mismatch.  */
5413     /* ??? Likewise for mismatches between the CONTROL register and the stack
5414        pointer.  */
5415 }
5416
5417 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5418 {
5419     ARMCPU *cpu = ARM_CPU(cs);
5420     CPUARMState *env = &cpu->env;
5421     uint32_t xpsr = xpsr_read(env);
5422     uint32_t lr;
5423     uint32_t addr;
5424
5425     arm_log_exception(cs->exception_index);
5426
5427     lr = 0xfffffff1;
5428     if (env->v7m.current_sp)
5429         lr |= 4;
5430     if (env->v7m.exception == 0)
5431         lr |= 8;
5432
5433     /* For exceptions we just mark as pending on the NVIC, and let that
5434        handle it.  */
5435     /* TODO: Need to escalate if the current priority is higher than the
5436        one we're raising.  */
5437     switch (cs->exception_index) {
5438     case EXCP_UDEF:
5439         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5440         return;
5441     case EXCP_SWI:
5442         /* The PC already points to the next instruction.  */
5443         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5444         return;
5445     case EXCP_PREFETCH_ABORT:
5446     case EXCP_DATA_ABORT:
5447         /* TODO: if we implemented the MPU registers, this is where we
5448          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5449          */
5450         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5451         return;
5452     case EXCP_BKPT:
5453         if (semihosting_enabled()) {
5454             int nr;
5455             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5456             if (nr == 0xab) {
5457                 env->regs[15] += 2;
5458                 qemu_log_mask(CPU_LOG_INT,
5459                               "...handling as semihosting call 0x%x\n",
5460                               env->regs[0]);
5461                 env->regs[0] = do_arm_semihosting(env);
5462                 return;
5463             }
5464         }
5465         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5466         return;
5467     case EXCP_IRQ:
5468         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5469         break;
5470     case EXCP_EXCEPTION_EXIT:
5471         do_v7m_exception_exit(env);
5472         return;
5473     default:
5474         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5475         return; /* Never happens.  Keep compiler happy.  */
5476     }
5477
5478     /* Align stack pointer.  */
5479     /* ??? Should only do this if Configuration Control Register
5480        STACKALIGN bit is set.  */
5481     if (env->regs[13] & 4) {
5482         env->regs[13] -= 4;
5483         xpsr |= 0x200;
5484     }
5485     /* Switch to the handler mode.  */
5486     v7m_push(env, xpsr);
5487     v7m_push(env, env->regs[15]);
5488     v7m_push(env, env->regs[14]);
5489     v7m_push(env, env->regs[12]);
5490     v7m_push(env, env->regs[3]);
5491     v7m_push(env, env->regs[2]);
5492     v7m_push(env, env->regs[1]);
5493     v7m_push(env, env->regs[0]);
5494     switch_v7m_sp(env, 0);
5495     /* Clear IT bits */
5496     env->condexec_bits = 0;
5497     env->regs[14] = lr;
5498     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5499     env->regs[15] = addr & 0xfffffffe;
5500     env->thumb = addr & 1;
5501 }
5502
5503 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5504  * register set.  This is necessary when switching between AArch32 and AArch64
5505  * execution state.
5506  */
5507 void aarch64_sync_32_to_64(CPUARMState *env)
5508 {
5509     int i;
5510     uint32_t mode = env->uncached_cpsr & CPSR_M;
5511
5512     /* We can blanket copy R[0:7] to X[0:7] */
5513     for (i = 0; i < 8; i++) {
5514         env->xregs[i] = env->regs[i];
5515     }
5516
5517     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5518      * Otherwise, they come from the banked user regs.
5519      */
5520     if (mode == ARM_CPU_MODE_FIQ) {
5521         for (i = 8; i < 13; i++) {
5522             env->xregs[i] = env->usr_regs[i - 8];
5523         }
5524     } else {
5525         for (i = 8; i < 13; i++) {
5526             env->xregs[i] = env->regs[i];
5527         }
5528     }
5529
5530     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5531      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5532      * from the mode banked register.
5533      */
5534     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5535         env->xregs[13] = env->regs[13];
5536         env->xregs[14] = env->regs[14];
5537     } else {
5538         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5539         /* HYP is an exception in that it is copied from r14 */
5540         if (mode == ARM_CPU_MODE_HYP) {
5541             env->xregs[14] = env->regs[14];
5542         } else {
5543             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5544         }
5545     }
5546
5547     if (mode == ARM_CPU_MODE_HYP) {
5548         env->xregs[15] = env->regs[13];
5549     } else {
5550         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5551     }
5552
5553     if (mode == ARM_CPU_MODE_IRQ) {
5554         env->xregs[16] = env->regs[14];
5555         env->xregs[17] = env->regs[13];
5556     } else {
5557         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5558         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5559     }
5560
5561     if (mode == ARM_CPU_MODE_SVC) {
5562         env->xregs[18] = env->regs[14];
5563         env->xregs[19] = env->regs[13];
5564     } else {
5565         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5566         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5567     }
5568
5569     if (mode == ARM_CPU_MODE_ABT) {
5570         env->xregs[20] = env->regs[14];
5571         env->xregs[21] = env->regs[13];
5572     } else {
5573         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5574         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5575     }
5576
5577     if (mode == ARM_CPU_MODE_UND) {
5578         env->xregs[22] = env->regs[14];
5579         env->xregs[23] = env->regs[13];
5580     } else {
5581         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5582         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5583     }
5584
5585     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5586      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5587      * FIQ bank for r8-r14.
5588      */
5589     if (mode == ARM_CPU_MODE_FIQ) {
5590         for (i = 24; i < 31; i++) {
5591             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5592         }
5593     } else {
5594         for (i = 24; i < 29; i++) {
5595             env->xregs[i] = env->fiq_regs[i - 24];
5596         }
5597         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5598         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5599     }
5600
5601     env->pc = env->regs[15];
5602 }
5603
5604 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5605  * register set.  This is necessary when switching between AArch32 and AArch64
5606  * execution state.
5607  */
5608 void aarch64_sync_64_to_32(CPUARMState *env)
5609 {
5610     int i;
5611     uint32_t mode = env->uncached_cpsr & CPSR_M;
5612
5613     /* We can blanket copy X[0:7] to R[0:7] */
5614     for (i = 0; i < 8; i++) {
5615         env->regs[i] = env->xregs[i];
5616     }
5617
5618     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5619      * Otherwise, we copy x8-x12 into the banked user regs.
5620      */
5621     if (mode == ARM_CPU_MODE_FIQ) {
5622         for (i = 8; i < 13; i++) {
5623             env->usr_regs[i - 8] = env->xregs[i];
5624         }
5625     } else {
5626         for (i = 8; i < 13; i++) {
5627             env->regs[i] = env->xregs[i];
5628         }
5629     }
5630
5631     /* Registers r13 & r14 depend on the current mode.
5632      * If we are in a given mode, we copy the corresponding x registers to r13
5633      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
5634      * for the mode.
5635      */
5636     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5637         env->regs[13] = env->xregs[13];
5638         env->regs[14] = env->xregs[14];
5639     } else {
5640         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
5641
5642         /* HYP is an exception in that it does not have its own banked r14 but
5643          * shares the USR r14
5644          */
5645         if (mode == ARM_CPU_MODE_HYP) {
5646             env->regs[14] = env->xregs[14];
5647         } else {
5648             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
5649         }
5650     }
5651
5652     if (mode == ARM_CPU_MODE_HYP) {
5653         env->regs[13] = env->xregs[15];
5654     } else {
5655         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
5656     }
5657
5658     if (mode == ARM_CPU_MODE_IRQ) {
5659         env->regs[14] = env->xregs[16];
5660         env->regs[13] = env->xregs[17];
5661     } else {
5662         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
5663         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
5664     }
5665
5666     if (mode == ARM_CPU_MODE_SVC) {
5667         env->regs[14] = env->xregs[18];
5668         env->regs[13] = env->xregs[19];
5669     } else {
5670         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
5671         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
5672     }
5673
5674     if (mode == ARM_CPU_MODE_ABT) {
5675         env->regs[14] = env->xregs[20];
5676         env->regs[13] = env->xregs[21];
5677     } else {
5678         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
5679         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
5680     }
5681
5682     if (mode == ARM_CPU_MODE_UND) {
5683         env->regs[14] = env->xregs[22];
5684         env->regs[13] = env->xregs[23];
5685     } else {
5686         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
5687         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
5688     }
5689
5690     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5691      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
5692      * FIQ bank for r8-r14.
5693      */
5694     if (mode == ARM_CPU_MODE_FIQ) {
5695         for (i = 24; i < 31; i++) {
5696             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
5697         }
5698     } else {
5699         for (i = 24; i < 29; i++) {
5700             env->fiq_regs[i - 24] = env->xregs[i];
5701         }
5702         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
5703         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
5704     }
5705
5706     env->regs[15] = env->pc;
5707 }
5708
5709 /* Handle a CPU exception.  */
5710 void arm_cpu_do_interrupt(CPUState *cs)
5711 {
5712     ARMCPU *cpu = ARM_CPU(cs);
5713     CPUARMState *env = &cpu->env;
5714     uint32_t addr;
5715     uint32_t mask;
5716     int new_mode;
5717     uint32_t offset;
5718     uint32_t moe;
5719
5720     assert(!IS_M(env));
5721
5722     arm_log_exception(cs->exception_index);
5723
5724     if (arm_is_psci_call(cpu, cs->exception_index)) {
5725         arm_handle_psci_call(cpu);
5726         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
5727         return;
5728     }
5729
5730     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5731     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
5732     case EC_BREAKPOINT:
5733     case EC_BREAKPOINT_SAME_EL:
5734         moe = 1;
5735         break;
5736     case EC_WATCHPOINT:
5737     case EC_WATCHPOINT_SAME_EL:
5738         moe = 10;
5739         break;
5740     case EC_AA32_BKPT:
5741         moe = 3;
5742         break;
5743     case EC_VECTORCATCH:
5744         moe = 5;
5745         break;
5746     default:
5747         moe = 0;
5748         break;
5749     }
5750
5751     if (moe) {
5752         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
5753     }
5754
5755     /* TODO: Vectored interrupt controller.  */
5756     switch (cs->exception_index) {
5757     case EXCP_UDEF:
5758         new_mode = ARM_CPU_MODE_UND;
5759         addr = 0x04;
5760         mask = CPSR_I;
5761         if (env->thumb)
5762             offset = 2;
5763         else
5764             offset = 4;
5765         break;
5766     case EXCP_SWI:
5767         if (semihosting_enabled()) {
5768             /* Check for semihosting interrupt.  */
5769             if (env->thumb) {
5770                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
5771                     & 0xff;
5772             } else {
5773                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
5774                     & 0xffffff;
5775             }
5776             /* Only intercept calls from privileged modes, to provide some
5777                semblance of security.  */
5778             if (((mask == 0x123456 && !env->thumb)
5779                     || (mask == 0xab && env->thumb))
5780                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5781                 qemu_log_mask(CPU_LOG_INT,
5782                               "...handling as semihosting call 0x%x\n",
5783                               env->regs[0]);
5784                 env->regs[0] = do_arm_semihosting(env);
5785                 return;
5786             }
5787         }
5788         new_mode = ARM_CPU_MODE_SVC;
5789         addr = 0x08;
5790         mask = CPSR_I;
5791         /* The PC already points to the next instruction.  */
5792         offset = 0;
5793         break;
5794     case EXCP_BKPT:
5795         /* See if this is a semihosting syscall.  */
5796         if (env->thumb && semihosting_enabled()) {
5797             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5798             if (mask == 0xab
5799                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
5800                 env->regs[15] += 2;
5801                 qemu_log_mask(CPU_LOG_INT,
5802                               "...handling as semihosting call 0x%x\n",
5803                               env->regs[0]);
5804                 env->regs[0] = do_arm_semihosting(env);
5805                 return;
5806             }
5807         }
5808         env->exception.fsr = 2;
5809         /* Fall through to prefetch abort.  */
5810     case EXCP_PREFETCH_ABORT:
5811         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
5812         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
5813         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
5814                       env->exception.fsr, (uint32_t)env->exception.vaddress);
5815         new_mode = ARM_CPU_MODE_ABT;
5816         addr = 0x0c;
5817         mask = CPSR_A | CPSR_I;
5818         offset = 4;
5819         break;
5820     case EXCP_DATA_ABORT:
5821         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
5822         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
5823         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
5824                       env->exception.fsr,
5825                       (uint32_t)env->exception.vaddress);
5826         new_mode = ARM_CPU_MODE_ABT;
5827         addr = 0x10;
5828         mask = CPSR_A | CPSR_I;
5829         offset = 8;
5830         break;
5831     case EXCP_IRQ:
5832         new_mode = ARM_CPU_MODE_IRQ;
5833         addr = 0x18;
5834         /* Disable IRQ and imprecise data aborts.  */
5835         mask = CPSR_A | CPSR_I;
5836         offset = 4;
5837         if (env->cp15.scr_el3 & SCR_IRQ) {
5838             /* IRQ routed to monitor mode */
5839             new_mode = ARM_CPU_MODE_MON;
5840             mask |= CPSR_F;
5841         }
5842         break;
5843     case EXCP_FIQ:
5844         new_mode = ARM_CPU_MODE_FIQ;
5845         addr = 0x1c;
5846         /* Disable FIQ, IRQ and imprecise data aborts.  */
5847         mask = CPSR_A | CPSR_I | CPSR_F;
5848         if (env->cp15.scr_el3 & SCR_FIQ) {
5849             /* FIQ routed to monitor mode */
5850             new_mode = ARM_CPU_MODE_MON;
5851         }
5852         offset = 4;
5853         break;
5854     case EXCP_SMC:
5855         new_mode = ARM_CPU_MODE_MON;
5856         addr = 0x08;
5857         mask = CPSR_A | CPSR_I | CPSR_F;
5858         offset = 0;
5859         break;
5860     default:
5861         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5862         return; /* Never happens.  Keep compiler happy.  */
5863     }
5864
5865     if (new_mode == ARM_CPU_MODE_MON) {
5866         addr += env->cp15.mvbar;
5867     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
5868         /* High vectors. When enabled, base address cannot be remapped. */
5869         addr += 0xffff0000;
5870     } else {
5871         /* ARM v7 architectures provide a vector base address register to remap
5872          * the interrupt vector table.
5873          * This register is only followed in non-monitor mode, and is banked.
5874          * Note: only bits 31:5 are valid.
5875          */
5876         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
5877     }
5878
5879     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
5880         env->cp15.scr_el3 &= ~SCR_NS;
5881     }
5882
5883     switch_mode (env, new_mode);
5884     /* For exceptions taken to AArch32 we must clear the SS bit in both
5885      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5886      */
5887     env->uncached_cpsr &= ~PSTATE_SS;
5888     env->spsr = cpsr_read(env);
5889     /* Clear IT bits.  */
5890     env->condexec_bits = 0;
5891     /* Switch to the new mode, and to the correct instruction set.  */
5892     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
5893     env->daif |= mask;
5894     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5895      * and we should just guard the thumb mode on V4 */
5896     if (arm_feature(env, ARM_FEATURE_V4T)) {
5897         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
5898     }
5899     env->regs[14] = env->regs[15] + offset;
5900     env->regs[15] = addr;
5901     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
5902 }
5903
5904
5905 /* Return the exception level which controls this address translation regime */
5906 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
5907 {
5908     switch (mmu_idx) {
5909     case ARMMMUIdx_S2NS:
5910     case ARMMMUIdx_S1E2:
5911         return 2;
5912     case ARMMMUIdx_S1E3:
5913         return 3;
5914     case ARMMMUIdx_S1SE0:
5915         return arm_el_is_aa64(env, 3) ? 1 : 3;
5916     case ARMMMUIdx_S1SE1:
5917     case ARMMMUIdx_S1NSE0:
5918     case ARMMMUIdx_S1NSE1:
5919         return 1;
5920     default:
5921         g_assert_not_reached();
5922     }
5923 }
5924
5925 /* Return true if this address translation regime is secure */
5926 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
5927 {
5928     switch (mmu_idx) {
5929     case ARMMMUIdx_S12NSE0:
5930     case ARMMMUIdx_S12NSE1:
5931     case ARMMMUIdx_S1NSE0:
5932     case ARMMMUIdx_S1NSE1:
5933     case ARMMMUIdx_S1E2:
5934     case ARMMMUIdx_S2NS:
5935         return false;
5936     case ARMMMUIdx_S1E3:
5937     case ARMMMUIdx_S1SE0:
5938     case ARMMMUIdx_S1SE1:
5939         return true;
5940     default:
5941         g_assert_not_reached();
5942     }
5943 }
5944
5945 /* Return the SCTLR value which controls this address translation regime */
5946 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
5947 {
5948     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
5949 }
5950
5951 /* Return true if the specified stage of address translation is disabled */
5952 static inline bool regime_translation_disabled(CPUARMState *env,
5953                                                ARMMMUIdx mmu_idx)
5954 {
5955     if (mmu_idx == ARMMMUIdx_S2NS) {
5956         return (env->cp15.hcr_el2 & HCR_VM) == 0;
5957     }
5958     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
5959 }
5960
5961 /* Return the TCR controlling this translation regime */
5962 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
5963 {
5964     if (mmu_idx == ARMMMUIdx_S2NS) {
5965         return &env->cp15.vtcr_el2;
5966     }
5967     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
5968 }
5969
5970 /* Return the TTBR associated with this translation regime */
5971 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
5972                                    int ttbrn)
5973 {
5974     if (mmu_idx == ARMMMUIdx_S2NS) {
5975         return env->cp15.vttbr_el2;
5976     }
5977     if (ttbrn == 0) {
5978         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
5979     } else {
5980         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
5981     }
5982 }
5983
5984 /* Return true if the translation regime is using LPAE format page tables */
5985 static inline bool regime_using_lpae_format(CPUARMState *env,
5986                                             ARMMMUIdx mmu_idx)
5987 {
5988     int el = regime_el(env, mmu_idx);
5989     if (el == 2 || arm_el_is_aa64(env, el)) {
5990         return true;
5991     }
5992     if (arm_feature(env, ARM_FEATURE_LPAE)
5993         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
5994         return true;
5995     }
5996     return false;
5997 }
5998
5999 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6000 {
6001     switch (mmu_idx) {
6002     case ARMMMUIdx_S1SE0:
6003     case ARMMMUIdx_S1NSE0:
6004         return true;
6005     default:
6006         return false;
6007     case ARMMMUIdx_S12NSE0:
6008     case ARMMMUIdx_S12NSE1:
6009         g_assert_not_reached();
6010     }
6011 }
6012
6013 /* Translate section/page access permissions to page
6014  * R/W protection flags
6015  *
6016  * @env:         CPUARMState
6017  * @mmu_idx:     MMU index indicating required translation regime
6018  * @ap:          The 3-bit access permissions (AP[2:0])
6019  * @domain_prot: The 2-bit domain access permissions
6020  */
6021 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6022                                 int ap, int domain_prot)
6023 {
6024     bool is_user = regime_is_user(env, mmu_idx);
6025
6026     if (domain_prot == 3) {
6027         return PAGE_READ | PAGE_WRITE;
6028     }
6029
6030     switch (ap) {
6031     case 0:
6032         if (arm_feature(env, ARM_FEATURE_V7)) {
6033             return 0;
6034         }
6035         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6036         case SCTLR_S:
6037             return is_user ? 0 : PAGE_READ;
6038         case SCTLR_R:
6039             return PAGE_READ;
6040         default:
6041             return 0;
6042         }
6043     case 1:
6044         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6045     case 2:
6046         if (is_user) {
6047             return PAGE_READ;
6048         } else {
6049             return PAGE_READ | PAGE_WRITE;
6050         }
6051     case 3:
6052         return PAGE_READ | PAGE_WRITE;
6053     case 4: /* Reserved.  */
6054         return 0;
6055     case 5:
6056         return is_user ? 0 : PAGE_READ;
6057     case 6:
6058         return PAGE_READ;
6059     case 7:
6060         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6061             return 0;
6062         }
6063         return PAGE_READ;
6064     default:
6065         g_assert_not_reached();
6066     }
6067 }
6068
6069 /* Translate section/page access permissions to page
6070  * R/W protection flags.
6071  *
6072  * @ap:      The 2-bit simple AP (AP[2:1])
6073  * @is_user: TRUE if accessing from PL0
6074  */
6075 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6076 {
6077     switch (ap) {
6078     case 0:
6079         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6080     case 1:
6081         return PAGE_READ | PAGE_WRITE;
6082     case 2:
6083         return is_user ? 0 : PAGE_READ;
6084     case 3:
6085         return PAGE_READ;
6086     default:
6087         g_assert_not_reached();
6088     }
6089 }
6090
6091 static inline int
6092 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6093 {
6094     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6095 }
6096
6097 /* Translate S2 section/page access permissions to protection flags
6098  *
6099  * @env:     CPUARMState
6100  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6101  * @xn:      XN (execute-never) bit
6102  */
6103 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6104 {
6105     int prot = 0;
6106
6107     if (s2ap & 1) {
6108         prot |= PAGE_READ;
6109     }
6110     if (s2ap & 2) {
6111         prot |= PAGE_WRITE;
6112     }
6113     if (!xn) {
6114         prot |= PAGE_EXEC;
6115     }
6116     return prot;
6117 }
6118
6119 /* Translate section/page access permissions to protection flags
6120  *
6121  * @env:     CPUARMState
6122  * @mmu_idx: MMU index indicating required translation regime
6123  * @is_aa64: TRUE if AArch64
6124  * @ap:      The 2-bit simple AP (AP[2:1])
6125  * @ns:      NS (non-secure) bit
6126  * @xn:      XN (execute-never) bit
6127  * @pxn:     PXN (privileged execute-never) bit
6128  */
6129 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6130                       int ap, int ns, int xn, int pxn)
6131 {
6132     bool is_user = regime_is_user(env, mmu_idx);
6133     int prot_rw, user_rw;
6134     bool have_wxn;
6135     int wxn = 0;
6136
6137     assert(mmu_idx != ARMMMUIdx_S2NS);
6138
6139     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6140     if (is_user) {
6141         prot_rw = user_rw;
6142     } else {
6143         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6144     }
6145
6146     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6147         return prot_rw;
6148     }
6149
6150     /* TODO have_wxn should be replaced with
6151      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6152      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6153      * compatible processors have EL2, which is required for [U]WXN.
6154      */
6155     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6156
6157     if (have_wxn) {
6158         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6159     }
6160
6161     if (is_aa64) {
6162         switch (regime_el(env, mmu_idx)) {
6163         case 1:
6164             if (!is_user) {
6165                 xn = pxn || (user_rw & PAGE_WRITE);
6166             }
6167             break;
6168         case 2:
6169         case 3:
6170             break;
6171         }
6172     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6173         switch (regime_el(env, mmu_idx)) {
6174         case 1:
6175         case 3:
6176             if (is_user) {
6177                 xn = xn || !(user_rw & PAGE_READ);
6178             } else {
6179                 int uwxn = 0;
6180                 if (have_wxn) {
6181                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6182                 }
6183                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6184                      (uwxn && (user_rw & PAGE_WRITE));
6185             }
6186             break;
6187         case 2:
6188             break;
6189         }
6190     } else {
6191         xn = wxn = 0;
6192     }
6193
6194     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6195         return prot_rw;
6196     }
6197     return prot_rw | PAGE_EXEC;
6198 }
6199
6200 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6201                                      uint32_t *table, uint32_t address)
6202 {
6203     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6204     TCR *tcr = regime_tcr(env, mmu_idx);
6205
6206     if (address & tcr->mask) {
6207         if (tcr->raw_tcr & TTBCR_PD1) {
6208             /* Translation table walk disabled for TTBR1 */
6209             return false;
6210         }
6211         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6212     } else {
6213         if (tcr->raw_tcr & TTBCR_PD0) {
6214             /* Translation table walk disabled for TTBR0 */
6215             return false;
6216         }
6217         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6218     }
6219     *table |= (address >> 18) & 0x3ffc;
6220     return true;
6221 }
6222
6223 /* Translate a S1 pagetable walk through S2 if needed.  */
6224 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6225                                hwaddr addr, MemTxAttrs txattrs,
6226                                uint32_t *fsr,
6227                                ARMMMUFaultInfo *fi)
6228 {
6229     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6230         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6231         target_ulong s2size;
6232         hwaddr s2pa;
6233         int s2prot;
6234         int ret;
6235
6236         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6237                                  &txattrs, &s2prot, &s2size, fsr, fi);
6238         if (ret) {
6239             fi->s2addr = addr;
6240             fi->stage2 = true;
6241             fi->s1ptw = true;
6242             return ~0;
6243         }
6244         addr = s2pa;
6245     }
6246     return addr;
6247 }
6248
6249 /* All loads done in the course of a page table walk go through here.
6250  * TODO: rather than ignoring errors from physical memory reads (which
6251  * are external aborts in ARM terminology) we should propagate this
6252  * error out so that we can turn it into a Data Abort if this walk
6253  * was being done for a CPU load/store or an address translation instruction
6254  * (but not if it was for a debug access).
6255  */
6256 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6257                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6258                             ARMMMUFaultInfo *fi)
6259 {
6260     ARMCPU *cpu = ARM_CPU(cs);
6261     CPUARMState *env = &cpu->env;
6262     MemTxAttrs attrs = {};
6263
6264     attrs.secure = is_secure;
6265     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6266     if (fi->s1ptw) {
6267         return 0;
6268     }
6269     return address_space_ldl(cs->as, addr, attrs, NULL);
6270 }
6271
6272 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6273                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6274                             ARMMMUFaultInfo *fi)
6275 {
6276     ARMCPU *cpu = ARM_CPU(cs);
6277     CPUARMState *env = &cpu->env;
6278     MemTxAttrs attrs = {};
6279
6280     attrs.secure = is_secure;
6281     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6282     if (fi->s1ptw) {
6283         return 0;
6284     }
6285     return address_space_ldq(cs->as, addr, attrs, NULL);
6286 }
6287
6288 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6289                              int access_type, ARMMMUIdx mmu_idx,
6290                              hwaddr *phys_ptr, int *prot,
6291                              target_ulong *page_size, uint32_t *fsr,
6292                              ARMMMUFaultInfo *fi)
6293 {
6294     CPUState *cs = CPU(arm_env_get_cpu(env));
6295     int code;
6296     uint32_t table;
6297     uint32_t desc;
6298     int type;
6299     int ap;
6300     int domain = 0;
6301     int domain_prot;
6302     hwaddr phys_addr;
6303     uint32_t dacr;
6304
6305     /* Pagetable walk.  */
6306     /* Lookup l1 descriptor.  */
6307     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6308         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6309         code = 5;
6310         goto do_fault;
6311     }
6312     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6313                        mmu_idx, fsr, fi);
6314     type = (desc & 3);
6315     domain = (desc >> 5) & 0x0f;
6316     if (regime_el(env, mmu_idx) == 1) {
6317         dacr = env->cp15.dacr_ns;
6318     } else {
6319         dacr = env->cp15.dacr_s;
6320     }
6321     domain_prot = (dacr >> (domain * 2)) & 3;
6322     if (type == 0) {
6323         /* Section translation fault.  */
6324         code = 5;
6325         goto do_fault;
6326     }
6327     if (domain_prot == 0 || domain_prot == 2) {
6328         if (type == 2)
6329             code = 9; /* Section domain fault.  */
6330         else
6331             code = 11; /* Page domain fault.  */
6332         goto do_fault;
6333     }
6334     if (type == 2) {
6335         /* 1Mb section.  */
6336         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6337         ap = (desc >> 10) & 3;
6338         code = 13;
6339         *page_size = 1024 * 1024;
6340     } else {
6341         /* Lookup l2 entry.  */
6342         if (type == 1) {
6343             /* Coarse pagetable.  */
6344             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6345         } else {
6346             /* Fine pagetable.  */
6347             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6348         }
6349         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6350                            mmu_idx, fsr, fi);
6351         switch (desc & 3) {
6352         case 0: /* Page translation fault.  */
6353             code = 7;
6354             goto do_fault;
6355         case 1: /* 64k page.  */
6356             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6357             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6358             *page_size = 0x10000;
6359             break;
6360         case 2: /* 4k page.  */
6361             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6362             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6363             *page_size = 0x1000;
6364             break;
6365         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6366             if (type == 1) {
6367                 /* ARMv6/XScale extended small page format */
6368                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6369                     || arm_feature(env, ARM_FEATURE_V6)) {
6370                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6371                     *page_size = 0x1000;
6372                 } else {
6373                     /* UNPREDICTABLE in ARMv5; we choose to take a
6374                      * page translation fault.
6375                      */
6376                     code = 7;
6377                     goto do_fault;
6378                 }
6379             } else {
6380                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6381                 *page_size = 0x400;
6382             }
6383             ap = (desc >> 4) & 3;
6384             break;
6385         default:
6386             /* Never happens, but compiler isn't smart enough to tell.  */
6387             abort();
6388         }
6389         code = 15;
6390     }
6391     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6392     *prot |= *prot ? PAGE_EXEC : 0;
6393     if (!(*prot & (1 << access_type))) {
6394         /* Access permission fault.  */
6395         goto do_fault;
6396     }
6397     *phys_ptr = phys_addr;
6398     return false;
6399 do_fault:
6400     *fsr = code | (domain << 4);
6401     return true;
6402 }
6403
6404 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6405                              int access_type, ARMMMUIdx mmu_idx,
6406                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6407                              target_ulong *page_size, uint32_t *fsr,
6408                              ARMMMUFaultInfo *fi)
6409 {
6410     CPUState *cs = CPU(arm_env_get_cpu(env));
6411     int code;
6412     uint32_t table;
6413     uint32_t desc;
6414     uint32_t xn;
6415     uint32_t pxn = 0;
6416     int type;
6417     int ap;
6418     int domain = 0;
6419     int domain_prot;
6420     hwaddr phys_addr;
6421     uint32_t dacr;
6422     bool ns;
6423
6424     /* Pagetable walk.  */
6425     /* Lookup l1 descriptor.  */
6426     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6427         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6428         code = 5;
6429         goto do_fault;
6430     }
6431     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6432                        mmu_idx, fsr, fi);
6433     type = (desc & 3);
6434     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
6435         /* Section translation fault, or attempt to use the encoding
6436          * which is Reserved on implementations without PXN.
6437          */
6438         code = 5;
6439         goto do_fault;
6440     }
6441     if ((type == 1) || !(desc & (1 << 18))) {
6442         /* Page or Section.  */
6443         domain = (desc >> 5) & 0x0f;
6444     }
6445     if (regime_el(env, mmu_idx) == 1) {
6446         dacr = env->cp15.dacr_ns;
6447     } else {
6448         dacr = env->cp15.dacr_s;
6449     }
6450     domain_prot = (dacr >> (domain * 2)) & 3;
6451     if (domain_prot == 0 || domain_prot == 2) {
6452         if (type != 1) {
6453             code = 9; /* Section domain fault.  */
6454         } else {
6455             code = 11; /* Page domain fault.  */
6456         }
6457         goto do_fault;
6458     }
6459     if (type != 1) {
6460         if (desc & (1 << 18)) {
6461             /* Supersection.  */
6462             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
6463             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
6464             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
6465             *page_size = 0x1000000;
6466         } else {
6467             /* Section.  */
6468             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6469             *page_size = 0x100000;
6470         }
6471         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
6472         xn = desc & (1 << 4);
6473         pxn = desc & 1;
6474         code = 13;
6475         ns = extract32(desc, 19, 1);
6476     } else {
6477         if (arm_feature(env, ARM_FEATURE_PXN)) {
6478             pxn = (desc >> 2) & 1;
6479         }
6480         ns = extract32(desc, 3, 1);
6481         /* Lookup l2 entry.  */
6482         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6483         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6484                            mmu_idx, fsr, fi);
6485         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
6486         switch (desc & 3) {
6487         case 0: /* Page translation fault.  */
6488             code = 7;
6489             goto do_fault;
6490         case 1: /* 64k page.  */
6491             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6492             xn = desc & (1 << 15);
6493             *page_size = 0x10000;
6494             break;
6495         case 2: case 3: /* 4k page.  */
6496             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6497             xn = desc & 1;
6498             *page_size = 0x1000;
6499             break;
6500         default:
6501             /* Never happens, but compiler isn't smart enough to tell.  */
6502             abort();
6503         }
6504         code = 15;
6505     }
6506     if (domain_prot == 3) {
6507         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
6508     } else {
6509         if (pxn && !regime_is_user(env, mmu_idx)) {
6510             xn = 1;
6511         }
6512         if (xn && access_type == 2)
6513             goto do_fault;
6514
6515         if (arm_feature(env, ARM_FEATURE_V6K) &&
6516                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
6517             /* The simplified model uses AP[0] as an access control bit.  */
6518             if ((ap & 1) == 0) {
6519                 /* Access flag fault.  */
6520                 code = (code == 15) ? 6 : 3;
6521                 goto do_fault;
6522             }
6523             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
6524         } else {
6525             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6526         }
6527         if (*prot && !xn) {
6528             *prot |= PAGE_EXEC;
6529         }
6530         if (!(*prot & (1 << access_type))) {
6531             /* Access permission fault.  */
6532             goto do_fault;
6533         }
6534     }
6535     if (ns) {
6536         /* The NS bit will (as required by the architecture) have no effect if
6537          * the CPU doesn't support TZ or this is a non-secure translation
6538          * regime, because the attribute will already be non-secure.
6539          */
6540         attrs->secure = false;
6541     }
6542     *phys_ptr = phys_addr;
6543     return false;
6544 do_fault:
6545     *fsr = code | (domain << 4);
6546     return true;
6547 }
6548
6549 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6550  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6551  */
6552 typedef enum {
6553     translation_fault = 1,
6554     access_fault = 2,
6555     permission_fault = 3,
6556 } MMUFaultType;
6557
6558 /*
6559  * check_s2_startlevel
6560  * @cpu:        ARMCPU
6561  * @is_aa64:    True if the translation regime is in AArch64 state
6562  * @startlevel: Suggested starting level
6563  * @inputsize:  Bitsize of IPAs
6564  * @stride:     Page-table stride (See the ARM ARM)
6565  *
6566  * Returns true if the suggested starting level is OK and false otherwise.
6567  */
6568 static bool check_s2_startlevel(ARMCPU *cpu, bool is_aa64, int level,
6569                                 int inputsize, int stride)
6570 {
6571     /* Negative levels are never allowed.  */
6572     if (level < 0) {
6573         return false;
6574     }
6575
6576     if (is_aa64) {
6577         unsigned int pamax = arm_pamax(cpu);
6578
6579         switch (stride) {
6580         case 13: /* 64KB Pages.  */
6581             if (level == 0 || (level == 1 && pamax <= 42)) {
6582                 return false;
6583             }
6584             break;
6585         case 11: /* 16KB Pages.  */
6586             if (level == 0 || (level == 1 && pamax <= 40)) {
6587                 return false;
6588             }
6589             break;
6590         case 9: /* 4KB Pages.  */
6591             if (level == 0 && pamax <= 42) {
6592                 return false;
6593             }
6594             break;
6595         default:
6596             g_assert_not_reached();
6597         }
6598     } else {
6599         const int grainsize = stride + 3;
6600         int startsizecheck;
6601
6602         /* AArch32 only supports 4KB pages. Assert on that.  */
6603         assert(stride == 9);
6604
6605         if (level == 0) {
6606             return false;
6607         }
6608
6609         startsizecheck = inputsize - ((3 - level) * stride + grainsize);
6610         if (startsizecheck < 1 || startsizecheck > stride + 4) {
6611             return false;
6612         }
6613     }
6614     return true;
6615 }
6616
6617 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
6618                                int access_type, ARMMMUIdx mmu_idx,
6619                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
6620                                target_ulong *page_size_ptr, uint32_t *fsr,
6621                                ARMMMUFaultInfo *fi)
6622 {
6623     ARMCPU *cpu = arm_env_get_cpu(env);
6624     CPUState *cs = CPU(cpu);
6625     /* Read an LPAE long-descriptor translation table. */
6626     MMUFaultType fault_type = translation_fault;
6627     uint32_t level = 1;
6628     uint32_t epd = 0;
6629     int32_t t0sz, t1sz;
6630     uint32_t tg;
6631     uint64_t ttbr;
6632     int ttbr_select;
6633     hwaddr descaddr, descmask;
6634     uint32_t tableattrs;
6635     target_ulong page_size;
6636     uint32_t attrs;
6637     int32_t stride = 9;
6638     int32_t va_size = 32;
6639     int inputsize;
6640     int32_t tbi = 0;
6641     TCR *tcr = regime_tcr(env, mmu_idx);
6642     int ap, ns, xn, pxn;
6643     uint32_t el = regime_el(env, mmu_idx);
6644     bool ttbr1_valid = true;
6645
6646     /* TODO:
6647      * This code does not handle the different format TCR for VTCR_EL2.
6648      * This code also does not support shareability levels.
6649      * Attribute and permission bit handling should also be checked when adding
6650      * support for those page table walks.
6651      */
6652     if (arm_el_is_aa64(env, el)) {
6653         va_size = 64;
6654         if (el > 1) {
6655             if (mmu_idx != ARMMMUIdx_S2NS) {
6656                 tbi = extract64(tcr->raw_tcr, 20, 1);
6657             }
6658         } else {
6659             if (extract64(address, 55, 1)) {
6660                 tbi = extract64(tcr->raw_tcr, 38, 1);
6661             } else {
6662                 tbi = extract64(tcr->raw_tcr, 37, 1);
6663             }
6664         }
6665         tbi *= 8;
6666
6667         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6668          * invalid.
6669          */
6670         if (el > 1) {
6671             ttbr1_valid = false;
6672         }
6673     } else {
6674         /* There is no TTBR1 for EL2 */
6675         if (el == 2) {
6676             ttbr1_valid = false;
6677         }
6678     }
6679
6680     /* Determine whether this address is in the region controlled by
6681      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6682      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6683      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6684      */
6685     if (va_size == 64) {
6686         /* AArch64 translation.  */
6687         t0sz = extract32(tcr->raw_tcr, 0, 6);
6688         t0sz = MIN(t0sz, 39);
6689         t0sz = MAX(t0sz, 16);
6690     } else if (mmu_idx != ARMMMUIdx_S2NS) {
6691         /* AArch32 stage 1 translation.  */
6692         t0sz = extract32(tcr->raw_tcr, 0, 3);
6693     } else {
6694         /* AArch32 stage 2 translation.  */
6695         bool sext = extract32(tcr->raw_tcr, 4, 1);
6696         bool sign = extract32(tcr->raw_tcr, 3, 1);
6697         t0sz = sextract32(tcr->raw_tcr, 0, 4);
6698
6699         /* If the sign-extend bit is not the same as t0sz[3], the result
6700          * is unpredictable. Flag this as a guest error.  */
6701         if (sign != sext) {
6702             qemu_log_mask(LOG_GUEST_ERROR,
6703                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
6704         }
6705     }
6706     t1sz = extract32(tcr->raw_tcr, 16, 6);
6707     if (va_size == 64) {
6708         t1sz = MIN(t1sz, 39);
6709         t1sz = MAX(t1sz, 16);
6710     }
6711     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
6712         /* there is a ttbr0 region and we are in it (high bits all zero) */
6713         ttbr_select = 0;
6714     } else if (ttbr1_valid && t1sz &&
6715                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
6716         /* there is a ttbr1 region and we are in it (high bits all one) */
6717         ttbr_select = 1;
6718     } else if (!t0sz) {
6719         /* ttbr0 region is "everything not in the ttbr1 region" */
6720         ttbr_select = 0;
6721     } else if (!t1sz && ttbr1_valid) {
6722         /* ttbr1 region is "everything not in the ttbr0 region" */
6723         ttbr_select = 1;
6724     } else {
6725         /* in the gap between the two regions, this is a Translation fault */
6726         fault_type = translation_fault;
6727         goto do_fault;
6728     }
6729
6730     /* Note that QEMU ignores shareability and cacheability attributes,
6731      * so we don't need to do anything with the SH, ORGN, IRGN fields
6732      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
6733      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6734      * implement any ASID-like capability so we can ignore it (instead
6735      * we will always flush the TLB any time the ASID is changed).
6736      */
6737     if (ttbr_select == 0) {
6738         ttbr = regime_ttbr(env, mmu_idx, 0);
6739         if (el < 2) {
6740             epd = extract32(tcr->raw_tcr, 7, 1);
6741         }
6742         inputsize = va_size - t0sz;
6743
6744         tg = extract32(tcr->raw_tcr, 14, 2);
6745         if (tg == 1) { /* 64KB pages */
6746             stride = 13;
6747         }
6748         if (tg == 2) { /* 16KB pages */
6749             stride = 11;
6750         }
6751     } else {
6752         /* We should only be here if TTBR1 is valid */
6753         assert(ttbr1_valid);
6754
6755         ttbr = regime_ttbr(env, mmu_idx, 1);
6756         epd = extract32(tcr->raw_tcr, 23, 1);
6757         inputsize = va_size - t1sz;
6758
6759         tg = extract32(tcr->raw_tcr, 30, 2);
6760         if (tg == 3)  { /* 64KB pages */
6761             stride = 13;
6762         }
6763         if (tg == 1) { /* 16KB pages */
6764             stride = 11;
6765         }
6766     }
6767
6768     /* Here we should have set up all the parameters for the translation:
6769      * va_size, inputsize, ttbr, epd, stride, tbi
6770      */
6771
6772     if (epd) {
6773         /* Translation table walk disabled => Translation fault on TLB miss
6774          * Note: This is always 0 on 64-bit EL2 and EL3.
6775          */
6776         goto do_fault;
6777     }
6778
6779     if (mmu_idx != ARMMMUIdx_S2NS) {
6780         /* The starting level depends on the virtual address size (which can
6781          * be up to 48 bits) and the translation granule size. It indicates
6782          * the number of strides (stride bits at a time) needed to
6783          * consume the bits of the input address. In the pseudocode this is:
6784          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
6785          * where their 'inputsize' is our 'inputsize', 'grainsize' is
6786          * our 'stride + 3' and 'stride' is our 'stride'.
6787          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6788          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
6789          * = 4 - (inputsize - 4) / stride;
6790          */
6791         level = 4 - (inputsize - 4) / stride;
6792     } else {
6793         /* For stage 2 translations the starting level is specified by the
6794          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
6795          */
6796         int startlevel = extract32(tcr->raw_tcr, 6, 2);
6797         bool ok;
6798
6799         if (va_size == 32 || stride == 9) {
6800             /* AArch32 or 4KB pages */
6801             level = 2 - startlevel;
6802         } else {
6803             /* 16KB or 64KB pages */
6804             level = 3 - startlevel;
6805         }
6806
6807         /* Check that the starting level is valid. */
6808         ok = check_s2_startlevel(cpu, va_size == 64, level,
6809                                  inputsize, stride);
6810         if (!ok) {
6811             /* AArch64 reports these as level 0 faults.
6812              * AArch32 reports these as level 1 faults.
6813              */
6814             level = va_size == 64 ? 0 : 1;
6815             fault_type = translation_fault;
6816             goto do_fault;
6817         }
6818     }
6819
6820     /* Clear the vaddr bits which aren't part of the within-region address,
6821      * so that we don't have to special case things when calculating the
6822      * first descriptor address.
6823      */
6824     if (va_size != inputsize) {
6825         address &= (1ULL << inputsize) - 1;
6826     }
6827
6828     descmask = (1ULL << (stride + 3)) - 1;
6829
6830     /* Now we can extract the actual base address from the TTBR */
6831     descaddr = extract64(ttbr, 0, 48);
6832     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
6833
6834     /* Secure accesses start with the page table in secure memory and
6835      * can be downgraded to non-secure at any step. Non-secure accesses
6836      * remain non-secure. We implement this by just ORing in the NSTable/NS
6837      * bits at each step.
6838      */
6839     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
6840     for (;;) {
6841         uint64_t descriptor;
6842         bool nstable;
6843
6844         descaddr |= (address >> (stride * (4 - level))) & descmask;
6845         descaddr &= ~7ULL;
6846         nstable = extract32(tableattrs, 4, 1);
6847         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
6848         if (fi->s1ptw) {
6849             goto do_fault;
6850         }
6851
6852         if (!(descriptor & 1) ||
6853             (!(descriptor & 2) && (level == 3))) {
6854             /* Invalid, or the Reserved level 3 encoding */
6855             goto do_fault;
6856         }
6857         descaddr = descriptor & 0xfffffff000ULL;
6858
6859         if ((descriptor & 2) && (level < 3)) {
6860             /* Table entry. The top five bits are attributes which  may
6861              * propagate down through lower levels of the table (and
6862              * which are all arranged so that 0 means "no effect", so
6863              * we can gather them up by ORing in the bits at each level).
6864              */
6865             tableattrs |= extract64(descriptor, 59, 5);
6866             level++;
6867             continue;
6868         }
6869         /* Block entry at level 1 or 2, or page entry at level 3.
6870          * These are basically the same thing, although the number
6871          * of bits we pull in from the vaddr varies.
6872          */
6873         page_size = (1ULL << ((stride * (4 - level)) + 3));
6874         descaddr |= (address & (page_size - 1));
6875         /* Extract attributes from the descriptor */
6876         attrs = extract64(descriptor, 2, 10)
6877             | (extract64(descriptor, 52, 12) << 10);
6878
6879         if (mmu_idx == ARMMMUIdx_S2NS) {
6880             /* Stage 2 table descriptors do not include any attribute fields */
6881             break;
6882         }
6883         /* Merge in attributes from table descriptors */
6884         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
6885         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
6886         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
6887          * means "force PL1 access only", which means forcing AP[1] to 0.
6888          */
6889         if (extract32(tableattrs, 2, 1)) {
6890             attrs &= ~(1 << 4);
6891         }
6892         attrs |= nstable << 3; /* NS */
6893         break;
6894     }
6895     /* Here descaddr is the final physical address, and attributes
6896      * are all in attrs.
6897      */
6898     fault_type = access_fault;
6899     if ((attrs & (1 << 8)) == 0) {
6900         /* Access flag */
6901         goto do_fault;
6902     }
6903
6904     ap = extract32(attrs, 4, 2);
6905     xn = extract32(attrs, 12, 1);
6906
6907     if (mmu_idx == ARMMMUIdx_S2NS) {
6908         ns = true;
6909         *prot = get_S2prot(env, ap, xn);
6910     } else {
6911         ns = extract32(attrs, 3, 1);
6912         pxn = extract32(attrs, 11, 1);
6913         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
6914     }
6915
6916     fault_type = permission_fault;
6917     if (!(*prot & (1 << access_type))) {
6918         goto do_fault;
6919     }
6920
6921     if (ns) {
6922         /* The NS bit will (as required by the architecture) have no effect if
6923          * the CPU doesn't support TZ or this is a non-secure translation
6924          * regime, because the attribute will already be non-secure.
6925          */
6926         txattrs->secure = false;
6927     }
6928     *phys_ptr = descaddr;
6929     *page_size_ptr = page_size;
6930     return false;
6931
6932 do_fault:
6933     /* Long-descriptor format IFSR/DFSR value */
6934     *fsr = (1 << 9) | (fault_type << 2) | level;
6935     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
6936     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
6937     return true;
6938 }
6939
6940 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
6941                                                 ARMMMUIdx mmu_idx,
6942                                                 int32_t address, int *prot)
6943 {
6944     *prot = PAGE_READ | PAGE_WRITE;
6945     switch (address) {
6946     case 0xF0000000 ... 0xFFFFFFFF:
6947         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
6948             *prot |= PAGE_EXEC;
6949         }
6950         break;
6951     case 0x00000000 ... 0x7FFFFFFF:
6952         *prot |= PAGE_EXEC;
6953         break;
6954     }
6955
6956 }
6957
6958 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
6959                                  int access_type, ARMMMUIdx mmu_idx,
6960                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
6961 {
6962     ARMCPU *cpu = arm_env_get_cpu(env);
6963     int n;
6964     bool is_user = regime_is_user(env, mmu_idx);
6965
6966     *phys_ptr = address;
6967     *prot = 0;
6968
6969     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
6970         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
6971     } else { /* MPU enabled */
6972         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
6973             /* region search */
6974             uint32_t base = env->pmsav7.drbar[n];
6975             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
6976             uint32_t rmask;
6977             bool srdis = false;
6978
6979             if (!(env->pmsav7.drsr[n] & 0x1)) {
6980                 continue;
6981             }
6982
6983             if (!rsize) {
6984                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
6985                 continue;
6986             }
6987             rsize++;
6988             rmask = (1ull << rsize) - 1;
6989
6990             if (base & rmask) {
6991                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
6992                               "to DRSR region size, mask = %" PRIx32,
6993                               base, rmask);
6994                 continue;
6995             }
6996
6997             if (address < base || address > base + rmask) {
6998                 continue;
6999             }
7000
7001             /* Region matched */
7002
7003             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7004                 int i, snd;
7005                 uint32_t srdis_mask;
7006
7007                 rsize -= 3; /* sub region size (power of 2) */
7008                 snd = ((address - base) >> rsize) & 0x7;
7009                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7010
7011                 srdis_mask = srdis ? 0x3 : 0x0;
7012                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7013                     /* This will check in groups of 2, 4 and then 8, whether
7014                      * the subregion bits are consistent. rsize is incremented
7015                      * back up to give the region size, considering consistent
7016                      * adjacent subregions as one region. Stop testing if rsize
7017                      * is already big enough for an entire QEMU page.
7018                      */
7019                     int snd_rounded = snd & ~(i - 1);
7020                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7021                                                      snd_rounded + 8, i);
7022                     if (srdis_mask ^ srdis_multi) {
7023                         break;
7024                     }
7025                     srdis_mask = (srdis_mask << i) | srdis_mask;
7026                     rsize++;
7027                 }
7028             }
7029             if (rsize < TARGET_PAGE_BITS) {
7030                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7031                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7032                               rsize, TARGET_PAGE_BITS);
7033                 continue;
7034             }
7035             if (srdis) {
7036                 continue;
7037             }
7038             break;
7039         }
7040
7041         if (n == -1) { /* no hits */
7042             if (cpu->pmsav7_dregion &&
7043                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7044                 /* background fault */
7045                 *fsr = 0;
7046                 return true;
7047             }
7048             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7049         } else { /* a MPU hit! */
7050             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7051
7052             if (is_user) { /* User mode AP bit decoding */
7053                 switch (ap) {
7054                 case 0:
7055                 case 1:
7056                 case 5:
7057                     break; /* no access */
7058                 case 3:
7059                     *prot |= PAGE_WRITE;
7060                     /* fall through */
7061                 case 2:
7062                 case 6:
7063                     *prot |= PAGE_READ | PAGE_EXEC;
7064                     break;
7065                 default:
7066                     qemu_log_mask(LOG_GUEST_ERROR,
7067                                   "Bad value for AP bits in DRACR %"
7068                                   PRIx32 "\n", ap);
7069                 }
7070             } else { /* Priv. mode AP bits decoding */
7071                 switch (ap) {
7072                 case 0:
7073                     break; /* no access */
7074                 case 1:
7075                 case 2:
7076                 case 3:
7077                     *prot |= PAGE_WRITE;
7078                     /* fall through */
7079                 case 5:
7080                 case 6:
7081                     *prot |= PAGE_READ | PAGE_EXEC;
7082                     break;
7083                 default:
7084                     qemu_log_mask(LOG_GUEST_ERROR,
7085                                   "Bad value for AP bits in DRACR %"
7086                                   PRIx32 "\n", ap);
7087                 }
7088             }
7089
7090             /* execute never */
7091             if (env->pmsav7.dracr[n] & (1 << 12)) {
7092                 *prot &= ~PAGE_EXEC;
7093             }
7094         }
7095     }
7096
7097     *fsr = 0x00d; /* Permission fault */
7098     return !(*prot & (1 << access_type));
7099 }
7100
7101 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7102                                  int access_type, ARMMMUIdx mmu_idx,
7103                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7104 {
7105     int n;
7106     uint32_t mask;
7107     uint32_t base;
7108     bool is_user = regime_is_user(env, mmu_idx);
7109
7110     *phys_ptr = address;
7111     for (n = 7; n >= 0; n--) {
7112         base = env->cp15.c6_region[n];
7113         if ((base & 1) == 0) {
7114             continue;
7115         }
7116         mask = 1 << ((base >> 1) & 0x1f);
7117         /* Keep this shift separate from the above to avoid an
7118            (undefined) << 32.  */
7119         mask = (mask << 1) - 1;
7120         if (((base ^ address) & ~mask) == 0) {
7121             break;
7122         }
7123     }
7124     if (n < 0) {
7125         *fsr = 2;
7126         return true;
7127     }
7128
7129     if (access_type == 2) {
7130         mask = env->cp15.pmsav5_insn_ap;
7131     } else {
7132         mask = env->cp15.pmsav5_data_ap;
7133     }
7134     mask = (mask >> (n * 4)) & 0xf;
7135     switch (mask) {
7136     case 0:
7137         *fsr = 1;
7138         return true;
7139     case 1:
7140         if (is_user) {
7141             *fsr = 1;
7142             return true;
7143         }
7144         *prot = PAGE_READ | PAGE_WRITE;
7145         break;
7146     case 2:
7147         *prot = PAGE_READ;
7148         if (!is_user) {
7149             *prot |= PAGE_WRITE;
7150         }
7151         break;
7152     case 3:
7153         *prot = PAGE_READ | PAGE_WRITE;
7154         break;
7155     case 5:
7156         if (is_user) {
7157             *fsr = 1;
7158             return true;
7159         }
7160         *prot = PAGE_READ;
7161         break;
7162     case 6:
7163         *prot = PAGE_READ;
7164         break;
7165     default:
7166         /* Bad permission.  */
7167         *fsr = 1;
7168         return true;
7169     }
7170     *prot |= PAGE_EXEC;
7171     return false;
7172 }
7173
7174 /* get_phys_addr - get the physical address for this virtual address
7175  *
7176  * Find the physical address corresponding to the given virtual address,
7177  * by doing a translation table walk on MMU based systems or using the
7178  * MPU state on MPU based systems.
7179  *
7180  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7181  * prot and page_size may not be filled in, and the populated fsr value provides
7182  * information on why the translation aborted, in the format of a
7183  * DFSR/IFSR fault register, with the following caveats:
7184  *  * we honour the short vs long DFSR format differences.
7185  *  * the WnR bit is never set (the caller must do this).
7186  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7187  *    value.
7188  *
7189  * @env: CPUARMState
7190  * @address: virtual address to get physical address for
7191  * @access_type: 0 for read, 1 for write, 2 for execute
7192  * @mmu_idx: MMU index indicating required translation regime
7193  * @phys_ptr: set to the physical address corresponding to the virtual address
7194  * @attrs: set to the memory transaction attributes to use
7195  * @prot: set to the permissions for the page containing phys_ptr
7196  * @page_size: set to the size of the page containing phys_ptr
7197  * @fsr: set to the DFSR/IFSR value on failure
7198  */
7199 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7200                           int access_type, ARMMMUIdx mmu_idx,
7201                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7202                           target_ulong *page_size, uint32_t *fsr,
7203                           ARMMMUFaultInfo *fi)
7204 {
7205     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7206         /* Call ourselves recursively to do the stage 1 and then stage 2
7207          * translations.
7208          */
7209         if (arm_feature(env, ARM_FEATURE_EL2)) {
7210             hwaddr ipa;
7211             int s2_prot;
7212             int ret;
7213
7214             ret = get_phys_addr(env, address, access_type,
7215                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7216                                 prot, page_size, fsr, fi);
7217
7218             /* If S1 fails or S2 is disabled, return early.  */
7219             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7220                 *phys_ptr = ipa;
7221                 return ret;
7222             }
7223
7224             /* S1 is done. Now do S2 translation.  */
7225             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7226                                      phys_ptr, attrs, &s2_prot,
7227                                      page_size, fsr, fi);
7228             fi->s2addr = ipa;
7229             /* Combine the S1 and S2 perms.  */
7230             *prot &= s2_prot;
7231             return ret;
7232         } else {
7233             /*
7234              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7235              */
7236             mmu_idx += ARMMMUIdx_S1NSE0;
7237         }
7238     }
7239
7240     /* The page table entries may downgrade secure to non-secure, but
7241      * cannot upgrade an non-secure translation regime's attributes
7242      * to secure.
7243      */
7244     attrs->secure = regime_is_secure(env, mmu_idx);
7245     attrs->user = regime_is_user(env, mmu_idx);
7246
7247     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7248      * In v7 and earlier it affects all stage 1 translations.
7249      */
7250     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7251         && !arm_feature(env, ARM_FEATURE_V8)) {
7252         if (regime_el(env, mmu_idx) == 3) {
7253             address += env->cp15.fcseidr_s;
7254         } else {
7255             address += env->cp15.fcseidr_ns;
7256         }
7257     }
7258
7259     /* pmsav7 has special handling for when MPU is disabled so call it before
7260      * the common MMU/MPU disabled check below.
7261      */
7262     if (arm_feature(env, ARM_FEATURE_MPU) &&
7263         arm_feature(env, ARM_FEATURE_V7)) {
7264         *page_size = TARGET_PAGE_SIZE;
7265         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7266                                     phys_ptr, prot, fsr);
7267     }
7268
7269     if (regime_translation_disabled(env, mmu_idx)) {
7270         /* MMU/MPU disabled.  */
7271         *phys_ptr = address;
7272         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7273         *page_size = TARGET_PAGE_SIZE;
7274         return 0;
7275     }
7276
7277     if (arm_feature(env, ARM_FEATURE_MPU)) {
7278         /* Pre-v7 MPU */
7279         *page_size = TARGET_PAGE_SIZE;
7280         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7281                                     phys_ptr, prot, fsr);
7282     }
7283
7284     if (regime_using_lpae_format(env, mmu_idx)) {
7285         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7286                                   attrs, prot, page_size, fsr, fi);
7287     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7288         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7289                                 attrs, prot, page_size, fsr, fi);
7290     } else {
7291         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7292                                 prot, page_size, fsr, fi);
7293     }
7294 }
7295
7296 /* Walk the page table and (if the mapping exists) add the page
7297  * to the TLB. Return false on success, or true on failure. Populate
7298  * fsr with ARM DFSR/IFSR fault register format value on failure.
7299  */
7300 bool arm_tlb_fill(CPUState *cs, vaddr address,
7301                   int access_type, int mmu_idx, uint32_t *fsr,
7302                   ARMMMUFaultInfo *fi)
7303 {
7304     ARMCPU *cpu = ARM_CPU(cs);
7305     CPUARMState *env = &cpu->env;
7306     hwaddr phys_addr;
7307     target_ulong page_size;
7308     int prot;
7309     int ret;
7310     MemTxAttrs attrs = {};
7311
7312     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7313                         &attrs, &prot, &page_size, fsr, fi);
7314     if (!ret) {
7315         /* Map a single [sub]page.  */
7316         phys_addr &= TARGET_PAGE_MASK;
7317         address &= TARGET_PAGE_MASK;
7318         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7319                                 prot, mmu_idx, page_size);
7320         return 0;
7321     }
7322
7323     return ret;
7324 }
7325
7326 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
7327 {
7328     ARMCPU *cpu = ARM_CPU(cs);
7329     CPUARMState *env = &cpu->env;
7330     hwaddr phys_addr;
7331     target_ulong page_size;
7332     int prot;
7333     bool ret;
7334     uint32_t fsr;
7335     MemTxAttrs attrs = {};
7336     ARMMMUFaultInfo fi = {};
7337
7338     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7339                         &attrs, &prot, &page_size, &fsr, &fi);
7340
7341     if (ret) {
7342         return -1;
7343     }
7344
7345     return phys_addr;
7346 }
7347
7348 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
7349 {
7350     if ((env->uncached_cpsr & CPSR_M) == mode) {
7351         env->regs[13] = val;
7352     } else {
7353         env->banked_r13[bank_number(mode)] = val;
7354     }
7355 }
7356
7357 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
7358 {
7359     if ((env->uncached_cpsr & CPSR_M) == mode) {
7360         return env->regs[13];
7361     } else {
7362         return env->banked_r13[bank_number(mode)];
7363     }
7364 }
7365
7366 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7367 {
7368     ARMCPU *cpu = arm_env_get_cpu(env);
7369
7370     switch (reg) {
7371     case 0: /* APSR */
7372         return xpsr_read(env) & 0xf8000000;
7373     case 1: /* IAPSR */
7374         return xpsr_read(env) & 0xf80001ff;
7375     case 2: /* EAPSR */
7376         return xpsr_read(env) & 0xff00fc00;
7377     case 3: /* xPSR */
7378         return xpsr_read(env) & 0xff00fdff;
7379     case 5: /* IPSR */
7380         return xpsr_read(env) & 0x000001ff;
7381     case 6: /* EPSR */
7382         return xpsr_read(env) & 0x0700fc00;
7383     case 7: /* IEPSR */
7384         return xpsr_read(env) & 0x0700edff;
7385     case 8: /* MSP */
7386         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7387     case 9: /* PSP */
7388         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7389     case 16: /* PRIMASK */
7390         return (env->daif & PSTATE_I) != 0;
7391     case 17: /* BASEPRI */
7392     case 18: /* BASEPRI_MAX */
7393         return env->v7m.basepri;
7394     case 19: /* FAULTMASK */
7395         return (env->daif & PSTATE_F) != 0;
7396     case 20: /* CONTROL */
7397         return env->v7m.control;
7398     default:
7399         /* ??? For debugging only.  */
7400         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
7401         return 0;
7402     }
7403 }
7404
7405 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
7406 {
7407     ARMCPU *cpu = arm_env_get_cpu(env);
7408
7409     switch (reg) {
7410     case 0: /* APSR */
7411         xpsr_write(env, val, 0xf8000000);
7412         break;
7413     case 1: /* IAPSR */
7414         xpsr_write(env, val, 0xf8000000);
7415         break;
7416     case 2: /* EAPSR */
7417         xpsr_write(env, val, 0xfe00fc00);
7418         break;
7419     case 3: /* xPSR */
7420         xpsr_write(env, val, 0xfe00fc00);
7421         break;
7422     case 5: /* IPSR */
7423         /* IPSR bits are readonly.  */
7424         break;
7425     case 6: /* EPSR */
7426         xpsr_write(env, val, 0x0600fc00);
7427         break;
7428     case 7: /* IEPSR */
7429         xpsr_write(env, val, 0x0600fc00);
7430         break;
7431     case 8: /* MSP */
7432         if (env->v7m.current_sp)
7433             env->v7m.other_sp = val;
7434         else
7435             env->regs[13] = val;
7436         break;
7437     case 9: /* PSP */
7438         if (env->v7m.current_sp)
7439             env->regs[13] = val;
7440         else
7441             env->v7m.other_sp = val;
7442         break;
7443     case 16: /* PRIMASK */
7444         if (val & 1) {
7445             env->daif |= PSTATE_I;
7446         } else {
7447             env->daif &= ~PSTATE_I;
7448         }
7449         break;
7450     case 17: /* BASEPRI */
7451         env->v7m.basepri = val & 0xff;
7452         break;
7453     case 18: /* BASEPRI_MAX */
7454         val &= 0xff;
7455         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
7456             env->v7m.basepri = val;
7457         break;
7458     case 19: /* FAULTMASK */
7459         if (val & 1) {
7460             env->daif |= PSTATE_F;
7461         } else {
7462             env->daif &= ~PSTATE_F;
7463         }
7464         break;
7465     case 20: /* CONTROL */
7466         env->v7m.control = val & 3;
7467         switch_v7m_sp(env, (val & 2) != 0);
7468         break;
7469     default:
7470         /* ??? For debugging only.  */
7471         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
7472         return;
7473     }
7474 }
7475
7476 #endif
7477
7478 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
7479 {
7480     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7481      * Note that we do not implement the (architecturally mandated)
7482      * alignment fault for attempts to use this on Device memory
7483      * (which matches the usual QEMU behaviour of not implementing either
7484      * alignment faults or any memory attribute handling).
7485      */
7486
7487     ARMCPU *cpu = arm_env_get_cpu(env);
7488     uint64_t blocklen = 4 << cpu->dcz_blocksize;
7489     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
7490
7491 #ifndef CONFIG_USER_ONLY
7492     {
7493         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7494          * the block size so we might have to do more than one TLB lookup.
7495          * We know that in fact for any v8 CPU the page size is at least 4K
7496          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7497          * 1K as an artefact of legacy v5 subpage support being present in the
7498          * same QEMU executable.
7499          */
7500         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
7501         void *hostaddr[maxidx];
7502         int try, i;
7503         unsigned mmu_idx = cpu_mmu_index(env, false);
7504         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
7505
7506         for (try = 0; try < 2; try++) {
7507
7508             for (i = 0; i < maxidx; i++) {
7509                 hostaddr[i] = tlb_vaddr_to_host(env,
7510                                                 vaddr + TARGET_PAGE_SIZE * i,
7511                                                 1, mmu_idx);
7512                 if (!hostaddr[i]) {
7513                     break;
7514                 }
7515             }
7516             if (i == maxidx) {
7517                 /* If it's all in the TLB it's fair game for just writing to;
7518                  * we know we don't need to update dirty status, etc.
7519                  */
7520                 for (i = 0; i < maxidx - 1; i++) {
7521                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
7522                 }
7523                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
7524                 return;
7525             }
7526             /* OK, try a store and see if we can populate the tlb. This
7527              * might cause an exception if the memory isn't writable,
7528              * in which case we will longjmp out of here. We must for
7529              * this purpose use the actual register value passed to us
7530              * so that we get the fault address right.
7531              */
7532             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
7533             /* Now we can populate the other TLB entries, if any */
7534             for (i = 0; i < maxidx; i++) {
7535                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
7536                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
7537                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
7538                 }
7539             }
7540         }
7541
7542         /* Slow path (probably attempt to do this to an I/O device or
7543          * similar, or clearing of a block of code we have translations
7544          * cached for). Just do a series of byte writes as the architecture
7545          * demands. It's not worth trying to use a cpu_physical_memory_map(),
7546          * memset(), unmap() sequence here because:
7547          *  + we'd need to account for the blocksize being larger than a page
7548          *  + the direct-RAM access case is almost always going to be dealt
7549          *    with in the fastpath code above, so there's no speed benefit
7550          *  + we would have to deal with the map returning NULL because the
7551          *    bounce buffer was in use
7552          */
7553         for (i = 0; i < blocklen; i++) {
7554             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
7555         }
7556     }
7557 #else
7558     memset(g2h(vaddr), 0, blocklen);
7559 #endif
7560 }
7561
7562 /* Note that signed overflow is undefined in C.  The following routines are
7563    careful to use unsigned types where modulo arithmetic is required.
7564    Failure to do so _will_ break on newer gcc.  */
7565
7566 /* Signed saturating arithmetic.  */
7567
7568 /* Perform 16-bit signed saturating addition.  */
7569 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
7570 {
7571     uint16_t res;
7572
7573     res = a + b;
7574     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
7575         if (a & 0x8000)
7576             res = 0x8000;
7577         else
7578             res = 0x7fff;
7579     }
7580     return res;
7581 }
7582
7583 /* Perform 8-bit signed saturating addition.  */
7584 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
7585 {
7586     uint8_t res;
7587
7588     res = a + b;
7589     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
7590         if (a & 0x80)
7591             res = 0x80;
7592         else
7593             res = 0x7f;
7594     }
7595     return res;
7596 }
7597
7598 /* Perform 16-bit signed saturating subtraction.  */
7599 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
7600 {
7601     uint16_t res;
7602
7603     res = a - b;
7604     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
7605         if (a & 0x8000)
7606             res = 0x8000;
7607         else
7608             res = 0x7fff;
7609     }
7610     return res;
7611 }
7612
7613 /* Perform 8-bit signed saturating subtraction.  */
7614 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
7615 {
7616     uint8_t res;
7617
7618     res = a - b;
7619     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
7620         if (a & 0x80)
7621             res = 0x80;
7622         else
7623             res = 0x7f;
7624     }
7625     return res;
7626 }
7627
7628 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7629 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7630 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
7631 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
7632 #define PFX q
7633
7634 #include "op_addsub.h"
7635
7636 /* Unsigned saturating arithmetic.  */
7637 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
7638 {
7639     uint16_t res;
7640     res = a + b;
7641     if (res < a)
7642         res = 0xffff;
7643     return res;
7644 }
7645
7646 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
7647 {
7648     if (a > b)
7649         return a - b;
7650     else
7651         return 0;
7652 }
7653
7654 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
7655 {
7656     uint8_t res;
7657     res = a + b;
7658     if (res < a)
7659         res = 0xff;
7660     return res;
7661 }
7662
7663 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
7664 {
7665     if (a > b)
7666         return a - b;
7667     else
7668         return 0;
7669 }
7670
7671 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7672 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7673 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
7674 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
7675 #define PFX uq
7676
7677 #include "op_addsub.h"
7678
7679 /* Signed modulo arithmetic.  */
7680 #define SARITH16(a, b, n, op) do { \
7681     int32_t sum; \
7682     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7683     RESULT(sum, n, 16); \
7684     if (sum >= 0) \
7685         ge |= 3 << (n * 2); \
7686     } while(0)
7687
7688 #define SARITH8(a, b, n, op) do { \
7689     int32_t sum; \
7690     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7691     RESULT(sum, n, 8); \
7692     if (sum >= 0) \
7693         ge |= 1 << n; \
7694     } while(0)
7695
7696
7697 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7698 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7699 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
7700 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
7701 #define PFX s
7702 #define ARITH_GE
7703
7704 #include "op_addsub.h"
7705
7706 /* Unsigned modulo arithmetic.  */
7707 #define ADD16(a, b, n) do { \
7708     uint32_t sum; \
7709     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7710     RESULT(sum, n, 16); \
7711     if ((sum >> 16) == 1) \
7712         ge |= 3 << (n * 2); \
7713     } while(0)
7714
7715 #define ADD8(a, b, n) do { \
7716     uint32_t sum; \
7717     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7718     RESULT(sum, n, 8); \
7719     if ((sum >> 8) == 1) \
7720         ge |= 1 << n; \
7721     } while(0)
7722
7723 #define SUB16(a, b, n) do { \
7724     uint32_t sum; \
7725     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7726     RESULT(sum, n, 16); \
7727     if ((sum >> 16) == 0) \
7728         ge |= 3 << (n * 2); \
7729     } while(0)
7730
7731 #define SUB8(a, b, n) do { \
7732     uint32_t sum; \
7733     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7734     RESULT(sum, n, 8); \
7735     if ((sum >> 8) == 0) \
7736         ge |= 1 << n; \
7737     } while(0)
7738
7739 #define PFX u
7740 #define ARITH_GE
7741
7742 #include "op_addsub.h"
7743
7744 /* Halved signed arithmetic.  */
7745 #define ADD16(a, b, n) \
7746   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7747 #define SUB16(a, b, n) \
7748   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7749 #define ADD8(a, b, n) \
7750   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7751 #define SUB8(a, b, n) \
7752   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7753 #define PFX sh
7754
7755 #include "op_addsub.h"
7756
7757 /* Halved unsigned arithmetic.  */
7758 #define ADD16(a, b, n) \
7759   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7760 #define SUB16(a, b, n) \
7761   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7762 #define ADD8(a, b, n) \
7763   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7764 #define SUB8(a, b, n) \
7765   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7766 #define PFX uh
7767
7768 #include "op_addsub.h"
7769
7770 static inline uint8_t do_usad(uint8_t a, uint8_t b)
7771 {
7772     if (a > b)
7773         return a - b;
7774     else
7775         return b - a;
7776 }
7777
7778 /* Unsigned sum of absolute byte differences.  */
7779 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
7780 {
7781     uint32_t sum;
7782     sum = do_usad(a, b);
7783     sum += do_usad(a >> 8, b >> 8);
7784     sum += do_usad(a >> 16, b >>16);
7785     sum += do_usad(a >> 24, b >> 24);
7786     return sum;
7787 }
7788
7789 /* For ARMv6 SEL instruction.  */
7790 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
7791 {
7792     uint32_t mask;
7793
7794     mask = 0;
7795     if (flags & 1)
7796         mask |= 0xff;
7797     if (flags & 2)
7798         mask |= 0xff00;
7799     if (flags & 4)
7800         mask |= 0xff0000;
7801     if (flags & 8)
7802         mask |= 0xff000000;
7803     return (a & mask) | (b & ~mask);
7804 }
7805
7806 /* VFP support.  We follow the convention used for VFP instructions:
7807    Single precision routines have a "s" suffix, double precision a
7808    "d" suffix.  */
7809
7810 /* Convert host exception flags to vfp form.  */
7811 static inline int vfp_exceptbits_from_host(int host_bits)
7812 {
7813     int target_bits = 0;
7814
7815     if (host_bits & float_flag_invalid)
7816         target_bits |= 1;
7817     if (host_bits & float_flag_divbyzero)
7818         target_bits |= 2;
7819     if (host_bits & float_flag_overflow)
7820         target_bits |= 4;
7821     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
7822         target_bits |= 8;
7823     if (host_bits & float_flag_inexact)
7824         target_bits |= 0x10;
7825     if (host_bits & float_flag_input_denormal)
7826         target_bits |= 0x80;
7827     return target_bits;
7828 }
7829
7830 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
7831 {
7832     int i;
7833     uint32_t fpscr;
7834
7835     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
7836             | (env->vfp.vec_len << 16)
7837             | (env->vfp.vec_stride << 20);
7838     i = get_float_exception_flags(&env->vfp.fp_status);
7839     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
7840     fpscr |= vfp_exceptbits_from_host(i);
7841     return fpscr;
7842 }
7843
7844 uint32_t vfp_get_fpscr(CPUARMState *env)
7845 {
7846     return HELPER(vfp_get_fpscr)(env);
7847 }
7848
7849 /* Convert vfp exception flags to target form.  */
7850 static inline int vfp_exceptbits_to_host(int target_bits)
7851 {
7852     int host_bits = 0;
7853
7854     if (target_bits & 1)
7855         host_bits |= float_flag_invalid;
7856     if (target_bits & 2)
7857         host_bits |= float_flag_divbyzero;
7858     if (target_bits & 4)
7859         host_bits |= float_flag_overflow;
7860     if (target_bits & 8)
7861         host_bits |= float_flag_underflow;
7862     if (target_bits & 0x10)
7863         host_bits |= float_flag_inexact;
7864     if (target_bits & 0x80)
7865         host_bits |= float_flag_input_denormal;
7866     return host_bits;
7867 }
7868
7869 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
7870 {
7871     int i;
7872     uint32_t changed;
7873
7874     changed = env->vfp.xregs[ARM_VFP_FPSCR];
7875     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
7876     env->vfp.vec_len = (val >> 16) & 7;
7877     env->vfp.vec_stride = (val >> 20) & 3;
7878
7879     changed ^= val;
7880     if (changed & (3 << 22)) {
7881         i = (val >> 22) & 3;
7882         switch (i) {
7883         case FPROUNDING_TIEEVEN:
7884             i = float_round_nearest_even;
7885             break;
7886         case FPROUNDING_POSINF:
7887             i = float_round_up;
7888             break;
7889         case FPROUNDING_NEGINF:
7890             i = float_round_down;
7891             break;
7892         case FPROUNDING_ZERO:
7893             i = float_round_to_zero;
7894             break;
7895         }
7896         set_float_rounding_mode(i, &env->vfp.fp_status);
7897     }
7898     if (changed & (1 << 24)) {
7899         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7900         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
7901     }
7902     if (changed & (1 << 25))
7903         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
7904
7905     i = vfp_exceptbits_to_host(val);
7906     set_float_exception_flags(i, &env->vfp.fp_status);
7907     set_float_exception_flags(0, &env->vfp.standard_fp_status);
7908 }
7909
7910 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
7911 {
7912     HELPER(vfp_set_fpscr)(env, val);
7913 }
7914
7915 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
7916
7917 #define VFP_BINOP(name) \
7918 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
7919 { \
7920     float_status *fpst = fpstp; \
7921     return float32_ ## name(a, b, fpst); \
7922 } \
7923 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
7924 { \
7925     float_status *fpst = fpstp; \
7926     return float64_ ## name(a, b, fpst); \
7927 }
7928 VFP_BINOP(add)
7929 VFP_BINOP(sub)
7930 VFP_BINOP(mul)
7931 VFP_BINOP(div)
7932 VFP_BINOP(min)
7933 VFP_BINOP(max)
7934 VFP_BINOP(minnum)
7935 VFP_BINOP(maxnum)
7936 #undef VFP_BINOP
7937
7938 float32 VFP_HELPER(neg, s)(float32 a)
7939 {
7940     return float32_chs(a);
7941 }
7942
7943 float64 VFP_HELPER(neg, d)(float64 a)
7944 {
7945     return float64_chs(a);
7946 }
7947
7948 float32 VFP_HELPER(abs, s)(float32 a)
7949 {
7950     return float32_abs(a);
7951 }
7952
7953 float64 VFP_HELPER(abs, d)(float64 a)
7954 {
7955     return float64_abs(a);
7956 }
7957
7958 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
7959 {
7960     return float32_sqrt(a, &env->vfp.fp_status);
7961 }
7962
7963 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
7964 {
7965     return float64_sqrt(a, &env->vfp.fp_status);
7966 }
7967
7968 /* XXX: check quiet/signaling case */
7969 #define DO_VFP_cmp(p, type) \
7970 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
7971 { \
7972     uint32_t flags; \
7973     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
7974     case 0: flags = 0x6; break; \
7975     case -1: flags = 0x8; break; \
7976     case 1: flags = 0x2; break; \
7977     default: case 2: flags = 0x3; break; \
7978     } \
7979     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7980         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7981 } \
7982 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
7983 { \
7984     uint32_t flags; \
7985     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
7986     case 0: flags = 0x6; break; \
7987     case -1: flags = 0x8; break; \
7988     case 1: flags = 0x2; break; \
7989     default: case 2: flags = 0x3; break; \
7990     } \
7991     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7992         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7993 }
7994 DO_VFP_cmp(s, float32)
7995 DO_VFP_cmp(d, float64)
7996 #undef DO_VFP_cmp
7997
7998 /* Integer to float and float to integer conversions */
7999
8000 #define CONV_ITOF(name, fsz, sign) \
8001     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8002 { \
8003     float_status *fpst = fpstp; \
8004     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8005 }
8006
8007 #define CONV_FTOI(name, fsz, sign, round) \
8008 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8009 { \
8010     float_status *fpst = fpstp; \
8011     if (float##fsz##_is_any_nan(x)) { \
8012         float_raise(float_flag_invalid, fpst); \
8013         return 0; \
8014     } \
8015     return float##fsz##_to_##sign##int32##round(x, fpst); \
8016 }
8017
8018 #define FLOAT_CONVS(name, p, fsz, sign) \
8019 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8020 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8021 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8022
8023 FLOAT_CONVS(si, s, 32, )
8024 FLOAT_CONVS(si, d, 64, )
8025 FLOAT_CONVS(ui, s, 32, u)
8026 FLOAT_CONVS(ui, d, 64, u)
8027
8028 #undef CONV_ITOF
8029 #undef CONV_FTOI
8030 #undef FLOAT_CONVS
8031
8032 /* floating point conversion */
8033 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8034 {
8035     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8036     /* ARM requires that S<->D conversion of any kind of NaN generates
8037      * a quiet NaN by forcing the most significant frac bit to 1.
8038      */
8039     return float64_maybe_silence_nan(r);
8040 }
8041
8042 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8043 {
8044     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8045     /* ARM requires that S<->D conversion of any kind of NaN generates
8046      * a quiet NaN by forcing the most significant frac bit to 1.
8047      */
8048     return float32_maybe_silence_nan(r);
8049 }
8050
8051 /* VFP3 fixed point conversion.  */
8052 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8053 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8054                                      void *fpstp) \
8055 { \
8056     float_status *fpst = fpstp; \
8057     float##fsz tmp; \
8058     tmp = itype##_to_##float##fsz(x, fpst); \
8059     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8060 }
8061
8062 /* Notice that we want only input-denormal exception flags from the
8063  * scalbn operation: the other possible flags (overflow+inexact if
8064  * we overflow to infinity, output-denormal) aren't correct for the
8065  * complete scale-and-convert operation.
8066  */
8067 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8068 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8069                                              uint32_t shift, \
8070                                              void *fpstp) \
8071 { \
8072     float_status *fpst = fpstp; \
8073     int old_exc_flags = get_float_exception_flags(fpst); \
8074     float##fsz tmp; \
8075     if (float##fsz##_is_any_nan(x)) { \
8076         float_raise(float_flag_invalid, fpst); \
8077         return 0; \
8078     } \
8079     tmp = float##fsz##_scalbn(x, shift, fpst); \
8080     old_exc_flags |= get_float_exception_flags(fpst) \
8081         & float_flag_input_denormal; \
8082     set_float_exception_flags(old_exc_flags, fpst); \
8083     return float##fsz##_to_##itype##round(tmp, fpst); \
8084 }
8085
8086 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8087 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8088 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8089 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8090
8091 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8092 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8093 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8094
8095 VFP_CONV_FIX(sh, d, 64, 64, int16)
8096 VFP_CONV_FIX(sl, d, 64, 64, int32)
8097 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8098 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8099 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8100 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8101 VFP_CONV_FIX(sh, s, 32, 32, int16)
8102 VFP_CONV_FIX(sl, s, 32, 32, int32)
8103 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8104 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8105 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8106 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8107 #undef VFP_CONV_FIX
8108 #undef VFP_CONV_FIX_FLOAT
8109 #undef VFP_CONV_FLOAT_FIX_ROUND
8110
8111 /* Set the current fp rounding mode and return the old one.
8112  * The argument is a softfloat float_round_ value.
8113  */
8114 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8115 {
8116     float_status *fp_status = &env->vfp.fp_status;
8117
8118     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8119     set_float_rounding_mode(rmode, fp_status);
8120
8121     return prev_rmode;
8122 }
8123
8124 /* Set the current fp rounding mode in the standard fp status and return
8125  * the old one. This is for NEON instructions that need to change the
8126  * rounding mode but wish to use the standard FPSCR values for everything
8127  * else. Always set the rounding mode back to the correct value after
8128  * modifying it.
8129  * The argument is a softfloat float_round_ value.
8130  */
8131 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8132 {
8133     float_status *fp_status = &env->vfp.standard_fp_status;
8134
8135     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8136     set_float_rounding_mode(rmode, fp_status);
8137
8138     return prev_rmode;
8139 }
8140
8141 /* Half precision conversions.  */
8142 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8143 {
8144     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8145     float32 r = float16_to_float32(make_float16(a), ieee, s);
8146     if (ieee) {
8147         return float32_maybe_silence_nan(r);
8148     }
8149     return r;
8150 }
8151
8152 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8153 {
8154     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8155     float16 r = float32_to_float16(a, ieee, s);
8156     if (ieee) {
8157         r = float16_maybe_silence_nan(r);
8158     }
8159     return float16_val(r);
8160 }
8161
8162 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8163 {
8164     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8165 }
8166
8167 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8168 {
8169     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8170 }
8171
8172 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8173 {
8174     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8175 }
8176
8177 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8178 {
8179     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8180 }
8181
8182 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8183 {
8184     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8185     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8186     if (ieee) {
8187         return float64_maybe_silence_nan(r);
8188     }
8189     return r;
8190 }
8191
8192 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8193 {
8194     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8195     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8196     if (ieee) {
8197         r = float16_maybe_silence_nan(r);
8198     }
8199     return float16_val(r);
8200 }
8201
8202 #define float32_two make_float32(0x40000000)
8203 #define float32_three make_float32(0x40400000)
8204 #define float32_one_point_five make_float32(0x3fc00000)
8205
8206 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8207 {
8208     float_status *s = &env->vfp.standard_fp_status;
8209     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8210         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8211         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8212             float_raise(float_flag_input_denormal, s);
8213         }
8214         return float32_two;
8215     }
8216     return float32_sub(float32_two, float32_mul(a, b, s), s);
8217 }
8218
8219 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8220 {
8221     float_status *s = &env->vfp.standard_fp_status;
8222     float32 product;
8223     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8224         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8225         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8226             float_raise(float_flag_input_denormal, s);
8227         }
8228         return float32_one_point_five;
8229     }
8230     product = float32_mul(a, b, s);
8231     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8232 }
8233
8234 /* NEON helpers.  */
8235
8236 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8237  * int->float conversions at run-time.  */
8238 #define float64_256 make_float64(0x4070000000000000LL)
8239 #define float64_512 make_float64(0x4080000000000000LL)
8240 #define float32_maxnorm make_float32(0x7f7fffff)
8241 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8242
8243 /* Reciprocal functions
8244  *
8245  * The algorithm that must be used to calculate the estimate
8246  * is specified by the ARM ARM, see FPRecipEstimate()
8247  */
8248
8249 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8250 {
8251     /* These calculations mustn't set any fp exception flags,
8252      * so we use a local copy of the fp_status.
8253      */
8254     float_status dummy_status = *real_fp_status;
8255     float_status *s = &dummy_status;
8256     /* q = (int)(a * 512.0) */
8257     float64 q = float64_mul(float64_512, a, s);
8258     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8259
8260     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8261     q = int64_to_float64(q_int, s);
8262     q = float64_add(q, float64_half, s);
8263     q = float64_div(q, float64_512, s);
8264     q = float64_div(float64_one, q, s);
8265
8266     /* s = (int)(256.0 * r + 0.5) */
8267     q = float64_mul(q, float64_256, s);
8268     q = float64_add(q, float64_half, s);
8269     q_int = float64_to_int64_round_to_zero(q, s);
8270
8271     /* return (double)s / 256.0 */
8272     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8273 }
8274
8275 /* Common wrapper to call recip_estimate */
8276 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8277 {
8278     uint64_t val64 = float64_val(num);
8279     uint64_t frac = extract64(val64, 0, 52);
8280     int64_t exp = extract64(val64, 52, 11);
8281     uint64_t sbit;
8282     float64 scaled, estimate;
8283
8284     /* Generate the scaled number for the estimate function */
8285     if (exp == 0) {
8286         if (extract64(frac, 51, 1) == 0) {
8287             exp = -1;
8288             frac = extract64(frac, 0, 50) << 2;
8289         } else {
8290             frac = extract64(frac, 0, 51) << 1;
8291         }
8292     }
8293
8294     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8295     scaled = make_float64((0x3feULL << 52)
8296                           | extract64(frac, 44, 8) << 44);
8297
8298     estimate = recip_estimate(scaled, fpst);
8299
8300     /* Build new result */
8301     val64 = float64_val(estimate);
8302     sbit = 0x8000000000000000ULL & val64;
8303     exp = off - exp;
8304     frac = extract64(val64, 0, 52);
8305
8306     if (exp == 0) {
8307         frac = 1ULL << 51 | extract64(frac, 1, 51);
8308     } else if (exp == -1) {
8309         frac = 1ULL << 50 | extract64(frac, 2, 50);
8310         exp = 0;
8311     }
8312
8313     return make_float64(sbit | (exp << 52) | frac);
8314 }
8315
8316 static bool round_to_inf(float_status *fpst, bool sign_bit)
8317 {
8318     switch (fpst->float_rounding_mode) {
8319     case float_round_nearest_even: /* Round to Nearest */
8320         return true;
8321     case float_round_up: /* Round to +Inf */
8322         return !sign_bit;
8323     case float_round_down: /* Round to -Inf */
8324         return sign_bit;
8325     case float_round_to_zero: /* Round to Zero */
8326         return false;
8327     }
8328
8329     g_assert_not_reached();
8330 }
8331
8332 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8333 {
8334     float_status *fpst = fpstp;
8335     float32 f32 = float32_squash_input_denormal(input, fpst);
8336     uint32_t f32_val = float32_val(f32);
8337     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8338     int32_t f32_exp = extract32(f32_val, 23, 8);
8339     uint32_t f32_frac = extract32(f32_val, 0, 23);
8340     float64 f64, r64;
8341     uint64_t r64_val;
8342     int64_t r64_exp;
8343     uint64_t r64_frac;
8344
8345     if (float32_is_any_nan(f32)) {
8346         float32 nan = f32;
8347         if (float32_is_signaling_nan(f32)) {
8348             float_raise(float_flag_invalid, fpst);
8349             nan = float32_maybe_silence_nan(f32);
8350         }
8351         if (fpst->default_nan_mode) {
8352             nan =  float32_default_nan;
8353         }
8354         return nan;
8355     } else if (float32_is_infinity(f32)) {
8356         return float32_set_sign(float32_zero, float32_is_neg(f32));
8357     } else if (float32_is_zero(f32)) {
8358         float_raise(float_flag_divbyzero, fpst);
8359         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8360     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8361         /* Abs(value) < 2.0^-128 */
8362         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8363         if (round_to_inf(fpst, f32_sbit)) {
8364             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8365         } else {
8366             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8367         }
8368     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8369         float_raise(float_flag_underflow, fpst);
8370         return float32_set_sign(float32_zero, float32_is_neg(f32));
8371     }
8372
8373
8374     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8375     r64 = call_recip_estimate(f64, 253, fpst);
8376     r64_val = float64_val(r64);
8377     r64_exp = extract64(r64_val, 52, 11);
8378     r64_frac = extract64(r64_val, 0, 52);
8379
8380     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8381     return make_float32(f32_sbit |
8382                         (r64_exp & 0xff) << 23 |
8383                         extract64(r64_frac, 29, 24));
8384 }
8385
8386 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8387 {
8388     float_status *fpst = fpstp;
8389     float64 f64 = float64_squash_input_denormal(input, fpst);
8390     uint64_t f64_val = float64_val(f64);
8391     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
8392     int64_t f64_exp = extract64(f64_val, 52, 11);
8393     float64 r64;
8394     uint64_t r64_val;
8395     int64_t r64_exp;
8396     uint64_t r64_frac;
8397
8398     /* Deal with any special cases */
8399     if (float64_is_any_nan(f64)) {
8400         float64 nan = f64;
8401         if (float64_is_signaling_nan(f64)) {
8402             float_raise(float_flag_invalid, fpst);
8403             nan = float64_maybe_silence_nan(f64);
8404         }
8405         if (fpst->default_nan_mode) {
8406             nan =  float64_default_nan;
8407         }
8408         return nan;
8409     } else if (float64_is_infinity(f64)) {
8410         return float64_set_sign(float64_zero, float64_is_neg(f64));
8411     } else if (float64_is_zero(f64)) {
8412         float_raise(float_flag_divbyzero, fpst);
8413         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8414     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
8415         /* Abs(value) < 2.0^-1024 */
8416         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8417         if (round_to_inf(fpst, f64_sbit)) {
8418             return float64_set_sign(float64_infinity, float64_is_neg(f64));
8419         } else {
8420             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
8421         }
8422     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
8423         float_raise(float_flag_underflow, fpst);
8424         return float64_set_sign(float64_zero, float64_is_neg(f64));
8425     }
8426
8427     r64 = call_recip_estimate(f64, 2045, fpst);
8428     r64_val = float64_val(r64);
8429     r64_exp = extract64(r64_val, 52, 11);
8430     r64_frac = extract64(r64_val, 0, 52);
8431
8432     /* result = sign : result_exp<10:0> : fraction<51:0> */
8433     return make_float64(f64_sbit |
8434                         ((r64_exp & 0x7ff) << 52) |
8435                         r64_frac);
8436 }
8437
8438 /* The algorithm that must be used to calculate the estimate
8439  * is specified by the ARM ARM.
8440  */
8441 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
8442 {
8443     /* These calculations mustn't set any fp exception flags,
8444      * so we use a local copy of the fp_status.
8445      */
8446     float_status dummy_status = *real_fp_status;
8447     float_status *s = &dummy_status;
8448     float64 q;
8449     int64_t q_int;
8450
8451     if (float64_lt(a, float64_half, s)) {
8452         /* range 0.25 <= a < 0.5 */
8453
8454         /* a in units of 1/512 rounded down */
8455         /* q0 = (int)(a * 512.0);  */
8456         q = float64_mul(float64_512, a, s);
8457         q_int = float64_to_int64_round_to_zero(q, s);
8458
8459         /* reciprocal root r */
8460         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
8461         q = int64_to_float64(q_int, s);
8462         q = float64_add(q, float64_half, s);
8463         q = float64_div(q, float64_512, s);
8464         q = float64_sqrt(q, s);
8465         q = float64_div(float64_one, q, s);
8466     } else {
8467         /* range 0.5 <= a < 1.0 */
8468
8469         /* a in units of 1/256 rounded down */
8470         /* q1 = (int)(a * 256.0); */
8471         q = float64_mul(float64_256, a, s);
8472         int64_t q_int = float64_to_int64_round_to_zero(q, s);
8473
8474         /* reciprocal root r */
8475         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8476         q = int64_to_float64(q_int, s);
8477         q = float64_add(q, float64_half, s);
8478         q = float64_div(q, float64_256, s);
8479         q = float64_sqrt(q, s);
8480         q = float64_div(float64_one, q, s);
8481     }
8482     /* r in units of 1/256 rounded to nearest */
8483     /* s = (int)(256.0 * r + 0.5); */
8484
8485     q = float64_mul(q, float64_256,s );
8486     q = float64_add(q, float64_half, s);
8487     q_int = float64_to_int64_round_to_zero(q, s);
8488
8489     /* return (double)s / 256.0;*/
8490     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8491 }
8492
8493 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
8494 {
8495     float_status *s = fpstp;
8496     float32 f32 = float32_squash_input_denormal(input, s);
8497     uint32_t val = float32_val(f32);
8498     uint32_t f32_sbit = 0x80000000 & val;
8499     int32_t f32_exp = extract32(val, 23, 8);
8500     uint32_t f32_frac = extract32(val, 0, 23);
8501     uint64_t f64_frac;
8502     uint64_t val64;
8503     int result_exp;
8504     float64 f64;
8505
8506     if (float32_is_any_nan(f32)) {
8507         float32 nan = f32;
8508         if (float32_is_signaling_nan(f32)) {
8509             float_raise(float_flag_invalid, s);
8510             nan = float32_maybe_silence_nan(f32);
8511         }
8512         if (s->default_nan_mode) {
8513             nan =  float32_default_nan;
8514         }
8515         return nan;
8516     } else if (float32_is_zero(f32)) {
8517         float_raise(float_flag_divbyzero, s);
8518         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8519     } else if (float32_is_neg(f32)) {
8520         float_raise(float_flag_invalid, s);
8521         return float32_default_nan;
8522     } else if (float32_is_infinity(f32)) {
8523         return float32_zero;
8524     }
8525
8526     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8527      * preserving the parity of the exponent.  */
8528
8529     f64_frac = ((uint64_t) f32_frac) << 29;
8530     if (f32_exp == 0) {
8531         while (extract64(f64_frac, 51, 1) == 0) {
8532             f64_frac = f64_frac << 1;
8533             f32_exp = f32_exp-1;
8534         }
8535         f64_frac = extract64(f64_frac, 0, 51) << 1;
8536     }
8537
8538     if (extract64(f32_exp, 0, 1) == 0) {
8539         f64 = make_float64(((uint64_t) f32_sbit) << 32
8540                            | (0x3feULL << 52)
8541                            | f64_frac);
8542     } else {
8543         f64 = make_float64(((uint64_t) f32_sbit) << 32
8544                            | (0x3fdULL << 52)
8545                            | f64_frac);
8546     }
8547
8548     result_exp = (380 - f32_exp) / 2;
8549
8550     f64 = recip_sqrt_estimate(f64, s);
8551
8552     val64 = float64_val(f64);
8553
8554     val = ((result_exp & 0xff) << 23)
8555         | ((val64 >> 29)  & 0x7fffff);
8556     return make_float32(val);
8557 }
8558
8559 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
8560 {
8561     float_status *s = fpstp;
8562     float64 f64 = float64_squash_input_denormal(input, s);
8563     uint64_t val = float64_val(f64);
8564     uint64_t f64_sbit = 0x8000000000000000ULL & val;
8565     int64_t f64_exp = extract64(val, 52, 11);
8566     uint64_t f64_frac = extract64(val, 0, 52);
8567     int64_t result_exp;
8568     uint64_t result_frac;
8569
8570     if (float64_is_any_nan(f64)) {
8571         float64 nan = f64;
8572         if (float64_is_signaling_nan(f64)) {
8573             float_raise(float_flag_invalid, s);
8574             nan = float64_maybe_silence_nan(f64);
8575         }
8576         if (s->default_nan_mode) {
8577             nan =  float64_default_nan;
8578         }
8579         return nan;
8580     } else if (float64_is_zero(f64)) {
8581         float_raise(float_flag_divbyzero, s);
8582         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8583     } else if (float64_is_neg(f64)) {
8584         float_raise(float_flag_invalid, s);
8585         return float64_default_nan;
8586     } else if (float64_is_infinity(f64)) {
8587         return float64_zero;
8588     }
8589
8590     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8591      * preserving the parity of the exponent.  */
8592
8593     if (f64_exp == 0) {
8594         while (extract64(f64_frac, 51, 1) == 0) {
8595             f64_frac = f64_frac << 1;
8596             f64_exp = f64_exp - 1;
8597         }
8598         f64_frac = extract64(f64_frac, 0, 51) << 1;
8599     }
8600
8601     if (extract64(f64_exp, 0, 1) == 0) {
8602         f64 = make_float64(f64_sbit
8603                            | (0x3feULL << 52)
8604                            | f64_frac);
8605     } else {
8606         f64 = make_float64(f64_sbit
8607                            | (0x3fdULL << 52)
8608                            | f64_frac);
8609     }
8610
8611     result_exp = (3068 - f64_exp) / 2;
8612
8613     f64 = recip_sqrt_estimate(f64, s);
8614
8615     result_frac = extract64(float64_val(f64), 0, 52);
8616
8617     return make_float64(f64_sbit |
8618                         ((result_exp & 0x7ff) << 52) |
8619                         result_frac);
8620 }
8621
8622 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
8623 {
8624     float_status *s = fpstp;
8625     float64 f64;
8626
8627     if ((a & 0x80000000) == 0) {
8628         return 0xffffffff;
8629     }
8630
8631     f64 = make_float64((0x3feULL << 52)
8632                        | ((int64_t)(a & 0x7fffffff) << 21));
8633
8634     f64 = recip_estimate(f64, s);
8635
8636     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8637 }
8638
8639 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
8640 {
8641     float_status *fpst = fpstp;
8642     float64 f64;
8643
8644     if ((a & 0xc0000000) == 0) {
8645         return 0xffffffff;
8646     }
8647
8648     if (a & 0x80000000) {
8649         f64 = make_float64((0x3feULL << 52)
8650                            | ((uint64_t)(a & 0x7fffffff) << 21));
8651     } else { /* bits 31-30 == '01' */
8652         f64 = make_float64((0x3fdULL << 52)
8653                            | ((uint64_t)(a & 0x3fffffff) << 22));
8654     }
8655
8656     f64 = recip_sqrt_estimate(f64, fpst);
8657
8658     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
8659 }
8660
8661 /* VFPv4 fused multiply-accumulate */
8662 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
8663 {
8664     float_status *fpst = fpstp;
8665     return float32_muladd(a, b, c, 0, fpst);
8666 }
8667
8668 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
8669 {
8670     float_status *fpst = fpstp;
8671     return float64_muladd(a, b, c, 0, fpst);
8672 }
8673
8674 /* ARMv8 round to integral */
8675 float32 HELPER(rints_exact)(float32 x, void *fp_status)
8676 {
8677     return float32_round_to_int(x, fp_status);
8678 }
8679
8680 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
8681 {
8682     return float64_round_to_int(x, fp_status);
8683 }
8684
8685 float32 HELPER(rints)(float32 x, void *fp_status)
8686 {
8687     int old_flags = get_float_exception_flags(fp_status), new_flags;
8688     float32 ret;
8689
8690     ret = float32_round_to_int(x, fp_status);
8691
8692     /* Suppress any inexact exceptions the conversion produced */
8693     if (!(old_flags & float_flag_inexact)) {
8694         new_flags = get_float_exception_flags(fp_status);
8695         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8696     }
8697
8698     return ret;
8699 }
8700
8701 float64 HELPER(rintd)(float64 x, void *fp_status)
8702 {
8703     int old_flags = get_float_exception_flags(fp_status), new_flags;
8704     float64 ret;
8705
8706     ret = float64_round_to_int(x, fp_status);
8707
8708     new_flags = get_float_exception_flags(fp_status);
8709
8710     /* Suppress any inexact exceptions the conversion produced */
8711     if (!(old_flags & float_flag_inexact)) {
8712         new_flags = get_float_exception_flags(fp_status);
8713         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
8714     }
8715
8716     return ret;
8717 }
8718
8719 /* Convert ARM rounding mode to softfloat */
8720 int arm_rmode_to_sf(int rmode)
8721 {
8722     switch (rmode) {
8723     case FPROUNDING_TIEAWAY:
8724         rmode = float_round_ties_away;
8725         break;
8726     case FPROUNDING_ODD:
8727         /* FIXME: add support for TIEAWAY and ODD */
8728         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
8729                       rmode);
8730     case FPROUNDING_TIEEVEN:
8731     default:
8732         rmode = float_round_nearest_even;
8733         break;
8734     case FPROUNDING_POSINF:
8735         rmode = float_round_up;
8736         break;
8737     case FPROUNDING_NEGINF:
8738         rmode = float_round_down;
8739         break;
8740     case FPROUNDING_ZERO:
8741         rmode = float_round_to_zero;
8742         break;
8743     }
8744     return rmode;
8745 }
8746
8747 /* CRC helpers.
8748  * The upper bytes of val (above the number specified by 'bytes') must have
8749  * been zeroed out by the caller.
8750  */
8751 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
8752 {
8753     uint8_t buf[4];
8754
8755     stl_le_p(buf, val);
8756
8757     /* zlib crc32 converts the accumulator and output to one's complement.  */
8758     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
8759 }
8760
8761 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
8762 {
8763     uint8_t buf[4];
8764
8765     stl_le_p(buf, val);
8766
8767     /* Linux crc32c converts the output to one's complement.  */
8768     return crc32c(acc, buf, bytes) ^ 0xffffffff;
8769 }