hw/ppc4xx_devs.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors shared devices emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc4xx.h"
  27 #include "qemu/log.h"
  28 #include "exec/address-spaces.h"
  29
  30 //#define DEBUG_MMIO
  31 //#define DEBUG_UNASSIGNED
  32 #define DEBUG_UIC
  33
  34
  35 #ifdef DEBUG_UIC
  36 #  define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
  37 #else
  38 #  define LOG_UIC(...) do { } while (0)
  39 #endif
  40
  41 static void ppc4xx_reset(void *opaque)
  42 {
  43     PowerPCCPU *cpu = opaque;
  44
  45     cpu_reset(CPU(cpu));
  46 }
  47
  48 /*****************************************************************************/
  49 /* Generic PowerPC 4xx processor instantiation */
  50 CPUPPCState *ppc4xx_init (const char *cpu_model,
  51                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  52                        uint32_t sysclk)
  53 {
  54     PowerPCCPU *cpu;
  55     CPUPPCState *env;
  56
  57     /* init CPUs */
  58     cpu = cpu_ppc_init(cpu_model);
  59     if (cpu == NULL) {
  60         fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
  61                 cpu_model);
  62         exit(1);
  63     }
  64     env = &cpu->env;
  65
  66     cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
  67     cpu_clk->opaque = env;
  68     /* Set time-base frequency to sysclk */
  69     tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
  70     tb_clk->opaque = env;
  71     ppc_dcr_init(env, NULL, NULL);
  72     /* Register qemu callbacks */
  73     qemu_register_reset(ppc4xx_reset, cpu);
  74
  75     return env;
  76 }
  77
  78 /*****************************************************************************/
  79 /* "Universal" Interrupt controller */
  80 enum {
  81     DCR_UICSR  = 0x000,
  82     DCR_UICSRS = 0x001,
  83     DCR_UICER  = 0x002,
  84     DCR_UICCR  = 0x003,
  85     DCR_UICPR  = 0x004,
  86     DCR_UICTR  = 0x005,
  87     DCR_UICMSR = 0x006,
  88     DCR_UICVR  = 0x007,
  89     DCR_UICVCR = 0x008,
  90     DCR_UICMAX = 0x009,
  91 };
  92
  93 #define UIC_MAX_IRQ 32
  94 typedef struct ppcuic_t ppcuic_t;
  95 struct ppcuic_t {
  96     uint32_t dcr_base;
  97     int use_vectors;
  98     uint32_t level;  /* Remembers the state of level-triggered interrupts. */
  99     uint32_t uicsr;  /* Status register */
 100     uint32_t uicer;  /* Enable register */
 101     uint32_t uiccr;  /* Critical register */
 102     uint32_t uicpr;  /* Polarity register */
 103     uint32_t uictr;  /* Triggering register */
 104     uint32_t uicvcr; /* Vector configuration register */
 105     uint32_t uicvr;
 106     qemu_irq *irqs;
 107 };
 108
 109 static void ppcuic_trigger_irq (ppcuic_t *uic)
 110 {
 111     uint32_t ir, cr;
 112     int start, end, inc, i;
 113
 114     /* Trigger interrupt if any is pending */
 115     ir = uic->uicsr & uic->uicer & (~uic->uiccr);
 116     cr = uic->uicsr & uic->uicer & uic->uiccr;
 117     LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
 118                 " uiccr %08" PRIx32 "\n"
 119                 "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
 120                 __func__, uic->uicsr, uic->uicer, uic->uiccr,
 121                 uic->uicsr & uic->uicer, ir, cr);
 122     if (ir != 0x0000000) {
 123         LOG_UIC("Raise UIC interrupt\n");
 124         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
 125     } else {
 126         LOG_UIC("Lower UIC interrupt\n");
 127         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
 128     }
 129     /* Trigger critical interrupt if any is pending and update vector */
 130     if (cr != 0x0000000) {
 131         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
 132         if (uic->use_vectors) {
 133             /* Compute critical IRQ vector */
 134             if (uic->uicvcr & 1) {
 135                 start = 31;
 136                 end = 0;
 137                 inc = -1;
 138             } else {
 139                 start = 0;
 140                 end = 31;
 141                 inc = 1;
 142             }
 143             uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
 144             for (i = start; i <= end; i += inc) {
 145                 if (cr & (1 << i)) {
 146                     uic->uicvr += (i - start) * 512 * inc;
 147                     break;
 148                 }
 149             }
 150         }
 151         LOG_UIC("Raise UIC critical interrupt - "
 152                     "vector %08" PRIx32 "\n", uic->uicvr);
 153     } else {
 154         LOG_UIC("Lower UIC critical interrupt\n");
 155         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
 156         uic->uicvr = 0x00000000;
 157     }
 158 }
 159
 160 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
 161 {
 162     ppcuic_t *uic;
 163     uint32_t mask, sr;
 164
 165     uic = opaque;
 166     mask = 1 << (31-irq_num);
 167     LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
 168                 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
 169                 __func__, irq_num, level,
 170                 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
 171     if (irq_num < 0 || irq_num > 31)
 172         return;
 173     sr = uic->uicsr;
 174
 175     /* Update status register */
 176     if (uic->uictr & mask) {
 177         /* Edge sensitive interrupt */
 178         if (level == 1)
 179             uic->uicsr |= mask;
 180     } else {
 181         /* Level sensitive interrupt */
 182         if (level == 1) {
 183             uic->uicsr |= mask;
 184             uic->level |= mask;
 185         } else {
 186             uic->uicsr &= ~mask;
 187             uic->level &= ~mask;
 188         }
 189     }
 190     LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
 191                 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
 192     if (sr != uic->uicsr)
 193         ppcuic_trigger_irq(uic);
 194 }
 195
 196 static uint32_t dcr_read_uic (void *opaque, int dcrn)
 197 {
 198     ppcuic_t *uic;
 199     uint32_t ret;
 200
 201     uic = opaque;
 202     dcrn -= uic->dcr_base;
 203     switch (dcrn) {
 204     case DCR_UICSR:
 205     case DCR_UICSRS:
 206         ret = uic->uicsr;
 207         break;
 208     case DCR_UICER:
 209         ret = uic->uicer;
 210         break;
 211     case DCR_UICCR:
 212         ret = uic->uiccr;
 213         break;
 214     case DCR_UICPR:
 215         ret = uic->uicpr;
 216         break;
 217     case DCR_UICTR:
 218         ret = uic->uictr;
 219         break;
 220     case DCR_UICMSR:
 221         ret = uic->uicsr & uic->uicer;
 222         break;
 223     case DCR_UICVR:
 224         if (!uic->use_vectors)
 225             goto no_read;
 226         ret = uic->uicvr;
 227         break;
 228     case DCR_UICVCR:
 229         if (!uic->use_vectors)
 230             goto no_read;
 231         ret = uic->uicvcr;
 232         break;
 233     default:
 234     no_read:
 235         ret = 0x00000000;
 236         break;
 237     }
 238
 239     return ret;
 240 }
 241
 242 static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
 243 {
 244     ppcuic_t *uic;
 245
 246     uic = opaque;
 247     dcrn -= uic->dcr_base;
 248     LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
 249     switch (dcrn) {
 250     case DCR_UICSR:
 251         uic->uicsr &= ~val;
 252         uic->uicsr |= uic->level;
 253         ppcuic_trigger_irq(uic);
 254         break;
 255     case DCR_UICSRS:
 256         uic->uicsr |= val;
 257         ppcuic_trigger_irq(uic);
 258         break;
 259     case DCR_UICER:
 260         uic->uicer = val;
 261         ppcuic_trigger_irq(uic);
 262         break;
 263     case DCR_UICCR:
 264         uic->uiccr = val;
 265         ppcuic_trigger_irq(uic);
 266         break;
 267     case DCR_UICPR:
 268         uic->uicpr = val;
 269         break;
 270     case DCR_UICTR:
 271         uic->uictr = val;
 272         ppcuic_trigger_irq(uic);
 273         break;
 274     case DCR_UICMSR:
 275         break;
 276     case DCR_UICVR:
 277         break;
 278     case DCR_UICVCR:
 279         uic->uicvcr = val & 0xFFFFFFFD;
 280         ppcuic_trigger_irq(uic);
 281         break;
 282     }
 283 }
 284
 285 static void ppcuic_reset (void *opaque)
 286 {
 287     ppcuic_t *uic;
 288
 289     uic = opaque;
 290     uic->uiccr = 0x00000000;
 291     uic->uicer = 0x00000000;
 292     uic->uicpr = 0x00000000;
 293     uic->uicsr = 0x00000000;
 294     uic->uictr = 0x00000000;
 295     if (uic->use_vectors) {
 296         uic->uicvcr = 0x00000000;
 297         uic->uicvr = 0x0000000;
 298     }
 299 }
 300
 301 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
 302                        uint32_t dcr_base, int has_ssr, int has_vr)
 303 {
 304     ppcuic_t *uic;
 305     int i;
 306
 307     uic = g_malloc0(sizeof(ppcuic_t));
 308     uic->dcr_base = dcr_base;
 309     uic->irqs = irqs;
 310     if (has_vr)
 311         uic->use_vectors = 1;
 312     for (i = 0; i < DCR_UICMAX; i++) {
 313         ppc_dcr_register(env, dcr_base + i, uic,
 314                          &dcr_read_uic, &dcr_write_uic);
 315     }
 316     qemu_register_reset(ppcuic_reset, uic);
 317
 318     return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
 319 }
 320
 321 /*****************************************************************************/
 322 /* SDRAM controller */
 323 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
 324 struct ppc4xx_sdram_t {
 325     uint32_t addr;
 326     int nbanks;
 327     MemoryRegion containers[4]; /* used for clipping */
 328     MemoryRegion *ram_memories;
 329     hwaddr ram_bases[4];
 330     hwaddr ram_sizes[4];
 331     uint32_t besr0;
 332     uint32_t besr1;
 333     uint32_t bear;
 334     uint32_t cfg;
 335     uint32_t status;
 336     uint32_t rtr;
 337     uint32_t pmit;
 338     uint32_t bcr[4];
 339     uint32_t tr;
 340     uint32_t ecccfg;
 341     uint32_t eccesr;
 342     qemu_irq irq;
 343 };
 344
 345 enum {
 346     SDRAM0_CFGADDR = 0x010,
 347     SDRAM0_CFGDATA = 0x011,
 348 };
 349
 350 /* XXX: TOFIX: some patches have made this code become inconsistent:
 351  *      there are type inconsistencies, mixing hwaddr, target_ulong
 352  *      and uint32_t
 353  */
 354 static uint32_t sdram_bcr (hwaddr ram_base,
 355                            hwaddr ram_size)
 356 {
 357     uint32_t bcr;
 358
 359     switch (ram_size) {
 360     case (4 * 1024 * 1024):
 361         bcr = 0x00000000;
 362         break;
 363     case (8 * 1024 * 1024):
 364         bcr = 0x00020000;
 365         break;
 366     case (16 * 1024 * 1024):
 367         bcr = 0x00040000;
 368         break;
 369     case (32 * 1024 * 1024):
 370         bcr = 0x00060000;
 371         break;
 372     case (64 * 1024 * 1024):
 373         bcr = 0x00080000;
 374         break;
 375     case (128 * 1024 * 1024):
 376         bcr = 0x000A0000;
 377         break;
 378     case (256 * 1024 * 1024):
 379         bcr = 0x000C0000;
 380         break;
 381     default:
 382         printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
 383                ram_size);
 384         return 0x00000000;
 385     }
 386     bcr |= ram_base & 0xFF800000;
 387     bcr |= 1;
 388
 389     return bcr;
 390 }
 391
 392 static inline hwaddr sdram_base(uint32_t bcr)
 393 {
 394     return bcr & 0xFF800000;
 395 }
 396
 397 static target_ulong sdram_size (uint32_t bcr)
 398 {
 399     target_ulong size;
 400     int sh;
 401
 402     sh = (bcr >> 17) & 0x7;
 403     if (sh == 7)
 404         size = -1;
 405     else
 406         size = (4 * 1024 * 1024) << sh;
 407
 408     return size;
 409 }
 410
 411 static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
 412                           uint32_t *bcrp, uint32_t bcr, int enabled)
 413 {
 414     unsigned n = bcrp - sdram->bcr;
 415
 416     if (*bcrp & 0x00000001) {
 417         /* Unmap RAM */
 418 #ifdef DEBUG_SDRAM
 419         printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 420                __func__, sdram_base(*bcrp), sdram_size(*bcrp));
 421 #endif
 422         memory_region_del_subregion(get_system_memory(),
 423                                     &sdram->containers[n]);
 424         memory_region_del_subregion(&sdram->containers[n],
 425                                     &sdram->ram_memories[n]);
 426         memory_region_destroy(&sdram->containers[n]);
 427     }
 428     *bcrp = bcr & 0xFFDEE001;
 429     if (enabled && (bcr & 0x00000001)) {
 430 #ifdef DEBUG_SDRAM
 431         printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 432                __func__, sdram_base(bcr), sdram_size(bcr));
 433 #endif
 434         memory_region_init(&sdram->containers[n], "sdram-containers",
 435                            sdram_size(bcr));
 436         memory_region_add_subregion(&sdram->containers[n], 0,
 437                                     &sdram->ram_memories[n]);
 438         memory_region_add_subregion(get_system_memory(),
 439                                     sdram_base(bcr),
 440                                     &sdram->containers[n]);
 441     }
 442 }
 443
 444 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
 445 {
 446     int i;
 447
 448     for (i = 0; i < sdram->nbanks; i++) {
 449         if (sdram->ram_sizes[i] != 0) {
 450             sdram_set_bcr(sdram,
 451                           &sdram->bcr[i],
 452                           sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
 453                           1);
 454         } else {
 455             sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
 456         }
 457     }
 458 }
 459
 460 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
 461 {
 462     int i;
 463
 464     for (i = 0; i < sdram->nbanks; i++) {
 465 #ifdef DEBUG_SDRAM
 466         printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 467                __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
 468 #endif
 469         memory_region_del_subregion(get_system_memory(),
 470                                     &sdram->ram_memories[i]);
 471     }
 472 }
 473
 474 static uint32_t dcr_read_sdram (void *opaque, int dcrn)
 475 {
 476     ppc4xx_sdram_t *sdram;
 477     uint32_t ret;
 478
 479     sdram = opaque;
 480     switch (dcrn) {
 481     case SDRAM0_CFGADDR:
 482         ret = sdram->addr;
 483         break;
 484     case SDRAM0_CFGDATA:
 485         switch (sdram->addr) {
 486         case 0x00: /* SDRAM_BESR0 */
 487             ret = sdram->besr0;
 488             break;
 489         case 0x08: /* SDRAM_BESR1 */
 490             ret = sdram->besr1;
 491             break;
 492         case 0x10: /* SDRAM_BEAR */
 493             ret = sdram->bear;
 494             break;
 495         case 0x20: /* SDRAM_CFG */
 496             ret = sdram->cfg;
 497             break;
 498         case 0x24: /* SDRAM_STATUS */
 499             ret = sdram->status;
 500             break;
 501         case 0x30: /* SDRAM_RTR */
 502             ret = sdram->rtr;
 503             break;
 504         case 0x34: /* SDRAM_PMIT */
 505             ret = sdram->pmit;
 506             break;
 507         case 0x40: /* SDRAM_B0CR */
 508             ret = sdram->bcr[0];
 509             break;
 510         case 0x44: /* SDRAM_B1CR */
 511             ret = sdram->bcr[1];
 512             break;
 513         case 0x48: /* SDRAM_B2CR */
 514             ret = sdram->bcr[2];
 515             break;
 516         case 0x4C: /* SDRAM_B3CR */
 517             ret = sdram->bcr[3];
 518             break;
 519         case 0x80: /* SDRAM_TR */
 520             ret = -1; /* ? */
 521             break;
 522         case 0x94: /* SDRAM_ECCCFG */
 523             ret = sdram->ecccfg;
 524             break;
 525         case 0x98: /* SDRAM_ECCESR */
 526             ret = sdram->eccesr;
 527             break;
 528         default: /* Error */
 529             ret = -1;
 530             break;
 531         }
 532         break;
 533     default:
 534         /* Avoid gcc warning */
 535         ret = 0x00000000;
 536         break;
 537     }
 538
 539     return ret;
 540 }
 541
 542 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
 543 {
 544     ppc4xx_sdram_t *sdram;
 545
 546     sdram = opaque;
 547     switch (dcrn) {
 548     case SDRAM0_CFGADDR:
 549         sdram->addr = val;
 550         break;
 551     case SDRAM0_CFGDATA:
 552         switch (sdram->addr) {
 553         case 0x00: /* SDRAM_BESR0 */
 554             sdram->besr0 &= ~val;
 555             break;
 556         case 0x08: /* SDRAM_BESR1 */
 557             sdram->besr1 &= ~val;
 558             break;
 559         case 0x10: /* SDRAM_BEAR */
 560             sdram->bear = val;
 561             break;
 562         case 0x20: /* SDRAM_CFG */
 563             val &= 0xFFE00000;
 564             if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
 565 #ifdef DEBUG_SDRAM
 566                 printf("%s: enable SDRAM controller\n", __func__);
 567 #endif
 568                 /* validate all RAM mappings */
 569                 sdram_map_bcr(sdram);
 570                 sdram->status &= ~0x80000000;
 571             } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
 572 #ifdef DEBUG_SDRAM
 573                 printf("%s: disable SDRAM controller\n", __func__);
 574 #endif
 575                 /* invalidate all RAM mappings */
 576                 sdram_unmap_bcr(sdram);
 577                 sdram->status |= 0x80000000;
 578             }
 579             if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
 580                 sdram->status |= 0x40000000;
 581             else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
 582                 sdram->status &= ~0x40000000;
 583             sdram->cfg = val;
 584             break;
 585         case 0x24: /* SDRAM_STATUS */
 586             /* Read-only register */
 587             break;
 588         case 0x30: /* SDRAM_RTR */
 589             sdram->rtr = val & 0x3FF80000;
 590             break;
 591         case 0x34: /* SDRAM_PMIT */
 592             sdram->pmit = (val & 0xF8000000) | 0x07C00000;
 593             break;
 594         case 0x40: /* SDRAM_B0CR */
 595             sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
 596             break;
 597         case 0x44: /* SDRAM_B1CR */
 598             sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
 599             break;
 600         case 0x48: /* SDRAM_B2CR */
 601             sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
 602             break;
 603         case 0x4C: /* SDRAM_B3CR */
 604             sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
 605             break;
 606         case 0x80: /* SDRAM_TR */
 607             sdram->tr = val & 0x018FC01F;
 608             break;
 609         case 0x94: /* SDRAM_ECCCFG */
 610             sdram->ecccfg = val & 0x00F00000;
 611             break;
 612         case 0x98: /* SDRAM_ECCESR */
 613             val &= 0xFFF0F000;
 614             if (sdram->eccesr == 0 && val != 0)
 615                 qemu_irq_raise(sdram->irq);
 616             else if (sdram->eccesr != 0 && val == 0)
 617                 qemu_irq_lower(sdram->irq);
 618             sdram->eccesr = val;
 619             break;
 620         default: /* Error */
 621             break;
 622         }
 623         break;
 624     }
 625 }
 626
 627 static void sdram_reset (void *opaque)
 628 {
 629     ppc4xx_sdram_t *sdram;
 630
 631     sdram = opaque;
 632     sdram->addr = 0x00000000;
 633     sdram->bear = 0x00000000;
 634     sdram->besr0 = 0x00000000; /* No error */
 635     sdram->besr1 = 0x00000000; /* No error */
 636     sdram->cfg = 0x00000000;
 637     sdram->ecccfg = 0x00000000; /* No ECC */
 638     sdram->eccesr = 0x00000000; /* No error */
 639     sdram->pmit = 0x07C00000;
 640     sdram->rtr = 0x05F00000;
 641     sdram->tr = 0x00854009;
 642     /* We pre-initialize RAM banks */
 643     sdram->status = 0x00000000;
 644     sdram->cfg = 0x00800000;
 645 }
 646
 647 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
 648                         MemoryRegion *ram_memories,
 649                         hwaddr *ram_bases,
 650                         hwaddr *ram_sizes,
 651                         int do_init)
 652 {
 653     ppc4xx_sdram_t *sdram;
 654
 655     sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
 656     sdram->irq = irq;
 657     sdram->nbanks = nbanks;
 658     sdram->ram_memories = ram_memories;
 659     memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
 660     memcpy(sdram->ram_bases, ram_bases,
 661            nbanks * sizeof(hwaddr));
 662     memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
 663     memcpy(sdram->ram_sizes, ram_sizes,
 664            nbanks * sizeof(hwaddr));
 665     qemu_register_reset(&sdram_reset, sdram);
 666     ppc_dcr_register(env, SDRAM0_CFGADDR,
 667                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 668     ppc_dcr_register(env, SDRAM0_CFGDATA,
 669                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 670     if (do_init)
 671         sdram_map_bcr(sdram);
 672 }
 673
 674 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
 675  *
 676  * sdram_bank_sizes[] must be 0-terminated.
 677  *
 678  * The 4xx SDRAM controller supports a small number of banks, and each bank
 679  * must be one of a small set of sizes. The number of banks and the supported
 680  * sizes varies by SoC. */
 681 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
 682                                MemoryRegion ram_memories[],
 683                                hwaddr ram_bases[],
 684                                hwaddr ram_sizes[],
 685                                const unsigned int sdram_bank_sizes[])
 686 {
 687     ram_addr_t size_left = ram_size;
 688     ram_addr_t base = 0;
 689     int i;
 690     int j;
 691
 692     for (i = 0; i < nr_banks; i++) {
 693         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
 694             unsigned int bank_size = sdram_bank_sizes[j];
 695
 696             if (bank_size <= size_left) {
 697                 char name[32];
 698                 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
 699                 memory_region_init_ram(&ram_memories[i], name, bank_size);
 700                 vmstate_register_ram_global(&ram_memories[i]);
 701                 ram_bases[i] = base;
 702                 ram_sizes[i] = bank_size;
 703                 base += ram_size;
 704                 size_left -= bank_size;
 705                 break;
 706             }
 707         }
 708
 709         if (!size_left) {
 710             /* No need to use the remaining banks. */
 711             break;
 712         }
 713     }
 714
 715     ram_size -= size_left;
 716     if (size_left)
 717         printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
 718                (int)(ram_size >> 20));
 719
 720     return ram_size;
 721 }