hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/arm.h"
  24 #include "hw/devices.h"
  25 #include "hw/loader.h"
  26 #include "net/net.h"
  27 #include "sysemu/kvm.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/boards.h"
  30 #include "sysemu/block-backend.h"
  31 #include "exec/address-spaces.h"
  32 #include "qemu/error-report.h"
  33
  34 #define SMP_BOOT_ADDR           0x100
  35 #define SMP_BOOT_REG            0x40
  36 #define MPCORE_PERIPHBASE       0xfff10000
  37
  38 #define MVBAR_ADDR              0x200
  39 #define BOARD_SETUP_ADDR        (MVBAR_ADDR + 8 * sizeof(uint32_t))
  40
  41 #define NIRQ_GIC                160
  42
  43 /* Board init.  */
  44
  45 static void hb_write_board_setup(ARMCPU *cpu,
  46                                  const struct arm_boot_info *info)
  47 {
  48     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
  49 }
  50
  51 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  52 {
  53     int n;
  54     uint32_t smpboot[] = {
  55         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  56         0xe210000f, /* ands r0, r0, #0x0f */
  57         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  58         0xe0830200, /* add r0, r3, r0, lsl #4 */
  59         0xe59f2024, /* ldr r2, privbase */
  60         0xe3a01001, /* mov r1, #1 */
  61         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  62         0xe3a010ff, /* mov r1, #0xff */
  63         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  64         0xf57ff04f, /* dsb */
  65         0xe320f003, /* wfi */
  66         0xe5901000, /* ldr     r1, [r0] */
  67         0xe1110001, /* tst     r1, r1 */
  68         0x0afffffb, /* beq     <wfi> */
  69         0xe12fff11, /* bx      r1 */
  70         MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
  71     };
  72     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  73         smpboot[n] = tswap32(smpboot[n]);
  74     }
  75     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  76 }
  77
  78 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  79 {
  80     CPUARMState *env = &cpu->env;
  81
  82     switch (info->nb_cpus) {
  83     case 4:
  84         address_space_stl_notdirty(&address_space_memory,
  85                                    SMP_BOOT_REG + 0x30, 0,
  86                                    MEMTXATTRS_UNSPECIFIED, NULL);
  87     case 3:
  88         address_space_stl_notdirty(&address_space_memory,
  89                                    SMP_BOOT_REG + 0x20, 0,
  90                                    MEMTXATTRS_UNSPECIFIED, NULL);
  91     case 2:
  92         address_space_stl_notdirty(&address_space_memory,
  93                                    SMP_BOOT_REG + 0x10, 0,
  94                                    MEMTXATTRS_UNSPECIFIED, NULL);
  95         env->regs[15] = SMP_BOOT_ADDR;
  96         break;
  97     default:
  98         break;
  99     }
 100 }
 101
 102 #define NUM_REGS      0x200
 103 static void hb_regs_write(void *opaque, hwaddr offset,
 104                           uint64_t value, unsigned size)
 105 {
 106     uint32_t *regs = opaque;
 107
 108     if (offset == 0xf00) {
 109         if (value == 1 || value == 2) {
 110             qemu_system_reset_request();
 111         } else if (value == 3) {
 112             qemu_system_shutdown_request();
 113         }
 114     }
 115
 116     regs[offset/4] = value;
 117 }
 118
 119 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 120                              unsigned size)
 121 {
 122     uint32_t *regs = opaque;
 123     uint32_t value = regs[offset/4];
 124
 125     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 126         value |= 0x30000000;
 127     }
 128
 129     return value;
 130 }
 131
 132 static const MemoryRegionOps hb_mem_ops = {
 133     .read = hb_regs_read,
 134     .write = hb_regs_write,
 135     .endianness = DEVICE_NATIVE_ENDIAN,
 136 };
 137
 138 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 139 #define HIGHBANK_REGISTERS(obj) \
 140     OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
 141
 142 typedef struct {
 143     /*< private >*/
 144     SysBusDevice parent_obj;
 145     /*< public >*/
 146
 147     MemoryRegion iomem;
 148     uint32_t regs[NUM_REGS];
 149 } HighbankRegsState;
 150
 151 static VMStateDescription vmstate_highbank_regs = {
 152     .name = "highbank-regs",
 153     .version_id = 0,
 154     .minimum_version_id = 0,
 155     .fields = (VMStateField[]) {
 156         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 157         VMSTATE_END_OF_LIST(),
 158     },
 159 };
 160
 161 static void highbank_regs_reset(DeviceState *dev)
 162 {
 163     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 164
 165     s->regs[0x40] = 0x05F20121;
 166     s->regs[0x41] = 0x2;
 167     s->regs[0x42] = 0x05F30121;
 168     s->regs[0x43] = 0x05F40121;
 169 }
 170
 171 static void highbank_regs_init(Object *obj)
 172 {
 173     HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
 174     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 175
 176     memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
 177                           "highbank_regs", 0x1000);
 178     sysbus_init_mmio(dev, &s->iomem);
 179 }
 180
 181 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 182 {
 183     DeviceClass *dc = DEVICE_CLASS(klass);
 184
 185     dc->desc = "Calxeda Highbank registers";
 186     dc->vmsd = &vmstate_highbank_regs;
 187     dc->reset = highbank_regs_reset;
 188 }
 189
 190 static const TypeInfo highbank_regs_info = {
 191     .name          = TYPE_HIGHBANK_REGISTERS,
 192     .parent        = TYPE_SYS_BUS_DEVICE,
 193     .instance_size = sizeof(HighbankRegsState),
 194     .instance_init = highbank_regs_init,
 195     .class_init    = highbank_regs_class_init,
 196 };
 197
 198 static void highbank_regs_register_types(void)
 199 {
 200     type_register_static(&highbank_regs_info);
 201 }
 202
 203 type_init(highbank_regs_register_types)
 204
 205 static struct arm_boot_info highbank_binfo;
 206
 207 enum cxmachines {
 208     CALXEDA_HIGHBANK,
 209     CALXEDA_MIDWAY,
 210 };
 211
 212 /* ram_size must be set to match the upper bound of memory in the
 213  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 214  * normally 0xff900000 or -m 4089. When running this board on a
 215  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 216  * device tree and pass -m 2047 to QEMU.
 217  */
 218 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 219 {
 220     ram_addr_t ram_size = machine->ram_size;
 221     const char *cpu_model = machine->cpu_model;
 222     const char *kernel_filename = machine->kernel_filename;
 223     const char *kernel_cmdline = machine->kernel_cmdline;
 224     const char *initrd_filename = machine->initrd_filename;
 225     DeviceState *dev = NULL;
 226     SysBusDevice *busdev;
 227     qemu_irq pic[128];
 228     int n;
 229     qemu_irq cpu_irq[4];
 230     qemu_irq cpu_fiq[4];
 231     MemoryRegion *sysram;
 232     MemoryRegion *dram;
 233     MemoryRegion *sysmem;
 234     char *sysboot_filename;
 235
 236     switch (machine_id) {
 237     case CALXEDA_HIGHBANK:
 238         cpu_model = "cortex-a9";
 239         break;
 240     case CALXEDA_MIDWAY:
 241         cpu_model = "cortex-a15";
 242         break;
 243     }
 244
 245     for (n = 0; n < smp_cpus; n++) {
 246         ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 247         Object *cpuobj;
 248         ARMCPU *cpu;
 249
 250         cpuobj = object_new(object_class_get_name(oc));
 251         cpu = ARM_CPU(cpuobj);
 252
 253         object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
 254                                 "psci-conduit", &error_abort);
 255
 256         if (n) {
 257             /* Secondary CPUs start in PSCI powered-down state */
 258             object_property_set_bool(cpuobj, true,
 259                                      "start-powered-off", &error_abort);
 260         }
 261
 262         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 263             object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
 264                                     "reset-cbar", &error_abort);
 265         }
 266         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 267         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
 268         cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
 269     }
 270
 271     sysmem = get_system_memory();
 272     dram = g_new(MemoryRegion, 1);
 273     memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
 274     /* SDRAM at address zero.  */
 275     memory_region_add_subregion(sysmem, 0, dram);
 276
 277     sysram = g_new(MemoryRegion, 1);
 278     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
 279                            &error_fatal);
 280     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 281     if (bios_name != NULL) {
 282         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 283         if (sysboot_filename != NULL) {
 284             if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
 285                 error_report("Unable to load %s", bios_name);
 286                 exit(1);
 287             }
 288             g_free(sysboot_filename);
 289         } else {
 290             error_report("Unable to find %s", bios_name);
 291             exit(1);
 292         }
 293     }
 294
 295     switch (machine_id) {
 296     case CALXEDA_HIGHBANK:
 297         dev = qdev_create(NULL, "l2x0");
 298         qdev_init_nofail(dev);
 299         busdev = SYS_BUS_DEVICE(dev);
 300         sysbus_mmio_map(busdev, 0, 0xfff12000);
 301
 302         dev = qdev_create(NULL, "a9mpcore_priv");
 303         break;
 304     case CALXEDA_MIDWAY:
 305         dev = qdev_create(NULL, "a15mpcore_priv");
 306         break;
 307     }
 308     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 309     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 310     qdev_init_nofail(dev);
 311     busdev = SYS_BUS_DEVICE(dev);
 312     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 313     for (n = 0; n < smp_cpus; n++) {
 314         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 315         sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
 316     }
 317
 318     for (n = 0; n < 128; n++) {
 319         pic[n] = qdev_get_gpio_in(dev, n);
 320     }
 321
 322     dev = qdev_create(NULL, "sp804");
 323     qdev_prop_set_uint32(dev, "freq0", 150000000);
 324     qdev_prop_set_uint32(dev, "freq1", 150000000);
 325     qdev_init_nofail(dev);
 326     busdev = SYS_BUS_DEVICE(dev);
 327     sysbus_mmio_map(busdev, 0, 0xfff34000);
 328     sysbus_connect_irq(busdev, 0, pic[18]);
 329     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 330
 331     dev = qdev_create(NULL, "highbank-regs");
 332     qdev_init_nofail(dev);
 333     busdev = SYS_BUS_DEVICE(dev);
 334     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 335
 336     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 337     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 338     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 339     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 340     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 341     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 342
 343     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 344
 345     if (nd_table[0].used) {
 346         qemu_check_nic_model(&nd_table[0], "xgmac");
 347         dev = qdev_create(NULL, "xgmac");
 348         qdev_set_nic_properties(dev, &nd_table[0]);
 349         qdev_init_nofail(dev);
 350         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 351         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 352         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 353         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 354
 355         qemu_check_nic_model(&nd_table[1], "xgmac");
 356         dev = qdev_create(NULL, "xgmac");
 357         qdev_set_nic_properties(dev, &nd_table[1]);
 358         qdev_init_nofail(dev);
 359         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 360         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 361         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 362         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 363     }
 364
 365     highbank_binfo.ram_size = ram_size;
 366     highbank_binfo.kernel_filename = kernel_filename;
 367     highbank_binfo.kernel_cmdline = kernel_cmdline;
 368     highbank_binfo.initrd_filename = initrd_filename;
 369     /* highbank requires a dtb in order to boot, and the dtb will override
 370      * the board ID. The following value is ignored, so set it to -1 to be
 371      * clear that the value is meaningless.
 372      */
 373     highbank_binfo.board_id = -1;
 374     highbank_binfo.nb_cpus = smp_cpus;
 375     highbank_binfo.loader_start = 0;
 376     highbank_binfo.write_secondary_boot = hb_write_secondary;
 377     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 378     if (!kvm_enabled()) {
 379         highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 380         highbank_binfo.write_board_setup = hb_write_board_setup;
 381         highbank_binfo.secure_board_setup = true;
 382     } else {
 383         error_report("WARNING: cannot load built-in Monitor support "
 384                      "if KVM is enabled. Some guests (such as Linux) "
 385                      "may not boot.");
 386     }
 387
 388     arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
 389 }
 390
 391 static void highbank_init(MachineState *machine)
 392 {
 393     calxeda_init(machine, CALXEDA_HIGHBANK);
 394 }
 395
 396 static void midway_init(MachineState *machine)
 397 {
 398     calxeda_init(machine, CALXEDA_MIDWAY);
 399 }
 400
 401 static void highbank_class_init(ObjectClass *oc, void *data)
 402 {
 403     MachineClass *mc = MACHINE_CLASS(oc);
 404
 405     mc->desc = "Calxeda Highbank (ECX-1000)";
 406     mc->init = highbank_init;
 407     mc->block_default_type = IF_SCSI;
 408     mc->max_cpus = 4;
 409 }
 410
 411 static const TypeInfo highbank_type = {
 412     .name = MACHINE_TYPE_NAME("highbank"),
 413     .parent = TYPE_MACHINE,
 414     .class_init = highbank_class_init,
 415 };
 416
 417 static void midway_class_init(ObjectClass *oc, void *data)
 418 {
 419     MachineClass *mc = MACHINE_CLASS(oc);
 420
 421     mc->desc = "Calxeda Midway (ECX-2000)";
 422     mc->init = midway_init;
 423     mc->block_default_type = IF_SCSI;
 424     mc->max_cpus = 4;
 425 }
 426
 427 static const TypeInfo midway_type = {
 428     .name = MACHINE_TYPE_NAME("midway"),
 429     .parent = TYPE_MACHINE,
 430     .class_init = midway_class_init,
 431 };
 432
 433 static void calxeda_machines_init(void)
 434 {
 435     type_register_static(&highbank_type);
 436     type_register_static(&midway_type);
 437 }
 438
 439 type_init(calxeda_machines_init)