4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X
[32];
41 static TCGv_i64 cpu_pc
;
43 /* Load/store exclusive handling */
44 static TCGv_i64 cpu_exclusive_high
;
45 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
47 static const char *regnames
[] = {
48 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
49 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
50 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
51 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 A64_SHIFT_TYPE_LSL
= 0,
56 A64_SHIFT_TYPE_LSR
= 1,
57 A64_SHIFT_TYPE_ASR
= 2,
58 A64_SHIFT_TYPE_ROR
= 3
61 /* Table based decoder typedefs - used when the relevant bits for decode
62 * are too awkwardly scattered across the instruction (eg SIMD).
64 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
66 typedef struct AArch64DecodeTable
{
69 AArch64DecodeFn
*disas_fn
;
72 /* Function prototype for gen_ functions for calling Neon helpers */
73 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
74 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
79 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
80 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
81 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
82 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
83 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
84 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
85 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
86 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
87 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
89 /* Note that the gvec expanders operate on offsets + sizes. */
90 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
91 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
93 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
94 uint32_t, uint32_t, uint32_t);
96 /* initialize TCG globals. */
97 void a64_translate_init(void)
101 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
102 offsetof(CPUARMState
, pc
),
104 for (i
= 0; i
< 32; i
++) {
105 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
106 offsetof(CPUARMState
, xregs
[i
]),
110 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
111 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
114 static inline int get_a64_user_mem_index(DisasContext
*s
)
116 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
117 * if EL1, access as if EL0; otherwise access at current EL
121 switch (s
->mmu_idx
) {
122 case ARMMMUIdx_S12NSE1
:
123 useridx
= ARMMMUIdx_S12NSE0
;
125 case ARMMMUIdx_S1SE1
:
126 useridx
= ARMMMUIdx_S1SE0
;
129 g_assert_not_reached();
131 useridx
= s
->mmu_idx
;
134 return arm_to_core_mmu_idx(useridx
);
137 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
138 fprintf_function cpu_fprintf
, int flags
)
140 ARMCPU
*cpu
= ARM_CPU(cs
);
141 CPUARMState
*env
= &cpu
->env
;
142 uint32_t psr
= pstate_read(env
);
144 int el
= arm_current_el(env
);
145 const char *ns_status
;
147 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
148 env
->pc
, env
->xregs
[31]);
149 for (i
= 0; i
< 31; i
++) {
150 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
152 cpu_fprintf(f
, "\n");
158 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
159 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
164 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
166 psr
& PSTATE_N
? 'N' : '-',
167 psr
& PSTATE_Z
? 'Z' : '-',
168 psr
& PSTATE_C
? 'C' : '-',
169 psr
& PSTATE_V
? 'V' : '-',
172 psr
& PSTATE_SP
? 'h' : 't');
174 if (flags
& CPU_DUMP_FPU
) {
176 for (i
= 0; i
< numvfpregs
; i
++) {
177 uint64_t *q
= aa64_vfp_qreg(env
, i
);
180 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"%c",
181 i
, vhi
, vlo
, (i
& 1 ? '\n' : ' '));
183 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
184 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
188 void gen_a64_set_pc_im(uint64_t val
)
190 tcg_gen_movi_i64(cpu_pc
, val
);
193 /* Load the PC from a generic TCG variable.
195 * If address tagging is enabled via the TCR TBI bits, then loading
196 * an address into the PC will clear out any tag in the it:
197 * + for EL2 and EL3 there is only one TBI bit, and if it is set
198 * then the address is zero-extended, clearing bits [63:56]
199 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
200 * and TBI1 controls addressses with bit 55 == 1.
201 * If the appropriate TBI bit is set for the address then
202 * the address is sign-extended from bit 55 into bits [63:56]
204 * We can avoid doing this for relative-branches, because the
205 * PC + offset can never overflow into the tag bits (assuming
206 * that virtual addresses are less than 56 bits wide, as they
207 * are currently), but we must handle it for branch-to-register.
209 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
212 if (s
->current_el
<= 1) {
213 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
214 * examine bit 55 of address, can just generate code.
215 * If mixed, then test via generated code
217 if (s
->tbi0
&& s
->tbi1
) {
218 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
219 /* Both bits set, sign extension from bit 55 into [63:56] will
222 tcg_gen_shli_i64(tmp_reg
, src
, 8);
223 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
224 tcg_temp_free_i64(tmp_reg
);
225 } else if (!s
->tbi0
&& !s
->tbi1
) {
226 /* Neither bit set, just load it as-is */
227 tcg_gen_mov_i64(cpu_pc
, src
);
229 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
230 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
231 TCGv_i64 tcg_zero
= tcg_const_i64(0);
233 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
236 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
237 tcg_gen_andi_i64(tcg_tmpval
, src
,
238 0x00FFFFFFFFFFFFFFull
);
239 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
242 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
243 tcg_gen_ori_i64(tcg_tmpval
, src
,
244 0xFF00000000000000ull
);
245 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
248 tcg_temp_free_i64(tcg_zero
);
249 tcg_temp_free_i64(tcg_bit55
);
250 tcg_temp_free_i64(tcg_tmpval
);
252 } else { /* EL > 1 */
254 /* Force tag byte to all zero */
255 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
257 /* Load unmodified address */
258 tcg_gen_mov_i64(cpu_pc
, src
);
263 typedef struct DisasCompare64
{
268 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
272 arm_test_cc(&c32
, cc
);
274 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
275 * properly. The NE/EQ comparisons are also fine with this choice. */
276 c64
->cond
= c32
.cond
;
277 c64
->value
= tcg_temp_new_i64();
278 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
283 static void a64_free_cc(DisasCompare64
*c64
)
285 tcg_temp_free_i64(c64
->value
);
288 static void gen_exception_internal(int excp
)
290 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
292 assert(excp_is_internal(excp
));
293 gen_helper_exception_internal(cpu_env
, tcg_excp
);
294 tcg_temp_free_i32(tcg_excp
);
297 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
299 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
300 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
301 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
303 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
305 tcg_temp_free_i32(tcg_el
);
306 tcg_temp_free_i32(tcg_syn
);
307 tcg_temp_free_i32(tcg_excp
);
310 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
312 gen_a64_set_pc_im(s
->pc
- offset
);
313 gen_exception_internal(excp
);
314 s
->base
.is_jmp
= DISAS_NORETURN
;
317 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
318 uint32_t syndrome
, uint32_t target_el
)
320 gen_a64_set_pc_im(s
->pc
- offset
);
321 gen_exception(excp
, syndrome
, target_el
);
322 s
->base
.is_jmp
= DISAS_NORETURN
;
325 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
330 gen_a64_set_pc_im(s
->pc
- offset
);
331 tcg_syn
= tcg_const_i32(syndrome
);
332 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
333 tcg_temp_free_i32(tcg_syn
);
334 s
->base
.is_jmp
= DISAS_NORETURN
;
337 static void gen_ss_advance(DisasContext
*s
)
339 /* If the singlestep state is Active-not-pending, advance to
344 gen_helper_clear_pstate_ss(cpu_env
);
348 static void gen_step_complete_exception(DisasContext
*s
)
350 /* We just completed step of an insn. Move from Active-not-pending
351 * to Active-pending, and then also take the swstep exception.
352 * This corresponds to making the (IMPDEF) choice to prioritize
353 * swstep exceptions over asynchronous exceptions taken to an exception
354 * level where debug is disabled. This choice has the advantage that
355 * we do not need to maintain internal state corresponding to the
356 * ISV/EX syndrome bits between completion of the step and generation
357 * of the exception, and our syndrome information is always correct.
360 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
361 default_exception_el(s
));
362 s
->base
.is_jmp
= DISAS_NORETURN
;
365 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
367 /* No direct tb linking with singlestep (either QEMU's or the ARM
368 * debug architecture kind) or deterministic io
370 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
371 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
375 #ifndef CONFIG_USER_ONLY
376 /* Only link tbs from inside the same guest page */
377 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
385 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
387 TranslationBlock
*tb
;
390 if (use_goto_tb(s
, n
, dest
)) {
392 gen_a64_set_pc_im(dest
);
393 tcg_gen_exit_tb((intptr_t)tb
+ n
);
394 s
->base
.is_jmp
= DISAS_NORETURN
;
396 gen_a64_set_pc_im(dest
);
398 gen_step_complete_exception(s
);
399 } else if (s
->base
.singlestep_enabled
) {
400 gen_exception_internal(EXCP_DEBUG
);
402 tcg_gen_lookup_and_goto_ptr();
403 s
->base
.is_jmp
= DISAS_NORETURN
;
408 static void unallocated_encoding(DisasContext
*s
)
410 /* Unallocated and reserved encodings are uncategorized */
411 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
412 default_exception_el(s
));
415 #define unsupported_encoding(s, insn) \
417 qemu_log_mask(LOG_UNIMP, \
418 "%s:%d: unsupported instruction encoding 0x%08x " \
419 "at pc=%016" PRIx64 "\n", \
420 __FILE__, __LINE__, insn, s->pc - 4); \
421 unallocated_encoding(s); \
424 static void init_tmp_a64_array(DisasContext
*s
)
426 #ifdef CONFIG_DEBUG_TCG
427 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
429 s
->tmp_a64_count
= 0;
432 static void free_tmp_a64(DisasContext
*s
)
435 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
436 tcg_temp_free_i64(s
->tmp_a64
[i
]);
438 init_tmp_a64_array(s
);
441 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
443 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
444 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
447 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
449 TCGv_i64 t
= new_tmp_a64(s
);
450 tcg_gen_movi_i64(t
, 0);
455 * Register access functions
457 * These functions are used for directly accessing a register in where
458 * changes to the final register value are likely to be made. If you
459 * need to use a register for temporary calculation (e.g. index type
460 * operations) use the read_* form.
462 * B1.2.1 Register mappings
464 * In instruction register encoding 31 can refer to ZR (zero register) or
465 * the SP (stack pointer) depending on context. In QEMU's case we map SP
466 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
467 * This is the point of the _sp forms.
469 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
472 return new_tmp_a64_zero(s
);
478 /* register access for when 31 == SP */
479 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
484 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
485 * representing the register contents. This TCGv is an auto-freed
486 * temporary so it need not be explicitly freed, and may be modified.
488 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
490 TCGv_i64 v
= new_tmp_a64(s
);
493 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
495 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
498 tcg_gen_movi_i64(v
, 0);
503 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
505 TCGv_i64 v
= new_tmp_a64(s
);
507 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
509 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
514 /* We should have at some point before trying to access an FP register
515 * done the necessary access check, so assert that
516 * (a) we did the check and
517 * (b) we didn't then just plough ahead anyway if it failed.
518 * Print the instruction pattern in the abort message so we can figure
519 * out what we need to fix if a user encounters this problem in the wild.
521 static inline void assert_fp_access_checked(DisasContext
*s
)
523 #ifdef CONFIG_DEBUG_TCG
524 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
525 fprintf(stderr
, "target-arm: FP access check missing for "
526 "instruction 0x%08x\n", s
->insn
);
532 /* Return the offset into CPUARMState of an element of specified
533 * size, 'element' places in from the least significant end of
534 * the FP/vector register Qn.
536 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
537 int element
, TCGMemOp size
)
540 #ifdef HOST_WORDS_BIGENDIAN
541 /* This is complicated slightly because vfp.zregs[n].d[0] is
542 * still the low half and vfp.zregs[n].d[1] the high half
543 * of the 128 bit vector, even on big endian systems.
544 * Calculate the offset assuming a fully bigendian 128 bits,
545 * then XOR to account for the order of the two 64 bit halves.
547 offs
+= (16 - ((element
+ 1) * (1 << size
)));
550 offs
+= element
* (1 << size
);
552 offs
+= offsetof(CPUARMState
, vfp
.zregs
[regno
]);
553 assert_fp_access_checked(s
);
557 /* Return the offset info CPUARMState of the "whole" vector register Qn. */
558 static inline int vec_full_reg_offset(DisasContext
*s
, int regno
)
560 assert_fp_access_checked(s
);
561 return offsetof(CPUARMState
, vfp
.zregs
[regno
]);
564 /* Return a newly allocated pointer to the vector register. */
565 static TCGv_ptr
vec_full_reg_ptr(DisasContext
*s
, int regno
)
567 TCGv_ptr ret
= tcg_temp_new_ptr();
568 tcg_gen_addi_ptr(ret
, cpu_env
, vec_full_reg_offset(s
, regno
));
572 /* Return the byte size of the "whole" vector register, VL / 8. */
573 static inline int vec_full_reg_size(DisasContext
*s
)
575 /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
576 In the meantime this is just the AdvSIMD length of 128. */
580 /* Return the offset into CPUARMState of a slice (from
581 * the least significant end) of FP register Qn (ie
583 * (Note that this is not the same mapping as for A32; see cpu.h)
585 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
587 return vec_reg_offset(s
, regno
, 0, size
);
590 /* Offset of the high half of the 128 bit vector Qn */
591 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
593 return vec_reg_offset(s
, regno
, 1, MO_64
);
596 /* Convenience accessors for reading and writing single and double
597 * FP registers. Writing clears the upper parts of the associated
598 * 128 bit vector register, as required by the architecture.
599 * Note that unlike the GP register accessors, the values returned
600 * by the read functions must be manually freed.
602 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
604 TCGv_i64 v
= tcg_temp_new_i64();
606 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
610 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
612 TCGv_i32 v
= tcg_temp_new_i32();
614 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
618 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
620 TCGv_i32 v
= tcg_temp_new_i32();
622 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
626 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
627 * If SVE is not enabled, then there are only 128 bits in the vector.
629 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
631 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
632 unsigned vsz
= vec_full_reg_size(s
);
635 TCGv_i64 tcg_zero
= tcg_const_i64(0);
636 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
637 tcg_temp_free_i64(tcg_zero
);
640 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
644 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
646 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
648 tcg_gen_st_i64(v
, cpu_env
, ofs
);
649 clear_vec_high(s
, false, reg
);
652 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
654 TCGv_i64 tmp
= tcg_temp_new_i64();
656 tcg_gen_extu_i32_i64(tmp
, v
);
657 write_fp_dreg(s
, reg
, tmp
);
658 tcg_temp_free_i64(tmp
);
661 static TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
663 TCGv_ptr statusptr
= tcg_temp_new_ptr();
666 /* In A64 all instructions (both FP and Neon) use the FPCR; there
667 * is no equivalent of the A32 Neon "standard FPSCR value".
668 * However half-precision operations operate under a different
669 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
672 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
674 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
676 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
680 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
681 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
682 GVecGen2Fn
*gvec_fn
, int vece
)
684 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
685 is_q
? 16 : 8, vec_full_reg_size(s
));
688 /* Expand a 2-operand + immediate AdvSIMD vector operation using
689 * an expander function.
691 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
692 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
694 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
695 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
698 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
699 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
700 GVecGen3Fn
*gvec_fn
, int vece
)
702 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
703 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
706 /* Expand a 2-operand + immediate AdvSIMD vector operation using
709 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
710 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
712 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
713 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
716 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
717 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
718 int rn
, int rm
, const GVecGen3
*gvec_op
)
720 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
721 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
722 vec_full_reg_size(s
), gvec_op
);
725 /* Expand a 3-operand + env pointer operation using
726 * an out-of-line helper.
728 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
729 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
731 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
732 vec_full_reg_offset(s
, rn
),
733 vec_full_reg_offset(s
, rm
), cpu_env
,
734 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
737 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
738 * an out-of-line helper.
740 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
741 int rm
, bool is_fp16
, int data
,
742 gen_helper_gvec_3_ptr
*fn
)
744 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
745 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
746 vec_full_reg_offset(s
, rn
),
747 vec_full_reg_offset(s
, rm
), fpst
,
748 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
749 tcg_temp_free_ptr(fpst
);
752 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
753 * than the 32 bit equivalent.
755 static inline void gen_set_NZ64(TCGv_i64 result
)
757 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
758 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
761 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
762 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
765 gen_set_NZ64(result
);
767 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
768 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
770 tcg_gen_movi_i32(cpu_CF
, 0);
771 tcg_gen_movi_i32(cpu_VF
, 0);
774 /* dest = T0 + T1; compute C, N, V and Z flags */
775 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
778 TCGv_i64 result
, flag
, tmp
;
779 result
= tcg_temp_new_i64();
780 flag
= tcg_temp_new_i64();
781 tmp
= tcg_temp_new_i64();
783 tcg_gen_movi_i64(tmp
, 0);
784 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
786 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
788 gen_set_NZ64(result
);
790 tcg_gen_xor_i64(flag
, result
, t0
);
791 tcg_gen_xor_i64(tmp
, t0
, t1
);
792 tcg_gen_andc_i64(flag
, flag
, tmp
);
793 tcg_temp_free_i64(tmp
);
794 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
796 tcg_gen_mov_i64(dest
, result
);
797 tcg_temp_free_i64(result
);
798 tcg_temp_free_i64(flag
);
800 /* 32 bit arithmetic */
801 TCGv_i32 t0_32
= tcg_temp_new_i32();
802 TCGv_i32 t1_32
= tcg_temp_new_i32();
803 TCGv_i32 tmp
= tcg_temp_new_i32();
805 tcg_gen_movi_i32(tmp
, 0);
806 tcg_gen_extrl_i64_i32(t0_32
, t0
);
807 tcg_gen_extrl_i64_i32(t1_32
, t1
);
808 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
809 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
810 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
811 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
812 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
813 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
815 tcg_temp_free_i32(tmp
);
816 tcg_temp_free_i32(t0_32
);
817 tcg_temp_free_i32(t1_32
);
821 /* dest = T0 - T1; compute C, N, V and Z flags */
822 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
825 /* 64 bit arithmetic */
826 TCGv_i64 result
, flag
, tmp
;
828 result
= tcg_temp_new_i64();
829 flag
= tcg_temp_new_i64();
830 tcg_gen_sub_i64(result
, t0
, t1
);
832 gen_set_NZ64(result
);
834 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
835 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
837 tcg_gen_xor_i64(flag
, result
, t0
);
838 tmp
= tcg_temp_new_i64();
839 tcg_gen_xor_i64(tmp
, t0
, t1
);
840 tcg_gen_and_i64(flag
, flag
, tmp
);
841 tcg_temp_free_i64(tmp
);
842 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
843 tcg_gen_mov_i64(dest
, result
);
844 tcg_temp_free_i64(flag
);
845 tcg_temp_free_i64(result
);
847 /* 32 bit arithmetic */
848 TCGv_i32 t0_32
= tcg_temp_new_i32();
849 TCGv_i32 t1_32
= tcg_temp_new_i32();
852 tcg_gen_extrl_i64_i32(t0_32
, t0
);
853 tcg_gen_extrl_i64_i32(t1_32
, t1
);
854 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
855 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
856 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
857 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
858 tmp
= tcg_temp_new_i32();
859 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
860 tcg_temp_free_i32(t0_32
);
861 tcg_temp_free_i32(t1_32
);
862 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
863 tcg_temp_free_i32(tmp
);
864 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
868 /* dest = T0 + T1 + CF; do not compute flags. */
869 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
871 TCGv_i64 flag
= tcg_temp_new_i64();
872 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
873 tcg_gen_add_i64(dest
, t0
, t1
);
874 tcg_gen_add_i64(dest
, dest
, flag
);
875 tcg_temp_free_i64(flag
);
878 tcg_gen_ext32u_i64(dest
, dest
);
882 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
883 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
886 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
887 result
= tcg_temp_new_i64();
888 cf_64
= tcg_temp_new_i64();
889 vf_64
= tcg_temp_new_i64();
890 tmp
= tcg_const_i64(0);
892 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
893 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
894 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
895 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
896 gen_set_NZ64(result
);
898 tcg_gen_xor_i64(vf_64
, result
, t0
);
899 tcg_gen_xor_i64(tmp
, t0
, t1
);
900 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
901 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
903 tcg_gen_mov_i64(dest
, result
);
905 tcg_temp_free_i64(tmp
);
906 tcg_temp_free_i64(vf_64
);
907 tcg_temp_free_i64(cf_64
);
908 tcg_temp_free_i64(result
);
910 TCGv_i32 t0_32
, t1_32
, tmp
;
911 t0_32
= tcg_temp_new_i32();
912 t1_32
= tcg_temp_new_i32();
913 tmp
= tcg_const_i32(0);
915 tcg_gen_extrl_i64_i32(t0_32
, t0
);
916 tcg_gen_extrl_i64_i32(t1_32
, t1
);
917 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
918 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
920 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
921 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
922 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
923 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
924 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
926 tcg_temp_free_i32(tmp
);
927 tcg_temp_free_i32(t1_32
);
928 tcg_temp_free_i32(t0_32
);
933 * Load/Store generators
937 * Store from GPR register to memory.
939 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
940 TCGv_i64 tcg_addr
, int size
, int memidx
,
942 unsigned int iss_srt
,
943 bool iss_sf
, bool iss_ar
)
946 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
951 syn
= syn_data_abort_with_iss(0,
957 0, 0, 0, 0, 0, false);
958 disas_set_insn_syndrome(s
, syn
);
962 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
963 TCGv_i64 tcg_addr
, int size
,
965 unsigned int iss_srt
,
966 bool iss_sf
, bool iss_ar
)
968 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
969 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
973 * Load from memory to GPR register
975 static void do_gpr_ld_memidx(DisasContext
*s
,
976 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
977 int size
, bool is_signed
,
978 bool extend
, int memidx
,
979 bool iss_valid
, unsigned int iss_srt
,
980 bool iss_sf
, bool iss_ar
)
982 TCGMemOp memop
= s
->be_data
+ size
;
990 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
992 if (extend
&& is_signed
) {
994 tcg_gen_ext32u_i64(dest
, dest
);
1000 syn
= syn_data_abort_with_iss(0,
1006 0, 0, 0, 0, 0, false);
1007 disas_set_insn_syndrome(s
, syn
);
1011 static void do_gpr_ld(DisasContext
*s
,
1012 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1013 int size
, bool is_signed
, bool extend
,
1014 bool iss_valid
, unsigned int iss_srt
,
1015 bool iss_sf
, bool iss_ar
)
1017 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1019 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1023 * Store from FP register to memory
1025 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1027 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1028 TCGv_i64 tmp
= tcg_temp_new_i64();
1029 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1031 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1034 bool be
= s
->be_data
== MO_BE
;
1035 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1037 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1038 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1040 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1041 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1043 tcg_temp_free_i64(tcg_hiaddr
);
1046 tcg_temp_free_i64(tmp
);
1050 * Load from memory to FP register
1052 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1054 /* This always zero-extends and writes to a full 128 bit wide vector */
1055 TCGv_i64 tmplo
= tcg_temp_new_i64();
1059 TCGMemOp memop
= s
->be_data
+ size
;
1060 tmphi
= tcg_const_i64(0);
1061 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1063 bool be
= s
->be_data
== MO_BE
;
1064 TCGv_i64 tcg_hiaddr
;
1066 tmphi
= tcg_temp_new_i64();
1067 tcg_hiaddr
= tcg_temp_new_i64();
1069 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1070 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1072 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1074 tcg_temp_free_i64(tcg_hiaddr
);
1077 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1078 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1080 tcg_temp_free_i64(tmplo
);
1081 tcg_temp_free_i64(tmphi
);
1083 clear_vec_high(s
, true, destidx
);
1087 * Vector load/store helpers.
1089 * The principal difference between this and a FP load is that we don't
1090 * zero extend as we are filling a partial chunk of the vector register.
1091 * These functions don't support 128 bit loads/stores, which would be
1092 * normal load/store operations.
1094 * The _i32 versions are useful when operating on 32 bit quantities
1095 * (eg for floating point single or using Neon helper functions).
1098 /* Get value of an element within a vector register */
1099 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1100 int element
, TCGMemOp memop
)
1102 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1105 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1108 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1111 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1114 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1117 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1120 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1124 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1127 g_assert_not_reached();
1131 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1132 int element
, TCGMemOp memop
)
1134 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1137 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1140 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1143 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1146 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1150 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1153 g_assert_not_reached();
1157 /* Set value of an element within a vector register */
1158 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1159 int element
, TCGMemOp memop
)
1161 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1164 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1167 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1170 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1173 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1176 g_assert_not_reached();
1180 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1181 int destidx
, int element
, TCGMemOp memop
)
1183 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1186 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1189 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1192 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1195 g_assert_not_reached();
1199 /* Store from vector register to memory */
1200 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1201 TCGv_i64 tcg_addr
, int size
)
1203 TCGMemOp memop
= s
->be_data
+ size
;
1204 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1206 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1207 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1209 tcg_temp_free_i64(tcg_tmp
);
1212 /* Load from memory to vector register */
1213 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1214 TCGv_i64 tcg_addr
, int size
)
1216 TCGMemOp memop
= s
->be_data
+ size
;
1217 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1219 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1220 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1222 tcg_temp_free_i64(tcg_tmp
);
1225 /* Check that FP/Neon access is enabled. If it is, return
1226 * true. If not, emit code to generate an appropriate exception,
1227 * and return false; the caller should not emit any code for
1228 * the instruction. Note that this check must happen after all
1229 * unallocated-encoding checks (otherwise the syndrome information
1230 * for the resulting exception will be incorrect).
1232 static inline bool fp_access_check(DisasContext
*s
)
1234 assert(!s
->fp_access_checked
);
1235 s
->fp_access_checked
= true;
1237 if (!s
->fp_excp_el
) {
1241 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1246 /* Check that SVE access is enabled. If it is, return true.
1247 * If not, emit code to generate an appropriate exception and return false.
1249 static inline bool sve_access_check(DisasContext
*s
)
1251 if (s
->sve_excp_el
) {
1252 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1260 * This utility function is for doing register extension with an
1261 * optional shift. You will likely want to pass a temporary for the
1262 * destination register. See DecodeRegExtend() in the ARM ARM.
1264 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1265 int option
, unsigned int shift
)
1267 int extsize
= extract32(option
, 0, 2);
1268 bool is_signed
= extract32(option
, 2, 1);
1273 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1276 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1279 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1282 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1288 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1291 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1294 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1297 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1303 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1307 static inline void gen_check_sp_alignment(DisasContext
*s
)
1309 /* The AArch64 architecture mandates that (if enabled via PSTATE
1310 * or SCTLR bits) there is a check that SP is 16-aligned on every
1311 * SP-relative load or store (with an exception generated if it is not).
1312 * In line with general QEMU practice regarding misaligned accesses,
1313 * we omit these checks for the sake of guest program performance.
1314 * This function is provided as a hook so we can more easily add these
1315 * checks in future (possibly as a "favour catching guest program bugs
1316 * over speed" user selectable option).
1321 * This provides a simple table based table lookup decoder. It is
1322 * intended to be used when the relevant bits for decode are too
1323 * awkwardly placed and switch/if based logic would be confusing and
1324 * deeply nested. Since it's a linear search through the table, tables
1325 * should be kept small.
1327 * It returns the first handler where insn & mask == pattern, or
1328 * NULL if there is no match.
1329 * The table is terminated by an empty mask (i.e. 0)
1331 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1334 const AArch64DecodeTable
*tptr
= table
;
1336 while (tptr
->mask
) {
1337 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1338 return tptr
->disas_fn
;
1346 * The instruction disassembly implemented here matches
1347 * the instruction encoding classifications in chapter C4
1348 * of the ARM Architecture Reference Manual (DDI0487B_a);
1349 * classification names and decode diagrams here should generally
1350 * match up with those in the manual.
1353 /* Unconditional branch (immediate)
1355 * +----+-----------+-------------------------------------+
1356 * | op | 0 0 1 0 1 | imm26 |
1357 * +----+-----------+-------------------------------------+
1359 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1361 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1363 if (insn
& (1U << 31)) {
1364 /* BL Branch with link */
1365 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1368 /* B Branch / BL Branch with link */
1369 gen_goto_tb(s
, 0, addr
);
1372 /* Compare and branch (immediate)
1373 * 31 30 25 24 23 5 4 0
1374 * +----+-------------+----+---------------------+--------+
1375 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1376 * +----+-------------+----+---------------------+--------+
1378 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1380 unsigned int sf
, op
, rt
;
1382 TCGLabel
*label_match
;
1385 sf
= extract32(insn
, 31, 1);
1386 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1387 rt
= extract32(insn
, 0, 5);
1388 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1390 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1391 label_match
= gen_new_label();
1393 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1394 tcg_cmp
, 0, label_match
);
1396 gen_goto_tb(s
, 0, s
->pc
);
1397 gen_set_label(label_match
);
1398 gen_goto_tb(s
, 1, addr
);
1401 /* Test and branch (immediate)
1402 * 31 30 25 24 23 19 18 5 4 0
1403 * +----+-------------+----+-------+-------------+------+
1404 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1405 * +----+-------------+----+-------+-------------+------+
1407 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1409 unsigned int bit_pos
, op
, rt
;
1411 TCGLabel
*label_match
;
1414 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1415 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1416 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1417 rt
= extract32(insn
, 0, 5);
1419 tcg_cmp
= tcg_temp_new_i64();
1420 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1421 label_match
= gen_new_label();
1422 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1423 tcg_cmp
, 0, label_match
);
1424 tcg_temp_free_i64(tcg_cmp
);
1425 gen_goto_tb(s
, 0, s
->pc
);
1426 gen_set_label(label_match
);
1427 gen_goto_tb(s
, 1, addr
);
1430 /* Conditional branch (immediate)
1431 * 31 25 24 23 5 4 3 0
1432 * +---------------+----+---------------------+----+------+
1433 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1434 * +---------------+----+---------------------+----+------+
1436 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1441 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1442 unallocated_encoding(s
);
1445 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1446 cond
= extract32(insn
, 0, 4);
1449 /* genuinely conditional branches */
1450 TCGLabel
*label_match
= gen_new_label();
1451 arm_gen_test_cc(cond
, label_match
);
1452 gen_goto_tb(s
, 0, s
->pc
);
1453 gen_set_label(label_match
);
1454 gen_goto_tb(s
, 1, addr
);
1456 /* 0xe and 0xf are both "always" conditions */
1457 gen_goto_tb(s
, 0, addr
);
1461 /* HINT instruction group, including various allocated HINTs */
1462 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1463 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1465 unsigned int selector
= crm
<< 3 | op2
;
1468 unallocated_encoding(s
);
1476 s
->base
.is_jmp
= DISAS_WFI
;
1478 /* When running in MTTCG we don't generate jumps to the yield and
1479 * WFE helpers as it won't affect the scheduling of other vCPUs.
1480 * If we wanted to more completely model WFE/SEV so we don't busy
1481 * spin unnecessarily we would need to do something more involved.
1484 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1485 s
->base
.is_jmp
= DISAS_YIELD
;
1489 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1490 s
->base
.is_jmp
= DISAS_WFE
;
1495 /* we treat all as NOP at least for now */
1498 /* default specified as NOP equivalent */
1503 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1505 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1508 /* CLREX, DSB, DMB, ISB */
1509 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1510 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1515 unallocated_encoding(s
);
1526 case 1: /* MBReqTypes_Reads */
1527 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1529 case 2: /* MBReqTypes_Writes */
1530 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1532 default: /* MBReqTypes_All */
1533 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1539 /* We need to break the TB after this insn to execute
1540 * a self-modified code correctly and also to take
1541 * any pending interrupts immediately.
1543 gen_goto_tb(s
, 0, s
->pc
);
1546 unallocated_encoding(s
);
1551 /* MSR (immediate) - move immediate to processor state field */
1552 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1553 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1555 int op
= op1
<< 3 | op2
;
1557 case 0x05: /* SPSel */
1558 if (s
->current_el
== 0) {
1559 unallocated_encoding(s
);
1563 case 0x1e: /* DAIFSet */
1564 case 0x1f: /* DAIFClear */
1566 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1567 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1568 gen_a64_set_pc_im(s
->pc
- 4);
1569 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1570 tcg_temp_free_i32(tcg_imm
);
1571 tcg_temp_free_i32(tcg_op
);
1572 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1573 gen_a64_set_pc_im(s
->pc
);
1574 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1578 unallocated_encoding(s
);
1583 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1585 TCGv_i32 tmp
= tcg_temp_new_i32();
1586 TCGv_i32 nzcv
= tcg_temp_new_i32();
1588 /* build bit 31, N */
1589 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1590 /* build bit 30, Z */
1591 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1592 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1593 /* build bit 29, C */
1594 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1595 /* build bit 28, V */
1596 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1597 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1598 /* generate result */
1599 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1601 tcg_temp_free_i32(nzcv
);
1602 tcg_temp_free_i32(tmp
);
1605 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1608 TCGv_i32 nzcv
= tcg_temp_new_i32();
1610 /* take NZCV from R[t] */
1611 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1614 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1616 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1617 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1619 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1620 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1622 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1623 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1624 tcg_temp_free_i32(nzcv
);
1627 /* MRS - move from system register
1628 * MSR (register) - move to system register
1631 * These are all essentially the same insn in 'read' and 'write'
1632 * versions, with varying op0 fields.
1634 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1635 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1636 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1638 const ARMCPRegInfo
*ri
;
1641 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1642 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1643 crn
, crm
, op0
, op1
, op2
));
1646 /* Unknown register; this might be a guest error or a QEMU
1647 * unimplemented feature.
1649 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1650 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1651 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1652 unallocated_encoding(s
);
1656 /* Check access permissions */
1657 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1658 unallocated_encoding(s
);
1663 /* Emit code to perform further access permissions checks at
1664 * runtime; this may result in an exception.
1667 TCGv_i32 tcg_syn
, tcg_isread
;
1670 gen_a64_set_pc_im(s
->pc
- 4);
1671 tmpptr
= tcg_const_ptr(ri
);
1672 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1673 tcg_syn
= tcg_const_i32(syndrome
);
1674 tcg_isread
= tcg_const_i32(isread
);
1675 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1676 tcg_temp_free_ptr(tmpptr
);
1677 tcg_temp_free_i32(tcg_syn
);
1678 tcg_temp_free_i32(tcg_isread
);
1681 /* Handle special cases first */
1682 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1686 tcg_rt
= cpu_reg(s
, rt
);
1688 gen_get_nzcv(tcg_rt
);
1690 gen_set_nzcv(tcg_rt
);
1693 case ARM_CP_CURRENTEL
:
1694 /* Reads as current EL value from pstate, which is
1695 * guaranteed to be constant by the tb flags.
1697 tcg_rt
= cpu_reg(s
, rt
);
1698 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1701 /* Writes clear the aligned block of memory which rt points into. */
1702 tcg_rt
= cpu_reg(s
, rt
);
1703 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1708 if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1711 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1715 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1719 tcg_rt
= cpu_reg(s
, rt
);
1722 if (ri
->type
& ARM_CP_CONST
) {
1723 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1724 } else if (ri
->readfn
) {
1726 tmpptr
= tcg_const_ptr(ri
);
1727 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1728 tcg_temp_free_ptr(tmpptr
);
1730 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1733 if (ri
->type
& ARM_CP_CONST
) {
1734 /* If not forbidden by access permissions, treat as WI */
1736 } else if (ri
->writefn
) {
1738 tmpptr
= tcg_const_ptr(ri
);
1739 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1740 tcg_temp_free_ptr(tmpptr
);
1742 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1746 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1747 /* I/O operations must end the TB here (whether read or write) */
1749 s
->base
.is_jmp
= DISAS_UPDATE
;
1750 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1751 /* We default to ending the TB on a coprocessor register write,
1752 * but allow this to be suppressed by the register definition
1753 * (usually only necessary to work around guest bugs).
1755 s
->base
.is_jmp
= DISAS_UPDATE
;
1760 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1761 * +---------------------+---+-----+-----+-------+-------+-----+------+
1762 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1763 * +---------------------+---+-----+-----+-------+-------+-----+------+
1765 static void disas_system(DisasContext
*s
, uint32_t insn
)
1767 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1768 l
= extract32(insn
, 21, 1);
1769 op0
= extract32(insn
, 19, 2);
1770 op1
= extract32(insn
, 16, 3);
1771 crn
= extract32(insn
, 12, 4);
1772 crm
= extract32(insn
, 8, 4);
1773 op2
= extract32(insn
, 5, 3);
1774 rt
= extract32(insn
, 0, 5);
1777 if (l
|| rt
!= 31) {
1778 unallocated_encoding(s
);
1782 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1783 handle_hint(s
, insn
, op1
, op2
, crm
);
1785 case 3: /* CLREX, DSB, DMB, ISB */
1786 handle_sync(s
, insn
, op1
, op2
, crm
);
1788 case 4: /* MSR (immediate) */
1789 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1792 unallocated_encoding(s
);
1797 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1800 /* Exception generation
1802 * 31 24 23 21 20 5 4 2 1 0
1803 * +-----------------+-----+------------------------+-----+----+
1804 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1805 * +-----------------------+------------------------+----------+
1807 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1809 int opc
= extract32(insn
, 21, 3);
1810 int op2_ll
= extract32(insn
, 0, 5);
1811 int imm16
= extract32(insn
, 5, 16);
1816 /* For SVC, HVC and SMC we advance the single-step state
1817 * machine before taking the exception. This is architecturally
1818 * mandated, to ensure that single-stepping a system call
1819 * instruction works properly.
1824 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1825 default_exception_el(s
));
1828 if (s
->current_el
== 0) {
1829 unallocated_encoding(s
);
1832 /* The pre HVC helper handles cases when HVC gets trapped
1833 * as an undefined insn by runtime configuration.
1835 gen_a64_set_pc_im(s
->pc
- 4);
1836 gen_helper_pre_hvc(cpu_env
);
1838 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1841 if (s
->current_el
== 0) {
1842 unallocated_encoding(s
);
1845 gen_a64_set_pc_im(s
->pc
- 4);
1846 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1847 gen_helper_pre_smc(cpu_env
, tmp
);
1848 tcg_temp_free_i32(tmp
);
1850 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1853 unallocated_encoding(s
);
1859 unallocated_encoding(s
);
1863 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1867 unallocated_encoding(s
);
1870 /* HLT. This has two purposes.
1871 * Architecturally, it is an external halting debug instruction.
1872 * Since QEMU doesn't implement external debug, we treat this as
1873 * it is required for halting debug disabled: it will UNDEF.
1874 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1876 if (semihosting_enabled() && imm16
== 0xf000) {
1877 #ifndef CONFIG_USER_ONLY
1878 /* In system mode, don't allow userspace access to semihosting,
1879 * to provide some semblance of security (and for consistency
1880 * with our 32-bit semihosting).
1882 if (s
->current_el
== 0) {
1883 unsupported_encoding(s
, insn
);
1887 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1889 unsupported_encoding(s
, insn
);
1893 if (op2_ll
< 1 || op2_ll
> 3) {
1894 unallocated_encoding(s
);
1897 /* DCPS1, DCPS2, DCPS3 */
1898 unsupported_encoding(s
, insn
);
1901 unallocated_encoding(s
);
1906 /* Unconditional branch (register)
1907 * 31 25 24 21 20 16 15 10 9 5 4 0
1908 * +---------------+-------+-------+-------+------+-------+
1909 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1910 * +---------------+-------+-------+-------+------+-------+
1912 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1914 unsigned int opc
, op2
, op3
, rn
, op4
;
1916 opc
= extract32(insn
, 21, 4);
1917 op2
= extract32(insn
, 16, 5);
1918 op3
= extract32(insn
, 10, 6);
1919 rn
= extract32(insn
, 5, 5);
1920 op4
= extract32(insn
, 0, 5);
1922 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1923 unallocated_encoding(s
);
1931 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1932 /* BLR also needs to load return address */
1934 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1938 if (s
->current_el
== 0) {
1939 unallocated_encoding(s
);
1942 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1945 gen_helper_exception_return(cpu_env
);
1946 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1949 /* Must exit loop to check un-masked IRQs */
1950 s
->base
.is_jmp
= DISAS_EXIT
;
1954 unallocated_encoding(s
);
1956 unsupported_encoding(s
, insn
);
1960 unallocated_encoding(s
);
1964 s
->base
.is_jmp
= DISAS_JUMP
;
1967 /* Branches, exception generating and system instructions */
1968 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1970 switch (extract32(insn
, 25, 7)) {
1971 case 0x0a: case 0x0b:
1972 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1973 disas_uncond_b_imm(s
, insn
);
1975 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1976 disas_comp_b_imm(s
, insn
);
1978 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1979 disas_test_b_imm(s
, insn
);
1981 case 0x2a: /* Conditional branch (immediate) */
1982 disas_cond_b_imm(s
, insn
);
1984 case 0x6a: /* Exception generation / System */
1985 if (insn
& (1 << 24)) {
1986 disas_system(s
, insn
);
1991 case 0x6b: /* Unconditional branch (register) */
1992 disas_uncond_b_reg(s
, insn
);
1995 unallocated_encoding(s
);
2001 * Load/Store exclusive instructions are implemented by remembering
2002 * the value/address loaded, and seeing if these are the same
2003 * when the store is performed. This is not actually the architecturally
2004 * mandated semantics, but it works for typical guest code sequences
2005 * and avoids having to monitor regular stores.
2007 * The store exclusive uses the atomic cmpxchg primitives to avoid
2008 * races in multi-threaded linux-user and when MTTCG softmmu is
2011 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2012 TCGv_i64 addr
, int size
, bool is_pair
)
2014 int idx
= get_mem_index(s
);
2015 TCGMemOp memop
= s
->be_data
;
2017 g_assert(size
<= 3);
2019 g_assert(size
>= 2);
2021 /* The pair must be single-copy atomic for the doubleword. */
2022 memop
|= MO_64
| MO_ALIGN
;
2023 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2024 if (s
->be_data
== MO_LE
) {
2025 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2026 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2028 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2029 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2032 /* The pair must be single-copy atomic for *each* doubleword, not
2033 the entire quadword, however it must be quadword aligned. */
2035 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2036 memop
| MO_ALIGN_16
);
2038 TCGv_i64 addr2
= tcg_temp_new_i64();
2039 tcg_gen_addi_i64(addr2
, addr
, 8);
2040 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2041 tcg_temp_free_i64(addr2
);
2043 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2044 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2047 memop
|= size
| MO_ALIGN
;
2048 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2049 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2051 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2054 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2055 TCGv_i64 addr
, int size
, int is_pair
)
2057 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2058 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2061 * [addr + datasize] = {Rt2};
2067 * env->exclusive_addr = -1;
2069 TCGLabel
*fail_label
= gen_new_label();
2070 TCGLabel
*done_label
= gen_new_label();
2073 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2075 tmp
= tcg_temp_new_i64();
2078 if (s
->be_data
== MO_LE
) {
2079 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2081 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2083 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2084 cpu_exclusive_val
, tmp
,
2086 MO_64
| MO_ALIGN
| s
->be_data
);
2087 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2088 } else if (s
->be_data
== MO_LE
) {
2089 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2090 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2095 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2096 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2099 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2100 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2105 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2106 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2110 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2111 cpu_reg(s
, rt
), get_mem_index(s
),
2112 size
| MO_ALIGN
| s
->be_data
);
2113 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2115 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2116 tcg_temp_free_i64(tmp
);
2117 tcg_gen_br(done_label
);
2119 gen_set_label(fail_label
);
2120 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2121 gen_set_label(done_label
);
2122 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2125 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2128 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2129 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2130 int memidx
= get_mem_index(s
);
2131 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2134 gen_check_sp_alignment(s
);
2136 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, addr
, tcg_rs
, tcg_rt
, memidx
,
2137 size
| MO_ALIGN
| s
->be_data
);
2140 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2143 TCGv_i64 s1
= cpu_reg(s
, rs
);
2144 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2145 TCGv_i64 t1
= cpu_reg(s
, rt
);
2146 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2147 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2148 int memidx
= get_mem_index(s
);
2151 gen_check_sp_alignment(s
);
2155 TCGv_i64 cmp
= tcg_temp_new_i64();
2156 TCGv_i64 val
= tcg_temp_new_i64();
2158 if (s
->be_data
== MO_LE
) {
2159 tcg_gen_concat32_i64(val
, t1
, t2
);
2160 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2162 tcg_gen_concat32_i64(val
, t2
, t1
);
2163 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2166 tcg_gen_atomic_cmpxchg_i64(cmp
, addr
, cmp
, val
, memidx
,
2167 MO_64
| MO_ALIGN
| s
->be_data
);
2168 tcg_temp_free_i64(val
);
2170 if (s
->be_data
== MO_LE
) {
2171 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2173 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2175 tcg_temp_free_i64(cmp
);
2176 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2177 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2179 if (s
->be_data
== MO_LE
) {
2180 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2182 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2184 tcg_temp_free_i32(tcg_rs
);
2186 TCGv_i64 d1
= tcg_temp_new_i64();
2187 TCGv_i64 d2
= tcg_temp_new_i64();
2188 TCGv_i64 a2
= tcg_temp_new_i64();
2189 TCGv_i64 c1
= tcg_temp_new_i64();
2190 TCGv_i64 c2
= tcg_temp_new_i64();
2191 TCGv_i64 zero
= tcg_const_i64(0);
2193 /* Load the two words, in memory order. */
2194 tcg_gen_qemu_ld_i64(d1
, addr
, memidx
,
2195 MO_64
| MO_ALIGN_16
| s
->be_data
);
2196 tcg_gen_addi_i64(a2
, addr
, 8);
2197 tcg_gen_qemu_ld_i64(d2
, addr
, memidx
, MO_64
| s
->be_data
);
2199 /* Compare the two words, also in memory order. */
2200 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2201 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2202 tcg_gen_and_i64(c2
, c2
, c1
);
2204 /* If compare equal, write back new data, else write back old data. */
2205 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2206 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2207 tcg_gen_qemu_st_i64(c1
, addr
, memidx
, MO_64
| s
->be_data
);
2208 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2209 tcg_temp_free_i64(a2
);
2210 tcg_temp_free_i64(c1
);
2211 tcg_temp_free_i64(c2
);
2212 tcg_temp_free_i64(zero
);
2214 /* Write back the data from memory to Rs. */
2215 tcg_gen_mov_i64(s1
, d1
);
2216 tcg_gen_mov_i64(s2
, d2
);
2217 tcg_temp_free_i64(d1
);
2218 tcg_temp_free_i64(d2
);
2222 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2223 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2225 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2227 int opc0
= extract32(opc
, 0, 1);
2231 regsize
= opc0
? 32 : 64;
2233 regsize
= size
== 3 ? 64 : 32;
2235 return regsize
== 64;
2238 /* Load/store exclusive
2240 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2241 * +-----+-------------+----+---+----+------+----+-------+------+------+
2242 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2243 * +-----+-------------+----+---+----+------+----+-------+------+------+
2245 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2246 * L: 0 -> store, 1 -> load
2247 * o2: 0 -> exclusive, 1 -> not
2248 * o1: 0 -> single register, 1 -> register pair
2249 * o0: 1 -> load-acquire/store-release, 0 -> not
2251 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2253 int rt
= extract32(insn
, 0, 5);
2254 int rn
= extract32(insn
, 5, 5);
2255 int rt2
= extract32(insn
, 10, 5);
2256 int rs
= extract32(insn
, 16, 5);
2257 int is_lasr
= extract32(insn
, 15, 1);
2258 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2259 int size
= extract32(insn
, 30, 2);
2262 switch (o2_L_o1_o0
) {
2263 case 0x0: /* STXR */
2264 case 0x1: /* STLXR */
2266 gen_check_sp_alignment(s
);
2269 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2271 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2272 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, false);
2275 case 0x4: /* LDXR */
2276 case 0x5: /* LDAXR */
2278 gen_check_sp_alignment(s
);
2280 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2282 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, false);
2284 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2288 case 0x9: /* STLR */
2289 /* Generate ISS for non-exclusive accesses including LASR. */
2291 gen_check_sp_alignment(s
);
2293 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2294 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2295 do_gpr_st(s
, cpu_reg(s
, rt
), tcg_addr
, size
, true, rt
,
2296 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2299 case 0xd: /* LDAR */
2300 /* Generate ISS for non-exclusive accesses including LASR. */
2302 gen_check_sp_alignment(s
);
2304 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2305 do_gpr_ld(s
, cpu_reg(s
, rt
), tcg_addr
, size
, false, false, true, rt
,
2306 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2307 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2310 case 0x2: case 0x3: /* CASP / STXP */
2311 if (size
& 2) { /* STXP / STLXP */
2313 gen_check_sp_alignment(s
);
2316 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2318 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2319 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, true);
2323 && ((rt
| rs
) & 1) == 0
2324 && arm_dc_feature(s
, ARM_FEATURE_V8_ATOMICS
)) {
2326 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2331 case 0x6: case 0x7: /* CASPA / LDXP */
2332 if (size
& 2) { /* LDXP / LDAXP */
2334 gen_check_sp_alignment(s
);
2336 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2338 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, true);
2340 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2345 && ((rt
| rs
) & 1) == 0
2346 && arm_dc_feature(s
, ARM_FEATURE_V8_ATOMICS
)) {
2347 /* CASPA / CASPAL */
2348 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2354 case 0xb: /* CASL */
2355 case 0xe: /* CASA */
2356 case 0xf: /* CASAL */
2357 if (rt2
== 31 && arm_dc_feature(s
, ARM_FEATURE_V8_ATOMICS
)) {
2358 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2363 unallocated_encoding(s
);
2367 * Load register (literal)
2369 * 31 30 29 27 26 25 24 23 5 4 0
2370 * +-----+-------+---+-----+-------------------+-------+
2371 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2372 * +-----+-------+---+-----+-------------------+-------+
2374 * V: 1 -> vector (simd/fp)
2375 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2376 * 10-> 32 bit signed, 11 -> prefetch
2377 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2379 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2381 int rt
= extract32(insn
, 0, 5);
2382 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2383 bool is_vector
= extract32(insn
, 26, 1);
2384 int opc
= extract32(insn
, 30, 2);
2385 bool is_signed
= false;
2387 TCGv_i64 tcg_rt
, tcg_addr
;
2391 unallocated_encoding(s
);
2395 if (!fp_access_check(s
)) {
2400 /* PRFM (literal) : prefetch */
2403 size
= 2 + extract32(opc
, 0, 1);
2404 is_signed
= extract32(opc
, 1, 1);
2407 tcg_rt
= cpu_reg(s
, rt
);
2409 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2411 do_fp_ld(s
, rt
, tcg_addr
, size
);
2413 /* Only unsigned 32bit loads target 32bit registers. */
2414 bool iss_sf
= opc
!= 0;
2416 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2417 true, rt
, iss_sf
, false);
2419 tcg_temp_free_i64(tcg_addr
);
2423 * LDNP (Load Pair - non-temporal hint)
2424 * LDP (Load Pair - non vector)
2425 * LDPSW (Load Pair Signed Word - non vector)
2426 * STNP (Store Pair - non-temporal hint)
2427 * STP (Store Pair - non vector)
2428 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2429 * LDP (Load Pair of SIMD&FP)
2430 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2431 * STP (Store Pair of SIMD&FP)
2433 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2434 * +-----+-------+---+---+-------+---+-----------------------------+
2435 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2436 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2438 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2440 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2441 * V: 0 -> GPR, 1 -> Vector
2442 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2443 * 10 -> signed offset, 11 -> pre-index
2444 * L: 0 -> Store 1 -> Load
2446 * Rt, Rt2 = GPR or SIMD registers to be stored
2447 * Rn = general purpose register containing address
2448 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2450 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2452 int rt
= extract32(insn
, 0, 5);
2453 int rn
= extract32(insn
, 5, 5);
2454 int rt2
= extract32(insn
, 10, 5);
2455 uint64_t offset
= sextract64(insn
, 15, 7);
2456 int index
= extract32(insn
, 23, 2);
2457 bool is_vector
= extract32(insn
, 26, 1);
2458 bool is_load
= extract32(insn
, 22, 1);
2459 int opc
= extract32(insn
, 30, 2);
2461 bool is_signed
= false;
2462 bool postindex
= false;
2465 TCGv_i64 tcg_addr
; /* calculated address */
2469 unallocated_encoding(s
);
2476 size
= 2 + extract32(opc
, 1, 1);
2477 is_signed
= extract32(opc
, 0, 1);
2478 if (!is_load
&& is_signed
) {
2479 unallocated_encoding(s
);
2485 case 1: /* post-index */
2490 /* signed offset with "non-temporal" hint. Since we don't emulate
2491 * caches we don't care about hints to the cache system about
2492 * data access patterns, and handle this identically to plain
2496 /* There is no non-temporal-hint version of LDPSW */
2497 unallocated_encoding(s
);
2502 case 2: /* signed offset, rn not updated */
2505 case 3: /* pre-index */
2511 if (is_vector
&& !fp_access_check(s
)) {
2518 gen_check_sp_alignment(s
);
2521 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2524 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2529 do_fp_ld(s
, rt
, tcg_addr
, size
);
2531 do_fp_st(s
, rt
, tcg_addr
, size
);
2533 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2535 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2537 do_fp_st(s
, rt2
, tcg_addr
, size
);
2540 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2541 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2544 TCGv_i64 tmp
= tcg_temp_new_i64();
2546 /* Do not modify tcg_rt before recognizing any exception
2547 * from the second load.
2549 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2550 false, 0, false, false);
2551 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2552 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2553 false, 0, false, false);
2555 tcg_gen_mov_i64(tcg_rt
, tmp
);
2556 tcg_temp_free_i64(tmp
);
2558 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2559 false, 0, false, false);
2560 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2561 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2562 false, 0, false, false);
2568 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2570 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2572 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2577 * Load/store (immediate post-indexed)
2578 * Load/store (immediate pre-indexed)
2579 * Load/store (unscaled immediate)
2581 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2582 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2583 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2584 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2586 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2588 * V = 0 -> non-vector
2589 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2590 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2592 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2598 int rn
= extract32(insn
, 5, 5);
2599 int imm9
= sextract32(insn
, 12, 9);
2600 int idx
= extract32(insn
, 10, 2);
2601 bool is_signed
= false;
2602 bool is_store
= false;
2603 bool is_extended
= false;
2604 bool is_unpriv
= (idx
== 2);
2605 bool iss_valid
= !is_vector
;
2612 size
|= (opc
& 2) << 1;
2613 if (size
> 4 || is_unpriv
) {
2614 unallocated_encoding(s
);
2617 is_store
= ((opc
& 1) == 0);
2618 if (!fp_access_check(s
)) {
2622 if (size
== 3 && opc
== 2) {
2623 /* PRFM - prefetch */
2625 unallocated_encoding(s
);
2630 if (opc
== 3 && size
> 1) {
2631 unallocated_encoding(s
);
2634 is_store
= (opc
== 0);
2635 is_signed
= extract32(opc
, 1, 1);
2636 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2654 g_assert_not_reached();
2658 gen_check_sp_alignment(s
);
2660 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2663 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2668 do_fp_st(s
, rt
, tcg_addr
, size
);
2670 do_fp_ld(s
, rt
, tcg_addr
, size
);
2673 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2674 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2675 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2678 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2679 iss_valid
, rt
, iss_sf
, false);
2681 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2682 is_signed
, is_extended
, memidx
,
2683 iss_valid
, rt
, iss_sf
, false);
2688 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2690 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2692 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2697 * Load/store (register offset)
2699 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2700 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2701 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2702 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2705 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2706 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2708 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2709 * opc<0>: 0 -> store, 1 -> load
2710 * V: 1 -> vector/simd
2711 * opt: extend encoding (see DecodeRegExtend)
2712 * S: if S=1 then scale (essentially index by sizeof(size))
2713 * Rt: register to transfer into/out of
2714 * Rn: address register or SP for base
2715 * Rm: offset register or ZR for offset
2717 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2723 int rn
= extract32(insn
, 5, 5);
2724 int shift
= extract32(insn
, 12, 1);
2725 int rm
= extract32(insn
, 16, 5);
2726 int opt
= extract32(insn
, 13, 3);
2727 bool is_signed
= false;
2728 bool is_store
= false;
2729 bool is_extended
= false;
2734 if (extract32(opt
, 1, 1) == 0) {
2735 unallocated_encoding(s
);
2740 size
|= (opc
& 2) << 1;
2742 unallocated_encoding(s
);
2745 is_store
= !extract32(opc
, 0, 1);
2746 if (!fp_access_check(s
)) {
2750 if (size
== 3 && opc
== 2) {
2751 /* PRFM - prefetch */
2754 if (opc
== 3 && size
> 1) {
2755 unallocated_encoding(s
);
2758 is_store
= (opc
== 0);
2759 is_signed
= extract32(opc
, 1, 1);
2760 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2764 gen_check_sp_alignment(s
);
2766 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2768 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2769 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2771 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2775 do_fp_st(s
, rt
, tcg_addr
, size
);
2777 do_fp_ld(s
, rt
, tcg_addr
, size
);
2780 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2781 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2783 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2784 true, rt
, iss_sf
, false);
2786 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2787 is_signed
, is_extended
,
2788 true, rt
, iss_sf
, false);
2794 * Load/store (unsigned immediate)
2796 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2797 * +----+-------+---+-----+-----+------------+-------+------+
2798 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2799 * +----+-------+---+-----+-----+------------+-------+------+
2802 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2803 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2805 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2806 * opc<0>: 0 -> store, 1 -> load
2807 * Rn: base address register (inc SP)
2808 * Rt: target register
2810 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2816 int rn
= extract32(insn
, 5, 5);
2817 unsigned int imm12
= extract32(insn
, 10, 12);
2818 unsigned int offset
;
2823 bool is_signed
= false;
2824 bool is_extended
= false;
2827 size
|= (opc
& 2) << 1;
2829 unallocated_encoding(s
);
2832 is_store
= !extract32(opc
, 0, 1);
2833 if (!fp_access_check(s
)) {
2837 if (size
== 3 && opc
== 2) {
2838 /* PRFM - prefetch */
2841 if (opc
== 3 && size
> 1) {
2842 unallocated_encoding(s
);
2845 is_store
= (opc
== 0);
2846 is_signed
= extract32(opc
, 1, 1);
2847 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2851 gen_check_sp_alignment(s
);
2853 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2854 offset
= imm12
<< size
;
2855 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2859 do_fp_st(s
, rt
, tcg_addr
, size
);
2861 do_fp_ld(s
, rt
, tcg_addr
, size
);
2864 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2865 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2867 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2868 true, rt
, iss_sf
, false);
2870 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2871 true, rt
, iss_sf
, false);
2876 /* Atomic memory operations
2878 * 31 30 27 26 24 22 21 16 15 12 10 5 0
2879 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
2880 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
2881 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
2883 * Rt: the result register
2884 * Rn: base address or SP
2885 * Rs: the source register for the operation
2886 * V: vector flag (always 0 as of v8.3)
2890 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
2891 int size
, int rt
, bool is_vector
)
2893 int rs
= extract32(insn
, 16, 5);
2894 int rn
= extract32(insn
, 5, 5);
2895 int o3_opc
= extract32(insn
, 12, 4);
2896 int feature
= ARM_FEATURE_V8_ATOMICS
;
2897 TCGv_i64 tcg_rn
, tcg_rs
;
2898 AtomicThreeOpFn
*fn
;
2901 unallocated_encoding(s
);
2905 case 000: /* LDADD */
2906 fn
= tcg_gen_atomic_fetch_add_i64
;
2908 case 001: /* LDCLR */
2909 fn
= tcg_gen_atomic_fetch_and_i64
;
2911 case 002: /* LDEOR */
2912 fn
= tcg_gen_atomic_fetch_xor_i64
;
2914 case 003: /* LDSET */
2915 fn
= tcg_gen_atomic_fetch_or_i64
;
2917 case 004: /* LDSMAX */
2918 fn
= tcg_gen_atomic_fetch_smax_i64
;
2920 case 005: /* LDSMIN */
2921 fn
= tcg_gen_atomic_fetch_smin_i64
;
2923 case 006: /* LDUMAX */
2924 fn
= tcg_gen_atomic_fetch_umax_i64
;
2926 case 007: /* LDUMIN */
2927 fn
= tcg_gen_atomic_fetch_umin_i64
;
2930 fn
= tcg_gen_atomic_xchg_i64
;
2933 unallocated_encoding(s
);
2936 if (!arm_dc_feature(s
, feature
)) {
2937 unallocated_encoding(s
);
2942 gen_check_sp_alignment(s
);
2944 tcg_rn
= cpu_reg_sp(s
, rn
);
2945 tcg_rs
= read_cpu_reg(s
, rs
, true);
2947 if (o3_opc
== 1) { /* LDCLR */
2948 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
2951 /* The tcg atomic primitives are all full barriers. Therefore we
2952 * can ignore the Acquire and Release bits of this instruction.
2954 fn(cpu_reg(s
, rt
), tcg_rn
, tcg_rs
, get_mem_index(s
),
2955 s
->be_data
| size
| MO_ALIGN
);
2958 /* Load/store register (all forms) */
2959 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2961 int rt
= extract32(insn
, 0, 5);
2962 int opc
= extract32(insn
, 22, 2);
2963 bool is_vector
= extract32(insn
, 26, 1);
2964 int size
= extract32(insn
, 30, 2);
2966 switch (extract32(insn
, 24, 2)) {
2968 if (extract32(insn
, 21, 1) == 0) {
2969 /* Load/store register (unscaled immediate)
2970 * Load/store immediate pre/post-indexed
2971 * Load/store register unprivileged
2973 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2976 switch (extract32(insn
, 10, 2)) {
2978 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
2981 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2986 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2989 unallocated_encoding(s
);
2992 /* AdvSIMD load/store multiple structures
2994 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2995 * +---+---+---------------+---+-------------+--------+------+------+------+
2996 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2997 * +---+---+---------------+---+-------------+--------+------+------+------+
2999 * AdvSIMD load/store multiple structures (post-indexed)
3001 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3002 * +---+---+---------------+---+---+---------+--------+------+------+------+
3003 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3004 * +---+---+---------------+---+---+---------+--------+------+------+------+
3006 * Rt: first (or only) SIMD&FP register to be transferred
3007 * Rn: base address or SP
3008 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3010 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3012 int rt
= extract32(insn
, 0, 5);
3013 int rn
= extract32(insn
, 5, 5);
3014 int size
= extract32(insn
, 10, 2);
3015 int opcode
= extract32(insn
, 12, 4);
3016 bool is_store
= !extract32(insn
, 22, 1);
3017 bool is_postidx
= extract32(insn
, 23, 1);
3018 bool is_q
= extract32(insn
, 30, 1);
3019 TCGv_i64 tcg_addr
, tcg_rn
;
3021 int ebytes
= 1 << size
;
3022 int elements
= (is_q
? 128 : 64) / (8 << size
);
3023 int rpt
; /* num iterations */
3024 int selem
; /* structure elements */
3027 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3028 unallocated_encoding(s
);
3032 /* From the shared decode logic */
3063 unallocated_encoding(s
);
3067 if (size
== 3 && !is_q
&& selem
!= 1) {
3069 unallocated_encoding(s
);
3073 if (!fp_access_check(s
)) {
3078 gen_check_sp_alignment(s
);
3081 tcg_rn
= cpu_reg_sp(s
, rn
);
3082 tcg_addr
= tcg_temp_new_i64();
3083 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3085 for (r
= 0; r
< rpt
; r
++) {
3087 for (e
= 0; e
< elements
; e
++) {
3088 int tt
= (rt
+ r
) % 32;
3090 for (xs
= 0; xs
< selem
; xs
++) {
3092 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
3094 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
3096 /* For non-quad operations, setting a slice of the low
3097 * 64 bits of the register clears the high 64 bits (in
3098 * the ARM ARM pseudocode this is implicit in the fact
3099 * that 'rval' is a 64 bit wide variable).
3100 * For quad operations, we might still need to zero the
3101 * high bits of SVE. We optimize by noticing that we only
3102 * need to do this the first time we touch a register.
3104 if (e
== 0 && (r
== 0 || xs
== selem
- 1)) {
3105 clear_vec_high(s
, is_q
, tt
);
3108 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
3115 int rm
= extract32(insn
, 16, 5);
3117 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3119 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3122 tcg_temp_free_i64(tcg_addr
);
3125 /* AdvSIMD load/store single structure
3127 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3128 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3129 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3130 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3132 * AdvSIMD load/store single structure (post-indexed)
3134 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3135 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3136 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3137 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3139 * Rt: first (or only) SIMD&FP register to be transferred
3140 * Rn: base address or SP
3141 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3142 * index = encoded in Q:S:size dependent on size
3144 * lane_size = encoded in R, opc
3145 * transfer width = encoded in opc, S, size
3147 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3149 int rt
= extract32(insn
, 0, 5);
3150 int rn
= extract32(insn
, 5, 5);
3151 int size
= extract32(insn
, 10, 2);
3152 int S
= extract32(insn
, 12, 1);
3153 int opc
= extract32(insn
, 13, 3);
3154 int R
= extract32(insn
, 21, 1);
3155 int is_load
= extract32(insn
, 22, 1);
3156 int is_postidx
= extract32(insn
, 23, 1);
3157 int is_q
= extract32(insn
, 30, 1);
3159 int scale
= extract32(opc
, 1, 2);
3160 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3161 bool replicate
= false;
3162 int index
= is_q
<< 3 | S
<< 2 | size
;
3164 TCGv_i64 tcg_addr
, tcg_rn
;
3168 if (!is_load
|| S
) {
3169 unallocated_encoding(s
);
3178 if (extract32(size
, 0, 1)) {
3179 unallocated_encoding(s
);
3185 if (extract32(size
, 1, 1)) {
3186 unallocated_encoding(s
);
3189 if (!extract32(size
, 0, 1)) {
3193 unallocated_encoding(s
);
3201 g_assert_not_reached();
3204 if (!fp_access_check(s
)) {
3208 ebytes
= 1 << scale
;
3211 gen_check_sp_alignment(s
);
3214 tcg_rn
= cpu_reg_sp(s
, rn
);
3215 tcg_addr
= tcg_temp_new_i64();
3216 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3218 for (xs
= 0; xs
< selem
; xs
++) {
3220 /* Load and replicate to all elements */
3222 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3224 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
3225 get_mem_index(s
), s
->be_data
+ scale
);
3228 mulconst
= 0x0101010101010101ULL
;
3231 mulconst
= 0x0001000100010001ULL
;
3234 mulconst
= 0x0000000100000001ULL
;
3240 g_assert_not_reached();
3243 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
3245 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
3247 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
3249 tcg_temp_free_i64(tcg_tmp
);
3250 clear_vec_high(s
, is_q
, rt
);
3252 /* Load/store one element per register */
3254 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
3256 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
3259 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
3264 int rm
= extract32(insn
, 16, 5);
3266 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3268 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3271 tcg_temp_free_i64(tcg_addr
);
3274 /* Loads and stores */
3275 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3277 switch (extract32(insn
, 24, 6)) {
3278 case 0x08: /* Load/store exclusive */
3279 disas_ldst_excl(s
, insn
);
3281 case 0x18: case 0x1c: /* Load register (literal) */
3282 disas_ld_lit(s
, insn
);
3284 case 0x28: case 0x29:
3285 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3286 disas_ldst_pair(s
, insn
);
3288 case 0x38: case 0x39:
3289 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3290 disas_ldst_reg(s
, insn
);
3292 case 0x0c: /* AdvSIMD load/store multiple structures */
3293 disas_ldst_multiple_struct(s
, insn
);
3295 case 0x0d: /* AdvSIMD load/store single structure */
3296 disas_ldst_single_struct(s
, insn
);
3299 unallocated_encoding(s
);
3304 /* PC-rel. addressing
3305 * 31 30 29 28 24 23 5 4 0
3306 * +----+-------+-----------+-------------------+------+
3307 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3308 * +----+-------+-----------+-------------------+------+
3310 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3312 unsigned int page
, rd
;
3316 page
= extract32(insn
, 31, 1);
3317 /* SignExtend(immhi:immlo) -> offset */
3318 offset
= sextract64(insn
, 5, 19);
3319 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3320 rd
= extract32(insn
, 0, 5);
3324 /* ADRP (page based) */
3329 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3333 * Add/subtract (immediate)
3335 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3336 * +--+--+--+-----------+-----+-------------+-----+-----+
3337 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3338 * +--+--+--+-----------+-----+-------------+-----+-----+
3340 * sf: 0 -> 32bit, 1 -> 64bit
3341 * op: 0 -> add , 1 -> sub
3343 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3345 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3347 int rd
= extract32(insn
, 0, 5);
3348 int rn
= extract32(insn
, 5, 5);
3349 uint64_t imm
= extract32(insn
, 10, 12);
3350 int shift
= extract32(insn
, 22, 2);
3351 bool setflags
= extract32(insn
, 29, 1);
3352 bool sub_op
= extract32(insn
, 30, 1);
3353 bool is_64bit
= extract32(insn
, 31, 1);
3355 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3356 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3357 TCGv_i64 tcg_result
;
3366 unallocated_encoding(s
);
3370 tcg_result
= tcg_temp_new_i64();
3373 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3375 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3378 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3380 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3382 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3384 tcg_temp_free_i64(tcg_imm
);
3388 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3390 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3393 tcg_temp_free_i64(tcg_result
);
3396 /* The input should be a value in the bottom e bits (with higher
3397 * bits zero); returns that value replicated into every element
3398 * of size e in a 64 bit integer.
3400 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3410 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3411 static inline uint64_t bitmask64(unsigned int length
)
3413 assert(length
> 0 && length
<= 64);
3414 return ~0ULL >> (64 - length
);
3417 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3418 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3419 * value (ie should cause a guest UNDEF exception), and true if they are
3420 * valid, in which case the decoded bit pattern is written to result.
3422 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3423 unsigned int imms
, unsigned int immr
)
3426 unsigned e
, levels
, s
, r
;
3429 assert(immn
< 2 && imms
< 64 && immr
< 64);
3431 /* The bit patterns we create here are 64 bit patterns which
3432 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3433 * 64 bits each. Each element contains the same value: a run
3434 * of between 1 and e-1 non-zero bits, rotated within the
3435 * element by between 0 and e-1 bits.
3437 * The element size and run length are encoded into immn (1 bit)
3438 * and imms (6 bits) as follows:
3439 * 64 bit elements: immn = 1, imms = <length of run - 1>
3440 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3441 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3442 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3443 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3444 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3445 * Notice that immn = 0, imms = 11111x is the only combination
3446 * not covered by one of the above options; this is reserved.
3447 * Further, <length of run - 1> all-ones is a reserved pattern.
3449 * In all cases the rotation is by immr % e (and immr is 6 bits).
3452 /* First determine the element size */
3453 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3455 /* This is the immn == 0, imms == 0x11111x case */
3465 /* <length of run - 1> mustn't be all-ones. */
3469 /* Create the value of one element: s+1 set bits rotated
3470 * by r within the element (which is e bits wide)...
3472 mask
= bitmask64(s
+ 1);
3474 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3475 mask
&= bitmask64(e
);
3477 /* ...then replicate the element over the whole 64 bit value */
3478 mask
= bitfield_replicate(mask
, e
);
3483 /* Logical (immediate)
3484 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3485 * +----+-----+-------------+---+------+------+------+------+
3486 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3487 * +----+-----+-------------+---+------+------+------+------+
3489 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3491 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3492 TCGv_i64 tcg_rd
, tcg_rn
;
3494 bool is_and
= false;
3496 sf
= extract32(insn
, 31, 1);
3497 opc
= extract32(insn
, 29, 2);
3498 is_n
= extract32(insn
, 22, 1);
3499 immr
= extract32(insn
, 16, 6);
3500 imms
= extract32(insn
, 10, 6);
3501 rn
= extract32(insn
, 5, 5);
3502 rd
= extract32(insn
, 0, 5);
3505 unallocated_encoding(s
);
3509 if (opc
== 0x3) { /* ANDS */
3510 tcg_rd
= cpu_reg(s
, rd
);
3512 tcg_rd
= cpu_reg_sp(s
, rd
);
3514 tcg_rn
= cpu_reg(s
, rn
);
3516 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3517 /* some immediate field values are reserved */
3518 unallocated_encoding(s
);
3523 wmask
&= 0xffffffff;
3527 case 0x3: /* ANDS */
3529 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3533 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3536 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3539 assert(FALSE
); /* must handle all above */
3543 if (!sf
&& !is_and
) {
3544 /* zero extend final result; we know we can skip this for AND
3545 * since the immediate had the high 32 bits clear.
3547 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3550 if (opc
== 3) { /* ANDS */
3551 gen_logic_CC(sf
, tcg_rd
);
3556 * Move wide (immediate)
3558 * 31 30 29 28 23 22 21 20 5 4 0
3559 * +--+-----+-------------+-----+----------------+------+
3560 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3561 * +--+-----+-------------+-----+----------------+------+
3563 * sf: 0 -> 32 bit, 1 -> 64 bit
3564 * opc: 00 -> N, 10 -> Z, 11 -> K
3565 * hw: shift/16 (0,16, and sf only 32, 48)
3567 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3569 int rd
= extract32(insn
, 0, 5);
3570 uint64_t imm
= extract32(insn
, 5, 16);
3571 int sf
= extract32(insn
, 31, 1);
3572 int opc
= extract32(insn
, 29, 2);
3573 int pos
= extract32(insn
, 21, 2) << 4;
3574 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3577 if (!sf
&& (pos
>= 32)) {
3578 unallocated_encoding(s
);
3592 tcg_gen_movi_i64(tcg_rd
, imm
);
3595 tcg_imm
= tcg_const_i64(imm
);
3596 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3597 tcg_temp_free_i64(tcg_imm
);
3599 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3603 unallocated_encoding(s
);
3609 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3610 * +----+-----+-------------+---+------+------+------+------+
3611 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3612 * +----+-----+-------------+---+------+------+------+------+
3614 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3616 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3617 TCGv_i64 tcg_rd
, tcg_tmp
;
3619 sf
= extract32(insn
, 31, 1);
3620 opc
= extract32(insn
, 29, 2);
3621 n
= extract32(insn
, 22, 1);
3622 ri
= extract32(insn
, 16, 6);
3623 si
= extract32(insn
, 10, 6);
3624 rn
= extract32(insn
, 5, 5);
3625 rd
= extract32(insn
, 0, 5);
3626 bitsize
= sf
? 64 : 32;
3628 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3629 unallocated_encoding(s
);
3633 tcg_rd
= cpu_reg(s
, rd
);
3635 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3636 to be smaller than bitsize, we'll never reference data outside the
3637 low 32-bits anyway. */
3638 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3640 /* Recognize simple(r) extractions. */
3642 /* Wd<s-r:0> = Wn<s:r> */
3643 len
= (si
- ri
) + 1;
3644 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3645 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3647 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3648 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3651 /* opc == 1, BXFIL fall through to deposit */
3652 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3655 /* Handle the ri > si case with a deposit
3656 * Wd<32+s-r,32-r> = Wn<s:0>
3659 pos
= (bitsize
- ri
) & (bitsize
- 1);
3662 if (opc
== 0 && len
< ri
) {
3663 /* SBFM: sign extend the destination field from len to fill
3664 the balance of the word. Let the deposit below insert all
3665 of those sign bits. */
3666 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3670 if (opc
== 1) { /* BFM, BXFIL */
3671 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3673 /* SBFM or UBFM: We start with zero, and we haven't modified
3674 any bits outside bitsize, therefore the zero-extension
3675 below is unneeded. */
3676 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3681 if (!sf
) { /* zero extend final result */
3682 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3687 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3688 * +----+------+-------------+---+----+------+--------+------+------+
3689 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3690 * +----+------+-------------+---+----+------+--------+------+------+
3692 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3694 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3696 sf
= extract32(insn
, 31, 1);
3697 n
= extract32(insn
, 22, 1);
3698 rm
= extract32(insn
, 16, 5);
3699 imm
= extract32(insn
, 10, 6);
3700 rn
= extract32(insn
, 5, 5);
3701 rd
= extract32(insn
, 0, 5);
3702 op21
= extract32(insn
, 29, 2);
3703 op0
= extract32(insn
, 21, 1);
3704 bitsize
= sf
? 64 : 32;
3706 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3707 unallocated_encoding(s
);
3709 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3711 tcg_rd
= cpu_reg(s
, rd
);
3713 if (unlikely(imm
== 0)) {
3714 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3715 * so an extract from bit 0 is a special case.
3718 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3720 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3722 } else if (rm
== rn
) { /* ROR */
3723 tcg_rm
= cpu_reg(s
, rm
);
3725 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3727 TCGv_i32 tmp
= tcg_temp_new_i32();
3728 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3729 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3730 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3731 tcg_temp_free_i32(tmp
);
3734 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3735 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3736 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3737 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3738 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3740 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3746 /* Data processing - immediate */
3747 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3749 switch (extract32(insn
, 23, 6)) {
3750 case 0x20: case 0x21: /* PC-rel. addressing */
3751 disas_pc_rel_adr(s
, insn
);
3753 case 0x22: case 0x23: /* Add/subtract (immediate) */
3754 disas_add_sub_imm(s
, insn
);
3756 case 0x24: /* Logical (immediate) */
3757 disas_logic_imm(s
, insn
);
3759 case 0x25: /* Move wide (immediate) */
3760 disas_movw_imm(s
, insn
);
3762 case 0x26: /* Bitfield */
3763 disas_bitfield(s
, insn
);
3765 case 0x27: /* Extract */
3766 disas_extract(s
, insn
);
3769 unallocated_encoding(s
);
3774 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3775 * Note that it is the caller's responsibility to ensure that the
3776 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3777 * mandated semantics for out of range shifts.
3779 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3780 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3782 switch (shift_type
) {
3783 case A64_SHIFT_TYPE_LSL
:
3784 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3786 case A64_SHIFT_TYPE_LSR
:
3787 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3789 case A64_SHIFT_TYPE_ASR
:
3791 tcg_gen_ext32s_i64(dst
, src
);
3793 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3795 case A64_SHIFT_TYPE_ROR
:
3797 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3800 t0
= tcg_temp_new_i32();
3801 t1
= tcg_temp_new_i32();
3802 tcg_gen_extrl_i64_i32(t0
, src
);
3803 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3804 tcg_gen_rotr_i32(t0
, t0
, t1
);
3805 tcg_gen_extu_i32_i64(dst
, t0
);
3806 tcg_temp_free_i32(t0
);
3807 tcg_temp_free_i32(t1
);
3811 assert(FALSE
); /* all shift types should be handled */
3815 if (!sf
) { /* zero extend final result */
3816 tcg_gen_ext32u_i64(dst
, dst
);
3820 /* Shift a TCGv src by immediate, put result in dst.
3821 * The shift amount must be in range (this should always be true as the
3822 * relevant instructions will UNDEF on bad shift immediates).
3824 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3825 enum a64_shift_type shift_type
, unsigned int shift_i
)
3827 assert(shift_i
< (sf
? 64 : 32));
3830 tcg_gen_mov_i64(dst
, src
);
3832 TCGv_i64 shift_const
;
3834 shift_const
= tcg_const_i64(shift_i
);
3835 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3836 tcg_temp_free_i64(shift_const
);
3840 /* Logical (shifted register)
3841 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3842 * +----+-----+-----------+-------+---+------+--------+------+------+
3843 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3844 * +----+-----+-----------+-------+---+------+--------+------+------+
3846 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3848 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3849 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3851 sf
= extract32(insn
, 31, 1);
3852 opc
= extract32(insn
, 29, 2);
3853 shift_type
= extract32(insn
, 22, 2);
3854 invert
= extract32(insn
, 21, 1);
3855 rm
= extract32(insn
, 16, 5);
3856 shift_amount
= extract32(insn
, 10, 6);
3857 rn
= extract32(insn
, 5, 5);
3858 rd
= extract32(insn
, 0, 5);
3860 if (!sf
&& (shift_amount
& (1 << 5))) {
3861 unallocated_encoding(s
);
3865 tcg_rd
= cpu_reg(s
, rd
);
3867 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3868 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3869 * register-register MOV and MVN, so it is worth special casing.
3871 tcg_rm
= cpu_reg(s
, rm
);
3873 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3875 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3879 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3881 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3887 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3890 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3893 tcg_rn
= cpu_reg(s
, rn
);
3895 switch (opc
| (invert
<< 2)) {
3898 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3901 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3904 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3908 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3911 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3914 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3922 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3926 gen_logic_CC(sf
, tcg_rd
);
3931 * Add/subtract (extended register)
3933 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3934 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3935 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3936 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3938 * sf: 0 -> 32bit, 1 -> 64bit
3939 * op: 0 -> add , 1 -> sub
3942 * option: extension type (see DecodeRegExtend)
3943 * imm3: optional shift to Rm
3945 * Rd = Rn + LSL(extend(Rm), amount)
3947 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3949 int rd
= extract32(insn
, 0, 5);
3950 int rn
= extract32(insn
, 5, 5);
3951 int imm3
= extract32(insn
, 10, 3);
3952 int option
= extract32(insn
, 13, 3);
3953 int rm
= extract32(insn
, 16, 5);
3954 bool setflags
= extract32(insn
, 29, 1);
3955 bool sub_op
= extract32(insn
, 30, 1);
3956 bool sf
= extract32(insn
, 31, 1);
3958 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3960 TCGv_i64 tcg_result
;
3963 unallocated_encoding(s
);
3967 /* non-flag setting ops may use SP */
3969 tcg_rd
= cpu_reg_sp(s
, rd
);
3971 tcg_rd
= cpu_reg(s
, rd
);
3973 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3975 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3976 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3978 tcg_result
= tcg_temp_new_i64();
3982 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3984 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3988 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3990 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3995 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3997 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4000 tcg_temp_free_i64(tcg_result
);
4004 * Add/subtract (shifted register)
4006 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4007 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4008 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4009 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4011 * sf: 0 -> 32bit, 1 -> 64bit
4012 * op: 0 -> add , 1 -> sub
4014 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4015 * imm6: Shift amount to apply to Rm before the add/sub
4017 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4019 int rd
= extract32(insn
, 0, 5);
4020 int rn
= extract32(insn
, 5, 5);
4021 int imm6
= extract32(insn
, 10, 6);
4022 int rm
= extract32(insn
, 16, 5);
4023 int shift_type
= extract32(insn
, 22, 2);
4024 bool setflags
= extract32(insn
, 29, 1);
4025 bool sub_op
= extract32(insn
, 30, 1);
4026 bool sf
= extract32(insn
, 31, 1);
4028 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4029 TCGv_i64 tcg_rn
, tcg_rm
;
4030 TCGv_i64 tcg_result
;
4032 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4033 unallocated_encoding(s
);
4037 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4038 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4040 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4042 tcg_result
= tcg_temp_new_i64();
4046 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4048 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4052 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4054 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4059 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4061 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4064 tcg_temp_free_i64(tcg_result
);
4067 /* Data-processing (3 source)
4069 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4070 * +--+------+-----------+------+------+----+------+------+------+
4071 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4072 * +--+------+-----------+------+------+----+------+------+------+
4074 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4076 int rd
= extract32(insn
, 0, 5);
4077 int rn
= extract32(insn
, 5, 5);
4078 int ra
= extract32(insn
, 10, 5);
4079 int rm
= extract32(insn
, 16, 5);
4080 int op_id
= (extract32(insn
, 29, 3) << 4) |
4081 (extract32(insn
, 21, 3) << 1) |
4082 extract32(insn
, 15, 1);
4083 bool sf
= extract32(insn
, 31, 1);
4084 bool is_sub
= extract32(op_id
, 0, 1);
4085 bool is_high
= extract32(op_id
, 2, 1);
4086 bool is_signed
= false;
4091 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4093 case 0x42: /* SMADDL */
4094 case 0x43: /* SMSUBL */
4095 case 0x44: /* SMULH */
4098 case 0x0: /* MADD (32bit) */
4099 case 0x1: /* MSUB (32bit) */
4100 case 0x40: /* MADD (64bit) */
4101 case 0x41: /* MSUB (64bit) */
4102 case 0x4a: /* UMADDL */
4103 case 0x4b: /* UMSUBL */
4104 case 0x4c: /* UMULH */
4107 unallocated_encoding(s
);
4112 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4113 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4114 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4115 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4118 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4120 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4123 tcg_temp_free_i64(low_bits
);
4127 tcg_op1
= tcg_temp_new_i64();
4128 tcg_op2
= tcg_temp_new_i64();
4129 tcg_tmp
= tcg_temp_new_i64();
4132 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4133 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4136 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4137 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4139 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4140 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4144 if (ra
== 31 && !is_sub
) {
4145 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4146 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4148 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4150 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4152 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4157 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4160 tcg_temp_free_i64(tcg_op1
);
4161 tcg_temp_free_i64(tcg_op2
);
4162 tcg_temp_free_i64(tcg_tmp
);
4165 /* Add/subtract (with carry)
4166 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4167 * +--+--+--+------------------------+------+---------+------+-----+
4168 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4169 * +--+--+--+------------------------+------+---------+------+-----+
4173 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4175 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4176 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4178 if (extract32(insn
, 10, 6) != 0) {
4179 unallocated_encoding(s
);
4183 sf
= extract32(insn
, 31, 1);
4184 op
= extract32(insn
, 30, 1);
4185 setflags
= extract32(insn
, 29, 1);
4186 rm
= extract32(insn
, 16, 5);
4187 rn
= extract32(insn
, 5, 5);
4188 rd
= extract32(insn
, 0, 5);
4190 tcg_rd
= cpu_reg(s
, rd
);
4191 tcg_rn
= cpu_reg(s
, rn
);
4194 tcg_y
= new_tmp_a64(s
);
4195 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4197 tcg_y
= cpu_reg(s
, rm
);
4201 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4203 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4207 /* Conditional compare (immediate / register)
4208 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4209 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4210 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4211 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4214 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4216 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4217 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4218 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4221 if (!extract32(insn
, 29, 1)) {
4222 unallocated_encoding(s
);
4225 if (insn
& (1 << 10 | 1 << 4)) {
4226 unallocated_encoding(s
);
4229 sf
= extract32(insn
, 31, 1);
4230 op
= extract32(insn
, 30, 1);
4231 is_imm
= extract32(insn
, 11, 1);
4232 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4233 cond
= extract32(insn
, 12, 4);
4234 rn
= extract32(insn
, 5, 5);
4235 nzcv
= extract32(insn
, 0, 4);
4237 /* Set T0 = !COND. */
4238 tcg_t0
= tcg_temp_new_i32();
4239 arm_test_cc(&c
, cond
);
4240 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4243 /* Load the arguments for the new comparison. */
4245 tcg_y
= new_tmp_a64(s
);
4246 tcg_gen_movi_i64(tcg_y
, y
);
4248 tcg_y
= cpu_reg(s
, y
);
4250 tcg_rn
= cpu_reg(s
, rn
);
4252 /* Set the flags for the new comparison. */
4253 tcg_tmp
= tcg_temp_new_i64();
4255 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4257 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4259 tcg_temp_free_i64(tcg_tmp
);
4261 /* If COND was false, force the flags to #nzcv. Compute two masks
4262 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4263 * For tcg hosts that support ANDC, we can make do with just T1.
4264 * In either case, allow the tcg optimizer to delete any unused mask.
4266 tcg_t1
= tcg_temp_new_i32();
4267 tcg_t2
= tcg_temp_new_i32();
4268 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4269 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4271 if (nzcv
& 8) { /* N */
4272 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4274 if (TCG_TARGET_HAS_andc_i32
) {
4275 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4277 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4280 if (nzcv
& 4) { /* Z */
4281 if (TCG_TARGET_HAS_andc_i32
) {
4282 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4284 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4287 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4289 if (nzcv
& 2) { /* C */
4290 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4292 if (TCG_TARGET_HAS_andc_i32
) {
4293 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4295 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4298 if (nzcv
& 1) { /* V */
4299 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4301 if (TCG_TARGET_HAS_andc_i32
) {
4302 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4304 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4307 tcg_temp_free_i32(tcg_t0
);
4308 tcg_temp_free_i32(tcg_t1
);
4309 tcg_temp_free_i32(tcg_t2
);
4312 /* Conditional select
4313 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4314 * +----+----+---+-----------------+------+------+-----+------+------+
4315 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4316 * +----+----+---+-----------------+------+------+-----+------+------+
4318 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4320 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4321 TCGv_i64 tcg_rd
, zero
;
4324 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4325 /* S == 1 or op2<1> == 1 */
4326 unallocated_encoding(s
);
4329 sf
= extract32(insn
, 31, 1);
4330 else_inv
= extract32(insn
, 30, 1);
4331 rm
= extract32(insn
, 16, 5);
4332 cond
= extract32(insn
, 12, 4);
4333 else_inc
= extract32(insn
, 10, 1);
4334 rn
= extract32(insn
, 5, 5);
4335 rd
= extract32(insn
, 0, 5);
4337 tcg_rd
= cpu_reg(s
, rd
);
4339 a64_test_cc(&c
, cond
);
4340 zero
= tcg_const_i64(0);
4342 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4344 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4346 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4349 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4350 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4351 if (else_inv
&& else_inc
) {
4352 tcg_gen_neg_i64(t_false
, t_false
);
4353 } else if (else_inv
) {
4354 tcg_gen_not_i64(t_false
, t_false
);
4355 } else if (else_inc
) {
4356 tcg_gen_addi_i64(t_false
, t_false
, 1);
4358 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4361 tcg_temp_free_i64(zero
);
4365 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4369 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4370 unsigned int rn
, unsigned int rd
)
4372 TCGv_i64 tcg_rd
, tcg_rn
;
4373 tcg_rd
= cpu_reg(s
, rd
);
4374 tcg_rn
= cpu_reg(s
, rn
);
4377 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4379 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4380 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4381 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4382 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4383 tcg_temp_free_i32(tcg_tmp32
);
4387 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4388 unsigned int rn
, unsigned int rd
)
4390 TCGv_i64 tcg_rd
, tcg_rn
;
4391 tcg_rd
= cpu_reg(s
, rd
);
4392 tcg_rn
= cpu_reg(s
, rn
);
4395 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4397 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4398 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4399 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4400 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4401 tcg_temp_free_i32(tcg_tmp32
);
4405 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4406 unsigned int rn
, unsigned int rd
)
4408 TCGv_i64 tcg_rd
, tcg_rn
;
4409 tcg_rd
= cpu_reg(s
, rd
);
4410 tcg_rn
= cpu_reg(s
, rn
);
4413 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4415 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4416 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4417 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4418 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4419 tcg_temp_free_i32(tcg_tmp32
);
4423 /* REV with sf==1, opcode==3 ("REV64") */
4424 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4425 unsigned int rn
, unsigned int rd
)
4428 unallocated_encoding(s
);
4431 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4434 /* REV with sf==0, opcode==2
4435 * REV32 (sf==1, opcode==2)
4437 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4438 unsigned int rn
, unsigned int rd
)
4440 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4443 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4444 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4446 /* bswap32_i64 requires zero high word */
4447 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4448 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4449 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4450 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4451 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4453 tcg_temp_free_i64(tcg_tmp
);
4455 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4456 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4460 /* REV16 (opcode==1) */
4461 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4462 unsigned int rn
, unsigned int rd
)
4464 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4465 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4466 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4467 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4469 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4470 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4471 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4472 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4473 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4475 tcg_temp_free_i64(mask
);
4476 tcg_temp_free_i64(tcg_tmp
);
4479 /* Data-processing (1 source)
4480 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4481 * +----+---+---+-----------------+---------+--------+------+------+
4482 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4483 * +----+---+---+-----------------+---------+--------+------+------+
4485 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4487 unsigned int sf
, opcode
, rn
, rd
;
4489 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4490 unallocated_encoding(s
);
4494 sf
= extract32(insn
, 31, 1);
4495 opcode
= extract32(insn
, 10, 6);
4496 rn
= extract32(insn
, 5, 5);
4497 rd
= extract32(insn
, 0, 5);
4501 handle_rbit(s
, sf
, rn
, rd
);
4504 handle_rev16(s
, sf
, rn
, rd
);
4507 handle_rev32(s
, sf
, rn
, rd
);
4510 handle_rev64(s
, sf
, rn
, rd
);
4513 handle_clz(s
, sf
, rn
, rd
);
4516 handle_cls(s
, sf
, rn
, rd
);
4521 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4522 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4524 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4525 tcg_rd
= cpu_reg(s
, rd
);
4527 if (!sf
&& is_signed
) {
4528 tcg_n
= new_tmp_a64(s
);
4529 tcg_m
= new_tmp_a64(s
);
4530 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4531 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4533 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4534 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4538 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4540 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4543 if (!sf
) { /* zero extend final result */
4544 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4548 /* LSLV, LSRV, ASRV, RORV */
4549 static void handle_shift_reg(DisasContext
*s
,
4550 enum a64_shift_type shift_type
, unsigned int sf
,
4551 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4553 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4554 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4555 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4557 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4558 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4559 tcg_temp_free_i64(tcg_shift
);
4562 /* CRC32[BHWX], CRC32C[BHWX] */
4563 static void handle_crc32(DisasContext
*s
,
4564 unsigned int sf
, unsigned int sz
, bool crc32c
,
4565 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4567 TCGv_i64 tcg_acc
, tcg_val
;
4570 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4571 || (sf
== 1 && sz
!= 3)
4572 || (sf
== 0 && sz
== 3)) {
4573 unallocated_encoding(s
);
4578 tcg_val
= cpu_reg(s
, rm
);
4592 g_assert_not_reached();
4594 tcg_val
= new_tmp_a64(s
);
4595 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4598 tcg_acc
= cpu_reg(s
, rn
);
4599 tcg_bytes
= tcg_const_i32(1 << sz
);
4602 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4604 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4607 tcg_temp_free_i32(tcg_bytes
);
4610 /* Data-processing (2 source)
4611 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4612 * +----+---+---+-----------------+------+--------+------+------+
4613 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4614 * +----+---+---+-----------------+------+--------+------+------+
4616 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4618 unsigned int sf
, rm
, opcode
, rn
, rd
;
4619 sf
= extract32(insn
, 31, 1);
4620 rm
= extract32(insn
, 16, 5);
4621 opcode
= extract32(insn
, 10, 6);
4622 rn
= extract32(insn
, 5, 5);
4623 rd
= extract32(insn
, 0, 5);
4625 if (extract32(insn
, 29, 1)) {
4626 unallocated_encoding(s
);
4632 handle_div(s
, false, sf
, rm
, rn
, rd
);
4635 handle_div(s
, true, sf
, rm
, rn
, rd
);
4638 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4641 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4644 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4647 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4656 case 23: /* CRC32 */
4658 int sz
= extract32(opcode
, 0, 2);
4659 bool crc32c
= extract32(opcode
, 2, 1);
4660 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4664 unallocated_encoding(s
);
4669 /* Data processing - register */
4670 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4672 switch (extract32(insn
, 24, 5)) {
4673 case 0x0a: /* Logical (shifted register) */
4674 disas_logic_reg(s
, insn
);
4676 case 0x0b: /* Add/subtract */
4677 if (insn
& (1 << 21)) { /* (extended register) */
4678 disas_add_sub_ext_reg(s
, insn
);
4680 disas_add_sub_reg(s
, insn
);
4683 case 0x1b: /* Data-processing (3 source) */
4684 disas_data_proc_3src(s
, insn
);
4687 switch (extract32(insn
, 21, 3)) {
4688 case 0x0: /* Add/subtract (with carry) */
4689 disas_adc_sbc(s
, insn
);
4691 case 0x2: /* Conditional compare */
4692 disas_cc(s
, insn
); /* both imm and reg forms */
4694 case 0x4: /* Conditional select */
4695 disas_cond_select(s
, insn
);
4697 case 0x6: /* Data-processing */
4698 if (insn
& (1 << 30)) { /* (1 source) */
4699 disas_data_proc_1src(s
, insn
);
4700 } else { /* (2 source) */
4701 disas_data_proc_2src(s
, insn
);
4705 unallocated_encoding(s
);
4710 unallocated_encoding(s
);
4715 static void handle_fp_compare(DisasContext
*s
, int size
,
4716 unsigned int rn
, unsigned int rm
,
4717 bool cmp_with_zero
, bool signal_all_nans
)
4719 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4720 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
4722 if (size
== MO_64
) {
4723 TCGv_i64 tcg_vn
, tcg_vm
;
4725 tcg_vn
= read_fp_dreg(s
, rn
);
4726 if (cmp_with_zero
) {
4727 tcg_vm
= tcg_const_i64(0);
4729 tcg_vm
= read_fp_dreg(s
, rm
);
4731 if (signal_all_nans
) {
4732 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4734 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4736 tcg_temp_free_i64(tcg_vn
);
4737 tcg_temp_free_i64(tcg_vm
);
4739 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
4740 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
4742 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
4743 if (cmp_with_zero
) {
4744 tcg_gen_movi_i32(tcg_vm
, 0);
4746 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
4751 if (signal_all_nans
) {
4752 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4754 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4758 if (signal_all_nans
) {
4759 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4761 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4765 g_assert_not_reached();
4768 tcg_temp_free_i32(tcg_vn
);
4769 tcg_temp_free_i32(tcg_vm
);
4772 tcg_temp_free_ptr(fpst
);
4774 gen_set_nzcv(tcg_flags
);
4776 tcg_temp_free_i64(tcg_flags
);
4779 /* Floating point compare
4780 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4781 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4782 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4783 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4785 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4787 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4790 mos
= extract32(insn
, 29, 3);
4791 type
= extract32(insn
, 22, 2);
4792 rm
= extract32(insn
, 16, 5);
4793 op
= extract32(insn
, 14, 2);
4794 rn
= extract32(insn
, 5, 5);
4795 opc
= extract32(insn
, 3, 2);
4796 op2r
= extract32(insn
, 0, 3);
4798 if (mos
|| op
|| op2r
) {
4799 unallocated_encoding(s
);
4812 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
4817 unallocated_encoding(s
);
4821 if (!fp_access_check(s
)) {
4825 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
4828 /* Floating point conditional compare
4829 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4830 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4831 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4832 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4834 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4836 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4838 TCGLabel
*label_continue
= NULL
;
4841 mos
= extract32(insn
, 29, 3);
4842 type
= extract32(insn
, 22, 2);
4843 rm
= extract32(insn
, 16, 5);
4844 cond
= extract32(insn
, 12, 4);
4845 rn
= extract32(insn
, 5, 5);
4846 op
= extract32(insn
, 4, 1);
4847 nzcv
= extract32(insn
, 0, 4);
4850 unallocated_encoding(s
);
4863 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
4868 unallocated_encoding(s
);
4872 if (!fp_access_check(s
)) {
4876 if (cond
< 0x0e) { /* not always */
4877 TCGLabel
*label_match
= gen_new_label();
4878 label_continue
= gen_new_label();
4879 arm_gen_test_cc(cond
, label_match
);
4881 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4882 gen_set_nzcv(tcg_flags
);
4883 tcg_temp_free_i64(tcg_flags
);
4884 tcg_gen_br(label_continue
);
4885 gen_set_label(label_match
);
4888 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
4891 gen_set_label(label_continue
);
4895 /* Floating point conditional select
4896 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4897 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4898 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4899 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4901 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4903 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4904 TCGv_i64 t_true
, t_false
, t_zero
;
4908 mos
= extract32(insn
, 29, 3);
4909 type
= extract32(insn
, 22, 2);
4910 rm
= extract32(insn
, 16, 5);
4911 cond
= extract32(insn
, 12, 4);
4912 rn
= extract32(insn
, 5, 5);
4913 rd
= extract32(insn
, 0, 5);
4916 unallocated_encoding(s
);
4929 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
4934 unallocated_encoding(s
);
4938 if (!fp_access_check(s
)) {
4942 /* Zero extend sreg & hreg inputs to 64 bits now. */
4943 t_true
= tcg_temp_new_i64();
4944 t_false
= tcg_temp_new_i64();
4945 read_vec_element(s
, t_true
, rn
, 0, sz
);
4946 read_vec_element(s
, t_false
, rm
, 0, sz
);
4948 a64_test_cc(&c
, cond
);
4949 t_zero
= tcg_const_i64(0);
4950 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4951 tcg_temp_free_i64(t_zero
);
4952 tcg_temp_free_i64(t_false
);
4955 /* Note that sregs & hregs write back zeros to the high bits,
4956 and we've already done the zero-extension. */
4957 write_fp_dreg(s
, rd
, t_true
);
4958 tcg_temp_free_i64(t_true
);
4961 /* Floating-point data-processing (1 source) - half precision */
4962 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
4964 TCGv_ptr fpst
= NULL
;
4965 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
4966 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4969 case 0x0: /* FMOV */
4970 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4972 case 0x1: /* FABS */
4973 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
4975 case 0x2: /* FNEG */
4976 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
4978 case 0x3: /* FSQRT */
4979 gen_helper_sqrt_f16(tcg_res
, tcg_op
, cpu_env
);
4981 case 0x8: /* FRINTN */
4982 case 0x9: /* FRINTP */
4983 case 0xa: /* FRINTM */
4984 case 0xb: /* FRINTZ */
4985 case 0xc: /* FRINTA */
4987 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4988 fpst
= get_fpstatus_ptr(true);
4990 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4991 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
4993 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4994 tcg_temp_free_i32(tcg_rmode
);
4997 case 0xe: /* FRINTX */
4998 fpst
= get_fpstatus_ptr(true);
4999 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5001 case 0xf: /* FRINTI */
5002 fpst
= get_fpstatus_ptr(true);
5003 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5009 write_fp_sreg(s
, rd
, tcg_res
);
5012 tcg_temp_free_ptr(fpst
);
5014 tcg_temp_free_i32(tcg_op
);
5015 tcg_temp_free_i32(tcg_res
);
5018 /* Floating-point data-processing (1 source) - single precision */
5019 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5025 fpst
= get_fpstatus_ptr(false);
5026 tcg_op
= read_fp_sreg(s
, rn
);
5027 tcg_res
= tcg_temp_new_i32();
5030 case 0x0: /* FMOV */
5031 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5033 case 0x1: /* FABS */
5034 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5036 case 0x2: /* FNEG */
5037 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5039 case 0x3: /* FSQRT */
5040 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5042 case 0x8: /* FRINTN */
5043 case 0x9: /* FRINTP */
5044 case 0xa: /* FRINTM */
5045 case 0xb: /* FRINTZ */
5046 case 0xc: /* FRINTA */
5048 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5050 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5051 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5053 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5054 tcg_temp_free_i32(tcg_rmode
);
5057 case 0xe: /* FRINTX */
5058 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5060 case 0xf: /* FRINTI */
5061 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5067 write_fp_sreg(s
, rd
, tcg_res
);
5069 tcg_temp_free_ptr(fpst
);
5070 tcg_temp_free_i32(tcg_op
);
5071 tcg_temp_free_i32(tcg_res
);
5074 /* Floating-point data-processing (1 source) - double precision */
5075 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5082 case 0x0: /* FMOV */
5083 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5087 fpst
= get_fpstatus_ptr(false);
5088 tcg_op
= read_fp_dreg(s
, rn
);
5089 tcg_res
= tcg_temp_new_i64();
5092 case 0x1: /* FABS */
5093 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5095 case 0x2: /* FNEG */
5096 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5098 case 0x3: /* FSQRT */
5099 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5101 case 0x8: /* FRINTN */
5102 case 0x9: /* FRINTP */
5103 case 0xa: /* FRINTM */
5104 case 0xb: /* FRINTZ */
5105 case 0xc: /* FRINTA */
5107 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5109 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5110 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5112 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5113 tcg_temp_free_i32(tcg_rmode
);
5116 case 0xe: /* FRINTX */
5117 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5119 case 0xf: /* FRINTI */
5120 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5126 write_fp_dreg(s
, rd
, tcg_res
);
5128 tcg_temp_free_ptr(fpst
);
5129 tcg_temp_free_i64(tcg_op
);
5130 tcg_temp_free_i64(tcg_res
);
5133 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5134 int rd
, int rn
, int dtype
, int ntype
)
5139 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5141 /* Single to double */
5142 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5143 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5144 write_fp_dreg(s
, rd
, tcg_rd
);
5145 tcg_temp_free_i64(tcg_rd
);
5147 /* Single to half */
5148 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5149 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
5150 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5151 write_fp_sreg(s
, rd
, tcg_rd
);
5152 tcg_temp_free_i32(tcg_rd
);
5154 tcg_temp_free_i32(tcg_rn
);
5159 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5160 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5162 /* Double to single */
5163 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5165 /* Double to half */
5166 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
5167 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5169 write_fp_sreg(s
, rd
, tcg_rd
);
5170 tcg_temp_free_i32(tcg_rd
);
5171 tcg_temp_free_i64(tcg_rn
);
5176 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5177 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5179 /* Half to single */
5180 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5181 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
5182 write_fp_sreg(s
, rd
, tcg_rd
);
5183 tcg_temp_free_i32(tcg_rd
);
5185 /* Half to double */
5186 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5187 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
5188 write_fp_dreg(s
, rd
, tcg_rd
);
5189 tcg_temp_free_i64(tcg_rd
);
5191 tcg_temp_free_i32(tcg_rn
);
5199 /* Floating point data-processing (1 source)
5200 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5201 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5202 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5203 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5205 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5207 int type
= extract32(insn
, 22, 2);
5208 int opcode
= extract32(insn
, 15, 6);
5209 int rn
= extract32(insn
, 5, 5);
5210 int rd
= extract32(insn
, 0, 5);
5213 case 0x4: case 0x5: case 0x7:
5215 /* FCVT between half, single and double precision */
5216 int dtype
= extract32(opcode
, 0, 2);
5217 if (type
== 2 || dtype
== type
) {
5218 unallocated_encoding(s
);
5221 if (!fp_access_check(s
)) {
5225 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5231 /* 32-to-32 and 64-to-64 ops */
5234 if (!fp_access_check(s
)) {
5238 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5241 if (!fp_access_check(s
)) {
5245 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5248 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5249 unallocated_encoding(s
);
5253 if (!fp_access_check(s
)) {
5257 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5260 unallocated_encoding(s
);
5264 unallocated_encoding(s
);
5269 /* Floating-point data-processing (2 source) - single precision */
5270 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5271 int rd
, int rn
, int rm
)
5278 tcg_res
= tcg_temp_new_i32();
5279 fpst
= get_fpstatus_ptr(false);
5280 tcg_op1
= read_fp_sreg(s
, rn
);
5281 tcg_op2
= read_fp_sreg(s
, rm
);
5284 case 0x0: /* FMUL */
5285 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5287 case 0x1: /* FDIV */
5288 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5290 case 0x2: /* FADD */
5291 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5293 case 0x3: /* FSUB */
5294 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5296 case 0x4: /* FMAX */
5297 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5299 case 0x5: /* FMIN */
5300 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5302 case 0x6: /* FMAXNM */
5303 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5305 case 0x7: /* FMINNM */
5306 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5308 case 0x8: /* FNMUL */
5309 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5310 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5314 write_fp_sreg(s
, rd
, tcg_res
);
5316 tcg_temp_free_ptr(fpst
);
5317 tcg_temp_free_i32(tcg_op1
);
5318 tcg_temp_free_i32(tcg_op2
);
5319 tcg_temp_free_i32(tcg_res
);
5322 /* Floating-point data-processing (2 source) - double precision */
5323 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5324 int rd
, int rn
, int rm
)
5331 tcg_res
= tcg_temp_new_i64();
5332 fpst
= get_fpstatus_ptr(false);
5333 tcg_op1
= read_fp_dreg(s
, rn
);
5334 tcg_op2
= read_fp_dreg(s
, rm
);
5337 case 0x0: /* FMUL */
5338 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5340 case 0x1: /* FDIV */
5341 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5343 case 0x2: /* FADD */
5344 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5346 case 0x3: /* FSUB */
5347 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5349 case 0x4: /* FMAX */
5350 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5352 case 0x5: /* FMIN */
5353 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5355 case 0x6: /* FMAXNM */
5356 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5358 case 0x7: /* FMINNM */
5359 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5361 case 0x8: /* FNMUL */
5362 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5363 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5367 write_fp_dreg(s
, rd
, tcg_res
);
5369 tcg_temp_free_ptr(fpst
);
5370 tcg_temp_free_i64(tcg_op1
);
5371 tcg_temp_free_i64(tcg_op2
);
5372 tcg_temp_free_i64(tcg_res
);
5375 /* Floating-point data-processing (2 source) - half precision */
5376 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5377 int rd
, int rn
, int rm
)
5384 tcg_res
= tcg_temp_new_i32();
5385 fpst
= get_fpstatus_ptr(true);
5386 tcg_op1
= read_fp_hreg(s
, rn
);
5387 tcg_op2
= read_fp_hreg(s
, rm
);
5390 case 0x0: /* FMUL */
5391 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5393 case 0x1: /* FDIV */
5394 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5396 case 0x2: /* FADD */
5397 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5399 case 0x3: /* FSUB */
5400 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5402 case 0x4: /* FMAX */
5403 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5405 case 0x5: /* FMIN */
5406 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5408 case 0x6: /* FMAXNM */
5409 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5411 case 0x7: /* FMINNM */
5412 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5414 case 0x8: /* FNMUL */
5415 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5416 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5419 g_assert_not_reached();
5422 write_fp_sreg(s
, rd
, tcg_res
);
5424 tcg_temp_free_ptr(fpst
);
5425 tcg_temp_free_i32(tcg_op1
);
5426 tcg_temp_free_i32(tcg_op2
);
5427 tcg_temp_free_i32(tcg_res
);
5430 /* Floating point data-processing (2 source)
5431 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5432 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5433 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5434 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5436 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5438 int type
= extract32(insn
, 22, 2);
5439 int rd
= extract32(insn
, 0, 5);
5440 int rn
= extract32(insn
, 5, 5);
5441 int rm
= extract32(insn
, 16, 5);
5442 int opcode
= extract32(insn
, 12, 4);
5445 unallocated_encoding(s
);
5451 if (!fp_access_check(s
)) {
5454 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5457 if (!fp_access_check(s
)) {
5460 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5463 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5464 unallocated_encoding(s
);
5467 if (!fp_access_check(s
)) {
5470 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5473 unallocated_encoding(s
);
5477 /* Floating-point data-processing (3 source) - single precision */
5478 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5479 int rd
, int rn
, int rm
, int ra
)
5481 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5482 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5483 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5485 tcg_op1
= read_fp_sreg(s
, rn
);
5486 tcg_op2
= read_fp_sreg(s
, rm
);
5487 tcg_op3
= read_fp_sreg(s
, ra
);
5489 /* These are fused multiply-add, and must be done as one
5490 * floating point operation with no rounding between the
5491 * multiplication and addition steps.
5492 * NB that doing the negations here as separate steps is
5493 * correct : an input NaN should come out with its sign bit
5494 * flipped if it is a negated-input.
5497 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
5501 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
5504 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5506 write_fp_sreg(s
, rd
, tcg_res
);
5508 tcg_temp_free_ptr(fpst
);
5509 tcg_temp_free_i32(tcg_op1
);
5510 tcg_temp_free_i32(tcg_op2
);
5511 tcg_temp_free_i32(tcg_op3
);
5512 tcg_temp_free_i32(tcg_res
);
5515 /* Floating-point data-processing (3 source) - double precision */
5516 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
5517 int rd
, int rn
, int rm
, int ra
)
5519 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
5520 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5521 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5523 tcg_op1
= read_fp_dreg(s
, rn
);
5524 tcg_op2
= read_fp_dreg(s
, rm
);
5525 tcg_op3
= read_fp_dreg(s
, ra
);
5527 /* These are fused multiply-add, and must be done as one
5528 * floating point operation with no rounding between the
5529 * multiplication and addition steps.
5530 * NB that doing the negations here as separate steps is
5531 * correct : an input NaN should come out with its sign bit
5532 * flipped if it is a negated-input.
5535 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
5539 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
5542 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5544 write_fp_dreg(s
, rd
, tcg_res
);
5546 tcg_temp_free_ptr(fpst
);
5547 tcg_temp_free_i64(tcg_op1
);
5548 tcg_temp_free_i64(tcg_op2
);
5549 tcg_temp_free_i64(tcg_op3
);
5550 tcg_temp_free_i64(tcg_res
);
5553 /* Floating-point data-processing (3 source) - half precision */
5554 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
5555 int rd
, int rn
, int rm
, int ra
)
5557 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5558 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5559 TCGv_ptr fpst
= get_fpstatus_ptr(true);
5561 tcg_op1
= read_fp_hreg(s
, rn
);
5562 tcg_op2
= read_fp_hreg(s
, rm
);
5563 tcg_op3
= read_fp_hreg(s
, ra
);
5565 /* These are fused multiply-add, and must be done as one
5566 * floating point operation with no rounding between the
5567 * multiplication and addition steps.
5568 * NB that doing the negations here as separate steps is
5569 * correct : an input NaN should come out with its sign bit
5570 * flipped if it is a negated-input.
5573 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
5577 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
5580 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5582 write_fp_sreg(s
, rd
, tcg_res
);
5584 tcg_temp_free_ptr(fpst
);
5585 tcg_temp_free_i32(tcg_op1
);
5586 tcg_temp_free_i32(tcg_op2
);
5587 tcg_temp_free_i32(tcg_op3
);
5588 tcg_temp_free_i32(tcg_res
);
5591 /* Floating point data-processing (3 source)
5592 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
5593 * +---+---+---+-----------+------+----+------+----+------+------+------+
5594 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
5595 * +---+---+---+-----------+------+----+------+----+------+------+------+
5597 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
5599 int type
= extract32(insn
, 22, 2);
5600 int rd
= extract32(insn
, 0, 5);
5601 int rn
= extract32(insn
, 5, 5);
5602 int ra
= extract32(insn
, 10, 5);
5603 int rm
= extract32(insn
, 16, 5);
5604 bool o0
= extract32(insn
, 15, 1);
5605 bool o1
= extract32(insn
, 21, 1);
5609 if (!fp_access_check(s
)) {
5612 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5615 if (!fp_access_check(s
)) {
5618 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5621 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5622 unallocated_encoding(s
);
5625 if (!fp_access_check(s
)) {
5628 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5631 unallocated_encoding(s
);
5635 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
5636 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
5637 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
5639 static uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
5645 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5646 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5647 extract32(imm8
, 0, 6);
5651 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5652 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5653 (extract32(imm8
, 0, 6) << 3);
5657 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5658 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
5659 (extract32(imm8
, 0, 6) << 6);
5662 g_assert_not_reached();
5667 /* Floating point immediate
5668 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5669 * +---+---+---+-----------+------+---+------------+-------+------+------+
5670 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5671 * +---+---+---+-----------+------+---+------------+-------+------+------+
5673 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5675 int rd
= extract32(insn
, 0, 5);
5676 int imm8
= extract32(insn
, 13, 8);
5677 int type
= extract32(insn
, 22, 2);
5691 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5696 unallocated_encoding(s
);
5700 if (!fp_access_check(s
)) {
5704 imm
= vfp_expand_imm(sz
, imm8
);
5706 tcg_res
= tcg_const_i64(imm
);
5707 write_fp_dreg(s
, rd
, tcg_res
);
5708 tcg_temp_free_i64(tcg_res
);
5711 /* Handle floating point <=> fixed point conversions. Note that we can
5712 * also deal with fp <=> integer conversions as a special case (scale == 64)
5713 * OPTME: consider handling that special case specially or at least skipping
5714 * the call to scalbn in the helpers for zero shifts.
5716 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5717 bool itof
, int rmode
, int scale
, int sf
, int type
)
5719 bool is_signed
= !(opcode
& 1);
5720 TCGv_ptr tcg_fpstatus
;
5721 TCGv_i32 tcg_shift
, tcg_single
;
5722 TCGv_i64 tcg_double
;
5724 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
5726 tcg_shift
= tcg_const_i32(64 - scale
);
5729 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5731 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5734 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5736 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5739 tcg_int
= tcg_extend
;
5743 case 1: /* float64 */
5744 tcg_double
= tcg_temp_new_i64();
5746 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5747 tcg_shift
, tcg_fpstatus
);
5749 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5750 tcg_shift
, tcg_fpstatus
);
5752 write_fp_dreg(s
, rd
, tcg_double
);
5753 tcg_temp_free_i64(tcg_double
);
5756 case 0: /* float32 */
5757 tcg_single
= tcg_temp_new_i32();
5759 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5760 tcg_shift
, tcg_fpstatus
);
5762 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5763 tcg_shift
, tcg_fpstatus
);
5765 write_fp_sreg(s
, rd
, tcg_single
);
5766 tcg_temp_free_i32(tcg_single
);
5769 case 3: /* float16 */
5770 tcg_single
= tcg_temp_new_i32();
5772 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
5773 tcg_shift
, tcg_fpstatus
);
5775 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
5776 tcg_shift
, tcg_fpstatus
);
5778 write_fp_sreg(s
, rd
, tcg_single
);
5779 tcg_temp_free_i32(tcg_single
);
5783 g_assert_not_reached();
5786 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5789 if (extract32(opcode
, 2, 1)) {
5790 /* There are too many rounding modes to all fit into rmode,
5791 * so FCVTA[US] is a special case.
5793 rmode
= FPROUNDING_TIEAWAY
;
5796 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5798 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5801 case 1: /* float64 */
5802 tcg_double
= read_fp_dreg(s
, rn
);
5805 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5806 tcg_shift
, tcg_fpstatus
);
5808 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5809 tcg_shift
, tcg_fpstatus
);
5813 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5814 tcg_shift
, tcg_fpstatus
);
5816 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5817 tcg_shift
, tcg_fpstatus
);
5821 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5823 tcg_temp_free_i64(tcg_double
);
5826 case 0: /* float32 */
5827 tcg_single
= read_fp_sreg(s
, rn
);
5830 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5831 tcg_shift
, tcg_fpstatus
);
5833 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5834 tcg_shift
, tcg_fpstatus
);
5837 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5839 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5840 tcg_shift
, tcg_fpstatus
);
5842 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5843 tcg_shift
, tcg_fpstatus
);
5845 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5846 tcg_temp_free_i32(tcg_dest
);
5848 tcg_temp_free_i32(tcg_single
);
5851 case 3: /* float16 */
5852 tcg_single
= read_fp_sreg(s
, rn
);
5855 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
5856 tcg_shift
, tcg_fpstatus
);
5858 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
5859 tcg_shift
, tcg_fpstatus
);
5862 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5864 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
5865 tcg_shift
, tcg_fpstatus
);
5867 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
5868 tcg_shift
, tcg_fpstatus
);
5870 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5871 tcg_temp_free_i32(tcg_dest
);
5873 tcg_temp_free_i32(tcg_single
);
5877 g_assert_not_reached();
5880 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5881 tcg_temp_free_i32(tcg_rmode
);
5884 tcg_temp_free_ptr(tcg_fpstatus
);
5885 tcg_temp_free_i32(tcg_shift
);
5888 /* Floating point <-> fixed point conversions
5889 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5890 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5891 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5892 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5894 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5896 int rd
= extract32(insn
, 0, 5);
5897 int rn
= extract32(insn
, 5, 5);
5898 int scale
= extract32(insn
, 10, 6);
5899 int opcode
= extract32(insn
, 16, 3);
5900 int rmode
= extract32(insn
, 19, 2);
5901 int type
= extract32(insn
, 22, 2);
5902 bool sbit
= extract32(insn
, 29, 1);
5903 bool sf
= extract32(insn
, 31, 1);
5906 if (sbit
|| (!sf
&& scale
< 32)) {
5907 unallocated_encoding(s
);
5912 case 0: /* float32 */
5913 case 1: /* float64 */
5915 case 3: /* float16 */
5916 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5921 unallocated_encoding(s
);
5925 switch ((rmode
<< 3) | opcode
) {
5926 case 0x2: /* SCVTF */
5927 case 0x3: /* UCVTF */
5930 case 0x18: /* FCVTZS */
5931 case 0x19: /* FCVTZU */
5935 unallocated_encoding(s
);
5939 if (!fp_access_check(s
)) {
5943 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5946 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5948 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5949 * without conversion.
5953 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5959 tmp
= tcg_temp_new_i64();
5960 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5961 write_fp_dreg(s
, rd
, tmp
);
5962 tcg_temp_free_i64(tmp
);
5966 write_fp_dreg(s
, rd
, tcg_rn
);
5969 /* 64 bit to top half. */
5970 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5971 clear_vec_high(s
, true, rd
);
5975 tmp
= tcg_temp_new_i64();
5976 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
5977 write_fp_dreg(s
, rd
, tmp
);
5978 tcg_temp_free_i64(tmp
);
5981 g_assert_not_reached();
5984 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5989 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5993 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5996 /* 64 bits from top half */
5997 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6001 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6004 g_assert_not_reached();
6009 /* Floating point <-> integer conversions
6010 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6011 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6012 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6013 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6015 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6017 int rd
= extract32(insn
, 0, 5);
6018 int rn
= extract32(insn
, 5, 5);
6019 int opcode
= extract32(insn
, 16, 3);
6020 int rmode
= extract32(insn
, 19, 2);
6021 int type
= extract32(insn
, 22, 2);
6022 bool sbit
= extract32(insn
, 29, 1);
6023 bool sf
= extract32(insn
, 31, 1);
6026 unallocated_encoding(s
);
6032 bool itof
= opcode
& 1;
6035 unallocated_encoding(s
);
6039 switch (sf
<< 3 | type
<< 1 | rmode
) {
6040 case 0x0: /* 32 bit */
6041 case 0xa: /* 64 bit */
6042 case 0xd: /* 64 bit to top half of quad */
6044 case 0x6: /* 16-bit float, 32-bit int */
6045 case 0xe: /* 16-bit float, 64-bit int */
6046 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
6051 /* all other sf/type/rmode combinations are invalid */
6052 unallocated_encoding(s
);
6056 if (!fp_access_check(s
)) {
6059 handle_fmov(s
, rd
, rn
, type
, itof
);
6061 /* actual FP conversions */
6062 bool itof
= extract32(opcode
, 1, 1);
6064 if (rmode
!= 0 && opcode
> 1) {
6065 unallocated_encoding(s
);
6069 case 0: /* float32 */
6070 case 1: /* float64 */
6072 case 3: /* float16 */
6073 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
6078 unallocated_encoding(s
);
6082 if (!fp_access_check(s
)) {
6085 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6089 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6090 * 31 30 29 28 25 24 0
6091 * +---+---+---+---------+-----------------------------+
6092 * | | 0 | | 1 1 1 1 | |
6093 * +---+---+---+---------+-----------------------------+
6095 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6097 if (extract32(insn
, 24, 1)) {
6098 /* Floating point data-processing (3 source) */
6099 disas_fp_3src(s
, insn
);
6100 } else if (extract32(insn
, 21, 1) == 0) {
6101 /* Floating point to fixed point conversions */
6102 disas_fp_fixed_conv(s
, insn
);
6104 switch (extract32(insn
, 10, 2)) {
6106 /* Floating point conditional compare */
6107 disas_fp_ccomp(s
, insn
);
6110 /* Floating point data-processing (2 source) */
6111 disas_fp_2src(s
, insn
);
6114 /* Floating point conditional select */
6115 disas_fp_csel(s
, insn
);
6118 switch (ctz32(extract32(insn
, 12, 4))) {
6119 case 0: /* [15:12] == xxx1 */
6120 /* Floating point immediate */
6121 disas_fp_imm(s
, insn
);
6123 case 1: /* [15:12] == xx10 */
6124 /* Floating point compare */
6125 disas_fp_compare(s
, insn
);
6127 case 2: /* [15:12] == x100 */
6128 /* Floating point data-processing (1 source) */
6129 disas_fp_1src(s
, insn
);
6131 case 3: /* [15:12] == 1000 */
6132 unallocated_encoding(s
);
6134 default: /* [15:12] == 0000 */
6135 /* Floating point <-> integer conversions */
6136 disas_fp_int_conv(s
, insn
);
6144 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6147 /* Extract 64 bits from the middle of two concatenated 64 bit
6148 * vector register slices left:right. The extracted bits start
6149 * at 'pos' bits into the right (least significant) side.
6150 * We return the result in tcg_right, and guarantee not to
6153 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6154 assert(pos
> 0 && pos
< 64);
6156 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6157 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6158 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6160 tcg_temp_free_i64(tcg_tmp
);
6164 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6165 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6166 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6167 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6169 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6171 int is_q
= extract32(insn
, 30, 1);
6172 int op2
= extract32(insn
, 22, 2);
6173 int imm4
= extract32(insn
, 11, 4);
6174 int rm
= extract32(insn
, 16, 5);
6175 int rn
= extract32(insn
, 5, 5);
6176 int rd
= extract32(insn
, 0, 5);
6177 int pos
= imm4
<< 3;
6178 TCGv_i64 tcg_resl
, tcg_resh
;
6180 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6181 unallocated_encoding(s
);
6185 if (!fp_access_check(s
)) {
6189 tcg_resh
= tcg_temp_new_i64();
6190 tcg_resl
= tcg_temp_new_i64();
6192 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6193 * either extracting 128 bits from a 128:128 concatenation, or
6194 * extracting 64 bits from a 64:64 concatenation.
6197 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6199 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6200 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6202 tcg_gen_movi_i64(tcg_resh
, 0);
6209 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6210 EltPosns
*elt
= eltposns
;
6217 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6219 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6222 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6223 tcg_hh
= tcg_temp_new_i64();
6224 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6225 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6226 tcg_temp_free_i64(tcg_hh
);
6230 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6231 tcg_temp_free_i64(tcg_resl
);
6232 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6233 tcg_temp_free_i64(tcg_resh
);
6237 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6238 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6239 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6240 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6242 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6244 int op2
= extract32(insn
, 22, 2);
6245 int is_q
= extract32(insn
, 30, 1);
6246 int rm
= extract32(insn
, 16, 5);
6247 int rn
= extract32(insn
, 5, 5);
6248 int rd
= extract32(insn
, 0, 5);
6249 int is_tblx
= extract32(insn
, 12, 1);
6250 int len
= extract32(insn
, 13, 2);
6251 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6252 TCGv_i32 tcg_regno
, tcg_numregs
;
6255 unallocated_encoding(s
);
6259 if (!fp_access_check(s
)) {
6263 /* This does a table lookup: for every byte element in the input
6264 * we index into a table formed from up to four vector registers,
6265 * and then the output is the result of the lookups. Our helper
6266 * function does the lookup operation for a single 64 bit part of
6269 tcg_resl
= tcg_temp_new_i64();
6270 tcg_resh
= tcg_temp_new_i64();
6273 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6275 tcg_gen_movi_i64(tcg_resl
, 0);
6277 if (is_tblx
&& is_q
) {
6278 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6280 tcg_gen_movi_i64(tcg_resh
, 0);
6283 tcg_idx
= tcg_temp_new_i64();
6284 tcg_regno
= tcg_const_i32(rn
);
6285 tcg_numregs
= tcg_const_i32(len
+ 1);
6286 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6287 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6288 tcg_regno
, tcg_numregs
);
6290 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6291 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6292 tcg_regno
, tcg_numregs
);
6294 tcg_temp_free_i64(tcg_idx
);
6295 tcg_temp_free_i32(tcg_regno
);
6296 tcg_temp_free_i32(tcg_numregs
);
6298 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6299 tcg_temp_free_i64(tcg_resl
);
6300 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6301 tcg_temp_free_i64(tcg_resh
);
6305 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6306 * +---+---+-------------+------+---+------+---+------------------+------+
6307 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6308 * +---+---+-------------+------+---+------+---+------------------+------+
6310 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6312 int rd
= extract32(insn
, 0, 5);
6313 int rn
= extract32(insn
, 5, 5);
6314 int rm
= extract32(insn
, 16, 5);
6315 int size
= extract32(insn
, 22, 2);
6316 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6317 * bit 2 indicates 1 vs 2 variant of the insn.
6319 int opcode
= extract32(insn
, 12, 2);
6320 bool part
= extract32(insn
, 14, 1);
6321 bool is_q
= extract32(insn
, 30, 1);
6322 int esize
= 8 << size
;
6324 int datasize
= is_q
? 128 : 64;
6325 int elements
= datasize
/ esize
;
6326 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6328 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6329 unallocated_encoding(s
);
6333 if (!fp_access_check(s
)) {
6337 tcg_resl
= tcg_const_i64(0);
6338 tcg_resh
= tcg_const_i64(0);
6339 tcg_res
= tcg_temp_new_i64();
6341 for (i
= 0; i
< elements
; i
++) {
6343 case 1: /* UZP1/2 */
6345 int midpoint
= elements
/ 2;
6347 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6349 read_vec_element(s
, tcg_res
, rm
,
6350 2 * (i
- midpoint
) + part
, size
);
6354 case 2: /* TRN1/2 */
6356 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6358 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6361 case 3: /* ZIP1/2 */
6363 int base
= part
* elements
/ 2;
6365 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6367 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6372 g_assert_not_reached();
6377 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6378 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6380 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6381 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6385 tcg_temp_free_i64(tcg_res
);
6387 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6388 tcg_temp_free_i64(tcg_resl
);
6389 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6390 tcg_temp_free_i64(tcg_resh
);
6394 * do_reduction_op helper
6396 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6397 * important for correct NaN propagation that we do these
6398 * operations in exactly the order specified by the pseudocode.
6400 * This is a recursive function, TCG temps should be freed by the
6401 * calling function once it is done with the values.
6403 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6404 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6406 if (esize
== size
) {
6408 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6411 /* We should have one register left here */
6412 assert(ctpop8(vmap
) == 1);
6413 element
= ctz32(vmap
);
6414 assert(element
< 8);
6416 tcg_elem
= tcg_temp_new_i32();
6417 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6420 int bits
= size
/ 2;
6421 int shift
= ctpop8(vmap
) / 2;
6422 int vmap_lo
= (vmap
>> shift
) & vmap
;
6423 int vmap_hi
= (vmap
& ~vmap_lo
);
6424 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6426 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6427 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6428 tcg_res
= tcg_temp_new_i32();
6431 case 0x0c: /* fmaxnmv half-precision */
6432 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6434 case 0x0f: /* fmaxv half-precision */
6435 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6437 case 0x1c: /* fminnmv half-precision */
6438 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6440 case 0x1f: /* fminv half-precision */
6441 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6443 case 0x2c: /* fmaxnmv */
6444 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6446 case 0x2f: /* fmaxv */
6447 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6449 case 0x3c: /* fminnmv */
6450 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6452 case 0x3f: /* fminv */
6453 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6456 g_assert_not_reached();
6459 tcg_temp_free_i32(tcg_hi
);
6460 tcg_temp_free_i32(tcg_lo
);
6465 /* AdvSIMD across lanes
6466 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6467 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6468 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6469 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6471 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6473 int rd
= extract32(insn
, 0, 5);
6474 int rn
= extract32(insn
, 5, 5);
6475 int size
= extract32(insn
, 22, 2);
6476 int opcode
= extract32(insn
, 12, 5);
6477 bool is_q
= extract32(insn
, 30, 1);
6478 bool is_u
= extract32(insn
, 29, 1);
6480 bool is_min
= false;
6484 TCGv_i64 tcg_res
, tcg_elt
;
6487 case 0x1b: /* ADDV */
6489 unallocated_encoding(s
);
6493 case 0x3: /* SADDLV, UADDLV */
6494 case 0xa: /* SMAXV, UMAXV */
6495 case 0x1a: /* SMINV, UMINV */
6496 if (size
== 3 || (size
== 2 && !is_q
)) {
6497 unallocated_encoding(s
);
6501 case 0xc: /* FMAXNMV, FMINNMV */
6502 case 0xf: /* FMAXV, FMINV */
6503 /* Bit 1 of size field encodes min vs max and the actual size
6504 * depends on the encoding of the U bit. If not set (and FP16
6505 * enabled) then we do half-precision float instead of single
6508 is_min
= extract32(size
, 1, 1);
6510 if (!is_u
&& arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
6512 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
6513 unallocated_encoding(s
);
6520 unallocated_encoding(s
);
6524 if (!fp_access_check(s
)) {
6529 elements
= (is_q
? 128 : 64) / esize
;
6531 tcg_res
= tcg_temp_new_i64();
6532 tcg_elt
= tcg_temp_new_i64();
6534 /* These instructions operate across all lanes of a vector
6535 * to produce a single result. We can guarantee that a 64
6536 * bit intermediate is sufficient:
6537 * + for [US]ADDLV the maximum element size is 32 bits, and
6538 * the result type is 64 bits
6539 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
6540 * same as the element size, which is 32 bits at most
6541 * For the integer operations we can choose to work at 64
6542 * or 32 bits and truncate at the end; for simplicity
6543 * we use 64 bits always. The floating point
6544 * ops do require 32 bit intermediates, though.
6547 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
6549 for (i
= 1; i
< elements
; i
++) {
6550 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
6553 case 0x03: /* SADDLV / UADDLV */
6554 case 0x1b: /* ADDV */
6555 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
6557 case 0x0a: /* SMAXV / UMAXV */
6559 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
6561 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
6564 case 0x1a: /* SMINV / UMINV */
6566 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
6568 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
6572 g_assert_not_reached();
6577 /* Floating point vector reduction ops which work across 32
6578 * bit (single) or 16 bit (half-precision) intermediates.
6579 * Note that correct NaN propagation requires that we do these
6580 * operations in exactly the order specified by the pseudocode.
6582 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
6583 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
6584 int vmap
= (1 << elements
) - 1;
6585 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
6586 (is_q
? 128 : 64), vmap
, fpst
);
6587 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
6588 tcg_temp_free_i32(tcg_res32
);
6589 tcg_temp_free_ptr(fpst
);
6592 tcg_temp_free_i64(tcg_elt
);
6594 /* Now truncate the result to the width required for the final output */
6595 if (opcode
== 0x03) {
6596 /* SADDLV, UADDLV: result is 2*esize */
6602 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
6605 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
6608 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6613 g_assert_not_reached();
6616 write_fp_dreg(s
, rd
, tcg_res
);
6617 tcg_temp_free_i64(tcg_res
);
6620 /* DUP (Element, Vector)
6622 * 31 30 29 21 20 16 15 10 9 5 4 0
6623 * +---+---+-------------------+--------+-------------+------+------+
6624 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6625 * +---+---+-------------------+--------+-------------+------+------+
6627 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6629 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
6632 int size
= ctz32(imm5
);
6633 int index
= imm5
>> (size
+ 1);
6635 if (size
> 3 || (size
== 3 && !is_q
)) {
6636 unallocated_encoding(s
);
6640 if (!fp_access_check(s
)) {
6644 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
6645 vec_reg_offset(s
, rn
, index
, size
),
6646 is_q
? 16 : 8, vec_full_reg_size(s
));
6649 /* DUP (element, scalar)
6650 * 31 21 20 16 15 10 9 5 4 0
6651 * +-----------------------+--------+-------------+------+------+
6652 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6653 * +-----------------------+--------+-------------+------+------+
6655 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
6658 int size
= ctz32(imm5
);
6663 unallocated_encoding(s
);
6667 if (!fp_access_check(s
)) {
6671 index
= imm5
>> (size
+ 1);
6673 /* This instruction just extracts the specified element and
6674 * zero-extends it into the bottom of the destination register.
6676 tmp
= tcg_temp_new_i64();
6677 read_vec_element(s
, tmp
, rn
, index
, size
);
6678 write_fp_dreg(s
, rd
, tmp
);
6679 tcg_temp_free_i64(tmp
);
6684 * 31 30 29 21 20 16 15 10 9 5 4 0
6685 * +---+---+-------------------+--------+-------------+------+------+
6686 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
6687 * +---+---+-------------------+--------+-------------+------+------+
6689 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6691 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
6694 int size
= ctz32(imm5
);
6695 uint32_t dofs
, oprsz
, maxsz
;
6697 if (size
> 3 || ((size
== 3) && !is_q
)) {
6698 unallocated_encoding(s
);
6702 if (!fp_access_check(s
)) {
6706 dofs
= vec_full_reg_offset(s
, rd
);
6707 oprsz
= is_q
? 16 : 8;
6708 maxsz
= vec_full_reg_size(s
);
6710 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
6715 * 31 21 20 16 15 14 11 10 9 5 4 0
6716 * +-----------------------+--------+------------+---+------+------+
6717 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6718 * +-----------------------+--------+------------+---+------+------+
6720 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6721 * index: encoded in imm5<4:size+1>
6723 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
6726 int size
= ctz32(imm5
);
6727 int src_index
, dst_index
;
6731 unallocated_encoding(s
);
6735 if (!fp_access_check(s
)) {
6739 dst_index
= extract32(imm5
, 1+size
, 5);
6740 src_index
= extract32(imm4
, size
, 4);
6742 tmp
= tcg_temp_new_i64();
6744 read_vec_element(s
, tmp
, rn
, src_index
, size
);
6745 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
6747 tcg_temp_free_i64(tmp
);
6753 * 31 21 20 16 15 10 9 5 4 0
6754 * +-----------------------+--------+-------------+------+------+
6755 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
6756 * +-----------------------+--------+-------------+------+------+
6758 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6759 * index: encoded in imm5<4:size+1>
6761 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
6763 int size
= ctz32(imm5
);
6767 unallocated_encoding(s
);
6771 if (!fp_access_check(s
)) {
6775 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6776 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6783 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6784 * +---+---+-------------------+--------+-------------+------+------+
6785 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6786 * +---+---+-------------------+--------+-------------+------+------+
6788 * U: unsigned when set
6789 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6791 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6792 int rn
, int rd
, int imm5
)
6794 int size
= ctz32(imm5
);
6798 /* Check for UnallocatedEncodings */
6800 if (size
> 2 || (size
== 2 && !is_q
)) {
6801 unallocated_encoding(s
);
6806 || (size
< 3 && is_q
)
6807 || (size
== 3 && !is_q
)) {
6808 unallocated_encoding(s
);
6813 if (!fp_access_check(s
)) {
6817 element
= extract32(imm5
, 1+size
, 4);
6819 tcg_rd
= cpu_reg(s
, rd
);
6820 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6821 if (is_signed
&& !is_q
) {
6822 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6827 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6828 * +---+---+----+-----------------+------+---+------+---+------+------+
6829 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6830 * +---+---+----+-----------------+------+---+------+---+------+------+
6832 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6834 int rd
= extract32(insn
, 0, 5);
6835 int rn
= extract32(insn
, 5, 5);
6836 int imm4
= extract32(insn
, 11, 4);
6837 int op
= extract32(insn
, 29, 1);
6838 int is_q
= extract32(insn
, 30, 1);
6839 int imm5
= extract32(insn
, 16, 5);
6844 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6846 unallocated_encoding(s
);
6851 /* DUP (element - vector) */
6852 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6856 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6861 handle_simd_insg(s
, rd
, rn
, imm5
);
6863 unallocated_encoding(s
);
6868 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6869 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6872 unallocated_encoding(s
);
6878 /* AdvSIMD modified immediate
6879 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6880 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6881 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6882 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6884 * There are a number of operations that can be carried out here:
6885 * MOVI - move (shifted) imm into register
6886 * MVNI - move inverted (shifted) imm into register
6887 * ORR - bitwise OR of (shifted) imm with register
6888 * BIC - bitwise clear of (shifted) imm with register
6889 * With ARMv8.2 we also have:
6890 * FMOV half-precision
6892 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6894 int rd
= extract32(insn
, 0, 5);
6895 int cmode
= extract32(insn
, 12, 4);
6896 int cmode_3_1
= extract32(cmode
, 1, 3);
6897 int cmode_0
= extract32(cmode
, 0, 1);
6898 int o2
= extract32(insn
, 11, 1);
6899 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6900 bool is_neg
= extract32(insn
, 29, 1);
6901 bool is_q
= extract32(insn
, 30, 1);
6904 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6905 /* Check for FMOV (vector, immediate) - half-precision */
6906 if (!(arm_dc_feature(s
, ARM_FEATURE_V8_FP16
) && o2
&& cmode
== 0xf)) {
6907 unallocated_encoding(s
);
6912 if (!fp_access_check(s
)) {
6916 /* See AdvSIMDExpandImm() in ARM ARM */
6917 switch (cmode_3_1
) {
6918 case 0: /* Replicate(Zeros(24):imm8, 2) */
6919 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6920 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6921 case 3: /* Replicate(imm8:Zeros(24), 2) */
6923 int shift
= cmode_3_1
* 8;
6924 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6927 case 4: /* Replicate(Zeros(8):imm8, 4) */
6928 case 5: /* Replicate(imm8:Zeros(8), 4) */
6930 int shift
= (cmode_3_1
& 0x1) * 8;
6931 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6936 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6937 imm
= (abcdefgh
<< 16) | 0xffff;
6939 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6940 imm
= (abcdefgh
<< 8) | 0xff;
6942 imm
= bitfield_replicate(imm
, 32);
6945 if (!cmode_0
&& !is_neg
) {
6946 imm
= bitfield_replicate(abcdefgh
, 8);
6947 } else if (!cmode_0
&& is_neg
) {
6950 for (i
= 0; i
< 8; i
++) {
6951 if ((abcdefgh
) & (1 << i
)) {
6952 imm
|= 0xffULL
<< (i
* 8);
6955 } else if (cmode_0
) {
6957 imm
= (abcdefgh
& 0x3f) << 48;
6958 if (abcdefgh
& 0x80) {
6959 imm
|= 0x8000000000000000ULL
;
6961 if (abcdefgh
& 0x40) {
6962 imm
|= 0x3fc0000000000000ULL
;
6964 imm
|= 0x4000000000000000ULL
;
6968 /* FMOV (vector, immediate) - half-precision */
6969 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
6970 /* now duplicate across the lanes */
6971 imm
= bitfield_replicate(imm
, 16);
6973 imm
= (abcdefgh
& 0x3f) << 19;
6974 if (abcdefgh
& 0x80) {
6977 if (abcdefgh
& 0x40) {
6988 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
6989 g_assert_not_reached();
6992 if (cmode_3_1
!= 7 && is_neg
) {
6996 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
6997 /* MOVI or MVNI, with MVNI negation handled above. */
6998 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
6999 vec_full_reg_size(s
), imm
);
7001 /* ORR or BIC, with BIC negation to AND handled above. */
7003 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7005 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7010 /* AdvSIMD scalar copy
7011 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7012 * +-----+----+-----------------+------+---+------+---+------+------+
7013 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7014 * +-----+----+-----------------+------+---+------+---+------+------+
7016 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7018 int rd
= extract32(insn
, 0, 5);
7019 int rn
= extract32(insn
, 5, 5);
7020 int imm4
= extract32(insn
, 11, 4);
7021 int imm5
= extract32(insn
, 16, 5);
7022 int op
= extract32(insn
, 29, 1);
7024 if (op
!= 0 || imm4
!= 0) {
7025 unallocated_encoding(s
);
7029 /* DUP (element, scalar) */
7030 handle_simd_dupes(s
, rd
, rn
, imm5
);
7033 /* AdvSIMD scalar pairwise
7034 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7035 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7036 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7037 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7039 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7041 int u
= extract32(insn
, 29, 1);
7042 int size
= extract32(insn
, 22, 2);
7043 int opcode
= extract32(insn
, 12, 5);
7044 int rn
= extract32(insn
, 5, 5);
7045 int rd
= extract32(insn
, 0, 5);
7048 /* For some ops (the FP ones), size[1] is part of the encoding.
7049 * For ADDP strictly it is not but size[1] is always 1 for valid
7052 opcode
|= (extract32(size
, 1, 1) << 5);
7055 case 0x3b: /* ADDP */
7056 if (u
|| size
!= 3) {
7057 unallocated_encoding(s
);
7060 if (!fp_access_check(s
)) {
7066 case 0xc: /* FMAXNMP */
7067 case 0xd: /* FADDP */
7068 case 0xf: /* FMAXP */
7069 case 0x2c: /* FMINNMP */
7070 case 0x2f: /* FMINP */
7071 /* FP op, size[0] is 32 or 64 bit*/
7073 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
7074 unallocated_encoding(s
);
7080 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7083 if (!fp_access_check(s
)) {
7087 fpst
= get_fpstatus_ptr(size
== MO_16
);
7090 unallocated_encoding(s
);
7094 if (size
== MO_64
) {
7095 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7096 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7097 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7099 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7100 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7103 case 0x3b: /* ADDP */
7104 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7106 case 0xc: /* FMAXNMP */
7107 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7109 case 0xd: /* FADDP */
7110 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7112 case 0xf: /* FMAXP */
7113 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7115 case 0x2c: /* FMINNMP */
7116 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7118 case 0x2f: /* FMINP */
7119 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7122 g_assert_not_reached();
7125 write_fp_dreg(s
, rd
, tcg_res
);
7127 tcg_temp_free_i64(tcg_op1
);
7128 tcg_temp_free_i64(tcg_op2
);
7129 tcg_temp_free_i64(tcg_res
);
7131 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7132 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7133 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7135 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7136 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7138 if (size
== MO_16
) {
7140 case 0xc: /* FMAXNMP */
7141 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7143 case 0xd: /* FADDP */
7144 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7146 case 0xf: /* FMAXP */
7147 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7149 case 0x2c: /* FMINNMP */
7150 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7152 case 0x2f: /* FMINP */
7153 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7156 g_assert_not_reached();
7160 case 0xc: /* FMAXNMP */
7161 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7163 case 0xd: /* FADDP */
7164 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7166 case 0xf: /* FMAXP */
7167 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7169 case 0x2c: /* FMINNMP */
7170 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7172 case 0x2f: /* FMINP */
7173 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7176 g_assert_not_reached();
7180 write_fp_sreg(s
, rd
, tcg_res
);
7182 tcg_temp_free_i32(tcg_op1
);
7183 tcg_temp_free_i32(tcg_op2
);
7184 tcg_temp_free_i32(tcg_res
);
7188 tcg_temp_free_ptr(fpst
);
7193 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7195 * This code is handles the common shifting code and is used by both
7196 * the vector and scalar code.
7198 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7199 TCGv_i64 tcg_rnd
, bool accumulate
,
7200 bool is_u
, int size
, int shift
)
7202 bool extended_result
= false;
7203 bool round
= tcg_rnd
!= NULL
;
7205 TCGv_i64 tcg_src_hi
;
7207 if (round
&& size
== 3) {
7208 extended_result
= true;
7209 ext_lshift
= 64 - shift
;
7210 tcg_src_hi
= tcg_temp_new_i64();
7211 } else if (shift
== 64) {
7212 if (!accumulate
&& is_u
) {
7213 /* result is zero */
7214 tcg_gen_movi_i64(tcg_res
, 0);
7219 /* Deal with the rounding step */
7221 if (extended_result
) {
7222 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7224 /* take care of sign extending tcg_res */
7225 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7226 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7227 tcg_src
, tcg_src_hi
,
7230 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7234 tcg_temp_free_i64(tcg_zero
);
7236 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7240 /* Now do the shift right */
7241 if (round
&& extended_result
) {
7242 /* extended case, >64 bit precision required */
7243 if (ext_lshift
== 0) {
7244 /* special case, only high bits matter */
7245 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7247 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7248 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7249 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7254 /* essentially shifting in 64 zeros */
7255 tcg_gen_movi_i64(tcg_src
, 0);
7257 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7261 /* effectively extending the sign-bit */
7262 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7264 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7270 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7272 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7275 if (extended_result
) {
7276 tcg_temp_free_i64(tcg_src_hi
);
7280 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7281 static void handle_scalar_simd_shri(DisasContext
*s
,
7282 bool is_u
, int immh
, int immb
,
7283 int opcode
, int rn
, int rd
)
7286 int immhb
= immh
<< 3 | immb
;
7287 int shift
= 2 * (8 << size
) - immhb
;
7288 bool accumulate
= false;
7290 bool insert
= false;
7295 if (!extract32(immh
, 3, 1)) {
7296 unallocated_encoding(s
);
7300 if (!fp_access_check(s
)) {
7305 case 0x02: /* SSRA / USRA (accumulate) */
7308 case 0x04: /* SRSHR / URSHR (rounding) */
7311 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7312 accumulate
= round
= true;
7314 case 0x08: /* SRI */
7320 uint64_t round_const
= 1ULL << (shift
- 1);
7321 tcg_round
= tcg_const_i64(round_const
);
7326 tcg_rn
= read_fp_dreg(s
, rn
);
7327 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7330 /* shift count same as element size is valid but does nothing;
7331 * special case to avoid potential shift by 64.
7333 int esize
= 8 << size
;
7334 if (shift
!= esize
) {
7335 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7336 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7339 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7340 accumulate
, is_u
, size
, shift
);
7343 write_fp_dreg(s
, rd
, tcg_rd
);
7345 tcg_temp_free_i64(tcg_rn
);
7346 tcg_temp_free_i64(tcg_rd
);
7348 tcg_temp_free_i64(tcg_round
);
7352 /* SHL/SLI - Scalar shift left */
7353 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7354 int immh
, int immb
, int opcode
,
7357 int size
= 32 - clz32(immh
) - 1;
7358 int immhb
= immh
<< 3 | immb
;
7359 int shift
= immhb
- (8 << size
);
7360 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7361 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7363 if (!extract32(immh
, 3, 1)) {
7364 unallocated_encoding(s
);
7368 if (!fp_access_check(s
)) {
7372 tcg_rn
= read_fp_dreg(s
, rn
);
7373 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7376 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7378 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7381 write_fp_dreg(s
, rd
, tcg_rd
);
7383 tcg_temp_free_i64(tcg_rn
);
7384 tcg_temp_free_i64(tcg_rd
);
7387 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7388 * (signed/unsigned) narrowing */
7389 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7390 bool is_u_shift
, bool is_u_narrow
,
7391 int immh
, int immb
, int opcode
,
7394 int immhb
= immh
<< 3 | immb
;
7395 int size
= 32 - clz32(immh
) - 1;
7396 int esize
= 8 << size
;
7397 int shift
= (2 * esize
) - immhb
;
7398 int elements
= is_scalar
? 1 : (64 / esize
);
7399 bool round
= extract32(opcode
, 0, 1);
7400 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7401 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7402 TCGv_i32 tcg_rd_narrowed
;
7405 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7406 { gen_helper_neon_narrow_sat_s8
,
7407 gen_helper_neon_unarrow_sat8
},
7408 { gen_helper_neon_narrow_sat_s16
,
7409 gen_helper_neon_unarrow_sat16
},
7410 { gen_helper_neon_narrow_sat_s32
,
7411 gen_helper_neon_unarrow_sat32
},
7414 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7415 gen_helper_neon_narrow_sat_u8
,
7416 gen_helper_neon_narrow_sat_u16
,
7417 gen_helper_neon_narrow_sat_u32
,
7420 NeonGenNarrowEnvFn
*narrowfn
;
7426 if (extract32(immh
, 3, 1)) {
7427 unallocated_encoding(s
);
7431 if (!fp_access_check(s
)) {
7436 narrowfn
= unsigned_narrow_fns
[size
];
7438 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7441 tcg_rn
= tcg_temp_new_i64();
7442 tcg_rd
= tcg_temp_new_i64();
7443 tcg_rd_narrowed
= tcg_temp_new_i32();
7444 tcg_final
= tcg_const_i64(0);
7447 uint64_t round_const
= 1ULL << (shift
- 1);
7448 tcg_round
= tcg_const_i64(round_const
);
7453 for (i
= 0; i
< elements
; i
++) {
7454 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7455 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7456 false, is_u_shift
, size
+1, shift
);
7457 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7458 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7459 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7463 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7465 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7469 tcg_temp_free_i64(tcg_round
);
7471 tcg_temp_free_i64(tcg_rn
);
7472 tcg_temp_free_i64(tcg_rd
);
7473 tcg_temp_free_i32(tcg_rd_narrowed
);
7474 tcg_temp_free_i64(tcg_final
);
7476 clear_vec_high(s
, is_q
, rd
);
7479 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7480 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
7481 bool src_unsigned
, bool dst_unsigned
,
7482 int immh
, int immb
, int rn
, int rd
)
7484 int immhb
= immh
<< 3 | immb
;
7485 int size
= 32 - clz32(immh
) - 1;
7486 int shift
= immhb
- (8 << size
);
7490 assert(!(scalar
&& is_q
));
7493 if (!is_q
&& extract32(immh
, 3, 1)) {
7494 unallocated_encoding(s
);
7498 /* Since we use the variable-shift helpers we must
7499 * replicate the shift count into each element of
7500 * the tcg_shift value.
7504 shift
|= shift
<< 8;
7507 shift
|= shift
<< 16;
7513 g_assert_not_reached();
7517 if (!fp_access_check(s
)) {
7522 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
7523 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
7524 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
7525 { NULL
, gen_helper_neon_qshl_u64
},
7527 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
7528 int maxpass
= is_q
? 2 : 1;
7530 for (pass
= 0; pass
< maxpass
; pass
++) {
7531 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7533 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7534 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7535 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7537 tcg_temp_free_i64(tcg_op
);
7539 tcg_temp_free_i64(tcg_shift
);
7540 clear_vec_high(s
, is_q
, rd
);
7542 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
7543 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
7545 { gen_helper_neon_qshl_s8
,
7546 gen_helper_neon_qshl_s16
,
7547 gen_helper_neon_qshl_s32
},
7548 { gen_helper_neon_qshlu_s8
,
7549 gen_helper_neon_qshlu_s16
,
7550 gen_helper_neon_qshlu_s32
}
7552 { NULL
, NULL
, NULL
},
7553 { gen_helper_neon_qshl_u8
,
7554 gen_helper_neon_qshl_u16
,
7555 gen_helper_neon_qshl_u32
}
7558 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
7559 TCGMemOp memop
= scalar
? size
: MO_32
;
7560 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
7562 for (pass
= 0; pass
< maxpass
; pass
++) {
7563 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7565 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
7566 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7570 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
7573 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
7578 g_assert_not_reached();
7580 write_fp_sreg(s
, rd
, tcg_op
);
7582 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
7585 tcg_temp_free_i32(tcg_op
);
7587 tcg_temp_free_i32(tcg_shift
);
7590 clear_vec_high(s
, is_q
, rd
);
7595 /* Common vector code for handling integer to FP conversion */
7596 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
7597 int elements
, int is_signed
,
7598 int fracbits
, int size
)
7600 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
7601 TCGv_i32 tcg_shift
= NULL
;
7603 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
7606 if (fracbits
|| size
== MO_64
) {
7607 tcg_shift
= tcg_const_i32(fracbits
);
7610 if (size
== MO_64
) {
7611 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
7612 TCGv_i64 tcg_double
= tcg_temp_new_i64();
7614 for (pass
= 0; pass
< elements
; pass
++) {
7615 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
7618 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
7619 tcg_shift
, tcg_fpst
);
7621 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
7622 tcg_shift
, tcg_fpst
);
7624 if (elements
== 1) {
7625 write_fp_dreg(s
, rd
, tcg_double
);
7627 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
7631 tcg_temp_free_i64(tcg_int64
);
7632 tcg_temp_free_i64(tcg_double
);
7635 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
7636 TCGv_i32 tcg_float
= tcg_temp_new_i32();
7638 for (pass
= 0; pass
< elements
; pass
++) {
7639 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
7645 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
7646 tcg_shift
, tcg_fpst
);
7648 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
7649 tcg_shift
, tcg_fpst
);
7653 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
7655 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
7662 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
7663 tcg_shift
, tcg_fpst
);
7665 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
7666 tcg_shift
, tcg_fpst
);
7670 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7672 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7677 g_assert_not_reached();
7680 if (elements
== 1) {
7681 write_fp_sreg(s
, rd
, tcg_float
);
7683 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
7687 tcg_temp_free_i32(tcg_int32
);
7688 tcg_temp_free_i32(tcg_float
);
7691 tcg_temp_free_ptr(tcg_fpst
);
7693 tcg_temp_free_i32(tcg_shift
);
7696 clear_vec_high(s
, elements
<< size
== 16, rd
);
7699 /* UCVTF/SCVTF - Integer to FP conversion */
7700 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
7701 bool is_q
, bool is_u
,
7702 int immh
, int immb
, int opcode
,
7705 int size
, elements
, fracbits
;
7706 int immhb
= immh
<< 3 | immb
;
7710 if (!is_scalar
&& !is_q
) {
7711 unallocated_encoding(s
);
7714 } else if (immh
& 4) {
7716 } else if (immh
& 2) {
7718 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
7719 unallocated_encoding(s
);
7723 /* immh == 0 would be a failure of the decode logic */
7724 g_assert(immh
== 1);
7725 unallocated_encoding(s
);
7732 elements
= (8 << is_q
) >> size
;
7734 fracbits
= (16 << size
) - immhb
;
7736 if (!fp_access_check(s
)) {
7740 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
7743 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
7744 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
7745 bool is_q
, bool is_u
,
7746 int immh
, int immb
, int rn
, int rd
)
7748 int immhb
= immh
<< 3 | immb
;
7749 int pass
, size
, fracbits
;
7750 TCGv_ptr tcg_fpstatus
;
7751 TCGv_i32 tcg_rmode
, tcg_shift
;
7755 if (!is_scalar
&& !is_q
) {
7756 unallocated_encoding(s
);
7759 } else if (immh
& 0x4) {
7761 } else if (immh
& 0x2) {
7763 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
7764 unallocated_encoding(s
);
7768 /* Should have split out AdvSIMD modified immediate earlier. */
7770 unallocated_encoding(s
);
7774 if (!fp_access_check(s
)) {
7778 assert(!(is_scalar
&& is_q
));
7780 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
7781 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
7782 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7783 fracbits
= (16 << size
) - immhb
;
7784 tcg_shift
= tcg_const_i32(fracbits
);
7786 if (size
== MO_64
) {
7787 int maxpass
= is_scalar
? 1 : 2;
7789 for (pass
= 0; pass
< maxpass
; pass
++) {
7790 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7792 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7794 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7796 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7798 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7799 tcg_temp_free_i64(tcg_op
);
7801 clear_vec_high(s
, is_q
, rd
);
7803 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
7804 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
7809 fn
= gen_helper_vfp_touhh
;
7811 fn
= gen_helper_vfp_toshh
;
7816 fn
= gen_helper_vfp_touls
;
7818 fn
= gen_helper_vfp_tosls
;
7822 g_assert_not_reached();
7825 for (pass
= 0; pass
< maxpass
; pass
++) {
7826 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7828 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
7829 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7831 write_fp_sreg(s
, rd
, tcg_op
);
7833 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
7835 tcg_temp_free_i32(tcg_op
);
7838 clear_vec_high(s
, is_q
, rd
);
7842 tcg_temp_free_ptr(tcg_fpstatus
);
7843 tcg_temp_free_i32(tcg_shift
);
7844 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7845 tcg_temp_free_i32(tcg_rmode
);
7848 /* AdvSIMD scalar shift by immediate
7849 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7850 * +-----+---+-------------+------+------+--------+---+------+------+
7851 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7852 * +-----+---+-------------+------+------+--------+---+------+------+
7854 * This is the scalar version so it works on a fixed sized registers
7856 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
7858 int rd
= extract32(insn
, 0, 5);
7859 int rn
= extract32(insn
, 5, 5);
7860 int opcode
= extract32(insn
, 11, 5);
7861 int immb
= extract32(insn
, 16, 3);
7862 int immh
= extract32(insn
, 19, 4);
7863 bool is_u
= extract32(insn
, 29, 1);
7866 unallocated_encoding(s
);
7871 case 0x08: /* SRI */
7873 unallocated_encoding(s
);
7877 case 0x00: /* SSHR / USHR */
7878 case 0x02: /* SSRA / USRA */
7879 case 0x04: /* SRSHR / URSHR */
7880 case 0x06: /* SRSRA / URSRA */
7881 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7883 case 0x0a: /* SHL / SLI */
7884 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7886 case 0x1c: /* SCVTF, UCVTF */
7887 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7890 case 0x10: /* SQSHRUN, SQSHRUN2 */
7891 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7893 unallocated_encoding(s
);
7896 handle_vec_simd_sqshrn(s
, true, false, false, true,
7897 immh
, immb
, opcode
, rn
, rd
);
7899 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7900 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7901 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7902 immh
, immb
, opcode
, rn
, rd
);
7904 case 0xc: /* SQSHLU */
7906 unallocated_encoding(s
);
7909 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7911 case 0xe: /* SQSHL, UQSHL */
7912 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7914 case 0x1f: /* FCVTZS, FCVTZU */
7915 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7918 unallocated_encoding(s
);
7923 /* AdvSIMD scalar three different
7924 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7925 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7926 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7927 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7929 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7931 bool is_u
= extract32(insn
, 29, 1);
7932 int size
= extract32(insn
, 22, 2);
7933 int opcode
= extract32(insn
, 12, 4);
7934 int rm
= extract32(insn
, 16, 5);
7935 int rn
= extract32(insn
, 5, 5);
7936 int rd
= extract32(insn
, 0, 5);
7939 unallocated_encoding(s
);
7944 case 0x9: /* SQDMLAL, SQDMLAL2 */
7945 case 0xb: /* SQDMLSL, SQDMLSL2 */
7946 case 0xd: /* SQDMULL, SQDMULL2 */
7947 if (size
== 0 || size
== 3) {
7948 unallocated_encoding(s
);
7953 unallocated_encoding(s
);
7957 if (!fp_access_check(s
)) {
7962 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7963 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7964 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7966 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7967 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7969 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7970 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7973 case 0xd: /* SQDMULL, SQDMULL2 */
7975 case 0xb: /* SQDMLSL, SQDMLSL2 */
7976 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7978 case 0x9: /* SQDMLAL, SQDMLAL2 */
7979 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7980 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7984 g_assert_not_reached();
7987 write_fp_dreg(s
, rd
, tcg_res
);
7989 tcg_temp_free_i64(tcg_op1
);
7990 tcg_temp_free_i64(tcg_op2
);
7991 tcg_temp_free_i64(tcg_res
);
7993 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
7994 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
7995 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7997 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7998 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8001 case 0xd: /* SQDMULL, SQDMULL2 */
8003 case 0xb: /* SQDMLSL, SQDMLSL2 */
8004 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8006 case 0x9: /* SQDMLAL, SQDMLAL2 */
8008 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8009 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8010 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8012 tcg_temp_free_i64(tcg_op3
);
8016 g_assert_not_reached();
8019 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8020 write_fp_dreg(s
, rd
, tcg_res
);
8022 tcg_temp_free_i32(tcg_op1
);
8023 tcg_temp_free_i32(tcg_op2
);
8024 tcg_temp_free_i64(tcg_res
);
8028 /* CMTST : test is "if (X & Y != 0)". */
8029 static void gen_cmtst_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
8031 tcg_gen_and_i32(d
, a
, b
);
8032 tcg_gen_setcondi_i32(TCG_COND_NE
, d
, d
, 0);
8033 tcg_gen_neg_i32(d
, d
);
8036 static void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
8038 tcg_gen_and_i64(d
, a
, b
);
8039 tcg_gen_setcondi_i64(TCG_COND_NE
, d
, d
, 0);
8040 tcg_gen_neg_i64(d
, d
);
8043 static void gen_cmtst_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
8045 tcg_gen_and_vec(vece
, d
, a
, b
);
8046 tcg_gen_dupi_vec(vece
, a
, 0);
8047 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, d
, d
, a
);
8050 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8051 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8053 /* Handle 64x64->64 opcodes which are shared between the scalar
8054 * and vector 3-same groups. We cover every opcode where size == 3
8055 * is valid in either the three-reg-same (integer, not pairwise)
8056 * or scalar-three-reg-same groups.
8061 case 0x1: /* SQADD */
8063 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8065 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8068 case 0x5: /* SQSUB */
8070 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8072 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8075 case 0x6: /* CMGT, CMHI */
8076 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8077 * We implement this using setcond (test) and then negating.
8079 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8081 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8082 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8084 case 0x7: /* CMGE, CMHS */
8085 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8087 case 0x11: /* CMTST, CMEQ */
8092 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8094 case 0x8: /* SSHL, USHL */
8096 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8098 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8101 case 0x9: /* SQSHL, UQSHL */
8103 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8105 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8108 case 0xa: /* SRSHL, URSHL */
8110 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8112 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8115 case 0xb: /* SQRSHL, UQRSHL */
8117 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8119 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8122 case 0x10: /* ADD, SUB */
8124 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8126 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8130 g_assert_not_reached();
8134 /* Handle the 3-same-operands float operations; shared by the scalar
8135 * and vector encodings. The caller must filter out any encodings
8136 * not allocated for the encoding it is dealing with.
8138 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8139 int fpopcode
, int rd
, int rn
, int rm
)
8142 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8144 for (pass
= 0; pass
< elements
; pass
++) {
8147 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8148 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8149 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8151 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8152 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8155 case 0x39: /* FMLS */
8156 /* As usual for ARM, separate negation for fused multiply-add */
8157 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8159 case 0x19: /* FMLA */
8160 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8161 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8164 case 0x18: /* FMAXNM */
8165 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8167 case 0x1a: /* FADD */
8168 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8170 case 0x1b: /* FMULX */
8171 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8173 case 0x1c: /* FCMEQ */
8174 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8176 case 0x1e: /* FMAX */
8177 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8179 case 0x1f: /* FRECPS */
8180 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8182 case 0x38: /* FMINNM */
8183 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8185 case 0x3a: /* FSUB */
8186 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8188 case 0x3e: /* FMIN */
8189 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8191 case 0x3f: /* FRSQRTS */
8192 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8194 case 0x5b: /* FMUL */
8195 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8197 case 0x5c: /* FCMGE */
8198 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8200 case 0x5d: /* FACGE */
8201 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8203 case 0x5f: /* FDIV */
8204 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8206 case 0x7a: /* FABD */
8207 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8208 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8210 case 0x7c: /* FCMGT */
8211 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8213 case 0x7d: /* FACGT */
8214 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8217 g_assert_not_reached();
8220 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8222 tcg_temp_free_i64(tcg_res
);
8223 tcg_temp_free_i64(tcg_op1
);
8224 tcg_temp_free_i64(tcg_op2
);
8227 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8228 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8229 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8231 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8232 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8235 case 0x39: /* FMLS */
8236 /* As usual for ARM, separate negation for fused multiply-add */
8237 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8239 case 0x19: /* FMLA */
8240 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8241 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8244 case 0x1a: /* FADD */
8245 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8247 case 0x1b: /* FMULX */
8248 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8250 case 0x1c: /* FCMEQ */
8251 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8253 case 0x1e: /* FMAX */
8254 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8256 case 0x1f: /* FRECPS */
8257 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8259 case 0x18: /* FMAXNM */
8260 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8262 case 0x38: /* FMINNM */
8263 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8265 case 0x3a: /* FSUB */
8266 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8268 case 0x3e: /* FMIN */
8269 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8271 case 0x3f: /* FRSQRTS */
8272 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8274 case 0x5b: /* FMUL */
8275 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8277 case 0x5c: /* FCMGE */
8278 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8280 case 0x5d: /* FACGE */
8281 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8283 case 0x5f: /* FDIV */
8284 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8286 case 0x7a: /* FABD */
8287 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8288 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8290 case 0x7c: /* FCMGT */
8291 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8293 case 0x7d: /* FACGT */
8294 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8297 g_assert_not_reached();
8300 if (elements
== 1) {
8301 /* scalar single so clear high part */
8302 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8304 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8305 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8306 tcg_temp_free_i64(tcg_tmp
);
8308 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8311 tcg_temp_free_i32(tcg_res
);
8312 tcg_temp_free_i32(tcg_op1
);
8313 tcg_temp_free_i32(tcg_op2
);
8317 tcg_temp_free_ptr(fpst
);
8319 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8322 /* AdvSIMD scalar three same
8323 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8324 * +-----+---+-----------+------+---+------+--------+---+------+------+
8325 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8326 * +-----+---+-----------+------+---+------+--------+---+------+------+
8328 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8330 int rd
= extract32(insn
, 0, 5);
8331 int rn
= extract32(insn
, 5, 5);
8332 int opcode
= extract32(insn
, 11, 5);
8333 int rm
= extract32(insn
, 16, 5);
8334 int size
= extract32(insn
, 22, 2);
8335 bool u
= extract32(insn
, 29, 1);
8338 if (opcode
>= 0x18) {
8339 /* Floating point: U, size[1] and opcode indicate operation */
8340 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8342 case 0x1b: /* FMULX */
8343 case 0x1f: /* FRECPS */
8344 case 0x3f: /* FRSQRTS */
8345 case 0x5d: /* FACGE */
8346 case 0x7d: /* FACGT */
8347 case 0x1c: /* FCMEQ */
8348 case 0x5c: /* FCMGE */
8349 case 0x7c: /* FCMGT */
8350 case 0x7a: /* FABD */
8353 unallocated_encoding(s
);
8357 if (!fp_access_check(s
)) {
8361 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8366 case 0x1: /* SQADD, UQADD */
8367 case 0x5: /* SQSUB, UQSUB */
8368 case 0x9: /* SQSHL, UQSHL */
8369 case 0xb: /* SQRSHL, UQRSHL */
8371 case 0x8: /* SSHL, USHL */
8372 case 0xa: /* SRSHL, URSHL */
8373 case 0x6: /* CMGT, CMHI */
8374 case 0x7: /* CMGE, CMHS */
8375 case 0x11: /* CMTST, CMEQ */
8376 case 0x10: /* ADD, SUB (vector) */
8378 unallocated_encoding(s
);
8382 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8383 if (size
!= 1 && size
!= 2) {
8384 unallocated_encoding(s
);
8389 unallocated_encoding(s
);
8393 if (!fp_access_check(s
)) {
8397 tcg_rd
= tcg_temp_new_i64();
8400 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8401 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8403 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8404 tcg_temp_free_i64(tcg_rn
);
8405 tcg_temp_free_i64(tcg_rm
);
8407 /* Do a single operation on the lowest element in the vector.
8408 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8409 * no side effects for all these operations.
8410 * OPTME: special-purpose helpers would avoid doing some
8411 * unnecessary work in the helper for the 8 and 16 bit cases.
8413 NeonGenTwoOpEnvFn
*genenvfn
;
8414 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8415 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8416 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8418 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8419 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8422 case 0x1: /* SQADD, UQADD */
8424 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8425 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8426 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8427 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8429 genenvfn
= fns
[size
][u
];
8432 case 0x5: /* SQSUB, UQSUB */
8434 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8435 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8436 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8437 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8439 genenvfn
= fns
[size
][u
];
8442 case 0x9: /* SQSHL, UQSHL */
8444 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8445 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8446 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8447 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8449 genenvfn
= fns
[size
][u
];
8452 case 0xb: /* SQRSHL, UQRSHL */
8454 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8455 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8456 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8457 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8459 genenvfn
= fns
[size
][u
];
8462 case 0x16: /* SQDMULH, SQRDMULH */
8464 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8465 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8466 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8468 assert(size
== 1 || size
== 2);
8469 genenvfn
= fns
[size
- 1][u
];
8473 g_assert_not_reached();
8476 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8477 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8478 tcg_temp_free_i32(tcg_rd32
);
8479 tcg_temp_free_i32(tcg_rn
);
8480 tcg_temp_free_i32(tcg_rm
);
8483 write_fp_dreg(s
, rd
, tcg_rd
);
8485 tcg_temp_free_i64(tcg_rd
);
8488 /* AdvSIMD scalar three same FP16
8489 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8490 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8491 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8492 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8493 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8494 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8496 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8499 int rd
= extract32(insn
, 0, 5);
8500 int rn
= extract32(insn
, 5, 5);
8501 int opcode
= extract32(insn
, 11, 3);
8502 int rm
= extract32(insn
, 16, 5);
8503 bool u
= extract32(insn
, 29, 1);
8504 bool a
= extract32(insn
, 23, 1);
8505 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
8512 case 0x03: /* FMULX */
8513 case 0x04: /* FCMEQ (reg) */
8514 case 0x07: /* FRECPS */
8515 case 0x0f: /* FRSQRTS */
8516 case 0x14: /* FCMGE (reg) */
8517 case 0x15: /* FACGE */
8518 case 0x1a: /* FABD */
8519 case 0x1c: /* FCMGT (reg) */
8520 case 0x1d: /* FACGT */
8523 unallocated_encoding(s
);
8527 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
8528 unallocated_encoding(s
);
8531 if (!fp_access_check(s
)) {
8535 fpst
= get_fpstatus_ptr(true);
8537 tcg_op1
= read_fp_hreg(s
, rn
);
8538 tcg_op2
= read_fp_hreg(s
, rm
);
8539 tcg_res
= tcg_temp_new_i32();
8542 case 0x03: /* FMULX */
8543 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8545 case 0x04: /* FCMEQ (reg) */
8546 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8548 case 0x07: /* FRECPS */
8549 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8551 case 0x0f: /* FRSQRTS */
8552 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8554 case 0x14: /* FCMGE (reg) */
8555 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8557 case 0x15: /* FACGE */
8558 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8560 case 0x1a: /* FABD */
8561 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8562 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
8564 case 0x1c: /* FCMGT (reg) */
8565 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8567 case 0x1d: /* FACGT */
8568 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8571 g_assert_not_reached();
8574 write_fp_sreg(s
, rd
, tcg_res
);
8577 tcg_temp_free_i32(tcg_res
);
8578 tcg_temp_free_i32(tcg_op1
);
8579 tcg_temp_free_i32(tcg_op2
);
8580 tcg_temp_free_ptr(fpst
);
8583 /* AdvSIMD scalar three same extra
8584 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
8585 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8586 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
8587 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8589 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
8592 int rd
= extract32(insn
, 0, 5);
8593 int rn
= extract32(insn
, 5, 5);
8594 int opcode
= extract32(insn
, 11, 4);
8595 int rm
= extract32(insn
, 16, 5);
8596 int size
= extract32(insn
, 22, 2);
8597 bool u
= extract32(insn
, 29, 1);
8598 TCGv_i32 ele1
, ele2
, ele3
;
8602 switch (u
* 16 + opcode
) {
8603 case 0x10: /* SQRDMLAH (vector) */
8604 case 0x11: /* SQRDMLSH (vector) */
8605 if (size
!= 1 && size
!= 2) {
8606 unallocated_encoding(s
);
8609 feature
= ARM_FEATURE_V8_RDM
;
8612 unallocated_encoding(s
);
8615 if (!arm_dc_feature(s
, feature
)) {
8616 unallocated_encoding(s
);
8619 if (!fp_access_check(s
)) {
8623 /* Do a single operation on the lowest element in the vector.
8624 * We use the standard Neon helpers and rely on 0 OP 0 == 0
8625 * with no side effects for all these operations.
8626 * OPTME: special-purpose helpers would avoid doing some
8627 * unnecessary work in the helper for the 16 bit cases.
8629 ele1
= tcg_temp_new_i32();
8630 ele2
= tcg_temp_new_i32();
8631 ele3
= tcg_temp_new_i32();
8633 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
8634 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
8635 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
8638 case 0x0: /* SQRDMLAH */
8640 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8642 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8645 case 0x1: /* SQRDMLSH */
8647 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8649 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8653 g_assert_not_reached();
8655 tcg_temp_free_i32(ele1
);
8656 tcg_temp_free_i32(ele2
);
8658 res
= tcg_temp_new_i64();
8659 tcg_gen_extu_i32_i64(res
, ele3
);
8660 tcg_temp_free_i32(ele3
);
8662 write_fp_dreg(s
, rd
, res
);
8663 tcg_temp_free_i64(res
);
8666 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
8667 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
8668 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
8670 /* Handle 64->64 opcodes which are shared between the scalar and
8671 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
8672 * is valid in either group and also the double-precision fp ops.
8673 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
8679 case 0x4: /* CLS, CLZ */
8681 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
8683 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
8687 /* This opcode is shared with CNT and RBIT but we have earlier
8688 * enforced that size == 3 if and only if this is the NOT insn.
8690 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
8692 case 0x7: /* SQABS, SQNEG */
8694 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
8696 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
8699 case 0xa: /* CMLT */
8700 /* 64 bit integer comparison against zero, result is
8701 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
8706 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
8707 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8709 case 0x8: /* CMGT, CMGE */
8710 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
8712 case 0x9: /* CMEQ, CMLE */
8713 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
8715 case 0xb: /* ABS, NEG */
8717 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8719 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8720 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8721 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
8723 tcg_temp_free_i64(tcg_zero
);
8726 case 0x2f: /* FABS */
8727 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
8729 case 0x6f: /* FNEG */
8730 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
8732 case 0x7f: /* FSQRT */
8733 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
8735 case 0x1a: /* FCVTNS */
8736 case 0x1b: /* FCVTMS */
8737 case 0x1c: /* FCVTAS */
8738 case 0x3a: /* FCVTPS */
8739 case 0x3b: /* FCVTZS */
8741 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8742 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8743 tcg_temp_free_i32(tcg_shift
);
8746 case 0x5a: /* FCVTNU */
8747 case 0x5b: /* FCVTMU */
8748 case 0x5c: /* FCVTAU */
8749 case 0x7a: /* FCVTPU */
8750 case 0x7b: /* FCVTZU */
8752 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8753 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8754 tcg_temp_free_i32(tcg_shift
);
8757 case 0x18: /* FRINTN */
8758 case 0x19: /* FRINTM */
8759 case 0x38: /* FRINTP */
8760 case 0x39: /* FRINTZ */
8761 case 0x58: /* FRINTA */
8762 case 0x79: /* FRINTI */
8763 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8765 case 0x59: /* FRINTX */
8766 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8769 g_assert_not_reached();
8773 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
8774 bool is_scalar
, bool is_u
, bool is_q
,
8775 int size
, int rn
, int rd
)
8777 bool is_double
= (size
== MO_64
);
8780 if (!fp_access_check(s
)) {
8784 fpst
= get_fpstatus_ptr(size
== MO_16
);
8787 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8788 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8789 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8790 NeonGenTwoDoubleOPFn
*genfn
;
8795 case 0x2e: /* FCMLT (zero) */
8798 case 0x2c: /* FCMGT (zero) */
8799 genfn
= gen_helper_neon_cgt_f64
;
8801 case 0x2d: /* FCMEQ (zero) */
8802 genfn
= gen_helper_neon_ceq_f64
;
8804 case 0x6d: /* FCMLE (zero) */
8807 case 0x6c: /* FCMGE (zero) */
8808 genfn
= gen_helper_neon_cge_f64
;
8811 g_assert_not_reached();
8814 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8815 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8817 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8819 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8821 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8823 tcg_temp_free_i64(tcg_res
);
8824 tcg_temp_free_i64(tcg_zero
);
8825 tcg_temp_free_i64(tcg_op
);
8827 clear_vec_high(s
, !is_scalar
, rd
);
8829 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8830 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8831 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8832 NeonGenTwoSingleOPFn
*genfn
;
8834 int pass
, maxpasses
;
8836 if (size
== MO_16
) {
8838 case 0x2e: /* FCMLT (zero) */
8841 case 0x2c: /* FCMGT (zero) */
8842 genfn
= gen_helper_advsimd_cgt_f16
;
8844 case 0x2d: /* FCMEQ (zero) */
8845 genfn
= gen_helper_advsimd_ceq_f16
;
8847 case 0x6d: /* FCMLE (zero) */
8850 case 0x6c: /* FCMGE (zero) */
8851 genfn
= gen_helper_advsimd_cge_f16
;
8854 g_assert_not_reached();
8858 case 0x2e: /* FCMLT (zero) */
8861 case 0x2c: /* FCMGT (zero) */
8862 genfn
= gen_helper_neon_cgt_f32
;
8864 case 0x2d: /* FCMEQ (zero) */
8865 genfn
= gen_helper_neon_ceq_f32
;
8867 case 0x6d: /* FCMLE (zero) */
8870 case 0x6c: /* FCMGE (zero) */
8871 genfn
= gen_helper_neon_cge_f32
;
8874 g_assert_not_reached();
8881 int vector_size
= 8 << is_q
;
8882 maxpasses
= vector_size
>> size
;
8885 for (pass
= 0; pass
< maxpasses
; pass
++) {
8886 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8888 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8890 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8893 write_fp_sreg(s
, rd
, tcg_res
);
8895 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
8898 tcg_temp_free_i32(tcg_res
);
8899 tcg_temp_free_i32(tcg_zero
);
8900 tcg_temp_free_i32(tcg_op
);
8902 clear_vec_high(s
, is_q
, rd
);
8906 tcg_temp_free_ptr(fpst
);
8909 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
8910 bool is_scalar
, bool is_u
, bool is_q
,
8911 int size
, int rn
, int rd
)
8913 bool is_double
= (size
== 3);
8914 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8917 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8918 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8921 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8922 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8924 case 0x3d: /* FRECPE */
8925 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
8927 case 0x3f: /* FRECPX */
8928 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
8930 case 0x7d: /* FRSQRTE */
8931 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
8934 g_assert_not_reached();
8936 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8938 tcg_temp_free_i64(tcg_res
);
8939 tcg_temp_free_i64(tcg_op
);
8940 clear_vec_high(s
, !is_scalar
, rd
);
8942 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8943 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8944 int pass
, maxpasses
;
8949 maxpasses
= is_q
? 4 : 2;
8952 for (pass
= 0; pass
< maxpasses
; pass
++) {
8953 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
8956 case 0x3c: /* URECPE */
8957 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
8959 case 0x3d: /* FRECPE */
8960 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
8962 case 0x3f: /* FRECPX */
8963 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
8965 case 0x7d: /* FRSQRTE */
8966 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
8969 g_assert_not_reached();
8973 write_fp_sreg(s
, rd
, tcg_res
);
8975 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8978 tcg_temp_free_i32(tcg_res
);
8979 tcg_temp_free_i32(tcg_op
);
8981 clear_vec_high(s
, is_q
, rd
);
8984 tcg_temp_free_ptr(fpst
);
8987 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
8988 int opcode
, bool u
, bool is_q
,
8989 int size
, int rn
, int rd
)
8991 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
8992 * in the source becomes a size element in the destination).
8995 TCGv_i32 tcg_res
[2];
8996 int destelt
= is_q
? 2 : 0;
8997 int passes
= scalar
? 1 : 2;
9000 tcg_res
[1] = tcg_const_i32(0);
9003 for (pass
= 0; pass
< passes
; pass
++) {
9004 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9005 NeonGenNarrowFn
*genfn
= NULL
;
9006 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9009 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9011 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9013 tcg_res
[pass
] = tcg_temp_new_i32();
9016 case 0x12: /* XTN, SQXTUN */
9018 static NeonGenNarrowFn
* const xtnfns
[3] = {
9019 gen_helper_neon_narrow_u8
,
9020 gen_helper_neon_narrow_u16
,
9021 tcg_gen_extrl_i64_i32
,
9023 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9024 gen_helper_neon_unarrow_sat8
,
9025 gen_helper_neon_unarrow_sat16
,
9026 gen_helper_neon_unarrow_sat32
,
9029 genenvfn
= sqxtunfns
[size
];
9031 genfn
= xtnfns
[size
];
9035 case 0x14: /* SQXTN, UQXTN */
9037 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9038 { gen_helper_neon_narrow_sat_s8
,
9039 gen_helper_neon_narrow_sat_u8
},
9040 { gen_helper_neon_narrow_sat_s16
,
9041 gen_helper_neon_narrow_sat_u16
},
9042 { gen_helper_neon_narrow_sat_s32
,
9043 gen_helper_neon_narrow_sat_u32
},
9045 genenvfn
= fns
[size
][u
];
9048 case 0x16: /* FCVTN, FCVTN2 */
9049 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9051 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9053 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9054 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9055 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9056 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
9057 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
9058 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9059 tcg_temp_free_i32(tcg_lo
);
9060 tcg_temp_free_i32(tcg_hi
);
9063 case 0x56: /* FCVTXN, FCVTXN2 */
9064 /* 64 bit to 32 bit float conversion
9065 * with von Neumann rounding (round to odd)
9068 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9071 g_assert_not_reached();
9075 genfn(tcg_res
[pass
], tcg_op
);
9076 } else if (genenvfn
) {
9077 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9080 tcg_temp_free_i64(tcg_op
);
9083 for (pass
= 0; pass
< 2; pass
++) {
9084 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9085 tcg_temp_free_i32(tcg_res
[pass
]);
9087 clear_vec_high(s
, is_q
, rd
);
9090 /* Remaining saturating accumulating ops */
9091 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9092 bool is_q
, int size
, int rn
, int rd
)
9094 bool is_double
= (size
== 3);
9097 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9098 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9101 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9102 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9103 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9105 if (is_u
) { /* USQADD */
9106 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9107 } else { /* SUQADD */
9108 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9110 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9112 tcg_temp_free_i64(tcg_rd
);
9113 tcg_temp_free_i64(tcg_rn
);
9114 clear_vec_high(s
, !is_scalar
, rd
);
9116 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9117 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9118 int pass
, maxpasses
;
9123 maxpasses
= is_q
? 4 : 2;
9126 for (pass
= 0; pass
< maxpasses
; pass
++) {
9128 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9129 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9131 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9132 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9135 if (is_u
) { /* USQADD */
9138 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9141 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9144 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9147 g_assert_not_reached();
9149 } else { /* SUQADD */
9152 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9155 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9158 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9161 g_assert_not_reached();
9166 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9167 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9168 tcg_temp_free_i64(tcg_zero
);
9170 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9172 tcg_temp_free_i32(tcg_rd
);
9173 tcg_temp_free_i32(tcg_rn
);
9174 clear_vec_high(s
, is_q
, rd
);
9178 /* AdvSIMD scalar two reg misc
9179 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9180 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9181 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9182 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9184 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9186 int rd
= extract32(insn
, 0, 5);
9187 int rn
= extract32(insn
, 5, 5);
9188 int opcode
= extract32(insn
, 12, 5);
9189 int size
= extract32(insn
, 22, 2);
9190 bool u
= extract32(insn
, 29, 1);
9191 bool is_fcvt
= false;
9194 TCGv_ptr tcg_fpstatus
;
9197 case 0x3: /* USQADD / SUQADD*/
9198 if (!fp_access_check(s
)) {
9201 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9203 case 0x7: /* SQABS / SQNEG */
9205 case 0xa: /* CMLT */
9207 unallocated_encoding(s
);
9211 case 0x8: /* CMGT, CMGE */
9212 case 0x9: /* CMEQ, CMLE */
9213 case 0xb: /* ABS, NEG */
9215 unallocated_encoding(s
);
9219 case 0x12: /* SQXTUN */
9221 unallocated_encoding(s
);
9225 case 0x14: /* SQXTN, UQXTN */
9227 unallocated_encoding(s
);
9230 if (!fp_access_check(s
)) {
9233 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9238 /* Floating point: U, size[1] and opcode indicate operation;
9239 * size[0] indicates single or double precision.
9241 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9242 size
= extract32(size
, 0, 1) ? 3 : 2;
9244 case 0x2c: /* FCMGT (zero) */
9245 case 0x2d: /* FCMEQ (zero) */
9246 case 0x2e: /* FCMLT (zero) */
9247 case 0x6c: /* FCMGE (zero) */
9248 case 0x6d: /* FCMLE (zero) */
9249 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9251 case 0x1d: /* SCVTF */
9252 case 0x5d: /* UCVTF */
9254 bool is_signed
= (opcode
== 0x1d);
9255 if (!fp_access_check(s
)) {
9258 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9261 case 0x3d: /* FRECPE */
9262 case 0x3f: /* FRECPX */
9263 case 0x7d: /* FRSQRTE */
9264 if (!fp_access_check(s
)) {
9267 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9269 case 0x1a: /* FCVTNS */
9270 case 0x1b: /* FCVTMS */
9271 case 0x3a: /* FCVTPS */
9272 case 0x3b: /* FCVTZS */
9273 case 0x5a: /* FCVTNU */
9274 case 0x5b: /* FCVTMU */
9275 case 0x7a: /* FCVTPU */
9276 case 0x7b: /* FCVTZU */
9278 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9280 case 0x1c: /* FCVTAS */
9281 case 0x5c: /* FCVTAU */
9282 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9284 rmode
= FPROUNDING_TIEAWAY
;
9286 case 0x56: /* FCVTXN, FCVTXN2 */
9288 unallocated_encoding(s
);
9291 if (!fp_access_check(s
)) {
9294 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9297 unallocated_encoding(s
);
9302 unallocated_encoding(s
);
9306 if (!fp_access_check(s
)) {
9311 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9312 tcg_fpstatus
= get_fpstatus_ptr(false);
9313 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9316 tcg_fpstatus
= NULL
;
9320 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9321 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9323 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9324 write_fp_dreg(s
, rd
, tcg_rd
);
9325 tcg_temp_free_i64(tcg_rd
);
9326 tcg_temp_free_i64(tcg_rn
);
9328 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9329 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9331 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9334 case 0x7: /* SQABS, SQNEG */
9336 NeonGenOneOpEnvFn
*genfn
;
9337 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9338 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9339 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9340 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9342 genfn
= fns
[size
][u
];
9343 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9346 case 0x1a: /* FCVTNS */
9347 case 0x1b: /* FCVTMS */
9348 case 0x1c: /* FCVTAS */
9349 case 0x3a: /* FCVTPS */
9350 case 0x3b: /* FCVTZS */
9352 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9353 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9354 tcg_temp_free_i32(tcg_shift
);
9357 case 0x5a: /* FCVTNU */
9358 case 0x5b: /* FCVTMU */
9359 case 0x5c: /* FCVTAU */
9360 case 0x7a: /* FCVTPU */
9361 case 0x7b: /* FCVTZU */
9363 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9364 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9365 tcg_temp_free_i32(tcg_shift
);
9369 g_assert_not_reached();
9372 write_fp_sreg(s
, rd
, tcg_rd
);
9373 tcg_temp_free_i32(tcg_rd
);
9374 tcg_temp_free_i32(tcg_rn
);
9378 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9379 tcg_temp_free_i32(tcg_rmode
);
9380 tcg_temp_free_ptr(tcg_fpstatus
);
9384 static void gen_ssra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9386 tcg_gen_vec_sar8i_i64(a
, a
, shift
);
9387 tcg_gen_vec_add8_i64(d
, d
, a
);
9390 static void gen_ssra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9392 tcg_gen_vec_sar16i_i64(a
, a
, shift
);
9393 tcg_gen_vec_add16_i64(d
, d
, a
);
9396 static void gen_ssra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9398 tcg_gen_sari_i32(a
, a
, shift
);
9399 tcg_gen_add_i32(d
, d
, a
);
9402 static void gen_ssra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9404 tcg_gen_sari_i64(a
, a
, shift
);
9405 tcg_gen_add_i64(d
, d
, a
);
9408 static void gen_ssra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9410 tcg_gen_sari_vec(vece
, a
, a
, sh
);
9411 tcg_gen_add_vec(vece
, d
, d
, a
);
9414 static void gen_usra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9416 tcg_gen_vec_shr8i_i64(a
, a
, shift
);
9417 tcg_gen_vec_add8_i64(d
, d
, a
);
9420 static void gen_usra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9422 tcg_gen_vec_shr16i_i64(a
, a
, shift
);
9423 tcg_gen_vec_add16_i64(d
, d
, a
);
9426 static void gen_usra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9428 tcg_gen_shri_i32(a
, a
, shift
);
9429 tcg_gen_add_i32(d
, d
, a
);
9432 static void gen_usra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9434 tcg_gen_shri_i64(a
, a
, shift
);
9435 tcg_gen_add_i64(d
, d
, a
);
9438 static void gen_usra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9440 tcg_gen_shri_vec(vece
, a
, a
, sh
);
9441 tcg_gen_add_vec(vece
, d
, d
, a
);
9444 static void gen_shr8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9446 uint64_t mask
= dup_const(MO_8
, 0xff >> shift
);
9447 TCGv_i64 t
= tcg_temp_new_i64();
9449 tcg_gen_shri_i64(t
, a
, shift
);
9450 tcg_gen_andi_i64(t
, t
, mask
);
9451 tcg_gen_andi_i64(d
, d
, ~mask
);
9452 tcg_gen_or_i64(d
, d
, t
);
9453 tcg_temp_free_i64(t
);
9456 static void gen_shr16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9458 uint64_t mask
= dup_const(MO_16
, 0xffff >> shift
);
9459 TCGv_i64 t
= tcg_temp_new_i64();
9461 tcg_gen_shri_i64(t
, a
, shift
);
9462 tcg_gen_andi_i64(t
, t
, mask
);
9463 tcg_gen_andi_i64(d
, d
, ~mask
);
9464 tcg_gen_or_i64(d
, d
, t
);
9465 tcg_temp_free_i64(t
);
9468 static void gen_shr32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9470 tcg_gen_shri_i32(a
, a
, shift
);
9471 tcg_gen_deposit_i32(d
, d
, a
, 0, 32 - shift
);
9474 static void gen_shr64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9476 tcg_gen_shri_i64(a
, a
, shift
);
9477 tcg_gen_deposit_i64(d
, d
, a
, 0, 64 - shift
);
9480 static void gen_shr_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9482 uint64_t mask
= (2ull << ((8 << vece
) - 1)) - 1;
9483 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
9484 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
9486 tcg_gen_dupi_vec(vece
, m
, mask
^ (mask
>> sh
));
9487 tcg_gen_shri_vec(vece
, t
, a
, sh
);
9488 tcg_gen_and_vec(vece
, d
, d
, m
);
9489 tcg_gen_or_vec(vece
, d
, d
, t
);
9491 tcg_temp_free_vec(t
);
9492 tcg_temp_free_vec(m
);
9495 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9496 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9497 int immh
, int immb
, int opcode
, int rn
, int rd
)
9499 static const GVecGen2i ssra_op
[4] = {
9500 { .fni8
= gen_ssra8_i64
,
9501 .fniv
= gen_ssra_vec
,
9503 .opc
= INDEX_op_sari_vec
,
9505 { .fni8
= gen_ssra16_i64
,
9506 .fniv
= gen_ssra_vec
,
9508 .opc
= INDEX_op_sari_vec
,
9510 { .fni4
= gen_ssra32_i32
,
9511 .fniv
= gen_ssra_vec
,
9513 .opc
= INDEX_op_sari_vec
,
9515 { .fni8
= gen_ssra64_i64
,
9516 .fniv
= gen_ssra_vec
,
9517 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9519 .opc
= INDEX_op_sari_vec
,
9522 static const GVecGen2i usra_op
[4] = {
9523 { .fni8
= gen_usra8_i64
,
9524 .fniv
= gen_usra_vec
,
9526 .opc
= INDEX_op_shri_vec
,
9528 { .fni8
= gen_usra16_i64
,
9529 .fniv
= gen_usra_vec
,
9531 .opc
= INDEX_op_shri_vec
,
9533 { .fni4
= gen_usra32_i32
,
9534 .fniv
= gen_usra_vec
,
9536 .opc
= INDEX_op_shri_vec
,
9538 { .fni8
= gen_usra64_i64
,
9539 .fniv
= gen_usra_vec
,
9540 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9542 .opc
= INDEX_op_shri_vec
,
9545 static const GVecGen2i sri_op
[4] = {
9546 { .fni8
= gen_shr8_ins_i64
,
9547 .fniv
= gen_shr_ins_vec
,
9549 .opc
= INDEX_op_shri_vec
,
9551 { .fni8
= gen_shr16_ins_i64
,
9552 .fniv
= gen_shr_ins_vec
,
9554 .opc
= INDEX_op_shri_vec
,
9556 { .fni4
= gen_shr32_ins_i32
,
9557 .fniv
= gen_shr_ins_vec
,
9559 .opc
= INDEX_op_shri_vec
,
9561 { .fni8
= gen_shr64_ins_i64
,
9562 .fniv
= gen_shr_ins_vec
,
9563 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9565 .opc
= INDEX_op_shri_vec
,
9569 int size
= 32 - clz32(immh
) - 1;
9570 int immhb
= immh
<< 3 | immb
;
9571 int shift
= 2 * (8 << size
) - immhb
;
9572 bool accumulate
= false;
9573 int dsize
= is_q
? 128 : 64;
9574 int esize
= 8 << size
;
9575 int elements
= dsize
/esize
;
9576 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9577 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9578 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9580 uint64_t round_const
;
9583 if (extract32(immh
, 3, 1) && !is_q
) {
9584 unallocated_encoding(s
);
9587 tcg_debug_assert(size
<= 3);
9589 if (!fp_access_check(s
)) {
9594 case 0x02: /* SSRA / USRA (accumulate) */
9596 /* Shift count same as element size produces zero to add. */
9597 if (shift
== 8 << size
) {
9600 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9602 /* Shift count same as element size produces all sign to add. */
9603 if (shift
== 8 << size
) {
9606 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9609 case 0x08: /* SRI */
9610 /* Shift count same as element size is valid but does nothing. */
9611 if (shift
== 8 << size
) {
9614 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9617 case 0x00: /* SSHR / USHR */
9619 if (shift
== 8 << size
) {
9620 /* Shift count the same size as element size produces zero. */
9621 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9622 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9624 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9627 /* Shift count the same size as element size produces all sign. */
9628 if (shift
== 8 << size
) {
9631 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9635 case 0x04: /* SRSHR / URSHR (rounding) */
9637 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9641 g_assert_not_reached();
9644 round_const
= 1ULL << (shift
- 1);
9645 tcg_round
= tcg_const_i64(round_const
);
9647 for (i
= 0; i
< elements
; i
++) {
9648 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9650 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9653 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9654 accumulate
, is_u
, size
, shift
);
9656 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9658 tcg_temp_free_i64(tcg_round
);
9661 clear_vec_high(s
, is_q
, rd
);
9664 static void gen_shl8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9666 uint64_t mask
= dup_const(MO_8
, 0xff << shift
);
9667 TCGv_i64 t
= tcg_temp_new_i64();
9669 tcg_gen_shli_i64(t
, a
, shift
);
9670 tcg_gen_andi_i64(t
, t
, mask
);
9671 tcg_gen_andi_i64(d
, d
, ~mask
);
9672 tcg_gen_or_i64(d
, d
, t
);
9673 tcg_temp_free_i64(t
);
9676 static void gen_shl16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9678 uint64_t mask
= dup_const(MO_16
, 0xffff << shift
);
9679 TCGv_i64 t
= tcg_temp_new_i64();
9681 tcg_gen_shli_i64(t
, a
, shift
);
9682 tcg_gen_andi_i64(t
, t
, mask
);
9683 tcg_gen_andi_i64(d
, d
, ~mask
);
9684 tcg_gen_or_i64(d
, d
, t
);
9685 tcg_temp_free_i64(t
);
9688 static void gen_shl32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9690 tcg_gen_deposit_i32(d
, d
, a
, shift
, 32 - shift
);
9693 static void gen_shl64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9695 tcg_gen_deposit_i64(d
, d
, a
, shift
, 64 - shift
);
9698 static void gen_shl_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9700 uint64_t mask
= (1ull << sh
) - 1;
9701 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
9702 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
9704 tcg_gen_dupi_vec(vece
, m
, mask
);
9705 tcg_gen_shli_vec(vece
, t
, a
, sh
);
9706 tcg_gen_and_vec(vece
, d
, d
, m
);
9707 tcg_gen_or_vec(vece
, d
, d
, t
);
9709 tcg_temp_free_vec(t
);
9710 tcg_temp_free_vec(m
);
9713 /* SHL/SLI - Vector shift left */
9714 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9715 int immh
, int immb
, int opcode
, int rn
, int rd
)
9717 static const GVecGen2i shi_op
[4] = {
9718 { .fni8
= gen_shl8_ins_i64
,
9719 .fniv
= gen_shl_ins_vec
,
9720 .opc
= INDEX_op_shli_vec
,
9721 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9724 { .fni8
= gen_shl16_ins_i64
,
9725 .fniv
= gen_shl_ins_vec
,
9726 .opc
= INDEX_op_shli_vec
,
9727 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9730 { .fni4
= gen_shl32_ins_i32
,
9731 .fniv
= gen_shl_ins_vec
,
9732 .opc
= INDEX_op_shli_vec
,
9733 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9736 { .fni8
= gen_shl64_ins_i64
,
9737 .fniv
= gen_shl_ins_vec
,
9738 .opc
= INDEX_op_shli_vec
,
9739 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9743 int size
= 32 - clz32(immh
) - 1;
9744 int immhb
= immh
<< 3 | immb
;
9745 int shift
= immhb
- (8 << size
);
9747 if (extract32(immh
, 3, 1) && !is_q
) {
9748 unallocated_encoding(s
);
9752 if (size
> 3 && !is_q
) {
9753 unallocated_encoding(s
);
9757 if (!fp_access_check(s
)) {
9762 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &shi_op
[size
]);
9764 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
9768 /* USHLL/SHLL - Vector shift left with widening */
9769 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
9770 int immh
, int immb
, int opcode
, int rn
, int rd
)
9772 int size
= 32 - clz32(immh
) - 1;
9773 int immhb
= immh
<< 3 | immb
;
9774 int shift
= immhb
- (8 << size
);
9776 int esize
= 8 << size
;
9777 int elements
= dsize
/esize
;
9778 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9779 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9783 unallocated_encoding(s
);
9787 if (!fp_access_check(s
)) {
9791 /* For the LL variants the store is larger than the load,
9792 * so if rd == rn we would overwrite parts of our input.
9793 * So load everything right now and use shifts in the main loop.
9795 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
9797 for (i
= 0; i
< elements
; i
++) {
9798 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
9799 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
9800 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
9801 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
9805 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
9806 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
9807 int immh
, int immb
, int opcode
, int rn
, int rd
)
9809 int immhb
= immh
<< 3 | immb
;
9810 int size
= 32 - clz32(immh
) - 1;
9812 int esize
= 8 << size
;
9813 int elements
= dsize
/esize
;
9814 int shift
= (2 * esize
) - immhb
;
9815 bool round
= extract32(opcode
, 0, 1);
9816 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
9820 if (extract32(immh
, 3, 1)) {
9821 unallocated_encoding(s
);
9825 if (!fp_access_check(s
)) {
9829 tcg_rn
= tcg_temp_new_i64();
9830 tcg_rd
= tcg_temp_new_i64();
9831 tcg_final
= tcg_temp_new_i64();
9832 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
9835 uint64_t round_const
= 1ULL << (shift
- 1);
9836 tcg_round
= tcg_const_i64(round_const
);
9841 for (i
= 0; i
< elements
; i
++) {
9842 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
9843 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9844 false, true, size
+1, shift
);
9846 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
9850 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
9852 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
9855 tcg_temp_free_i64(tcg_round
);
9857 tcg_temp_free_i64(tcg_rn
);
9858 tcg_temp_free_i64(tcg_rd
);
9859 tcg_temp_free_i64(tcg_final
);
9861 clear_vec_high(s
, is_q
, rd
);
9865 /* AdvSIMD shift by immediate
9866 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9867 * +---+---+---+-------------+------+------+--------+---+------+------+
9868 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9869 * +---+---+---+-------------+------+------+--------+---+------+------+
9871 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
9873 int rd
= extract32(insn
, 0, 5);
9874 int rn
= extract32(insn
, 5, 5);
9875 int opcode
= extract32(insn
, 11, 5);
9876 int immb
= extract32(insn
, 16, 3);
9877 int immh
= extract32(insn
, 19, 4);
9878 bool is_u
= extract32(insn
, 29, 1);
9879 bool is_q
= extract32(insn
, 30, 1);
9882 case 0x08: /* SRI */
9884 unallocated_encoding(s
);
9888 case 0x00: /* SSHR / USHR */
9889 case 0x02: /* SSRA / USRA (accumulate) */
9890 case 0x04: /* SRSHR / URSHR (rounding) */
9891 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9892 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9894 case 0x0a: /* SHL / SLI */
9895 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9897 case 0x10: /* SHRN */
9898 case 0x11: /* RSHRN / SQRSHRUN */
9900 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
9903 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
9906 case 0x12: /* SQSHRN / UQSHRN */
9907 case 0x13: /* SQRSHRN / UQRSHRN */
9908 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
9911 case 0x14: /* SSHLL / USHLL */
9912 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9914 case 0x1c: /* SCVTF / UCVTF */
9915 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
9918 case 0xc: /* SQSHLU */
9920 unallocated_encoding(s
);
9923 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
9925 case 0xe: /* SQSHL, UQSHL */
9926 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
9928 case 0x1f: /* FCVTZS/ FCVTZU */
9929 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
9932 unallocated_encoding(s
);
9937 /* Generate code to do a "long" addition or subtraction, ie one done in
9938 * TCGv_i64 on vector lanes twice the width specified by size.
9940 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
9941 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
9943 static NeonGenTwo64OpFn
* const fns
[3][2] = {
9944 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
9945 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
9946 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
9948 NeonGenTwo64OpFn
*genfn
;
9951 genfn
= fns
[size
][is_sub
];
9952 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9955 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
9956 int opcode
, int rd
, int rn
, int rm
)
9958 /* 3-reg-different widening insns: 64 x 64 -> 128 */
9959 TCGv_i64 tcg_res
[2];
9962 tcg_res
[0] = tcg_temp_new_i64();
9963 tcg_res
[1] = tcg_temp_new_i64();
9965 /* Does this op do an adding accumulate, a subtracting accumulate,
9966 * or no accumulate at all?
9984 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9985 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9988 /* size == 2 means two 32x32->64 operations; this is worth special
9989 * casing because we can generally handle it inline.
9992 for (pass
= 0; pass
< 2; pass
++) {
9993 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9994 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9995 TCGv_i64 tcg_passres
;
9996 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
9998 int elt
= pass
+ is_q
* 2;
10000 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10001 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10004 tcg_passres
= tcg_res
[pass
];
10006 tcg_passres
= tcg_temp_new_i64();
10010 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10011 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10013 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10014 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10016 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10017 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10019 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10020 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10022 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10023 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10024 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10026 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10027 tcg_temp_free_i64(tcg_tmp1
);
10028 tcg_temp_free_i64(tcg_tmp2
);
10031 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10032 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10033 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10034 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10036 case 9: /* SQDMLAL, SQDMLAL2 */
10037 case 11: /* SQDMLSL, SQDMLSL2 */
10038 case 13: /* SQDMULL, SQDMULL2 */
10039 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10040 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10041 tcg_passres
, tcg_passres
);
10044 g_assert_not_reached();
10047 if (opcode
== 9 || opcode
== 11) {
10048 /* saturating accumulate ops */
10050 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10052 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10053 tcg_res
[pass
], tcg_passres
);
10054 } else if (accop
> 0) {
10055 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10056 } else if (accop
< 0) {
10057 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10061 tcg_temp_free_i64(tcg_passres
);
10064 tcg_temp_free_i64(tcg_op1
);
10065 tcg_temp_free_i64(tcg_op2
);
10068 /* size 0 or 1, generally helper functions */
10069 for (pass
= 0; pass
< 2; pass
++) {
10070 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10071 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10072 TCGv_i64 tcg_passres
;
10073 int elt
= pass
+ is_q
* 2;
10075 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10076 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10079 tcg_passres
= tcg_res
[pass
];
10081 tcg_passres
= tcg_temp_new_i64();
10085 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10086 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10088 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10089 static NeonGenWidenFn
* const widenfns
[2][2] = {
10090 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10091 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10093 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10095 widenfn(tcg_op2_64
, tcg_op2
);
10096 widenfn(tcg_passres
, tcg_op1
);
10097 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10098 tcg_passres
, tcg_op2_64
);
10099 tcg_temp_free_i64(tcg_op2_64
);
10102 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10103 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10106 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10108 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10112 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10114 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10118 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10119 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10120 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10123 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10125 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10129 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10131 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10135 case 9: /* SQDMLAL, SQDMLAL2 */
10136 case 11: /* SQDMLSL, SQDMLSL2 */
10137 case 13: /* SQDMULL, SQDMULL2 */
10139 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10140 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10141 tcg_passres
, tcg_passres
);
10143 case 14: /* PMULL */
10145 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10148 g_assert_not_reached();
10150 tcg_temp_free_i32(tcg_op1
);
10151 tcg_temp_free_i32(tcg_op2
);
10154 if (opcode
== 9 || opcode
== 11) {
10155 /* saturating accumulate ops */
10157 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10159 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10163 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10164 tcg_res
[pass
], tcg_passres
);
10166 tcg_temp_free_i64(tcg_passres
);
10171 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10172 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10173 tcg_temp_free_i64(tcg_res
[0]);
10174 tcg_temp_free_i64(tcg_res
[1]);
10177 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10178 int opcode
, int rd
, int rn
, int rm
)
10180 TCGv_i64 tcg_res
[2];
10181 int part
= is_q
? 2 : 0;
10184 for (pass
= 0; pass
< 2; pass
++) {
10185 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10186 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10187 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10188 static NeonGenWidenFn
* const widenfns
[3][2] = {
10189 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10190 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10191 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10193 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10195 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10196 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10197 widenfn(tcg_op2_wide
, tcg_op2
);
10198 tcg_temp_free_i32(tcg_op2
);
10199 tcg_res
[pass
] = tcg_temp_new_i64();
10200 gen_neon_addl(size
, (opcode
== 3),
10201 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10202 tcg_temp_free_i64(tcg_op1
);
10203 tcg_temp_free_i64(tcg_op2_wide
);
10206 for (pass
= 0; pass
< 2; pass
++) {
10207 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10208 tcg_temp_free_i64(tcg_res
[pass
]);
10212 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10214 tcg_gen_addi_i64(in
, in
, 1U << 31);
10215 tcg_gen_extrh_i64_i32(res
, in
);
10218 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10219 int opcode
, int rd
, int rn
, int rm
)
10221 TCGv_i32 tcg_res
[2];
10222 int part
= is_q
? 2 : 0;
10225 for (pass
= 0; pass
< 2; pass
++) {
10226 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10227 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10228 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10229 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10230 { gen_helper_neon_narrow_high_u8
,
10231 gen_helper_neon_narrow_round_high_u8
},
10232 { gen_helper_neon_narrow_high_u16
,
10233 gen_helper_neon_narrow_round_high_u16
},
10234 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10236 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10238 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10239 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10241 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10243 tcg_temp_free_i64(tcg_op1
);
10244 tcg_temp_free_i64(tcg_op2
);
10246 tcg_res
[pass
] = tcg_temp_new_i32();
10247 gennarrow(tcg_res
[pass
], tcg_wideres
);
10248 tcg_temp_free_i64(tcg_wideres
);
10251 for (pass
= 0; pass
< 2; pass
++) {
10252 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10253 tcg_temp_free_i32(tcg_res
[pass
]);
10255 clear_vec_high(s
, is_q
, rd
);
10258 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10260 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10261 * is the only three-reg-diff instruction which produces a
10262 * 128-bit wide result from a single operation. However since
10263 * it's possible to calculate the two halves more or less
10264 * separately we just use two helper calls.
10266 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10267 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10268 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10270 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10271 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10272 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10273 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10274 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10275 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10277 tcg_temp_free_i64(tcg_op1
);
10278 tcg_temp_free_i64(tcg_op2
);
10279 tcg_temp_free_i64(tcg_res
);
10282 /* AdvSIMD three different
10283 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10284 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10285 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10286 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10288 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10290 /* Instructions in this group fall into three basic classes
10291 * (in each case with the operation working on each element in
10292 * the input vectors):
10293 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10295 * (2) wide 64 x 128 -> 128
10296 * (3) narrowing 128 x 128 -> 64
10297 * Here we do initial decode, catch unallocated cases and
10298 * dispatch to separate functions for each class.
10300 int is_q
= extract32(insn
, 30, 1);
10301 int is_u
= extract32(insn
, 29, 1);
10302 int size
= extract32(insn
, 22, 2);
10303 int opcode
= extract32(insn
, 12, 4);
10304 int rm
= extract32(insn
, 16, 5);
10305 int rn
= extract32(insn
, 5, 5);
10306 int rd
= extract32(insn
, 0, 5);
10309 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10310 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10311 /* 64 x 128 -> 128 */
10313 unallocated_encoding(s
);
10316 if (!fp_access_check(s
)) {
10319 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10321 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10322 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10323 /* 128 x 128 -> 64 */
10325 unallocated_encoding(s
);
10328 if (!fp_access_check(s
)) {
10331 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10333 case 14: /* PMULL, PMULL2 */
10334 if (is_u
|| size
== 1 || size
== 2) {
10335 unallocated_encoding(s
);
10339 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
10340 unallocated_encoding(s
);
10343 if (!fp_access_check(s
)) {
10346 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10350 case 9: /* SQDMLAL, SQDMLAL2 */
10351 case 11: /* SQDMLSL, SQDMLSL2 */
10352 case 13: /* SQDMULL, SQDMULL2 */
10353 if (is_u
|| size
== 0) {
10354 unallocated_encoding(s
);
10358 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10359 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10360 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10361 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10362 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10363 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10364 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10365 /* 64 x 64 -> 128 */
10367 unallocated_encoding(s
);
10371 if (!fp_access_check(s
)) {
10375 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10378 /* opcode 15 not allocated */
10379 unallocated_encoding(s
);
10384 static void gen_bsl_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10386 tcg_gen_xor_i64(rn
, rn
, rm
);
10387 tcg_gen_and_i64(rn
, rn
, rd
);
10388 tcg_gen_xor_i64(rd
, rm
, rn
);
10391 static void gen_bit_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10393 tcg_gen_xor_i64(rn
, rn
, rd
);
10394 tcg_gen_and_i64(rn
, rn
, rm
);
10395 tcg_gen_xor_i64(rd
, rd
, rn
);
10398 static void gen_bif_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10400 tcg_gen_xor_i64(rn
, rn
, rd
);
10401 tcg_gen_andc_i64(rn
, rn
, rm
);
10402 tcg_gen_xor_i64(rd
, rd
, rn
);
10405 static void gen_bsl_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10407 tcg_gen_xor_vec(vece
, rn
, rn
, rm
);
10408 tcg_gen_and_vec(vece
, rn
, rn
, rd
);
10409 tcg_gen_xor_vec(vece
, rd
, rm
, rn
);
10412 static void gen_bit_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10414 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
10415 tcg_gen_and_vec(vece
, rn
, rn
, rm
);
10416 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
10419 static void gen_bif_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10421 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
10422 tcg_gen_andc_vec(vece
, rn
, rn
, rm
);
10423 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
10426 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10427 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10429 static const GVecGen3 bsl_op
= {
10430 .fni8
= gen_bsl_i64
,
10431 .fniv
= gen_bsl_vec
,
10432 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10435 static const GVecGen3 bit_op
= {
10436 .fni8
= gen_bit_i64
,
10437 .fniv
= gen_bit_vec
,
10438 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10441 static const GVecGen3 bif_op
= {
10442 .fni8
= gen_bif_i64
,
10443 .fniv
= gen_bif_vec
,
10444 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10448 int rd
= extract32(insn
, 0, 5);
10449 int rn
= extract32(insn
, 5, 5);
10450 int rm
= extract32(insn
, 16, 5);
10451 int size
= extract32(insn
, 22, 2);
10452 bool is_u
= extract32(insn
, 29, 1);
10453 bool is_q
= extract32(insn
, 30, 1);
10455 if (!fp_access_check(s
)) {
10459 switch (size
+ 4 * is_u
) {
10461 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10464 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10467 if (rn
== rm
) { /* MOV */
10468 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_mov
, 0);
10470 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10474 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10477 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10480 case 5: /* BSL bitwise select */
10481 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10483 case 6: /* BIT, bitwise insert if true */
10484 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10486 case 7: /* BIF, bitwise insert if false */
10487 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10491 g_assert_not_reached();
10495 /* Pairwise op subgroup of C3.6.16.
10497 * This is called directly or via the handle_3same_float for float pairwise
10498 * operations where the opcode and size are calculated differently.
10500 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10501 int size
, int rn
, int rm
, int rd
)
10506 /* Floating point operations need fpst */
10507 if (opcode
>= 0x58) {
10508 fpst
= get_fpstatus_ptr(false);
10513 if (!fp_access_check(s
)) {
10517 /* These operations work on the concatenated rm:rn, with each pair of
10518 * adjacent elements being operated on to produce an element in the result.
10521 TCGv_i64 tcg_res
[2];
10523 for (pass
= 0; pass
< 2; pass
++) {
10524 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10525 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10526 int passreg
= (pass
== 0) ? rn
: rm
;
10528 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10529 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10530 tcg_res
[pass
] = tcg_temp_new_i64();
10533 case 0x17: /* ADDP */
10534 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10536 case 0x58: /* FMAXNMP */
10537 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10539 case 0x5a: /* FADDP */
10540 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10542 case 0x5e: /* FMAXP */
10543 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10545 case 0x78: /* FMINNMP */
10546 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10548 case 0x7e: /* FMINP */
10549 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10552 g_assert_not_reached();
10555 tcg_temp_free_i64(tcg_op1
);
10556 tcg_temp_free_i64(tcg_op2
);
10559 for (pass
= 0; pass
< 2; pass
++) {
10560 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10561 tcg_temp_free_i64(tcg_res
[pass
]);
10564 int maxpass
= is_q
? 4 : 2;
10565 TCGv_i32 tcg_res
[4];
10567 for (pass
= 0; pass
< maxpass
; pass
++) {
10568 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10569 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10570 NeonGenTwoOpFn
*genfn
= NULL
;
10571 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10572 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10574 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10575 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10576 tcg_res
[pass
] = tcg_temp_new_i32();
10579 case 0x17: /* ADDP */
10581 static NeonGenTwoOpFn
* const fns
[3] = {
10582 gen_helper_neon_padd_u8
,
10583 gen_helper_neon_padd_u16
,
10589 case 0x14: /* SMAXP, UMAXP */
10591 static NeonGenTwoOpFn
* const fns
[3][2] = {
10592 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10593 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10594 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10596 genfn
= fns
[size
][u
];
10599 case 0x15: /* SMINP, UMINP */
10601 static NeonGenTwoOpFn
* const fns
[3][2] = {
10602 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10603 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10604 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10606 genfn
= fns
[size
][u
];
10609 /* The FP operations are all on single floats (32 bit) */
10610 case 0x58: /* FMAXNMP */
10611 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10613 case 0x5a: /* FADDP */
10614 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10616 case 0x5e: /* FMAXP */
10617 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10619 case 0x78: /* FMINNMP */
10620 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10622 case 0x7e: /* FMINP */
10623 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10626 g_assert_not_reached();
10629 /* FP ops called directly, otherwise call now */
10631 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10634 tcg_temp_free_i32(tcg_op1
);
10635 tcg_temp_free_i32(tcg_op2
);
10638 for (pass
= 0; pass
< maxpass
; pass
++) {
10639 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10640 tcg_temp_free_i32(tcg_res
[pass
]);
10642 clear_vec_high(s
, is_q
, rd
);
10646 tcg_temp_free_ptr(fpst
);
10650 /* Floating point op subgroup of C3.6.16. */
10651 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10653 /* For floating point ops, the U, size[1] and opcode bits
10654 * together indicate the operation. size[0] indicates single
10657 int fpopcode
= extract32(insn
, 11, 5)
10658 | (extract32(insn
, 23, 1) << 5)
10659 | (extract32(insn
, 29, 1) << 6);
10660 int is_q
= extract32(insn
, 30, 1);
10661 int size
= extract32(insn
, 22, 1);
10662 int rm
= extract32(insn
, 16, 5);
10663 int rn
= extract32(insn
, 5, 5);
10664 int rd
= extract32(insn
, 0, 5);
10666 int datasize
= is_q
? 128 : 64;
10667 int esize
= 32 << size
;
10668 int elements
= datasize
/ esize
;
10670 if (size
== 1 && !is_q
) {
10671 unallocated_encoding(s
);
10675 switch (fpopcode
) {
10676 case 0x58: /* FMAXNMP */
10677 case 0x5a: /* FADDP */
10678 case 0x5e: /* FMAXP */
10679 case 0x78: /* FMINNMP */
10680 case 0x7e: /* FMINP */
10681 if (size
&& !is_q
) {
10682 unallocated_encoding(s
);
10685 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10688 case 0x1b: /* FMULX */
10689 case 0x1f: /* FRECPS */
10690 case 0x3f: /* FRSQRTS */
10691 case 0x5d: /* FACGE */
10692 case 0x7d: /* FACGT */
10693 case 0x19: /* FMLA */
10694 case 0x39: /* FMLS */
10695 case 0x18: /* FMAXNM */
10696 case 0x1a: /* FADD */
10697 case 0x1c: /* FCMEQ */
10698 case 0x1e: /* FMAX */
10699 case 0x38: /* FMINNM */
10700 case 0x3a: /* FSUB */
10701 case 0x3e: /* FMIN */
10702 case 0x5b: /* FMUL */
10703 case 0x5c: /* FCMGE */
10704 case 0x5f: /* FDIV */
10705 case 0x7a: /* FABD */
10706 case 0x7c: /* FCMGT */
10707 if (!fp_access_check(s
)) {
10711 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10714 unallocated_encoding(s
);
10719 static void gen_mla8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10721 gen_helper_neon_mul_u8(a
, a
, b
);
10722 gen_helper_neon_add_u8(d
, d
, a
);
10725 static void gen_mla16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10727 gen_helper_neon_mul_u16(a
, a
, b
);
10728 gen_helper_neon_add_u16(d
, d
, a
);
10731 static void gen_mla32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10733 tcg_gen_mul_i32(a
, a
, b
);
10734 tcg_gen_add_i32(d
, d
, a
);
10737 static void gen_mla64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
10739 tcg_gen_mul_i64(a
, a
, b
);
10740 tcg_gen_add_i64(d
, d
, a
);
10743 static void gen_mla_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
10745 tcg_gen_mul_vec(vece
, a
, a
, b
);
10746 tcg_gen_add_vec(vece
, d
, d
, a
);
10749 static void gen_mls8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10751 gen_helper_neon_mul_u8(a
, a
, b
);
10752 gen_helper_neon_sub_u8(d
, d
, a
);
10755 static void gen_mls16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10757 gen_helper_neon_mul_u16(a
, a
, b
);
10758 gen_helper_neon_sub_u16(d
, d
, a
);
10761 static void gen_mls32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10763 tcg_gen_mul_i32(a
, a
, b
);
10764 tcg_gen_sub_i32(d
, d
, a
);
10767 static void gen_mls64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
10769 tcg_gen_mul_i64(a
, a
, b
);
10770 tcg_gen_sub_i64(d
, d
, a
);
10773 static void gen_mls_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
10775 tcg_gen_mul_vec(vece
, a
, a
, b
);
10776 tcg_gen_sub_vec(vece
, d
, d
, a
);
10779 /* Integer op subgroup of C3.6.16. */
10780 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10782 static const GVecGen3 cmtst_op
[4] = {
10783 { .fni4
= gen_helper_neon_tst_u8
,
10784 .fniv
= gen_cmtst_vec
,
10786 { .fni4
= gen_helper_neon_tst_u16
,
10787 .fniv
= gen_cmtst_vec
,
10789 { .fni4
= gen_cmtst_i32
,
10790 .fniv
= gen_cmtst_vec
,
10792 { .fni8
= gen_cmtst_i64
,
10793 .fniv
= gen_cmtst_vec
,
10794 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10797 static const GVecGen3 mla_op
[4] = {
10798 { .fni4
= gen_mla8_i32
,
10799 .fniv
= gen_mla_vec
,
10800 .opc
= INDEX_op_mul_vec
,
10803 { .fni4
= gen_mla16_i32
,
10804 .fniv
= gen_mla_vec
,
10805 .opc
= INDEX_op_mul_vec
,
10808 { .fni4
= gen_mla32_i32
,
10809 .fniv
= gen_mla_vec
,
10810 .opc
= INDEX_op_mul_vec
,
10813 { .fni8
= gen_mla64_i64
,
10814 .fniv
= gen_mla_vec
,
10815 .opc
= INDEX_op_mul_vec
,
10816 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10820 static const GVecGen3 mls_op
[4] = {
10821 { .fni4
= gen_mls8_i32
,
10822 .fniv
= gen_mls_vec
,
10823 .opc
= INDEX_op_mul_vec
,
10826 { .fni4
= gen_mls16_i32
,
10827 .fniv
= gen_mls_vec
,
10828 .opc
= INDEX_op_mul_vec
,
10831 { .fni4
= gen_mls32_i32
,
10832 .fniv
= gen_mls_vec
,
10833 .opc
= INDEX_op_mul_vec
,
10836 { .fni8
= gen_mls64_i64
,
10837 .fniv
= gen_mls_vec
,
10838 .opc
= INDEX_op_mul_vec
,
10839 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10844 int is_q
= extract32(insn
, 30, 1);
10845 int u
= extract32(insn
, 29, 1);
10846 int size
= extract32(insn
, 22, 2);
10847 int opcode
= extract32(insn
, 11, 5);
10848 int rm
= extract32(insn
, 16, 5);
10849 int rn
= extract32(insn
, 5, 5);
10850 int rd
= extract32(insn
, 0, 5);
10855 case 0x13: /* MUL, PMUL */
10856 if (u
&& size
!= 0) {
10857 unallocated_encoding(s
);
10861 case 0x0: /* SHADD, UHADD */
10862 case 0x2: /* SRHADD, URHADD */
10863 case 0x4: /* SHSUB, UHSUB */
10864 case 0xc: /* SMAX, UMAX */
10865 case 0xd: /* SMIN, UMIN */
10866 case 0xe: /* SABD, UABD */
10867 case 0xf: /* SABA, UABA */
10868 case 0x12: /* MLA, MLS */
10870 unallocated_encoding(s
);
10874 case 0x16: /* SQDMULH, SQRDMULH */
10875 if (size
== 0 || size
== 3) {
10876 unallocated_encoding(s
);
10881 if (size
== 3 && !is_q
) {
10882 unallocated_encoding(s
);
10888 if (!fp_access_check(s
)) {
10893 case 0x10: /* ADD, SUB */
10895 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10897 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10900 case 0x13: /* MUL, PMUL */
10901 if (!u
) { /* MUL */
10902 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10906 case 0x12: /* MLA, MLS */
10908 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10910 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10914 if (!u
) { /* CMTST */
10915 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10919 cond
= TCG_COND_EQ
;
10921 case 0x06: /* CMGT, CMHI */
10922 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10924 case 0x07: /* CMGE, CMHS */
10925 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10927 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10928 vec_full_reg_offset(s
, rn
),
10929 vec_full_reg_offset(s
, rm
),
10930 is_q
? 16 : 8, vec_full_reg_size(s
));
10936 for (pass
= 0; pass
< 2; pass
++) {
10937 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10938 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10939 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10941 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10942 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10944 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
10946 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10948 tcg_temp_free_i64(tcg_res
);
10949 tcg_temp_free_i64(tcg_op1
);
10950 tcg_temp_free_i64(tcg_op2
);
10953 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10954 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10955 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10956 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10957 NeonGenTwoOpFn
*genfn
= NULL
;
10958 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
10960 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
10961 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
10964 case 0x0: /* SHADD, UHADD */
10966 static NeonGenTwoOpFn
* const fns
[3][2] = {
10967 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
10968 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
10969 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
10971 genfn
= fns
[size
][u
];
10974 case 0x1: /* SQADD, UQADD */
10976 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10977 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
10978 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
10979 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
10981 genenvfn
= fns
[size
][u
];
10984 case 0x2: /* SRHADD, URHADD */
10986 static NeonGenTwoOpFn
* const fns
[3][2] = {
10987 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
10988 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
10989 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
10991 genfn
= fns
[size
][u
];
10994 case 0x4: /* SHSUB, UHSUB */
10996 static NeonGenTwoOpFn
* const fns
[3][2] = {
10997 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
10998 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
10999 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11001 genfn
= fns
[size
][u
];
11004 case 0x5: /* SQSUB, UQSUB */
11006 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11007 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
11008 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
11009 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
11011 genenvfn
= fns
[size
][u
];
11014 case 0x8: /* SSHL, USHL */
11016 static NeonGenTwoOpFn
* const fns
[3][2] = {
11017 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11018 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11019 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11021 genfn
= fns
[size
][u
];
11024 case 0x9: /* SQSHL, UQSHL */
11026 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11027 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11028 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11029 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11031 genenvfn
= fns
[size
][u
];
11034 case 0xa: /* SRSHL, URSHL */
11036 static NeonGenTwoOpFn
* const fns
[3][2] = {
11037 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11038 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11039 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11041 genfn
= fns
[size
][u
];
11044 case 0xb: /* SQRSHL, UQRSHL */
11046 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11047 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11048 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11049 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11051 genenvfn
= fns
[size
][u
];
11054 case 0xc: /* SMAX, UMAX */
11056 static NeonGenTwoOpFn
* const fns
[3][2] = {
11057 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
11058 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
11059 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11061 genfn
= fns
[size
][u
];
11065 case 0xd: /* SMIN, UMIN */
11067 static NeonGenTwoOpFn
* const fns
[3][2] = {
11068 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
11069 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
11070 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11072 genfn
= fns
[size
][u
];
11075 case 0xe: /* SABD, UABD */
11076 case 0xf: /* SABA, UABA */
11078 static NeonGenTwoOpFn
* const fns
[3][2] = {
11079 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11080 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11081 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11083 genfn
= fns
[size
][u
];
11086 case 0x13: /* MUL, PMUL */
11087 assert(u
); /* PMUL */
11089 genfn
= gen_helper_neon_mul_p8
;
11091 case 0x16: /* SQDMULH, SQRDMULH */
11093 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11094 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11095 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11097 assert(size
== 1 || size
== 2);
11098 genenvfn
= fns
[size
- 1][u
];
11102 g_assert_not_reached();
11106 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11108 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11111 if (opcode
== 0xf) {
11112 /* SABA, UABA: accumulating ops */
11113 static NeonGenTwoOpFn
* const fns
[3] = {
11114 gen_helper_neon_add_u8
,
11115 gen_helper_neon_add_u16
,
11119 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11120 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11123 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11125 tcg_temp_free_i32(tcg_res
);
11126 tcg_temp_free_i32(tcg_op1
);
11127 tcg_temp_free_i32(tcg_op2
);
11130 clear_vec_high(s
, is_q
, rd
);
11133 /* AdvSIMD three same
11134 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11135 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11136 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11137 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11139 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11141 int opcode
= extract32(insn
, 11, 5);
11144 case 0x3: /* logic ops */
11145 disas_simd_3same_logic(s
, insn
);
11147 case 0x17: /* ADDP */
11148 case 0x14: /* SMAXP, UMAXP */
11149 case 0x15: /* SMINP, UMINP */
11151 /* Pairwise operations */
11152 int is_q
= extract32(insn
, 30, 1);
11153 int u
= extract32(insn
, 29, 1);
11154 int size
= extract32(insn
, 22, 2);
11155 int rm
= extract32(insn
, 16, 5);
11156 int rn
= extract32(insn
, 5, 5);
11157 int rd
= extract32(insn
, 0, 5);
11158 if (opcode
== 0x17) {
11159 if (u
|| (size
== 3 && !is_q
)) {
11160 unallocated_encoding(s
);
11165 unallocated_encoding(s
);
11169 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11172 case 0x18 ... 0x31:
11173 /* floating point ops, sz[1] and U are part of opcode */
11174 disas_simd_3same_float(s
, insn
);
11177 disas_simd_3same_int(s
, insn
);
11183 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11185 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11186 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11187 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11188 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11190 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11191 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11194 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11196 int opcode
, fpopcode
;
11197 int is_q
, u
, a
, rm
, rn
, rd
;
11198 int datasize
, elements
;
11201 bool pairwise
= false;
11203 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
11204 unallocated_encoding(s
);
11208 if (!fp_access_check(s
)) {
11212 /* For these floating point ops, the U, a and opcode bits
11213 * together indicate the operation.
11215 opcode
= extract32(insn
, 11, 3);
11216 u
= extract32(insn
, 29, 1);
11217 a
= extract32(insn
, 23, 1);
11218 is_q
= extract32(insn
, 30, 1);
11219 rm
= extract32(insn
, 16, 5);
11220 rn
= extract32(insn
, 5, 5);
11221 rd
= extract32(insn
, 0, 5);
11223 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11224 datasize
= is_q
? 128 : 64;
11225 elements
= datasize
/ 16;
11227 switch (fpopcode
) {
11228 case 0x10: /* FMAXNMP */
11229 case 0x12: /* FADDP */
11230 case 0x16: /* FMAXP */
11231 case 0x18: /* FMINNMP */
11232 case 0x1e: /* FMINP */
11237 fpst
= get_fpstatus_ptr(true);
11240 int maxpass
= is_q
? 8 : 4;
11241 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11242 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11243 TCGv_i32 tcg_res
[8];
11245 for (pass
= 0; pass
< maxpass
; pass
++) {
11246 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11247 int passelt
= (pass
<< 1) & (maxpass
- 1);
11249 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11250 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11251 tcg_res
[pass
] = tcg_temp_new_i32();
11253 switch (fpopcode
) {
11254 case 0x10: /* FMAXNMP */
11255 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11258 case 0x12: /* FADDP */
11259 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11261 case 0x16: /* FMAXP */
11262 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11264 case 0x18: /* FMINNMP */
11265 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11268 case 0x1e: /* FMINP */
11269 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11272 g_assert_not_reached();
11276 for (pass
= 0; pass
< maxpass
; pass
++) {
11277 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11278 tcg_temp_free_i32(tcg_res
[pass
]);
11281 tcg_temp_free_i32(tcg_op1
);
11282 tcg_temp_free_i32(tcg_op2
);
11285 for (pass
= 0; pass
< elements
; pass
++) {
11286 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11287 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11288 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11290 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11291 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11293 switch (fpopcode
) {
11294 case 0x0: /* FMAXNM */
11295 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11297 case 0x1: /* FMLA */
11298 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11299 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11302 case 0x2: /* FADD */
11303 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11305 case 0x3: /* FMULX */
11306 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11308 case 0x4: /* FCMEQ */
11309 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11311 case 0x6: /* FMAX */
11312 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11314 case 0x7: /* FRECPS */
11315 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11317 case 0x8: /* FMINNM */
11318 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11320 case 0x9: /* FMLS */
11321 /* As usual for ARM, separate negation for fused multiply-add */
11322 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11323 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11324 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11327 case 0xa: /* FSUB */
11328 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11330 case 0xe: /* FMIN */
11331 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11333 case 0xf: /* FRSQRTS */
11334 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11336 case 0x13: /* FMUL */
11337 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11339 case 0x14: /* FCMGE */
11340 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11342 case 0x15: /* FACGE */
11343 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11345 case 0x17: /* FDIV */
11346 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11348 case 0x1a: /* FABD */
11349 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11350 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11352 case 0x1c: /* FCMGT */
11353 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11355 case 0x1d: /* FACGT */
11356 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11359 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11360 __func__
, insn
, fpopcode
, s
->pc
);
11361 g_assert_not_reached();
11364 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11365 tcg_temp_free_i32(tcg_res
);
11366 tcg_temp_free_i32(tcg_op1
);
11367 tcg_temp_free_i32(tcg_op2
);
11371 tcg_temp_free_ptr(fpst
);
11373 clear_vec_high(s
, is_q
, rd
);
11376 /* AdvSIMD three same extra
11377 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11378 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11379 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11380 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11382 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11384 int rd
= extract32(insn
, 0, 5);
11385 int rn
= extract32(insn
, 5, 5);
11386 int opcode
= extract32(insn
, 11, 4);
11387 int rm
= extract32(insn
, 16, 5);
11388 int size
= extract32(insn
, 22, 2);
11389 bool u
= extract32(insn
, 29, 1);
11390 bool is_q
= extract32(insn
, 30, 1);
11393 switch (u
* 16 + opcode
) {
11394 case 0x10: /* SQRDMLAH (vector) */
11395 case 0x11: /* SQRDMLSH (vector) */
11396 if (size
!= 1 && size
!= 2) {
11397 unallocated_encoding(s
);
11400 feature
= ARM_FEATURE_V8_RDM
;
11402 case 0x8: /* FCMLA, #0 */
11403 case 0x9: /* FCMLA, #90 */
11404 case 0xa: /* FCMLA, #180 */
11405 case 0xb: /* FCMLA, #270 */
11406 case 0xc: /* FCADD, #90 */
11407 case 0xe: /* FCADD, #270 */
11409 || (size
== 1 && !arm_dc_feature(s
, ARM_FEATURE_V8_FP16
))
11410 || (size
== 3 && !is_q
)) {
11411 unallocated_encoding(s
);
11414 feature
= ARM_FEATURE_V8_FCMA
;
11417 unallocated_encoding(s
);
11420 if (!arm_dc_feature(s
, feature
)) {
11421 unallocated_encoding(s
);
11424 if (!fp_access_check(s
)) {
11429 case 0x0: /* SQRDMLAH (vector) */
11432 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11435 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11438 g_assert_not_reached();
11442 case 0x1: /* SQRDMLSH (vector) */
11445 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11448 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11451 g_assert_not_reached();
11455 case 0x8: /* FCMLA, #0 */
11456 case 0x9: /* FCMLA, #90 */
11457 case 0xa: /* FCMLA, #180 */
11458 case 0xb: /* FCMLA, #270 */
11459 rot
= extract32(opcode
, 0, 2);
11462 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11463 gen_helper_gvec_fcmlah
);
11466 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11467 gen_helper_gvec_fcmlas
);
11470 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11471 gen_helper_gvec_fcmlad
);
11474 g_assert_not_reached();
11478 case 0xc: /* FCADD, #90 */
11479 case 0xe: /* FCADD, #270 */
11480 rot
= extract32(opcode
, 1, 1);
11483 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11484 gen_helper_gvec_fcaddh
);
11487 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11488 gen_helper_gvec_fcadds
);
11491 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11492 gen_helper_gvec_fcaddd
);
11495 g_assert_not_reached();
11500 g_assert_not_reached();
11504 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11505 int size
, int rn
, int rd
)
11507 /* Handle 2-reg-misc ops which are widening (so each size element
11508 * in the source becomes a 2*size element in the destination.
11509 * The only instruction like this is FCVTL.
11514 /* 32 -> 64 bit fp conversion */
11515 TCGv_i64 tcg_res
[2];
11516 int srcelt
= is_q
? 2 : 0;
11518 for (pass
= 0; pass
< 2; pass
++) {
11519 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11520 tcg_res
[pass
] = tcg_temp_new_i64();
11522 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11523 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11524 tcg_temp_free_i32(tcg_op
);
11526 for (pass
= 0; pass
< 2; pass
++) {
11527 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11528 tcg_temp_free_i64(tcg_res
[pass
]);
11531 /* 16 -> 32 bit fp conversion */
11532 int srcelt
= is_q
? 4 : 0;
11533 TCGv_i32 tcg_res
[4];
11535 for (pass
= 0; pass
< 4; pass
++) {
11536 tcg_res
[pass
] = tcg_temp_new_i32();
11538 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11539 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11542 for (pass
= 0; pass
< 4; pass
++) {
11543 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11544 tcg_temp_free_i32(tcg_res
[pass
]);
11549 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11550 bool is_q
, int size
, int rn
, int rd
)
11552 int op
= (opcode
<< 1) | u
;
11553 int opsz
= op
+ size
;
11554 int grp_size
= 3 - opsz
;
11555 int dsize
= is_q
? 128 : 64;
11559 unallocated_encoding(s
);
11563 if (!fp_access_check(s
)) {
11568 /* Special case bytes, use bswap op on each group of elements */
11569 int groups
= dsize
/ (8 << grp_size
);
11571 for (i
= 0; i
< groups
; i
++) {
11572 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11574 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11575 switch (grp_size
) {
11577 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11580 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11583 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11586 g_assert_not_reached();
11588 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11589 tcg_temp_free_i64(tcg_tmp
);
11591 clear_vec_high(s
, is_q
, rd
);
11593 int revmask
= (1 << grp_size
) - 1;
11594 int esize
= 8 << size
;
11595 int elements
= dsize
/ esize
;
11596 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11597 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11598 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11600 for (i
= 0; i
< elements
; i
++) {
11601 int e_rev
= (i
& 0xf) ^ revmask
;
11602 int off
= e_rev
* esize
;
11603 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11605 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11606 tcg_rn
, off
- 64, esize
);
11608 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11611 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11612 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11614 tcg_temp_free_i64(tcg_rd_hi
);
11615 tcg_temp_free_i64(tcg_rd
);
11616 tcg_temp_free_i64(tcg_rn
);
11620 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11621 bool is_q
, int size
, int rn
, int rd
)
11623 /* Implement the pairwise operations from 2-misc:
11624 * SADDLP, UADDLP, SADALP, UADALP.
11625 * These all add pairs of elements in the input to produce a
11626 * double-width result element in the output (possibly accumulating).
11628 bool accum
= (opcode
== 0x6);
11629 int maxpass
= is_q
? 2 : 1;
11631 TCGv_i64 tcg_res
[2];
11634 /* 32 + 32 -> 64 op */
11635 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11637 for (pass
= 0; pass
< maxpass
; pass
++) {
11638 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11639 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11641 tcg_res
[pass
] = tcg_temp_new_i64();
11643 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11644 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11645 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11647 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11648 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11651 tcg_temp_free_i64(tcg_op1
);
11652 tcg_temp_free_i64(tcg_op2
);
11655 for (pass
= 0; pass
< maxpass
; pass
++) {
11656 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11657 NeonGenOneOpFn
*genfn
;
11658 static NeonGenOneOpFn
* const fns
[2][2] = {
11659 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11660 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11663 genfn
= fns
[size
][u
];
11665 tcg_res
[pass
] = tcg_temp_new_i64();
11667 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11668 genfn(tcg_res
[pass
], tcg_op
);
11671 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11673 gen_helper_neon_addl_u16(tcg_res
[pass
],
11674 tcg_res
[pass
], tcg_op
);
11676 gen_helper_neon_addl_u32(tcg_res
[pass
],
11677 tcg_res
[pass
], tcg_op
);
11680 tcg_temp_free_i64(tcg_op
);
11684 tcg_res
[1] = tcg_const_i64(0);
11686 for (pass
= 0; pass
< 2; pass
++) {
11687 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11688 tcg_temp_free_i64(tcg_res
[pass
]);
11692 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11694 /* Implement SHLL and SHLL2 */
11696 int part
= is_q
? 2 : 0;
11697 TCGv_i64 tcg_res
[2];
11699 for (pass
= 0; pass
< 2; pass
++) {
11700 static NeonGenWidenFn
* const widenfns
[3] = {
11701 gen_helper_neon_widen_u8
,
11702 gen_helper_neon_widen_u16
,
11703 tcg_gen_extu_i32_i64
,
11705 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11706 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11708 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11709 tcg_res
[pass
] = tcg_temp_new_i64();
11710 widenfn(tcg_res
[pass
], tcg_op
);
11711 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11713 tcg_temp_free_i32(tcg_op
);
11716 for (pass
= 0; pass
< 2; pass
++) {
11717 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11718 tcg_temp_free_i64(tcg_res
[pass
]);
11722 /* AdvSIMD two reg misc
11723 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11724 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11725 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11726 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11728 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11730 int size
= extract32(insn
, 22, 2);
11731 int opcode
= extract32(insn
, 12, 5);
11732 bool u
= extract32(insn
, 29, 1);
11733 bool is_q
= extract32(insn
, 30, 1);
11734 int rn
= extract32(insn
, 5, 5);
11735 int rd
= extract32(insn
, 0, 5);
11736 bool need_fpstatus
= false;
11737 bool need_rmode
= false;
11739 TCGv_i32 tcg_rmode
;
11740 TCGv_ptr tcg_fpstatus
;
11743 case 0x0: /* REV64, REV32 */
11744 case 0x1: /* REV16 */
11745 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11747 case 0x5: /* CNT, NOT, RBIT */
11748 if (u
&& size
== 0) {
11751 } else if (u
&& size
== 1) {
11754 } else if (!u
&& size
== 0) {
11758 unallocated_encoding(s
);
11760 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11761 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11763 unallocated_encoding(s
);
11766 if (!fp_access_check(s
)) {
11770 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11772 case 0x4: /* CLS, CLZ */
11774 unallocated_encoding(s
);
11778 case 0x2: /* SADDLP, UADDLP */
11779 case 0x6: /* SADALP, UADALP */
11781 unallocated_encoding(s
);
11784 if (!fp_access_check(s
)) {
11787 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11789 case 0x13: /* SHLL, SHLL2 */
11790 if (u
== 0 || size
== 3) {
11791 unallocated_encoding(s
);
11794 if (!fp_access_check(s
)) {
11797 handle_shll(s
, is_q
, size
, rn
, rd
);
11799 case 0xa: /* CMLT */
11801 unallocated_encoding(s
);
11805 case 0x8: /* CMGT, CMGE */
11806 case 0x9: /* CMEQ, CMLE */
11807 case 0xb: /* ABS, NEG */
11808 if (size
== 3 && !is_q
) {
11809 unallocated_encoding(s
);
11813 case 0x3: /* SUQADD, USQADD */
11814 if (size
== 3 && !is_q
) {
11815 unallocated_encoding(s
);
11818 if (!fp_access_check(s
)) {
11821 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11823 case 0x7: /* SQABS, SQNEG */
11824 if (size
== 3 && !is_q
) {
11825 unallocated_encoding(s
);
11830 case 0x16 ... 0x1d:
11833 /* Floating point: U, size[1] and opcode indicate operation;
11834 * size[0] indicates single or double precision.
11836 int is_double
= extract32(size
, 0, 1);
11837 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11838 size
= is_double
? 3 : 2;
11840 case 0x2f: /* FABS */
11841 case 0x6f: /* FNEG */
11842 if (size
== 3 && !is_q
) {
11843 unallocated_encoding(s
);
11847 case 0x1d: /* SCVTF */
11848 case 0x5d: /* UCVTF */
11850 bool is_signed
= (opcode
== 0x1d) ? true : false;
11851 int elements
= is_double
? 2 : is_q
? 4 : 2;
11852 if (is_double
&& !is_q
) {
11853 unallocated_encoding(s
);
11856 if (!fp_access_check(s
)) {
11859 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11862 case 0x2c: /* FCMGT (zero) */
11863 case 0x2d: /* FCMEQ (zero) */
11864 case 0x2e: /* FCMLT (zero) */
11865 case 0x6c: /* FCMGE (zero) */
11866 case 0x6d: /* FCMLE (zero) */
11867 if (size
== 3 && !is_q
) {
11868 unallocated_encoding(s
);
11871 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11873 case 0x7f: /* FSQRT */
11874 if (size
== 3 && !is_q
) {
11875 unallocated_encoding(s
);
11879 case 0x1a: /* FCVTNS */
11880 case 0x1b: /* FCVTMS */
11881 case 0x3a: /* FCVTPS */
11882 case 0x3b: /* FCVTZS */
11883 case 0x5a: /* FCVTNU */
11884 case 0x5b: /* FCVTMU */
11885 case 0x7a: /* FCVTPU */
11886 case 0x7b: /* FCVTZU */
11887 need_fpstatus
= true;
11889 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11890 if (size
== 3 && !is_q
) {
11891 unallocated_encoding(s
);
11895 case 0x5c: /* FCVTAU */
11896 case 0x1c: /* FCVTAS */
11897 need_fpstatus
= true;
11899 rmode
= FPROUNDING_TIEAWAY
;
11900 if (size
== 3 && !is_q
) {
11901 unallocated_encoding(s
);
11905 case 0x3c: /* URECPE */
11907 unallocated_encoding(s
);
11911 case 0x3d: /* FRECPE */
11912 case 0x7d: /* FRSQRTE */
11913 if (size
== 3 && !is_q
) {
11914 unallocated_encoding(s
);
11917 if (!fp_access_check(s
)) {
11920 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11922 case 0x56: /* FCVTXN, FCVTXN2 */
11924 unallocated_encoding(s
);
11928 case 0x16: /* FCVTN, FCVTN2 */
11929 /* handle_2misc_narrow does a 2*size -> size operation, but these
11930 * instructions encode the source size rather than dest size.
11932 if (!fp_access_check(s
)) {
11935 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
11937 case 0x17: /* FCVTL, FCVTL2 */
11938 if (!fp_access_check(s
)) {
11941 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
11943 case 0x18: /* FRINTN */
11944 case 0x19: /* FRINTM */
11945 case 0x38: /* FRINTP */
11946 case 0x39: /* FRINTZ */
11948 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11950 case 0x59: /* FRINTX */
11951 case 0x79: /* FRINTI */
11952 need_fpstatus
= true;
11953 if (size
== 3 && !is_q
) {
11954 unallocated_encoding(s
);
11958 case 0x58: /* FRINTA */
11960 rmode
= FPROUNDING_TIEAWAY
;
11961 need_fpstatus
= true;
11962 if (size
== 3 && !is_q
) {
11963 unallocated_encoding(s
);
11967 case 0x7c: /* URSQRTE */
11969 unallocated_encoding(s
);
11972 need_fpstatus
= true;
11975 unallocated_encoding(s
);
11981 unallocated_encoding(s
);
11985 if (!fp_access_check(s
)) {
11989 if (need_fpstatus
|| need_rmode
) {
11990 tcg_fpstatus
= get_fpstatus_ptr(false);
11992 tcg_fpstatus
= NULL
;
11995 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
11996 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12003 if (u
&& size
== 0) { /* NOT */
12004 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12010 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12017 /* All 64-bit element operations can be shared with scalar 2misc */
12020 /* Coverity claims (size == 3 && !is_q) has been eliminated
12021 * from all paths leading to here.
12023 tcg_debug_assert(is_q
);
12024 for (pass
= 0; pass
< 2; pass
++) {
12025 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12026 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12028 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12030 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12031 tcg_rmode
, tcg_fpstatus
);
12033 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12035 tcg_temp_free_i64(tcg_res
);
12036 tcg_temp_free_i64(tcg_op
);
12041 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12042 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12043 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12046 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12049 /* Special cases for 32 bit elements */
12051 case 0xa: /* CMLT */
12052 /* 32 bit integer comparison against zero, result is
12053 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12056 cond
= TCG_COND_LT
;
12058 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12059 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12061 case 0x8: /* CMGT, CMGE */
12062 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12064 case 0x9: /* CMEQ, CMLE */
12065 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12067 case 0x4: /* CLS */
12069 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12071 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12074 case 0x7: /* SQABS, SQNEG */
12076 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12078 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12081 case 0xb: /* ABS, NEG */
12083 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12085 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12086 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12087 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12088 tcg_zero
, tcg_op
, tcg_res
);
12089 tcg_temp_free_i32(tcg_zero
);
12092 case 0x2f: /* FABS */
12093 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12095 case 0x6f: /* FNEG */
12096 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12098 case 0x7f: /* FSQRT */
12099 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12101 case 0x1a: /* FCVTNS */
12102 case 0x1b: /* FCVTMS */
12103 case 0x1c: /* FCVTAS */
12104 case 0x3a: /* FCVTPS */
12105 case 0x3b: /* FCVTZS */
12107 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12108 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12109 tcg_shift
, tcg_fpstatus
);
12110 tcg_temp_free_i32(tcg_shift
);
12113 case 0x5a: /* FCVTNU */
12114 case 0x5b: /* FCVTMU */
12115 case 0x5c: /* FCVTAU */
12116 case 0x7a: /* FCVTPU */
12117 case 0x7b: /* FCVTZU */
12119 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12120 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12121 tcg_shift
, tcg_fpstatus
);
12122 tcg_temp_free_i32(tcg_shift
);
12125 case 0x18: /* FRINTN */
12126 case 0x19: /* FRINTM */
12127 case 0x38: /* FRINTP */
12128 case 0x39: /* FRINTZ */
12129 case 0x58: /* FRINTA */
12130 case 0x79: /* FRINTI */
12131 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12133 case 0x59: /* FRINTX */
12134 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12136 case 0x7c: /* URSQRTE */
12137 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12140 g_assert_not_reached();
12143 /* Use helpers for 8 and 16 bit elements */
12145 case 0x5: /* CNT, RBIT */
12146 /* For these two insns size is part of the opcode specifier
12147 * (handled earlier); they always operate on byte elements.
12150 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12152 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12155 case 0x7: /* SQABS, SQNEG */
12157 NeonGenOneOpEnvFn
*genfn
;
12158 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12159 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12160 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12162 genfn
= fns
[size
][u
];
12163 genfn(tcg_res
, cpu_env
, tcg_op
);
12166 case 0x8: /* CMGT, CMGE */
12167 case 0x9: /* CMEQ, CMLE */
12168 case 0xa: /* CMLT */
12170 static NeonGenTwoOpFn
* const fns
[3][2] = {
12171 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12172 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12173 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12175 NeonGenTwoOpFn
*genfn
;
12178 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12180 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12181 comp
= (opcode
- 0x8) * 2 + u
;
12182 /* ...but LE, LT are implemented as reverse GE, GT */
12183 reverse
= (comp
> 2);
12187 genfn
= fns
[comp
][size
];
12189 genfn(tcg_res
, tcg_zero
, tcg_op
);
12191 genfn(tcg_res
, tcg_op
, tcg_zero
);
12193 tcg_temp_free_i32(tcg_zero
);
12196 case 0xb: /* ABS, NEG */
12198 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12200 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12202 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12204 tcg_temp_free_i32(tcg_zero
);
12207 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12209 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12213 case 0x4: /* CLS, CLZ */
12216 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12218 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12222 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12224 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12229 g_assert_not_reached();
12233 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12235 tcg_temp_free_i32(tcg_res
);
12236 tcg_temp_free_i32(tcg_op
);
12239 clear_vec_high(s
, is_q
, rd
);
12242 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12243 tcg_temp_free_i32(tcg_rmode
);
12245 if (need_fpstatus
) {
12246 tcg_temp_free_ptr(tcg_fpstatus
);
12250 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12252 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12253 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12254 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12255 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12256 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12257 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12259 * This actually covers two groups where scalar access is governed by
12260 * bit 28. A bunch of the instructions (float to integral) only exist
12261 * in the vector form and are un-allocated for the scalar decode. Also
12262 * in the scalar decode Q is always 1.
12264 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12266 int fpop
, opcode
, a
, u
;
12270 bool only_in_vector
= false;
12273 TCGv_i32 tcg_rmode
= NULL
;
12274 TCGv_ptr tcg_fpstatus
= NULL
;
12275 bool need_rmode
= false;
12276 bool need_fpst
= true;
12279 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
12280 unallocated_encoding(s
);
12284 rd
= extract32(insn
, 0, 5);
12285 rn
= extract32(insn
, 5, 5);
12287 a
= extract32(insn
, 23, 1);
12288 u
= extract32(insn
, 29, 1);
12289 is_scalar
= extract32(insn
, 28, 1);
12290 is_q
= extract32(insn
, 30, 1);
12292 opcode
= extract32(insn
, 12, 5);
12293 fpop
= deposit32(opcode
, 5, 1, a
);
12294 fpop
= deposit32(fpop
, 6, 1, u
);
12296 rd
= extract32(insn
, 0, 5);
12297 rn
= extract32(insn
, 5, 5);
12300 case 0x1d: /* SCVTF */
12301 case 0x5d: /* UCVTF */
12308 elements
= (is_q
? 8 : 4);
12311 if (!fp_access_check(s
)) {
12314 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12318 case 0x2c: /* FCMGT (zero) */
12319 case 0x2d: /* FCMEQ (zero) */
12320 case 0x2e: /* FCMLT (zero) */
12321 case 0x6c: /* FCMGE (zero) */
12322 case 0x6d: /* FCMLE (zero) */
12323 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12325 case 0x3d: /* FRECPE */
12326 case 0x3f: /* FRECPX */
12328 case 0x18: /* FRINTN */
12330 only_in_vector
= true;
12331 rmode
= FPROUNDING_TIEEVEN
;
12333 case 0x19: /* FRINTM */
12335 only_in_vector
= true;
12336 rmode
= FPROUNDING_NEGINF
;
12338 case 0x38: /* FRINTP */
12340 only_in_vector
= true;
12341 rmode
= FPROUNDING_POSINF
;
12343 case 0x39: /* FRINTZ */
12345 only_in_vector
= true;
12346 rmode
= FPROUNDING_ZERO
;
12348 case 0x58: /* FRINTA */
12350 only_in_vector
= true;
12351 rmode
= FPROUNDING_TIEAWAY
;
12353 case 0x59: /* FRINTX */
12354 case 0x79: /* FRINTI */
12355 only_in_vector
= true;
12356 /* current rounding mode */
12358 case 0x1a: /* FCVTNS */
12360 rmode
= FPROUNDING_TIEEVEN
;
12362 case 0x1b: /* FCVTMS */
12364 rmode
= FPROUNDING_NEGINF
;
12366 case 0x1c: /* FCVTAS */
12368 rmode
= FPROUNDING_TIEAWAY
;
12370 case 0x3a: /* FCVTPS */
12372 rmode
= FPROUNDING_POSINF
;
12374 case 0x3b: /* FCVTZS */
12376 rmode
= FPROUNDING_ZERO
;
12378 case 0x5a: /* FCVTNU */
12380 rmode
= FPROUNDING_TIEEVEN
;
12382 case 0x5b: /* FCVTMU */
12384 rmode
= FPROUNDING_NEGINF
;
12386 case 0x5c: /* FCVTAU */
12388 rmode
= FPROUNDING_TIEAWAY
;
12390 case 0x7a: /* FCVTPU */
12392 rmode
= FPROUNDING_POSINF
;
12394 case 0x7b: /* FCVTZU */
12396 rmode
= FPROUNDING_ZERO
;
12398 case 0x2f: /* FABS */
12399 case 0x6f: /* FNEG */
12402 case 0x7d: /* FRSQRTE */
12403 case 0x7f: /* FSQRT (vector) */
12406 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12407 g_assert_not_reached();
12411 /* Check additional constraints for the scalar encoding */
12414 unallocated_encoding(s
);
12417 /* FRINTxx is only in the vector form */
12418 if (only_in_vector
) {
12419 unallocated_encoding(s
);
12424 if (!fp_access_check(s
)) {
12428 if (need_rmode
|| need_fpst
) {
12429 tcg_fpstatus
= get_fpstatus_ptr(true);
12433 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12434 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12438 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12439 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12442 case 0x1a: /* FCVTNS */
12443 case 0x1b: /* FCVTMS */
12444 case 0x1c: /* FCVTAS */
12445 case 0x3a: /* FCVTPS */
12446 case 0x3b: /* FCVTZS */
12447 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12449 case 0x3d: /* FRECPE */
12450 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12452 case 0x3f: /* FRECPX */
12453 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12455 case 0x5a: /* FCVTNU */
12456 case 0x5b: /* FCVTMU */
12457 case 0x5c: /* FCVTAU */
12458 case 0x7a: /* FCVTPU */
12459 case 0x7b: /* FCVTZU */
12460 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12462 case 0x6f: /* FNEG */
12463 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12465 case 0x7d: /* FRSQRTE */
12466 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12469 g_assert_not_reached();
12472 /* limit any sign extension going on */
12473 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12474 write_fp_sreg(s
, rd
, tcg_res
);
12476 tcg_temp_free_i32(tcg_res
);
12477 tcg_temp_free_i32(tcg_op
);
12479 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12480 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12481 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12483 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12486 case 0x1a: /* FCVTNS */
12487 case 0x1b: /* FCVTMS */
12488 case 0x1c: /* FCVTAS */
12489 case 0x3a: /* FCVTPS */
12490 case 0x3b: /* FCVTZS */
12491 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12493 case 0x3d: /* FRECPE */
12494 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12496 case 0x5a: /* FCVTNU */
12497 case 0x5b: /* FCVTMU */
12498 case 0x5c: /* FCVTAU */
12499 case 0x7a: /* FCVTPU */
12500 case 0x7b: /* FCVTZU */
12501 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12503 case 0x18: /* FRINTN */
12504 case 0x19: /* FRINTM */
12505 case 0x38: /* FRINTP */
12506 case 0x39: /* FRINTZ */
12507 case 0x58: /* FRINTA */
12508 case 0x79: /* FRINTI */
12509 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12511 case 0x59: /* FRINTX */
12512 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12514 case 0x2f: /* FABS */
12515 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12517 case 0x6f: /* FNEG */
12518 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12520 case 0x7d: /* FRSQRTE */
12521 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12523 case 0x7f: /* FSQRT */
12524 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12527 g_assert_not_reached();
12530 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12532 tcg_temp_free_i32(tcg_res
);
12533 tcg_temp_free_i32(tcg_op
);
12536 clear_vec_high(s
, is_q
, rd
);
12540 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12541 tcg_temp_free_i32(tcg_rmode
);
12544 if (tcg_fpstatus
) {
12545 tcg_temp_free_ptr(tcg_fpstatus
);
12549 /* AdvSIMD scalar x indexed element
12550 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12551 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12552 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12553 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12554 * AdvSIMD vector x indexed element
12555 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12556 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12557 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12558 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12560 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12562 /* This encoding has two kinds of instruction:
12563 * normal, where we perform elt x idxelt => elt for each
12564 * element in the vector
12565 * long, where we perform elt x idxelt and generate a result of
12566 * double the width of the input element
12567 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12569 bool is_scalar
= extract32(insn
, 28, 1);
12570 bool is_q
= extract32(insn
, 30, 1);
12571 bool u
= extract32(insn
, 29, 1);
12572 int size
= extract32(insn
, 22, 2);
12573 int l
= extract32(insn
, 21, 1);
12574 int m
= extract32(insn
, 20, 1);
12575 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12576 int rm
= extract32(insn
, 16, 4);
12577 int opcode
= extract32(insn
, 12, 4);
12578 int h
= extract32(insn
, 11, 1);
12579 int rn
= extract32(insn
, 5, 5);
12580 int rd
= extract32(insn
, 0, 5);
12581 bool is_long
= false;
12583 bool is_fp16
= false;
12587 switch (16 * u
+ opcode
) {
12588 case 0x08: /* MUL */
12589 case 0x10: /* MLA */
12590 case 0x14: /* MLS */
12592 unallocated_encoding(s
);
12596 case 0x02: /* SMLAL, SMLAL2 */
12597 case 0x12: /* UMLAL, UMLAL2 */
12598 case 0x06: /* SMLSL, SMLSL2 */
12599 case 0x16: /* UMLSL, UMLSL2 */
12600 case 0x0a: /* SMULL, SMULL2 */
12601 case 0x1a: /* UMULL, UMULL2 */
12603 unallocated_encoding(s
);
12608 case 0x03: /* SQDMLAL, SQDMLAL2 */
12609 case 0x07: /* SQDMLSL, SQDMLSL2 */
12610 case 0x0b: /* SQDMULL, SQDMULL2 */
12613 case 0x0c: /* SQDMULH */
12614 case 0x0d: /* SQRDMULH */
12616 case 0x01: /* FMLA */
12617 case 0x05: /* FMLS */
12618 case 0x09: /* FMUL */
12619 case 0x19: /* FMULX */
12622 case 0x1d: /* SQRDMLAH */
12623 case 0x1f: /* SQRDMLSH */
12624 if (!arm_dc_feature(s
, ARM_FEATURE_V8_RDM
)) {
12625 unallocated_encoding(s
);
12629 case 0x11: /* FCMLA #0 */
12630 case 0x13: /* FCMLA #90 */
12631 case 0x15: /* FCMLA #180 */
12632 case 0x17: /* FCMLA #270 */
12633 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FCMA
)) {
12634 unallocated_encoding(s
);
12640 unallocated_encoding(s
);
12645 case 1: /* normal fp */
12646 /* convert insn encoded size to TCGMemOp size */
12648 case 0: /* half-precision */
12652 case MO_32
: /* single precision */
12653 case MO_64
: /* double precision */
12656 unallocated_encoding(s
);
12661 case 2: /* complex fp */
12662 /* Each indexable element is a complex pair. */
12667 unallocated_encoding(s
);
12675 unallocated_encoding(s
);
12680 default: /* integer */
12684 unallocated_encoding(s
);
12689 if (is_fp16
&& !arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
12690 unallocated_encoding(s
);
12694 /* Given TCGMemOp size, adjust register and indexing. */
12697 index
= h
<< 2 | l
<< 1 | m
;
12700 index
= h
<< 1 | l
;
12705 unallocated_encoding(s
);
12712 g_assert_not_reached();
12715 if (!fp_access_check(s
)) {
12720 fpst
= get_fpstatus_ptr(is_fp16
);
12725 switch (16 * u
+ opcode
) {
12726 case 0x11: /* FCMLA #0 */
12727 case 0x13: /* FCMLA #90 */
12728 case 0x15: /* FCMLA #180 */
12729 case 0x17: /* FCMLA #270 */
12730 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12731 vec_full_reg_offset(s
, rn
),
12732 vec_reg_offset(s
, rm
, index
, size
), fpst
,
12733 is_q
? 16 : 8, vec_full_reg_size(s
),
12734 extract32(insn
, 13, 2), /* rot */
12736 ? gen_helper_gvec_fcmlas_idx
12737 : gen_helper_gvec_fcmlah_idx
);
12738 tcg_temp_free_ptr(fpst
);
12743 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12746 assert(is_fp
&& is_q
&& !is_long
);
12748 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12750 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12751 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12752 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12754 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12756 switch (16 * u
+ opcode
) {
12757 case 0x05: /* FMLS */
12758 /* As usual for ARM, separate negation for fused multiply-add */
12759 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12761 case 0x01: /* FMLA */
12762 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12763 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12765 case 0x09: /* FMUL */
12766 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12768 case 0x19: /* FMULX */
12769 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12772 g_assert_not_reached();
12775 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12776 tcg_temp_free_i64(tcg_op
);
12777 tcg_temp_free_i64(tcg_res
);
12780 tcg_temp_free_i64(tcg_idx
);
12781 clear_vec_high(s
, !is_scalar
, rd
);
12782 } else if (!is_long
) {
12783 /* 32 bit floating point, or 16 or 32 bit integer.
12784 * For the 16 bit scalar case we use the usual Neon helpers and
12785 * rely on the fact that 0 op 0 == 0 with no side effects.
12787 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12788 int pass
, maxpasses
;
12793 maxpasses
= is_q
? 4 : 2;
12796 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12798 if (size
== 1 && !is_scalar
) {
12799 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12800 * the index into both halves of the 32 bit tcg_idx and then use
12801 * the usual Neon helpers.
12803 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12806 for (pass
= 0; pass
< maxpasses
; pass
++) {
12807 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12808 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12810 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12812 switch (16 * u
+ opcode
) {
12813 case 0x08: /* MUL */
12814 case 0x10: /* MLA */
12815 case 0x14: /* MLS */
12817 static NeonGenTwoOpFn
* const fns
[2][2] = {
12818 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12819 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12821 NeonGenTwoOpFn
*genfn
;
12822 bool is_sub
= opcode
== 0x4;
12825 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12827 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12829 if (opcode
== 0x8) {
12832 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12833 genfn
= fns
[size
- 1][is_sub
];
12834 genfn(tcg_res
, tcg_op
, tcg_res
);
12837 case 0x05: /* FMLS */
12838 case 0x01: /* FMLA */
12839 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12840 is_scalar
? size
: MO_32
);
12843 if (opcode
== 0x5) {
12844 /* As usual for ARM, separate negation for fused
12846 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12849 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12852 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12857 if (opcode
== 0x5) {
12858 /* As usual for ARM, separate negation for
12859 * fused multiply-add */
12860 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12862 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12866 g_assert_not_reached();
12869 case 0x09: /* FMUL */
12873 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12876 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12881 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12884 g_assert_not_reached();
12887 case 0x19: /* FMULX */
12891 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12894 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12899 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12902 g_assert_not_reached();
12905 case 0x0c: /* SQDMULH */
12907 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
12910 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
12914 case 0x0d: /* SQRDMULH */
12916 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
12919 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
12923 case 0x1d: /* SQRDMLAH */
12924 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12925 is_scalar
? size
: MO_32
);
12927 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
12928 tcg_op
, tcg_idx
, tcg_res
);
12930 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
12931 tcg_op
, tcg_idx
, tcg_res
);
12934 case 0x1f: /* SQRDMLSH */
12935 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12936 is_scalar
? size
: MO_32
);
12938 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
12939 tcg_op
, tcg_idx
, tcg_res
);
12941 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
12942 tcg_op
, tcg_idx
, tcg_res
);
12946 g_assert_not_reached();
12950 write_fp_sreg(s
, rd
, tcg_res
);
12952 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12955 tcg_temp_free_i32(tcg_op
);
12956 tcg_temp_free_i32(tcg_res
);
12959 tcg_temp_free_i32(tcg_idx
);
12960 clear_vec_high(s
, is_q
, rd
);
12962 /* long ops: 16x16->32 or 32x32->64 */
12963 TCGv_i64 tcg_res
[2];
12965 bool satop
= extract32(opcode
, 0, 1);
12966 TCGMemOp memop
= MO_32
;
12973 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12975 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
12977 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12978 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12979 TCGv_i64 tcg_passres
;
12985 passelt
= pass
+ (is_q
* 2);
12988 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
12990 tcg_res
[pass
] = tcg_temp_new_i64();
12992 if (opcode
== 0xa || opcode
== 0xb) {
12993 /* Non-accumulating ops */
12994 tcg_passres
= tcg_res
[pass
];
12996 tcg_passres
= tcg_temp_new_i64();
12999 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13000 tcg_temp_free_i64(tcg_op
);
13003 /* saturating, doubling */
13004 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13005 tcg_passres
, tcg_passres
);
13008 if (opcode
== 0xa || opcode
== 0xb) {
13012 /* Accumulating op: handle accumulate step */
13013 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13016 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13017 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13019 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13020 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13022 case 0x7: /* SQDMLSL, SQDMLSL2 */
13023 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13025 case 0x3: /* SQDMLAL, SQDMLAL2 */
13026 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13031 g_assert_not_reached();
13033 tcg_temp_free_i64(tcg_passres
);
13035 tcg_temp_free_i64(tcg_idx
);
13037 clear_vec_high(s
, !is_scalar
, rd
);
13039 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13042 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13045 /* The simplest way to handle the 16x16 indexed ops is to
13046 * duplicate the index into both halves of the 32 bit tcg_idx
13047 * and then use the usual Neon helpers.
13049 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13052 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13053 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13054 TCGv_i64 tcg_passres
;
13057 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13059 read_vec_element_i32(s
, tcg_op
, rn
,
13060 pass
+ (is_q
* 2), MO_32
);
13063 tcg_res
[pass
] = tcg_temp_new_i64();
13065 if (opcode
== 0xa || opcode
== 0xb) {
13066 /* Non-accumulating ops */
13067 tcg_passres
= tcg_res
[pass
];
13069 tcg_passres
= tcg_temp_new_i64();
13072 if (memop
& MO_SIGN
) {
13073 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13075 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13078 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13079 tcg_passres
, tcg_passres
);
13081 tcg_temp_free_i32(tcg_op
);
13083 if (opcode
== 0xa || opcode
== 0xb) {
13087 /* Accumulating op: handle accumulate step */
13088 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13091 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13092 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13095 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13096 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13099 case 0x7: /* SQDMLSL, SQDMLSL2 */
13100 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13102 case 0x3: /* SQDMLAL, SQDMLAL2 */
13103 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13108 g_assert_not_reached();
13110 tcg_temp_free_i64(tcg_passres
);
13112 tcg_temp_free_i32(tcg_idx
);
13115 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13120 tcg_res
[1] = tcg_const_i64(0);
13123 for (pass
= 0; pass
< 2; pass
++) {
13124 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13125 tcg_temp_free_i64(tcg_res
[pass
]);
13130 tcg_temp_free_ptr(fpst
);
13135 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13136 * +-----------------+------+-----------+--------+-----+------+------+
13137 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13138 * +-----------------+------+-----------+--------+-----+------+------+
13140 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13142 int size
= extract32(insn
, 22, 2);
13143 int opcode
= extract32(insn
, 12, 5);
13144 int rn
= extract32(insn
, 5, 5);
13145 int rd
= extract32(insn
, 0, 5);
13147 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13148 TCGv_i32 tcg_decrypt
;
13149 CryptoThreeOpIntFn
*genfn
;
13151 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
13153 unallocated_encoding(s
);
13158 case 0x4: /* AESE */
13160 genfn
= gen_helper_crypto_aese
;
13162 case 0x6: /* AESMC */
13164 genfn
= gen_helper_crypto_aesmc
;
13166 case 0x5: /* AESD */
13168 genfn
= gen_helper_crypto_aese
;
13170 case 0x7: /* AESIMC */
13172 genfn
= gen_helper_crypto_aesmc
;
13175 unallocated_encoding(s
);
13179 if (!fp_access_check(s
)) {
13183 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13184 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13185 tcg_decrypt
= tcg_const_i32(decrypt
);
13187 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13189 tcg_temp_free_ptr(tcg_rd_ptr
);
13190 tcg_temp_free_ptr(tcg_rn_ptr
);
13191 tcg_temp_free_i32(tcg_decrypt
);
13194 /* Crypto three-reg SHA
13195 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13196 * +-----------------+------+---+------+---+--------+-----+------+------+
13197 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13198 * +-----------------+------+---+------+---+--------+-----+------+------+
13200 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13202 int size
= extract32(insn
, 22, 2);
13203 int opcode
= extract32(insn
, 12, 3);
13204 int rm
= extract32(insn
, 16, 5);
13205 int rn
= extract32(insn
, 5, 5);
13206 int rd
= extract32(insn
, 0, 5);
13207 CryptoThreeOpFn
*genfn
;
13208 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13209 int feature
= ARM_FEATURE_V8_SHA256
;
13212 unallocated_encoding(s
);
13217 case 0: /* SHA1C */
13218 case 1: /* SHA1P */
13219 case 2: /* SHA1M */
13220 case 3: /* SHA1SU0 */
13222 feature
= ARM_FEATURE_V8_SHA1
;
13224 case 4: /* SHA256H */
13225 genfn
= gen_helper_crypto_sha256h
;
13227 case 5: /* SHA256H2 */
13228 genfn
= gen_helper_crypto_sha256h2
;
13230 case 6: /* SHA256SU1 */
13231 genfn
= gen_helper_crypto_sha256su1
;
13234 unallocated_encoding(s
);
13238 if (!arm_dc_feature(s
, feature
)) {
13239 unallocated_encoding(s
);
13243 if (!fp_access_check(s
)) {
13247 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13248 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13249 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13252 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13254 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13256 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13257 tcg_rm_ptr
, tcg_opcode
);
13258 tcg_temp_free_i32(tcg_opcode
);
13261 tcg_temp_free_ptr(tcg_rd_ptr
);
13262 tcg_temp_free_ptr(tcg_rn_ptr
);
13263 tcg_temp_free_ptr(tcg_rm_ptr
);
13266 /* Crypto two-reg SHA
13267 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13268 * +-----------------+------+-----------+--------+-----+------+------+
13269 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13270 * +-----------------+------+-----------+--------+-----+------+------+
13272 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13274 int size
= extract32(insn
, 22, 2);
13275 int opcode
= extract32(insn
, 12, 5);
13276 int rn
= extract32(insn
, 5, 5);
13277 int rd
= extract32(insn
, 0, 5);
13278 CryptoTwoOpFn
*genfn
;
13280 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13283 unallocated_encoding(s
);
13288 case 0: /* SHA1H */
13289 feature
= ARM_FEATURE_V8_SHA1
;
13290 genfn
= gen_helper_crypto_sha1h
;
13292 case 1: /* SHA1SU1 */
13293 feature
= ARM_FEATURE_V8_SHA1
;
13294 genfn
= gen_helper_crypto_sha1su1
;
13296 case 2: /* SHA256SU0 */
13297 feature
= ARM_FEATURE_V8_SHA256
;
13298 genfn
= gen_helper_crypto_sha256su0
;
13301 unallocated_encoding(s
);
13305 if (!arm_dc_feature(s
, feature
)) {
13306 unallocated_encoding(s
);
13310 if (!fp_access_check(s
)) {
13314 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13315 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13317 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13319 tcg_temp_free_ptr(tcg_rd_ptr
);
13320 tcg_temp_free_ptr(tcg_rn_ptr
);
13323 /* Crypto three-reg SHA512
13324 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13325 * +-----------------------+------+---+---+-----+--------+------+------+
13326 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13327 * +-----------------------+------+---+---+-----+--------+------+------+
13329 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13331 int opcode
= extract32(insn
, 10, 2);
13332 int o
= extract32(insn
, 14, 1);
13333 int rm
= extract32(insn
, 16, 5);
13334 int rn
= extract32(insn
, 5, 5);
13335 int rd
= extract32(insn
, 0, 5);
13337 CryptoThreeOpFn
*genfn
;
13341 case 0: /* SHA512H */
13342 feature
= ARM_FEATURE_V8_SHA512
;
13343 genfn
= gen_helper_crypto_sha512h
;
13345 case 1: /* SHA512H2 */
13346 feature
= ARM_FEATURE_V8_SHA512
;
13347 genfn
= gen_helper_crypto_sha512h2
;
13349 case 2: /* SHA512SU1 */
13350 feature
= ARM_FEATURE_V8_SHA512
;
13351 genfn
= gen_helper_crypto_sha512su1
;
13354 feature
= ARM_FEATURE_V8_SHA3
;
13360 case 0: /* SM3PARTW1 */
13361 feature
= ARM_FEATURE_V8_SM3
;
13362 genfn
= gen_helper_crypto_sm3partw1
;
13364 case 1: /* SM3PARTW2 */
13365 feature
= ARM_FEATURE_V8_SM3
;
13366 genfn
= gen_helper_crypto_sm3partw2
;
13368 case 2: /* SM4EKEY */
13369 feature
= ARM_FEATURE_V8_SM4
;
13370 genfn
= gen_helper_crypto_sm4ekey
;
13373 unallocated_encoding(s
);
13378 if (!arm_dc_feature(s
, feature
)) {
13379 unallocated_encoding(s
);
13383 if (!fp_access_check(s
)) {
13388 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13390 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13391 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13392 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13394 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13396 tcg_temp_free_ptr(tcg_rd_ptr
);
13397 tcg_temp_free_ptr(tcg_rn_ptr
);
13398 tcg_temp_free_ptr(tcg_rm_ptr
);
13400 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13403 tcg_op1
= tcg_temp_new_i64();
13404 tcg_op2
= tcg_temp_new_i64();
13405 tcg_res
[0] = tcg_temp_new_i64();
13406 tcg_res
[1] = tcg_temp_new_i64();
13408 for (pass
= 0; pass
< 2; pass
++) {
13409 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13410 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13412 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13413 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13415 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13416 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13418 tcg_temp_free_i64(tcg_op1
);
13419 tcg_temp_free_i64(tcg_op2
);
13420 tcg_temp_free_i64(tcg_res
[0]);
13421 tcg_temp_free_i64(tcg_res
[1]);
13425 /* Crypto two-reg SHA512
13426 * 31 12 11 10 9 5 4 0
13427 * +-----------------------------------------+--------+------+------+
13428 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13429 * +-----------------------------------------+--------+------+------+
13431 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13433 int opcode
= extract32(insn
, 10, 2);
13434 int rn
= extract32(insn
, 5, 5);
13435 int rd
= extract32(insn
, 0, 5);
13436 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13438 CryptoTwoOpFn
*genfn
;
13441 case 0: /* SHA512SU0 */
13442 feature
= ARM_FEATURE_V8_SHA512
;
13443 genfn
= gen_helper_crypto_sha512su0
;
13446 feature
= ARM_FEATURE_V8_SM4
;
13447 genfn
= gen_helper_crypto_sm4e
;
13450 unallocated_encoding(s
);
13454 if (!arm_dc_feature(s
, feature
)) {
13455 unallocated_encoding(s
);
13459 if (!fp_access_check(s
)) {
13463 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13464 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13466 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13468 tcg_temp_free_ptr(tcg_rd_ptr
);
13469 tcg_temp_free_ptr(tcg_rn_ptr
);
13472 /* Crypto four-register
13473 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13474 * +-------------------+-----+------+---+------+------+------+
13475 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13476 * +-------------------+-----+------+---+------+------+------+
13478 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13480 int op0
= extract32(insn
, 21, 2);
13481 int rm
= extract32(insn
, 16, 5);
13482 int ra
= extract32(insn
, 10, 5);
13483 int rn
= extract32(insn
, 5, 5);
13484 int rd
= extract32(insn
, 0, 5);
13490 feature
= ARM_FEATURE_V8_SHA3
;
13492 case 2: /* SM3SS1 */
13493 feature
= ARM_FEATURE_V8_SM3
;
13496 unallocated_encoding(s
);
13500 if (!arm_dc_feature(s
, feature
)) {
13501 unallocated_encoding(s
);
13505 if (!fp_access_check(s
)) {
13510 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13513 tcg_op1
= tcg_temp_new_i64();
13514 tcg_op2
= tcg_temp_new_i64();
13515 tcg_op3
= tcg_temp_new_i64();
13516 tcg_res
[0] = tcg_temp_new_i64();
13517 tcg_res
[1] = tcg_temp_new_i64();
13519 for (pass
= 0; pass
< 2; pass
++) {
13520 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13521 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13522 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13526 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13529 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13531 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13533 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13534 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13536 tcg_temp_free_i64(tcg_op1
);
13537 tcg_temp_free_i64(tcg_op2
);
13538 tcg_temp_free_i64(tcg_op3
);
13539 tcg_temp_free_i64(tcg_res
[0]);
13540 tcg_temp_free_i64(tcg_res
[1]);
13542 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13544 tcg_op1
= tcg_temp_new_i32();
13545 tcg_op2
= tcg_temp_new_i32();
13546 tcg_op3
= tcg_temp_new_i32();
13547 tcg_res
= tcg_temp_new_i32();
13548 tcg_zero
= tcg_const_i32(0);
13550 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13551 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13552 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13554 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13555 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13556 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13557 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13559 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13560 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13561 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13562 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13564 tcg_temp_free_i32(tcg_op1
);
13565 tcg_temp_free_i32(tcg_op2
);
13566 tcg_temp_free_i32(tcg_op3
);
13567 tcg_temp_free_i32(tcg_res
);
13568 tcg_temp_free_i32(tcg_zero
);
13573 * 31 21 20 16 15 10 9 5 4 0
13574 * +-----------------------+------+--------+------+------+
13575 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13576 * +-----------------------+------+--------+------+------+
13578 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13580 int rm
= extract32(insn
, 16, 5);
13581 int imm6
= extract32(insn
, 10, 6);
13582 int rn
= extract32(insn
, 5, 5);
13583 int rd
= extract32(insn
, 0, 5);
13584 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13587 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SHA3
)) {
13588 unallocated_encoding(s
);
13592 if (!fp_access_check(s
)) {
13596 tcg_op1
= tcg_temp_new_i64();
13597 tcg_op2
= tcg_temp_new_i64();
13598 tcg_res
[0] = tcg_temp_new_i64();
13599 tcg_res
[1] = tcg_temp_new_i64();
13601 for (pass
= 0; pass
< 2; pass
++) {
13602 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13603 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13605 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13606 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13608 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13609 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13611 tcg_temp_free_i64(tcg_op1
);
13612 tcg_temp_free_i64(tcg_op2
);
13613 tcg_temp_free_i64(tcg_res
[0]);
13614 tcg_temp_free_i64(tcg_res
[1]);
13617 /* Crypto three-reg imm2
13618 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13619 * +-----------------------+------+-----+------+--------+------+------+
13620 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13621 * +-----------------------+------+-----+------+--------+------+------+
13623 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13625 int opcode
= extract32(insn
, 10, 2);
13626 int imm2
= extract32(insn
, 12, 2);
13627 int rm
= extract32(insn
, 16, 5);
13628 int rn
= extract32(insn
, 5, 5);
13629 int rd
= extract32(insn
, 0, 5);
13630 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13631 TCGv_i32 tcg_imm2
, tcg_opcode
;
13633 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SM3
)) {
13634 unallocated_encoding(s
);
13638 if (!fp_access_check(s
)) {
13642 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13643 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13644 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13645 tcg_imm2
= tcg_const_i32(imm2
);
13646 tcg_opcode
= tcg_const_i32(opcode
);
13648 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13651 tcg_temp_free_ptr(tcg_rd_ptr
);
13652 tcg_temp_free_ptr(tcg_rn_ptr
);
13653 tcg_temp_free_ptr(tcg_rm_ptr
);
13654 tcg_temp_free_i32(tcg_imm2
);
13655 tcg_temp_free_i32(tcg_opcode
);
13658 /* C3.6 Data processing - SIMD, inc Crypto
13660 * As the decode gets a little complex we are using a table based
13661 * approach for this part of the decode.
13663 static const AArch64DecodeTable data_proc_simd
[] = {
13664 /* pattern , mask , fn */
13665 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13666 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13667 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13668 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13669 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13670 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13671 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13672 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13673 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13674 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13675 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13676 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13677 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13678 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13679 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13680 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13681 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13682 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13683 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13684 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13685 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13686 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13687 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13688 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13689 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13690 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13691 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13692 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13693 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13694 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13695 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13696 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13697 { 0x00000000, 0x00000000, NULL
}
13700 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13702 /* Note that this is called with all non-FP cases from
13703 * table C3-6 so it must UNDEF for entries not specifically
13704 * allocated to instructions in that table.
13706 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13710 unallocated_encoding(s
);
13714 /* C3.6 Data processing - SIMD and floating point */
13715 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13717 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13718 disas_data_proc_fp(s
, insn
);
13720 /* SIMD, including crypto */
13721 disas_data_proc_simd(s
, insn
);
13725 /* C3.1 A64 instruction index by encoding */
13726 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13730 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13734 s
->fp_access_checked
= false;
13736 switch (extract32(insn
, 25, 4)) {
13737 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
13738 unallocated_encoding(s
);
13740 case 0x8: case 0x9: /* Data processing - immediate */
13741 disas_data_proc_imm(s
, insn
);
13743 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13744 disas_b_exc_sys(s
, insn
);
13749 case 0xe: /* Loads and stores */
13750 disas_ldst(s
, insn
);
13753 case 0xd: /* Data processing - register */
13754 disas_data_proc_reg(s
, insn
);
13757 case 0xf: /* Data processing - SIMD and floating point */
13758 disas_data_proc_simd_fp(s
, insn
);
13761 assert(FALSE
); /* all 15 cases should be handled above */
13765 /* if we allocated any temporaries, free them here */
13769 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
13772 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13773 CPUARMState
*env
= cpu
->env_ptr
;
13774 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
13777 dc
->pc
= dc
->base
.pc_first
;
13781 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13782 * there is no secure EL1, so we route exceptions to EL3.
13784 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
13785 !arm_el_is_aa64(env
, 3);
13788 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
13789 dc
->condexec_mask
= 0;
13790 dc
->condexec_cond
= 0;
13791 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
13792 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
13793 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
13794 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
13795 #if !defined(CONFIG_USER_ONLY)
13796 dc
->user
= (dc
->current_el
== 0);
13798 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
13799 dc
->sve_excp_el
= ARM_TBFLAG_SVEEXC_EL(dc
->base
.tb
->flags
);
13800 dc
->sve_len
= (ARM_TBFLAG_ZCR_LEN(dc
->base
.tb
->flags
) + 1) * 16;
13802 dc
->vec_stride
= 0;
13803 dc
->cp_regs
= arm_cpu
->cp_regs
;
13804 dc
->features
= env
->features
;
13806 /* Single step state. The code-generation logic here is:
13808 * generate code with no special handling for single-stepping (except
13809 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13810 * this happens anyway because those changes are all system register or
13812 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13813 * emit code for one insn
13814 * emit code to clear PSTATE.SS
13815 * emit code to generate software step exception for completed step
13816 * end TB (as usual for having generated an exception)
13817 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13818 * emit code to generate a software step exception
13821 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
13822 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
13823 dc
->is_ldex
= false;
13824 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
13826 /* Bound the number of insns to execute to those left on the page. */
13827 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
13829 /* If architectural single step active, limit to 1. */
13830 if (dc
->ss_active
) {
13833 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
13835 init_tmp_a64_array(dc
);
13838 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
13840 tcg_clear_temp_count();
13843 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13845 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13847 tcg_gen_insn_start(dc
->pc
, 0, 0);
13848 dc
->insn_start
= tcg_last_op();
13851 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
13852 const CPUBreakpoint
*bp
)
13854 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13856 if (bp
->flags
& BP_CPU
) {
13857 gen_a64_set_pc_im(dc
->pc
);
13858 gen_helper_check_breakpoints(cpu_env
);
13859 /* End the TB early; it likely won't be executed */
13860 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13862 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
13863 /* The address covered by the breakpoint must be
13864 included in [tb->pc, tb->pc + tb->size) in order
13865 to for it to be properly cleared -- thus we
13866 increment the PC here so that the logic setting
13867 tb->size below does the right thing. */
13869 dc
->base
.is_jmp
= DISAS_NORETURN
;
13875 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13877 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13878 CPUARMState
*env
= cpu
->env_ptr
;
13880 if (dc
->ss_active
&& !dc
->pstate_ss
) {
13881 /* Singlestep state is Active-pending.
13882 * If we're in this state at the start of a TB then either
13883 * a) we just took an exception to an EL which is being debugged
13884 * and this is the first insn in the exception handler
13885 * b) debug exceptions were masked and we just unmasked them
13886 * without changing EL (eg by clearing PSTATE.D)
13887 * In either case we're going to take a swstep exception in the
13888 * "did not step an insn" case, and so the syndrome ISV and EX
13889 * bits should be zero.
13891 assert(dc
->base
.num_insns
== 1);
13892 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
13893 default_exception_el(dc
));
13894 dc
->base
.is_jmp
= DISAS_NORETURN
;
13896 disas_a64_insn(env
, dc
);
13899 dc
->base
.pc_next
= dc
->pc
;
13900 translator_loop_temp_check(&dc
->base
);
13903 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
13905 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13907 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
13908 /* Note that this means single stepping WFI doesn't halt the CPU.
13909 * For conditional branch insns this is harmless unreachable code as
13910 * gen_goto_tb() has already handled emitting the debug exception
13911 * (and thus a tb-jump is not possible when singlestepping).
13913 switch (dc
->base
.is_jmp
) {
13915 gen_a64_set_pc_im(dc
->pc
);
13919 if (dc
->base
.singlestep_enabled
) {
13920 gen_exception_internal(EXCP_DEBUG
);
13922 gen_step_complete_exception(dc
);
13925 case DISAS_NORETURN
:
13929 switch (dc
->base
.is_jmp
) {
13931 case DISAS_TOO_MANY
:
13932 gen_goto_tb(dc
, 1, dc
->pc
);
13936 gen_a64_set_pc_im(dc
->pc
);
13939 tcg_gen_exit_tb(0);
13942 tcg_gen_lookup_and_goto_ptr();
13944 case DISAS_NORETURN
:
13948 gen_a64_set_pc_im(dc
->pc
);
13949 gen_helper_wfe(cpu_env
);
13952 gen_a64_set_pc_im(dc
->pc
);
13953 gen_helper_yield(cpu_env
);
13957 /* This is a special case because we don't want to just halt the CPU
13958 * if trying to debug across a WFI.
13960 TCGv_i32 tmp
= tcg_const_i32(4);
13962 gen_a64_set_pc_im(dc
->pc
);
13963 gen_helper_wfi(cpu_env
, tmp
);
13964 tcg_temp_free_i32(tmp
);
13965 /* The helper doesn't necessarily throw an exception, but we
13966 * must go back to the main loop to check for interrupts anyway.
13968 tcg_gen_exit_tb(0);
13974 /* Functions above can change dc->pc, so re-align db->pc_next */
13975 dc
->base
.pc_next
= dc
->pc
;
13978 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
13981 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13983 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
13984 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
13987 const TranslatorOps aarch64_translator_ops
= {
13988 .init_disas_context
= aarch64_tr_init_disas_context
,
13989 .tb_start
= aarch64_tr_tb_start
,
13990 .insn_start
= aarch64_tr_insn_start
,
13991 .breakpoint_check
= aarch64_tr_breakpoint_check
,
13992 .translate_insn
= aarch64_tr_translate_insn
,
13993 .tb_stop
= aarch64_tr_tb_stop
,
13994 .disas_log
= aarch64_tr_disas_log
,