4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/pcie.h"
25 #include "hw/pci/msix.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pcie_regs.h"
29 #include "hw/pci/pcie_port.h"
30 #include "qemu/range.h"
34 # define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
37 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
43 /***************************************************************************
44 * pci express capability helper functions
48 pcie_cap_v1_fill(PCIDevice
*dev
, uint8_t port
, uint8_t type
, uint8_t version
)
50 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
51 uint8_t *cmask
= dev
->cmask
+ dev
->exp
.exp_cap
;
53 /* capability register
54 interrupt message number defaults to 0 */
55 pci_set_word(exp_cap
+ PCI_EXP_FLAGS
,
56 ((type
<< PCI_EXP_FLAGS_TYPE_SHIFT
) & PCI_EXP_FLAGS_TYPE
) |
59 /* device capability register
61 * roll based error reporting bit must be set by all
62 * Functions conforming to the ECN, PCI Express Base
63 * Specification, Revision 1.1., or subsequent PCI Express Base
64 * Specification revisions.
66 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP
, PCI_EXP_DEVCAP_RBER
);
68 pci_set_long(exp_cap
+ PCI_EXP_LNKCAP
,
69 (port
<< PCI_EXP_LNKCAP_PN_SHIFT
) |
70 PCI_EXP_LNKCAP_ASPMS_0S
|
71 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1
) |
72 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT
));
74 pci_set_word(exp_cap
+ PCI_EXP_LNKSTA
,
75 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1
) |
76 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT
));
78 if (dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
79 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
80 PCI_EXP_LNKSTA_DLLLA
);
83 /* We changed link status bits over time, and changing them across
84 * migrations is generally fine as hardware changes them too.
85 * Let's not bother checking.
87 pci_set_word(cmask
+ PCI_EXP_LNKSTA
, 0);
90 static void pcie_cap_fill_slot_lnk(PCIDevice
*dev
)
92 PCIESlot
*s
= (PCIESlot
*)object_dynamic_cast(OBJECT(dev
), TYPE_PCIE_SLOT
);
93 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
95 /* Skip anything that isn't a PCIESlot */
100 /* Clear and fill LNKCAP from what was configured above */
101 pci_long_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKCAP
,
102 PCI_EXP_LNKCAP_MLW
| PCI_EXP_LNKCAP_SLS
);
103 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP
,
104 QEMU_PCI_EXP_LNKCAP_MLW(s
->width
) |
105 QEMU_PCI_EXP_LNKCAP_MLS(s
->speed
));
108 * Link bandwidth notification is required for all root ports and
109 * downstream ports supporting links wider than x1 or multiple link
112 if (s
->width
> QEMU_PCI_EXP_LNK_X1
||
113 s
->speed
> QEMU_PCI_EXP_LNK_2_5GT
) {
114 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP
,
115 PCI_EXP_LNKCAP_LBNC
);
118 if (s
->speed
> QEMU_PCI_EXP_LNK_2_5GT
) {
120 * Hot-plug capable downstream ports and downstream ports supporting
121 * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC
122 * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which
123 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also
124 * technically implement this, but it's not done here for compatibility.
126 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP
,
127 PCI_EXP_LNKCAP_DLLLARC
);
128 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
129 PCI_EXP_LNKSTA_DLLLA
);
132 * Target Link Speed defaults to the highest link speed supported by
133 * the component. 2.5GT/s devices are permitted to hardwire to zero.
135 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKCTL2
,
136 PCI_EXP_LNKCTL2_TLS
);
137 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCTL2
,
138 QEMU_PCI_EXP_LNKCAP_MLS(s
->speed
) &
139 PCI_EXP_LNKCTL2_TLS
);
143 * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is
144 * actually a reference to the highest bit supported in this register.
145 * We assume the device supports all link speeds.
147 if (s
->speed
> QEMU_PCI_EXP_LNK_5GT
) {
148 pci_long_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKCAP2
, ~0U);
149 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP2
,
150 PCI_EXP_LNKCAP2_SLS_2_5GB
|
151 PCI_EXP_LNKCAP2_SLS_5_0GB
|
152 PCI_EXP_LNKCAP2_SLS_8_0GB
);
153 if (s
->speed
> QEMU_PCI_EXP_LNK_8GT
) {
154 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP2
,
155 PCI_EXP_LNKCAP2_SLS_16_0GB
);
160 int pcie_cap_init(PCIDevice
*dev
, uint8_t offset
,
161 uint8_t type
, uint8_t port
,
164 /* PCIe cap v2 init */
168 assert(pci_is_express(dev
));
170 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
171 PCI_EXP_VER2_SIZEOF
, errp
);
175 dev
->exp
.exp_cap
= pos
;
176 exp_cap
= dev
->config
+ pos
;
178 /* Filling values common with v1 */
179 pcie_cap_v1_fill(dev
, port
, type
, PCI_EXP_FLAGS_VER2
);
181 /* Fill link speed and width options */
182 pcie_cap_fill_slot_lnk(dev
);
184 /* Filling v2 specific values */
185 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP2
,
186 PCI_EXP_DEVCAP2_EFF
| PCI_EXP_DEVCAP2_EETLPP
);
188 pci_set_word(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
, PCI_EXP_DEVCTL2_EETLPPB
);
190 if (dev
->cap_present
& QEMU_PCIE_EXTCAP_INIT
) {
191 /* read-only to behave like a 'NULL' Extended Capability Header */
192 pci_set_long(dev
->wmask
+ PCI_CONFIG_SPACE_SIZE
, 0);
198 int pcie_cap_v1_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
,
201 /* PCIe cap v1 init */
203 Error
*local_err
= NULL
;
205 assert(pci_is_express(dev
));
207 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
208 PCI_EXP_VER1_SIZEOF
, &local_err
);
210 error_report_err(local_err
);
213 dev
->exp
.exp_cap
= pos
;
215 pcie_cap_v1_fill(dev
, port
, type
, PCI_EXP_FLAGS_VER1
);
221 pcie_endpoint_cap_common_init(PCIDevice
*dev
, uint8_t offset
, uint8_t cap_size
)
223 uint8_t type
= PCI_EXP_TYPE_ENDPOINT
;
224 Error
*local_err
= NULL
;
228 * Windows guests will report Code 10, device cannot start, if
229 * a regular Endpoint type is exposed on a root complex. These
230 * should instead be Root Complex Integrated Endpoints.
232 if (pci_bus_is_express(pci_get_bus(dev
))
233 && pci_bus_is_root(pci_get_bus(dev
))) {
234 type
= PCI_EXP_TYPE_RC_END
;
237 if (cap_size
== PCI_EXP_VER1_SIZEOF
) {
238 return pcie_cap_v1_init(dev
, offset
, type
, 0);
240 ret
= pcie_cap_init(dev
, offset
, type
, 0, &local_err
);
243 error_report_err(local_err
);
250 int pcie_endpoint_cap_init(PCIDevice
*dev
, uint8_t offset
)
252 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER2_SIZEOF
);
255 int pcie_endpoint_cap_v1_init(PCIDevice
*dev
, uint8_t offset
)
257 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER1_SIZEOF
);
260 void pcie_cap_exit(PCIDevice
*dev
)
262 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER2_SIZEOF
);
265 void pcie_cap_v1_exit(PCIDevice
*dev
)
267 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER1_SIZEOF
);
270 uint8_t pcie_cap_get_type(const PCIDevice
*dev
)
272 uint32_t pos
= dev
->exp
.exp_cap
;
274 return (pci_get_word(dev
->config
+ pos
+ PCI_EXP_FLAGS
) &
275 PCI_EXP_FLAGS_TYPE
) >> PCI_EXP_FLAGS_TYPE_SHIFT
;
279 /* pci express interrupt message number */
280 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
281 void pcie_cap_flags_set_vector(PCIDevice
*dev
, uint8_t vector
)
283 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
285 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_FLAGS
, PCI_EXP_FLAGS_IRQ
);
286 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_FLAGS
,
287 vector
<< PCI_EXP_FLAGS_IRQ_SHIFT
);
290 uint8_t pcie_cap_flags_get_vector(PCIDevice
*dev
)
292 return (pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_FLAGS
) &
293 PCI_EXP_FLAGS_IRQ
) >> PCI_EXP_FLAGS_IRQ_SHIFT
;
296 void pcie_cap_deverr_init(PCIDevice
*dev
)
298 uint32_t pos
= dev
->exp
.exp_cap
;
299 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP
,
300 PCI_EXP_DEVCAP_RBER
);
301 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
,
302 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
303 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
304 pci_long_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_DEVSTA
,
305 PCI_EXP_DEVSTA_CED
| PCI_EXP_DEVSTA_NFED
|
306 PCI_EXP_DEVSTA_FED
| PCI_EXP_DEVSTA_URD
);
309 void pcie_cap_deverr_reset(PCIDevice
*dev
)
311 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
312 pci_long_test_and_clear_mask(devctl
,
313 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
314 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
317 void pcie_cap_lnkctl_init(PCIDevice
*dev
)
319 uint32_t pos
= dev
->exp
.exp_cap
;
320 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_LNKCTL
,
321 PCI_EXP_LNKCTL_CCC
| PCI_EXP_LNKCTL_ES
);
324 void pcie_cap_lnkctl_reset(PCIDevice
*dev
)
326 uint8_t *lnkctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_LNKCTL
;
327 pci_long_test_and_clear_mask(lnkctl
,
328 PCI_EXP_LNKCTL_CCC
| PCI_EXP_LNKCTL_ES
);
331 static void hotplug_event_update_event_status(PCIDevice
*dev
)
333 uint32_t pos
= dev
->exp
.exp_cap
;
334 uint8_t *exp_cap
= dev
->config
+ pos
;
335 uint16_t sltctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
336 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
338 dev
->exp
.hpev_notified
= (sltctl
& PCI_EXP_SLTCTL_HPIE
) &&
339 (sltsta
& sltctl
& PCI_EXP_HP_EV_SUPPORTED
);
342 static void hotplug_event_notify(PCIDevice
*dev
)
344 bool prev
= dev
->exp
.hpev_notified
;
346 hotplug_event_update_event_status(dev
);
348 if (prev
== dev
->exp
.hpev_notified
) {
352 /* Note: the logic above does not take into account whether interrupts
353 * are masked. The result is that interrupt will be sent when it is
354 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
355 * The Port may optionally send an MSI when there are hot-plug events that
356 * occur while interrupt generation is disabled, and interrupt generation is
357 * subsequently enabled. */
358 if (msix_enabled(dev
)) {
359 msix_notify(dev
, pcie_cap_flags_get_vector(dev
));
360 } else if (msi_enabled(dev
)) {
361 msi_notify(dev
, pcie_cap_flags_get_vector(dev
));
363 pci_set_irq(dev
, dev
->exp
.hpev_notified
);
367 static void hotplug_event_clear(PCIDevice
*dev
)
369 hotplug_event_update_event_status(dev
);
370 if (!msix_enabled(dev
) && !msi_enabled(dev
) && !dev
->exp
.hpev_notified
) {
371 pci_irq_deassert(dev
);
376 * A PCI Express Hot-Plug Event has occurred, so update slot status register
377 * and notify OS of the event if necessary.
379 * 6.7.3 PCI Express Hot-Plug Events
380 * 6.7.3.4 Software Notification of Hot-Plug Events
382 static void pcie_cap_slot_event(PCIDevice
*dev
, PCIExpressHotPlugEvent event
)
384 /* Minor optimization: if nothing changed - no event is needed. */
385 if (pci_word_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+
386 PCI_EXP_SLTSTA
, event
) == event
) {
389 hotplug_event_notify(dev
);
392 static void pcie_cap_slot_plug_common(PCIDevice
*hotplug_dev
, DeviceState
*dev
,
395 uint8_t *exp_cap
= hotplug_dev
->config
+ hotplug_dev
->exp
.exp_cap
;
396 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
398 PCIE_DEV_PRINTF(PCI_DEVICE(dev
), "hotplug state: 0x%x\n", sltsta
);
399 if (sltsta
& PCI_EXP_SLTSTA_EIS
) {
400 /* the slot is electromechanically locked.
401 * This error is propagated up to qdev and then to HMP/QMP.
403 error_setg_errno(errp
, EBUSY
, "slot is electromechanically locked");
407 void pcie_cap_slot_pre_plug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
410 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev
), dev
, errp
);
413 void pcie_cap_slot_plug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
416 PCIDevice
*hotplug_pdev
= PCI_DEVICE(hotplug_dev
);
417 uint8_t *exp_cap
= hotplug_pdev
->config
+ hotplug_pdev
->exp
.exp_cap
;
418 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
420 /* Don't send event when device is enabled during qemu machine creation:
421 * it is present on boot, no hotplug event is necessary. We do send an
422 * event when the device is disabled later. */
423 if (!dev
->hotplugged
) {
424 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
426 if (pci_dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
427 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
428 PCI_EXP_LNKSTA_DLLLA
);
433 /* To enable multifunction hot-plug, we just ensure the function
434 * 0 added last. When function 0 is added, we set the sltsta and
435 * inform OS via event notification.
437 if (pci_get_function_0(pci_dev
)) {
438 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
440 if (pci_dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
441 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
442 PCI_EXP_LNKSTA_DLLLA
);
444 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev
),
445 PCI_EXP_HP_EV_PDC
| PCI_EXP_HP_EV_ABP
);
449 void pcie_cap_slot_unplug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
452 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
455 static void pcie_unplug_device(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
457 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(DEVICE(dev
));
459 if (dev
->partially_hotplugged
) {
460 dev
->qdev
.pending_deleted_event
= false;
463 hotplug_handler_unplug(hotplug_ctrl
, DEVICE(dev
), &error_abort
);
464 object_unparent(OBJECT(dev
));
467 void pcie_cap_slot_unplug_request_cb(HotplugHandler
*hotplug_dev
,
468 DeviceState
*dev
, Error
**errp
)
470 Error
*local_err
= NULL
;
471 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
472 PCIBus
*bus
= pci_get_bus(pci_dev
);
474 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev
), dev
, &local_err
);
476 error_propagate(errp
, local_err
);
480 dev
->pending_deleted_event
= true;
482 /* In case user cancel the operation of multi-function hot-add,
483 * remove the function that is unexposed to guest individually,
484 * without interaction with guest.
486 if (pci_dev
->devfn
&&
488 pcie_unplug_device(bus
, pci_dev
, NULL
);
493 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev
));
496 /* pci express slot for pci express root/downstream port
497 PCI express capability slot registers */
498 void pcie_cap_slot_init(PCIDevice
*dev
, PCIESlot
*s
)
500 uint32_t pos
= dev
->exp
.exp_cap
;
502 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_FLAGS
,
505 pci_long_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
506 ~PCI_EXP_SLTCAP_PSN
);
507 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
508 (s
->slot
<< PCI_EXP_SLTCAP_PSN_SHIFT
) |
514 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
519 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
520 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
522 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
524 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
528 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
531 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
532 PCI_EXP_SLTCTL_PIC_OFF
|
533 PCI_EXP_SLTCTL_AIC_OFF
);
534 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
537 PCI_EXP_SLTCTL_HPIE
|
538 PCI_EXP_SLTCTL_CCIE
|
539 PCI_EXP_SLTCTL_PDCE
|
540 PCI_EXP_SLTCTL_ABPE
);
541 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
542 * make the bit writable here in order to detect 1b is written.
543 * pcie_cap_slot_write_config() test-and-clear the bit, so
544 * this bit always returns 0 to the guest.
546 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
549 pci_word_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_SLTSTA
,
550 PCI_EXP_HP_EV_SUPPORTED
);
552 dev
->exp
.hpev_notified
= false;
554 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))),
558 void pcie_cap_slot_reset(PCIDevice
*dev
)
560 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
561 uint8_t port_type
= pcie_cap_get_type(dev
);
563 assert(port_type
== PCI_EXP_TYPE_DOWNSTREAM
||
564 port_type
== PCI_EXP_TYPE_ROOT_PORT
);
566 PCIE_DEV_PRINTF(dev
, "reset\n");
568 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
572 PCI_EXP_SLTCTL_HPIE
|
573 PCI_EXP_SLTCTL_CCIE
|
574 PCI_EXP_SLTCTL_PDCE
|
575 PCI_EXP_SLTCTL_ABPE
);
576 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
577 PCI_EXP_SLTCTL_AIC_OFF
);
579 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
580 /* Downstream ports enforce device number 0. */
581 bool populated
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))->devices
[0];
585 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
588 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
592 pic
= populated
? PCI_EXP_SLTCTL_PIC_ON
: PCI_EXP_SLTCTL_PIC_OFF
;
593 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
, pic
);
596 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
597 PCI_EXP_SLTSTA_EIS
|/* on reset,
598 the lock is released */
603 hotplug_event_update_event_status(dev
);
606 void pcie_cap_slot_get(PCIDevice
*dev
, uint16_t *slt_ctl
, uint16_t *slt_sta
)
608 uint32_t pos
= dev
->exp
.exp_cap
;
609 uint8_t *exp_cap
= dev
->config
+ pos
;
610 *slt_ctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
611 *slt_sta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
614 void pcie_cap_slot_write_config(PCIDevice
*dev
,
615 uint16_t old_slt_ctl
, uint16_t old_slt_sta
,
616 uint32_t addr
, uint32_t val
, int len
)
618 uint32_t pos
= dev
->exp
.exp_cap
;
619 uint8_t *exp_cap
= dev
->config
+ pos
;
620 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
622 if (ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTSTA
, 2)) {
624 * Guests tend to clears all bits during init.
625 * If they clear bits that weren't set this is racy and will lose events:
626 * not a big problem for manual button presses, but a problem for us.
627 * As a work-around, detect this and revert status to what it was
630 * Note: in theory this can be detected as a duplicate button press
631 * which cancels the previous press. Does not seem to happen in
632 * practice as guests seem to only have this bug during init.
634 #define PCIE_SLOT_EVENTS (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | \
635 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | \
638 if (val
& ~old_slt_sta
& PCIE_SLOT_EVENTS
) {
639 sltsta
= (sltsta
& ~PCIE_SLOT_EVENTS
) | (old_slt_sta
& PCIE_SLOT_EVENTS
);
640 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
642 hotplug_event_clear(dev
);
645 if (!ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTCTL
, 2)) {
649 if (pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
650 PCI_EXP_SLTCTL_EIC
)) {
651 sltsta
^= PCI_EXP_SLTSTA_EIS
; /* toggle PCI_EXP_SLTSTA_EIS bit */
652 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
653 PCIE_DEV_PRINTF(dev
, "PCI_EXP_SLTCTL_EIC: "
654 "sltsta -> 0x%02"PRIx16
"\n",
659 * If the slot is populated, power indicator is off and power
660 * controller is off, it is safe to detach the devices.
662 * Note: don't detach if condition was already true:
663 * this is a work around for guests that overwrite
664 * control of powered off slots before powering them on.
666 if ((sltsta
& PCI_EXP_SLTSTA_PDS
) && (val
& PCI_EXP_SLTCTL_PCC
) &&
667 (val
& PCI_EXP_SLTCTL_PIC_OFF
) == PCI_EXP_SLTCTL_PIC_OFF
&&
668 (!(old_slt_ctl
& PCI_EXP_SLTCTL_PCC
) ||
669 (old_slt_ctl
& PCI_EXP_SLTCTL_PIC_OFF
) != PCI_EXP_SLTCTL_PIC_OFF
)) {
670 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
671 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
672 pcie_unplug_device
, NULL
);
674 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
676 if (dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
677 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKSTA
,
678 PCI_EXP_LNKSTA_DLLLA
);
680 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
684 hotplug_event_notify(dev
);
687 * 6.7.3.2 Command Completed Events
689 * Software issues a command to a hot-plug capable Downstream Port by
690 * issuing a write transaction that targets any portion of the Port’s Slot
691 * Control register. A single write to the Slot Control register is
692 * considered to be a single command, even if the write affects more than
693 * one field in the Slot Control register. In response to this transaction,
694 * the Port must carry out the requested actions and then set the
695 * associated status field for the command completed event. */
697 /* Real hardware might take a while to complete requested command because
698 * physical movement would be involved like locking the electromechanical
699 * lock. However in our case, command is completed instantaneously above,
700 * so send a command completion event right now.
702 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_CCI
);
705 int pcie_cap_slot_post_load(void *opaque
, int version_id
)
707 PCIDevice
*dev
= opaque
;
708 hotplug_event_update_event_status(dev
);
712 void pcie_cap_slot_push_attention_button(PCIDevice
*dev
)
714 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_ABP
);
717 /* root control/capabilities/status. PME isn't emulated for now */
718 void pcie_cap_root_init(PCIDevice
*dev
)
720 pci_set_word(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
,
721 PCI_EXP_RTCTL_SECEE
| PCI_EXP_RTCTL_SENFEE
|
722 PCI_EXP_RTCTL_SEFEE
);
725 void pcie_cap_root_reset(PCIDevice
*dev
)
727 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
, 0);
730 /* function level reset(FLR) */
731 void pcie_cap_flr_init(PCIDevice
*dev
)
733 pci_long_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCAP
,
736 /* Although reading BCR_FLR returns always 0,
737 * the bit is made writable here in order to detect the 1b is written
738 * pcie_cap_flr_write_config() test-and-clear the bit, so
739 * this bit always returns 0 to the guest.
741 pci_word_test_and_set_mask(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
,
742 PCI_EXP_DEVCTL_BCR_FLR
);
745 void pcie_cap_flr_write_config(PCIDevice
*dev
,
746 uint32_t addr
, uint32_t val
, int len
)
748 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
749 if (pci_get_word(devctl
) & PCI_EXP_DEVCTL_BCR_FLR
) {
750 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
751 so the handler can detect FLR by looking at this bit. */
752 pci_device_reset(dev
);
753 pci_word_test_and_clear_mask(devctl
, PCI_EXP_DEVCTL_BCR_FLR
);
757 /* Alternative Routing-ID Interpretation (ARI)
758 * forwarding support for root and downstream ports
760 void pcie_cap_arifwd_init(PCIDevice
*dev
)
762 uint32_t pos
= dev
->exp
.exp_cap
;
763 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP2
,
764 PCI_EXP_DEVCAP2_ARI
);
765 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
,
766 PCI_EXP_DEVCTL2_ARI
);
769 void pcie_cap_arifwd_reset(PCIDevice
*dev
)
771 uint8_t *devctl2
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
;
772 pci_long_test_and_clear_mask(devctl2
, PCI_EXP_DEVCTL2_ARI
);
775 bool pcie_cap_is_arifwd_enabled(const PCIDevice
*dev
)
777 if (!pci_is_express(dev
)) {
780 if (!dev
->exp
.exp_cap
) {
784 return pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
788 /**************************************************************************
789 * pci express extended capability list management functions
790 * uint16_t ext_cap_id (16 bit)
791 * uint8_t cap_ver (4 bit)
792 * uint16_t cap_offset (12 bit)
793 * uint16_t ext_cap_size
796 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */
797 static uint16_t pcie_find_capability_list(PCIDevice
*dev
, uint32_t cap_id
,
802 uint32_t header
= pci_get_long(dev
->config
+ PCI_CONFIG_SPACE_SIZE
);
805 /* no extended capability */
809 for (next
= PCI_CONFIG_SPACE_SIZE
; next
;
810 prev
= next
, next
= PCI_EXT_CAP_NEXT(header
)) {
812 assert(next
>= PCI_CONFIG_SPACE_SIZE
);
813 assert(next
<= PCIE_CONFIG_SPACE_SIZE
- 8);
815 header
= pci_get_long(dev
->config
+ next
);
816 if (PCI_EXT_CAP_ID(header
) == cap_id
) {
828 uint16_t pcie_find_capability(PCIDevice
*dev
, uint16_t cap_id
)
830 return pcie_find_capability_list(dev
, cap_id
, NULL
);
833 static void pcie_ext_cap_set_next(PCIDevice
*dev
, uint16_t pos
, uint16_t next
)
835 uint32_t header
= pci_get_long(dev
->config
+ pos
);
836 assert(!(next
& (PCI_EXT_CAP_ALIGN
- 1)));
837 header
= (header
& ~PCI_EXT_CAP_NEXT_MASK
) |
838 ((next
<< PCI_EXT_CAP_NEXT_SHIFT
) & PCI_EXT_CAP_NEXT_MASK
);
839 pci_set_long(dev
->config
+ pos
, header
);
843 * Caller must supply valid (offset, size) such that the range wouldn't
844 * overlap with other capability or other registers.
845 * This function doesn't check it.
847 void pcie_add_capability(PCIDevice
*dev
,
848 uint16_t cap_id
, uint8_t cap_ver
,
849 uint16_t offset
, uint16_t size
)
851 assert(offset
>= PCI_CONFIG_SPACE_SIZE
);
852 assert(offset
< offset
+ size
);
853 assert(offset
+ size
<= PCIE_CONFIG_SPACE_SIZE
);
855 assert(pci_is_express(dev
));
857 if (offset
!= PCI_CONFIG_SPACE_SIZE
) {
861 * 0xffffffff is not a valid cap id (it's a 16 bit field). use
862 * internally to find the last capability in the linked list.
864 pcie_find_capability_list(dev
, 0xffffffff, &prev
);
865 assert(prev
>= PCI_CONFIG_SPACE_SIZE
);
866 pcie_ext_cap_set_next(dev
, prev
, offset
);
868 pci_set_long(dev
->config
+ offset
, PCI_EXT_CAP(cap_id
, cap_ver
, 0));
870 /* Make capability read-only by default */
871 memset(dev
->wmask
+ offset
, 0, size
);
872 memset(dev
->w1cmask
+ offset
, 0, size
);
873 /* Check capability by default */
874 memset(dev
->cmask
+ offset
, 0xFF, size
);
878 * Sync the PCIe Link Status negotiated speed and width of a bridge with the
879 * downstream device. If downstream device is not present, re-write with the
880 * Link Capability fields. If downstream device reports invalid width or
881 * speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such
882 * values interfere with PCIe native hotplug detecting new devices). Limit
883 * width and speed to bridge capabilities for compatibility. Use config_read
884 * to access the downstream device since it could be an assigned device with
885 * volatile link information.
887 void pcie_sync_bridge_lnk(PCIDevice
*bridge_dev
)
889 PCIBridge
*br
= PCI_BRIDGE(bridge_dev
);
890 PCIBus
*bus
= pci_bridge_get_sec_bus(br
);
891 PCIDevice
*target
= bus
->devices
[0];
892 uint8_t *exp_cap
= bridge_dev
->config
+ bridge_dev
->exp
.exp_cap
;
893 uint16_t lnksta
, lnkcap
= pci_get_word(exp_cap
+ PCI_EXP_LNKCAP
);
895 if (!target
|| !target
->exp
.exp_cap
) {
898 lnksta
= target
->config_read(target
,
899 target
->exp
.exp_cap
+ PCI_EXP_LNKSTA
,
902 if ((lnksta
& PCI_EXP_LNKSTA_NLW
) > (lnkcap
& PCI_EXP_LNKCAP_MLW
)) {
903 lnksta
&= ~PCI_EXP_LNKSTA_NLW
;
904 lnksta
|= lnkcap
& PCI_EXP_LNKCAP_MLW
;
905 } else if (!(lnksta
& PCI_EXP_LNKSTA_NLW
)) {
906 lnksta
|= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1
);
909 if ((lnksta
& PCI_EXP_LNKSTA_CLS
) > (lnkcap
& PCI_EXP_LNKCAP_SLS
)) {
910 lnksta
&= ~PCI_EXP_LNKSTA_CLS
;
911 lnksta
|= lnkcap
& PCI_EXP_LNKCAP_SLS
;
912 } else if (!(lnksta
& PCI_EXP_LNKSTA_CLS
)) {
913 lnksta
|= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT
);
917 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKSTA
,
918 PCI_EXP_LNKSTA_CLS
| PCI_EXP_LNKSTA_NLW
);
919 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
, lnksta
&
920 (PCI_EXP_LNKSTA_CLS
| PCI_EXP_LNKSTA_NLW
));
923 /**************************************************************************
924 * pci express extended capability helper functions
928 void pcie_ari_init(PCIDevice
*dev
, uint16_t offset
, uint16_t nextfn
)
930 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ARI
, PCI_ARI_VER
,
931 offset
, PCI_ARI_SIZEOF
);
932 pci_set_long(dev
->config
+ offset
+ PCI_ARI_CAP
, (nextfn
& 0xff) << 8);
935 void pcie_dev_ser_num_init(PCIDevice
*dev
, uint16_t offset
, uint64_t ser_num
)
937 static const int pci_dsn_ver
= 1;
938 static const int pci_dsn_cap
= 4;
940 pcie_add_capability(dev
, PCI_EXT_CAP_ID_DSN
, pci_dsn_ver
, offset
,
941 PCI_EXT_CAP_DSN_SIZEOF
);
942 pci_set_quad(dev
->config
+ offset
+ pci_dsn_cap
, ser_num
);
945 void pcie_ats_init(PCIDevice
*dev
, uint16_t offset
)
947 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ATS
, 0x1,
948 offset
, PCI_EXT_CAP_ATS_SIZEOF
);
950 dev
->exp
.ats_cap
= offset
;
952 /* Invalidate Queue Depth 0, Page Aligned Request 0 */
953 pci_set_word(dev
->config
+ offset
+ PCI_ATS_CAP
, 0);
954 /* STU 0, Disabled by default */
955 pci_set_word(dev
->config
+ offset
+ PCI_ATS_CTRL
, 0);
957 pci_set_word(dev
->wmask
+ dev
->exp
.ats_cap
+ PCI_ATS_CTRL
, 0x800f);
960 /* ACS (Access Control Services) */
961 void pcie_acs_init(PCIDevice
*dev
, uint16_t offset
)
963 bool is_downstream
= pci_is_express_downstream_port(dev
);
964 uint16_t cap_bits
= 0;
966 /* For endpoints, only multifunction devs may have an ACS capability: */
967 assert(is_downstream
||
968 (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) ||
969 PCI_FUNC(dev
->devfn
));
971 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ACS
, PCI_ACS_VER
, offset
,
973 dev
->exp
.acs_cap
= offset
;
977 * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with
978 * caveats on the latter four that we ignore for simplicity).
979 * Endpoints may also implement a subset of ACS capabilities,
980 * but these are optional if the endpoint does not support
981 * peer-to-peer between functions and thus omitted here.
983 cap_bits
= PCI_ACS_SV
| PCI_ACS_TB
| PCI_ACS_RR
|
984 PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_DT
;
987 pci_set_word(dev
->config
+ offset
+ PCI_ACS_CAP
, cap_bits
);
988 pci_set_word(dev
->wmask
+ offset
+ PCI_ACS_CTRL
, cap_bits
);
991 void pcie_acs_reset(PCIDevice
*dev
)
993 if (dev
->exp
.acs_cap
) {
994 pci_set_word(dev
->config
+ dev
->exp
.acs_cap
+ PCI_ACS_CTRL
, 0);