include/hw/arm/xlnx-zynqmp.h

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #ifndef XLNX_ZYNQMP_H
  19
  20 #include "qemu-common.h"
  21 #include "hw/arm/arm.h"
  22 #include "hw/intc/arm_gic.h"
  23 #include "hw/net/cadence_gem.h"
  24 #include "hw/char/cadence_uart.h"
  25 #include "hw/ide/pci.h"
  26 #include "hw/ide/ahci.h"
  27
  28 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
  29 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
  30                                        TYPE_XLNX_ZYNQMP)
  31
  32 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
  33 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
  34 #define XLNX_ZYNQMP_NUM_GEMS 4
  35 #define XLNX_ZYNQMP_NUM_UARTS 2
  36
  37 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
  38 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
  39 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
  40
  41 #define XLNX_ZYNQMP_GIC_REGIONS 2
  42
  43 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
  44  * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
  45  * aligned address in the 64k region. To implement each GIC region needs a
  46  * number of memory region aliases.
  47  */
  48
  49 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
  50 #define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
  51
  52 typedef struct XlnxZynqMPState {
  53     /*< private >*/
  54     DeviceState parent_obj;
  55
  56     /*< public >*/
  57     ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
  58     ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
  59     GICState gic;
  60     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
  61     MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
  62
  63     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
  64     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
  65     SysbusAHCIState sata;
  66
  67     char *boot_cpu;
  68     ARMCPU *boot_cpu_ptr;
  69 }  XlnxZynqMPState;
  70
  71 #define XLNX_ZYNQMP_H
  72 #endif