include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  66
  67 #include "qemu/log.h"
  68
  69 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  70 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  71                           target_ulong *data);
  72
  73 void cpu_gen_init(void);
  74 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  75 void page_size_init(void);
  76
  77 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  78 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  79 TranslationBlock *tb_gen_code(CPUState *cpu,
  80                               target_ulong pc, target_ulong cs_base, int flags,
  81                               int cflags);
  82 void cpu_exec_init(CPUState *cpu, Error **errp);
  83 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  84 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
  85
  86 #if !defined(CONFIG_USER_ONLY)
  87 bool qemu_in_vcpu_thread(void);
  88 void cpu_reload_memory_map(CPUState *cpu);
  89 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
  90 /* cputlb.c */
  91 /**
  92  * tlb_flush_page:
  93  * @cpu: CPU whose TLB should be flushed
  94  * @addr: virtual address of page to be flushed
  95  *
  96  * Flush one page from the TLB of the specified CPU, for all
  97  * MMU indexes.
  98  */
  99 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 100 /**
 101  * tlb_flush:
 102  * @cpu: CPU whose TLB should be flushed
 103  * @flush_global: ignored
 104  *
 105  * Flush the entire TLB for the specified CPU.
 106  * The flush_global flag is in theory an indicator of whether the whole
 107  * TLB should be flushed, or only those entries not marked global.
 108  * In practice QEMU does not implement any global/not global flag for
 109  * TLB entries, and the argument is ignored.
 110  */
 111 void tlb_flush(CPUState *cpu, int flush_global);
 112 /**
 113  * tlb_flush_page_by_mmuidx:
 114  * @cpu: CPU whose TLB should be flushed
 115  * @addr: virtual address of page to be flushed
 116  * @...: list of MMU indexes to flush, terminated by a negative value
 117  *
 118  * Flush one page from the TLB of the specified CPU, for the specified
 119  * MMU indexes.
 120  */
 121 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...);
 122 /**
 123  * tlb_flush_by_mmuidx:
 124  * @cpu: CPU whose TLB should be flushed
 125  * @...: list of MMU indexes to flush, terminated by a negative value
 126  *
 127  * Flush all entries from the TLB of the specified CPU, for the specified
 128  * MMU indexes.
 129  */
 130 void tlb_flush_by_mmuidx(CPUState *cpu, ...);
 131 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 132                   hwaddr paddr, int prot,
 133                   int mmu_idx, target_ulong size);
 134 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 135                              hwaddr paddr, MemTxAttrs attrs,
 136                              int prot, int mmu_idx, target_ulong size);
 137 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 138 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
 139                  uintptr_t retaddr);
 140 #else
 141 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 142 {
 143 }
 144
 145 static inline void tlb_flush(CPUState *cpu, int flush_global)
 146 {
 147 }
 148
 149 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 150                                             target_ulong addr, ...)
 151 {
 152 }
 153
 154 static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...)
 155 {
 156 }
 157 #endif
 158
 159 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 160
 161 #define CODE_GEN_PHYS_HASH_BITS     15
 162 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 163
 164 /* Estimated block size for TB allocation.  */
 165 /* ??? The following is based on a 2015 survey of x86_64 host output.
 166    Better would seem to be some sort of dynamically sized TB array,
 167    adapting to the block sizes actually being produced.  */
 168 #if defined(CONFIG_SOFTMMU)
 169 #define CODE_GEN_AVG_BLOCK_SIZE 400
 170 #else
 171 #define CODE_GEN_AVG_BLOCK_SIZE 150
 172 #endif
 173
 174 #if defined(__arm__) || defined(_ARCH_PPC) \
 175     || defined(__x86_64__) || defined(__i386__) \
 176     || defined(__sparc__) || defined(__aarch64__) \
 177     || defined(__s390x__) || defined(__mips__) \
 178     || defined(CONFIG_TCG_INTERPRETER)
 179 #define USE_DIRECT_JUMP
 180 #endif
 181
 182 struct TranslationBlock {
 183     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 184     target_ulong cs_base; /* CS base for this block */
 185     uint64_t flags; /* flags defining in which context the code was generated */
 186     uint16_t size;      /* size of target code for this block (1 <=
 187                            size <= TARGET_PAGE_SIZE) */
 188     uint16_t icount;
 189     uint32_t cflags;    /* compile flags */
 190 #define CF_COUNT_MASK  0x7fff
 191 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 192 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 193 #define CF_USE_ICOUNT  0x20000
 194
 195     void *tc_ptr;    /* pointer to the translated code */
 196     uint8_t *tc_search;  /* pointer to search data */
 197     /* next matching tb for physical address. */
 198     struct TranslationBlock *phys_hash_next;
 199     /* original tb when cflags has CF_NOCACHE */
 200     struct TranslationBlock *orig_tb;
 201     /* first and second physical page containing code. The lower bit
 202        of the pointer tells the index in page_next[] */
 203     struct TranslationBlock *page_next[2];
 204     tb_page_addr_t page_addr[2];
 205
 206     /* the following data are used to directly call another TB from
 207        the code of this one. */
 208     uint16_t tb_next_offset[2]; /* offset of original jump target */
 209 #ifdef USE_DIRECT_JUMP
 210     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 211 #else
 212     uintptr_t tb_next[2]; /* address of jump generated code */
 213 #endif
 214     /* list of TBs jumping to this one. This is a circular list using
 215        the two least significant bits of the pointers to tell what is
 216        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 217        jmp_first */
 218     struct TranslationBlock *jmp_next[2];
 219     struct TranslationBlock *jmp_first;
 220 };
 221
 222 #include "qemu/thread.h"
 223
 224 typedef struct TBContext TBContext;
 225
 226 struct TBContext {
 227
 228     TranslationBlock *tbs;
 229     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 230     int nb_tbs;
 231     /* any access to the tbs or the page table must use this lock */
 232     QemuMutex tb_lock;
 233
 234     /* statistics */
 235     int tb_flush_count;
 236     int tb_phys_invalidate_count;
 237
 238     int tb_invalidated_flag;
 239 };
 240
 241 void tb_free(TranslationBlock *tb);
 242 void tb_flush(CPUState *cpu);
 243 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 244
 245 #if defined(USE_DIRECT_JUMP)
 246
 247 #if defined(CONFIG_TCG_INTERPRETER)
 248 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 249 {
 250     /* patch the branch destination */
 251     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 252     /* no need to flush icache explicitly */
 253 }
 254 #elif defined(_ARCH_PPC)
 255 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 256 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 257 #elif defined(__i386__) || defined(__x86_64__)
 258 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 259 {
 260     /* patch the branch destination */
 261     stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
 262     /* no need to flush icache explicitly */
 263 }
 264 #elif defined(__s390x__)
 265 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 266 {
 267     /* patch the branch destination */
 268     intptr_t disp = addr - (jmp_addr - 2);
 269     stl_be_p((void*)jmp_addr, disp / 2);
 270     /* no need to flush icache explicitly */
 271 }
 272 #elif defined(__aarch64__)
 273 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 274 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 275 #elif defined(__arm__)
 276 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 277 {
 278 #if !QEMU_GNUC_PREREQ(4, 1)
 279     register unsigned long _beg __asm ("a1");
 280     register unsigned long _end __asm ("a2");
 281     register unsigned long _flg __asm ("a3");
 282 #endif
 283
 284     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 285     *(uint32_t *)jmp_addr =
 286         (*(uint32_t *)jmp_addr & ~0xffffff)
 287         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 288
 289 #if QEMU_GNUC_PREREQ(4, 1)
 290     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 291 #else
 292     /* flush icache */
 293     _beg = jmp_addr;
 294     _end = jmp_addr + 4;
 295     _flg = 0;
 296     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 297 #endif
 298 }
 299 #elif defined(__sparc__) || defined(__mips__)
 300 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 301 #else
 302 #error tb_set_jmp_target1 is missing
 303 #endif
 304
 305 static inline void tb_set_jmp_target(TranslationBlock *tb,
 306                                      int n, uintptr_t addr)
 307 {
 308     uint16_t offset = tb->tb_jmp_offset[n];
 309     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 310 }
 311
 312 #else
 313
 314 /* set the jump target */
 315 static inline void tb_set_jmp_target(TranslationBlock *tb,
 316                                      int n, uintptr_t addr)
 317 {
 318     tb->tb_next[n] = addr;
 319 }
 320
 321 #endif
 322
 323 static inline void tb_add_jump(TranslationBlock *tb, int n,
 324                                TranslationBlock *tb_next)
 325 {
 326     /* NOTE: this test is only needed for thread safety */
 327     if (!tb->jmp_next[n]) {
 328         /* patch the native jump address */
 329         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 330
 331         /* add in TB jmp circular list */
 332         tb->jmp_next[n] = tb_next->jmp_first;
 333         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
 334     }
 335 }
 336
 337 /* GETRA is the true target of the return instruction that we'll execute,
 338    defined here for simplicity of defining the follow-up macros.  */
 339 #if defined(CONFIG_TCG_INTERPRETER)
 340 extern uintptr_t tci_tb_ptr;
 341 # define GETRA() tci_tb_ptr
 342 #else
 343 # define GETRA() \
 344     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 345 #endif
 346
 347 /* The true return address will often point to a host insn that is part of
 348    the next translated guest insn.  Adjust the address backward to point to
 349    the middle of the call insn.  Subtracting one would do the job except for
 350    several compressed mode architectures (arm, mips) which set the low bit
 351    to indicate the compressed mode; subtracting two works around that.  It
 352    is also the case that there are no host isas that contain a call insn
 353    smaller than 4 bytes, so we don't worry about special-casing this.  */
 354 #define GETPC_ADJ   2
 355
 356 #define GETPC()  (GETRA() - GETPC_ADJ)
 357
 358 #if !defined(CONFIG_USER_ONLY)
 359
 360 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
 361
 362 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 363                                      hwaddr index);
 364
 365 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 366               uintptr_t retaddr);
 367
 368 #endif
 369
 370 #if defined(CONFIG_USER_ONLY)
 371 void mmap_lock(void);
 372 void mmap_unlock(void);
 373
 374 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 375 {
 376     return addr;
 377 }
 378 #else
 379 static inline void mmap_lock(void) {}
 380 static inline void mmap_unlock(void) {}
 381
 382 /* cputlb.c */
 383 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 384
 385 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 386 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
 387
 388 /* exec.c */
 389 void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
 390
 391 MemoryRegionSection *
 392 address_space_translate_for_iotlb(CPUState *cpu, hwaddr addr, hwaddr *xlat,
 393                                   hwaddr *plen);
 394 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 395                                        MemoryRegionSection *section,
 396                                        target_ulong vaddr,
 397                                        hwaddr paddr, hwaddr xlat,
 398                                        int prot,
 399                                        target_ulong *address);
 400 bool memory_region_is_unassigned(MemoryRegion *mr);
 401
 402 #endif
 403
 404 /* vl.c */
 405 extern int singlestep;
 406
 407 /* cpu-exec.c, accessed with atomic_mb_read/atomic_mb_set */
 408 extern CPUState *tcg_current_cpu;
 409 extern bool exit_request;
 410
 411 #if !defined(CONFIG_USER_ONLY)
 412 void migration_bitmap_extend(ram_addr_t old, ram_addr_t new);
 413 #endif
 414 #endif