target/alpha/cpu.c

   1 /*
   2  * QEMU Alpha CPU
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "exec/exec-all.h"
  27
  28
  29 static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     AlphaCPU *cpu = ALPHA_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 static bool alpha_cpu_has_work(CPUState *cs)
  37 {
  38     /* Here we are checking to see if the CPU should wake up from HALT.
  39        We will have gotten into this state only for WTINT from PALmode.  */
  40     /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
  41        asleep even if (some) interrupts have been asserted.  For now,
  42        assume that if a CPU really wants to stay asleep, it will mask
  43        interrupts at the chipset level, which will prevent these bits
  44        from being set in the first place.  */
  45     return cs->interrupt_request & (CPU_INTERRUPT_HARD
  46                                     | CPU_INTERRUPT_TIMER
  47                                     | CPU_INTERRUPT_SMP
  48                                     | CPU_INTERRUPT_MCHK);
  49 }
  50
  51 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  52 {
  53     info->mach = bfd_mach_alpha_ev6;
  54     info->print_insn = print_insn_alpha;
  55 }
  56
  57 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
  58 {
  59     CPUState *cs = CPU(dev);
  60     AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
  61     Error *local_err = NULL;
  62
  63     cpu_exec_realizefn(cs, &local_err);
  64     if (local_err != NULL) {
  65         error_propagate(errp, local_err);
  66         return;
  67     }
  68
  69     qemu_init_vcpu(cs);
  70
  71     acc->parent_realize(dev, errp);
  72 }
  73
  74 /* Sort alphabetically by type name. */
  75 static gint alpha_cpu_list_compare(gconstpointer a, gconstpointer b)
  76 {
  77     ObjectClass *class_a = (ObjectClass *)a;
  78     ObjectClass *class_b = (ObjectClass *)b;
  79     const char *name_a, *name_b;
  80
  81     name_a = object_class_get_name(class_a);
  82     name_b = object_class_get_name(class_b);
  83     return strcmp(name_a, name_b);
  84 }
  85
  86 static void alpha_cpu_list_entry(gpointer data, gpointer user_data)
  87 {
  88     ObjectClass *oc = data;
  89     CPUListState *s = user_data;
  90
  91     (*s->cpu_fprintf)(s->file, "  %s\n",
  92                       object_class_get_name(oc));
  93 }
  94
  95 void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf)
  96 {
  97     CPUListState s = {
  98         .file = f,
  99         .cpu_fprintf = cpu_fprintf,
 100     };
 101     GSList *list;
 102
 103     list = object_class_get_list(TYPE_ALPHA_CPU, false);
 104     list = g_slist_sort(list, alpha_cpu_list_compare);
 105     (*cpu_fprintf)(f, "Available CPUs:\n");
 106     g_slist_foreach(list, alpha_cpu_list_entry, &s);
 107     g_slist_free(list);
 108 }
 109
 110 /* Models */
 111 typedef struct AlphaCPUAlias {
 112     const char *alias;
 113     const char *typename;
 114 } AlphaCPUAlias;
 115
 116 static const AlphaCPUAlias alpha_cpu_aliases[] = {
 117     { "21064",   ALPHA_CPU_TYPE_NAME("ev4") },
 118     { "21164",   ALPHA_CPU_TYPE_NAME("ev5") },
 119     { "21164a",  ALPHA_CPU_TYPE_NAME("ev56") },
 120     { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
 121     { "21264",   ALPHA_CPU_TYPE_NAME("ev6") },
 122     { "21264a",  ALPHA_CPU_TYPE_NAME("ev67") },
 123 };
 124
 125 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
 126 {
 127     ObjectClass *oc;
 128     char *typename;
 129     int i;
 130
 131     oc = object_class_by_name(cpu_model);
 132     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL &&
 133         !object_class_is_abstract(oc)) {
 134         return oc;
 135     }
 136
 137     for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
 138         if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
 139             oc = object_class_by_name(alpha_cpu_aliases[i].typename);
 140             assert(oc != NULL && !object_class_is_abstract(oc));
 141             return oc;
 142         }
 143     }
 144
 145     typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model);
 146     oc = object_class_by_name(typename);
 147     g_free(typename);
 148     if (oc != NULL && object_class_is_abstract(oc)) {
 149         oc = NULL;
 150     }
 151
 152     /* TODO: remove match everything nonsense */
 153     /* Default to ev67; no reason not to emulate insns by default. */
 154     if (!oc) {
 155         oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
 156     }
 157
 158     return oc;
 159 }
 160
 161 static void ev4_cpu_initfn(Object *obj)
 162 {
 163     AlphaCPU *cpu = ALPHA_CPU(obj);
 164     CPUAlphaState *env = &cpu->env;
 165
 166     env->implver = IMPLVER_2106x;
 167 }
 168
 169 static void ev5_cpu_initfn(Object *obj)
 170 {
 171     AlphaCPU *cpu = ALPHA_CPU(obj);
 172     CPUAlphaState *env = &cpu->env;
 173
 174     env->implver = IMPLVER_21164;
 175 }
 176
 177 static void ev56_cpu_initfn(Object *obj)
 178 {
 179     AlphaCPU *cpu = ALPHA_CPU(obj);
 180     CPUAlphaState *env = &cpu->env;
 181
 182     env->amask |= AMASK_BWX;
 183 }
 184
 185 static void pca56_cpu_initfn(Object *obj)
 186 {
 187     AlphaCPU *cpu = ALPHA_CPU(obj);
 188     CPUAlphaState *env = &cpu->env;
 189
 190     env->amask |= AMASK_MVI;
 191 }
 192
 193 static void ev6_cpu_initfn(Object *obj)
 194 {
 195     AlphaCPU *cpu = ALPHA_CPU(obj);
 196     CPUAlphaState *env = &cpu->env;
 197
 198     env->implver = IMPLVER_21264;
 199     env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
 200 }
 201
 202 static void ev67_cpu_initfn(Object *obj)
 203 {
 204     AlphaCPU *cpu = ALPHA_CPU(obj);
 205     CPUAlphaState *env = &cpu->env;
 206
 207     env->amask |= AMASK_CIX | AMASK_PREFETCH;
 208 }
 209
 210 static void alpha_cpu_initfn(Object *obj)
 211 {
 212     CPUState *cs = CPU(obj);
 213     AlphaCPU *cpu = ALPHA_CPU(obj);
 214     CPUAlphaState *env = &cpu->env;
 215
 216     cs->env_ptr = env;
 217     tlb_flush(cs);
 218
 219     env->lock_addr = -1;
 220 #if defined(CONFIG_USER_ONLY)
 221     env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
 222     cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
 223                                | FPCR_UNFD | FPCR_INED | FPCR_DNOD
 224                                | FPCR_DYN_NORMAL));
 225 #else
 226     env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN;
 227 #endif
 228 }
 229
 230 static void alpha_cpu_class_init(ObjectClass *oc, void *data)
 231 {
 232     DeviceClass *dc = DEVICE_CLASS(oc);
 233     CPUClass *cc = CPU_CLASS(oc);
 234     AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
 235
 236     device_class_set_parent_realize(dc, alpha_cpu_realizefn,
 237                                     &acc->parent_realize);
 238
 239     cc->class_by_name = alpha_cpu_class_by_name;
 240     cc->has_work = alpha_cpu_has_work;
 241     cc->do_interrupt = alpha_cpu_do_interrupt;
 242     cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
 243     cc->dump_state = alpha_cpu_dump_state;
 244     cc->set_pc = alpha_cpu_set_pc;
 245     cc->gdb_read_register = alpha_cpu_gdb_read_register;
 246     cc->gdb_write_register = alpha_cpu_gdb_write_register;
 247 #ifdef CONFIG_USER_ONLY
 248     cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
 249 #else
 250     cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
 251     cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
 252     cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
 253     dc->vmsd = &vmstate_alpha_cpu;
 254 #endif
 255     cc->disas_set_info = alpha_cpu_disas_set_info;
 256     cc->tcg_initialize = alpha_translate_init;
 257
 258     cc->gdb_num_core_regs = 67;
 259 }
 260
 261 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
 262      {                                                      \
 263          .parent = base_type,                               \
 264          .instance_init = initfn,                           \
 265          .name = ALPHA_CPU_TYPE_NAME(cpu_model),            \
 266      }
 267
 268 static const TypeInfo alpha_cpu_type_infos[] = {
 269     {
 270         .name = TYPE_ALPHA_CPU,
 271         .parent = TYPE_CPU,
 272         .instance_size = sizeof(AlphaCPU),
 273         .instance_init = alpha_cpu_initfn,
 274         .abstract = true,
 275         .class_size = sizeof(AlphaCPUClass),
 276         .class_init = alpha_cpu_class_init,
 277     },
 278     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn),
 279     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn),
 280     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn),
 281     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
 282                           pca56_cpu_initfn),
 283     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn),
 284     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn),
 285     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL),
 286 };
 287
 288 DEFINE_TYPES(alpha_cpu_type_infos)