4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
121 case ARMMMUIdx_SE20_2
:
122 case ARMMMUIdx_SE20_2_PAN
:
123 useridx
= ARMMMUIdx_SE20_0
;
126 g_assert_not_reached();
129 return arm_to_core_mmu_idx(useridx
);
132 static void reset_btype(DisasContext
*s
)
135 TCGv_i32 zero
= tcg_const_i32(0);
136 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
137 tcg_temp_free_i32(zero
);
142 static void set_btype(DisasContext
*s
, int val
)
146 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
147 tcg_debug_assert(val
>= 1 && val
<= 3);
149 tcg_val
= tcg_const_i32(val
);
150 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
151 tcg_temp_free_i32(tcg_val
);
155 void gen_a64_set_pc_im(uint64_t val
)
157 tcg_gen_movi_i64(cpu_pc
, val
);
161 * Handle Top Byte Ignore (TBI) bits.
163 * If address tagging is enabled via the TCR TBI bits:
164 * + for EL2 and EL3 there is only one TBI bit, and if it is set
165 * then the address is zero-extended, clearing bits [63:56]
166 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
167 * and TBI1 controls addressses with bit 55 == 1.
168 * If the appropriate TBI bit is set for the address then
169 * the address is sign-extended from bit 55 into bits [63:56]
171 * Here We have concatenated TBI{1,0} into tbi.
173 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
174 TCGv_i64 src
, int tbi
)
177 /* Load unmodified address */
178 tcg_gen_mov_i64(dst
, src
);
179 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
180 /* Force tag byte to all zero */
181 tcg_gen_extract_i64(dst
, src
, 0, 56);
183 /* Sign-extend from bit 55. */
184 tcg_gen_sextract_i64(dst
, src
, 0, 56);
188 /* tbi0 but !tbi1: only use the extension if positive */
189 tcg_gen_and_i64(dst
, dst
, src
);
192 /* !tbi0 but tbi1: only use the extension if negative */
193 tcg_gen_or_i64(dst
, dst
, src
);
196 /* tbi0 and tbi1: always use the extension */
199 g_assert_not_reached();
204 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
207 * If address tagging is enabled for instructions via the TCR TBI bits,
208 * then loading an address into the PC will clear out any tag.
210 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
214 * Handle MTE and/or TBI.
216 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
217 * for the tag to be present in the FAR_ELx register. But for user-only
218 * mode we do not have a TLB with which to implement this, so we must
219 * remove the top byte now.
221 * Always return a fresh temporary that we can increment independently
222 * of the write-back address.
225 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
227 TCGv_i64 clean
= new_tmp_a64(s
);
228 #ifdef CONFIG_USER_ONLY
229 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
231 tcg_gen_mov_i64(clean
, addr
);
236 /* Insert a zero tag into src, with the result at dst. */
237 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
239 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
242 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
243 MMUAccessType acc
, int log2_size
)
245 TCGv_i32 t_acc
= tcg_const_i32(acc
);
246 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
247 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
249 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
250 tcg_temp_free_i32(t_acc
);
251 tcg_temp_free_i32(t_idx
);
252 tcg_temp_free_i32(t_size
);
256 * For MTE, check a single logical or atomic access. This probes a single
257 * address, the exact one specified. The size and alignment of the access
258 * is not relevant to MTE, per se, but watchpoints do require the size,
259 * and we want to recognize those before making any other changes to state.
261 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
262 bool is_write
, bool tag_checked
,
263 int log2_size
, bool is_unpriv
,
266 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
271 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
272 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
273 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
274 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
275 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_size
);
276 tcg_desc
= tcg_const_i32(desc
);
278 ret
= new_tmp_a64(s
);
279 gen_helper_mte_check1(ret
, cpu_env
, tcg_desc
, addr
);
280 tcg_temp_free_i32(tcg_desc
);
284 return clean_data_tbi(s
, addr
);
287 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
288 bool tag_checked
, int log2_size
)
290 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
291 false, get_mem_index(s
));
295 * For MTE, check multiple logical sequential accesses.
297 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
298 bool tag_checked
, int log2_esize
, int total_size
)
300 if (tag_checked
&& s
->mte_active
[0] && total_size
!= (1 << log2_esize
)) {
305 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
306 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
307 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
308 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
309 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_esize
);
310 desc
= FIELD_DP32(desc
, MTEDESC
, TSIZE
, total_size
);
311 tcg_desc
= tcg_const_i32(desc
);
313 ret
= new_tmp_a64(s
);
314 gen_helper_mte_checkN(ret
, cpu_env
, tcg_desc
, addr
);
315 tcg_temp_free_i32(tcg_desc
);
319 return gen_mte_check1(s
, addr
, is_write
, tag_checked
, log2_esize
);
322 typedef struct DisasCompare64
{
327 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
331 arm_test_cc(&c32
, cc
);
333 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
334 * properly. The NE/EQ comparisons are also fine with this choice. */
335 c64
->cond
= c32
.cond
;
336 c64
->value
= tcg_temp_new_i64();
337 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
342 static void a64_free_cc(DisasCompare64
*c64
)
344 tcg_temp_free_i64(c64
->value
);
347 static void gen_exception_internal(int excp
)
349 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
351 assert(excp_is_internal(excp
));
352 gen_helper_exception_internal(cpu_env
, tcg_excp
);
353 tcg_temp_free_i32(tcg_excp
);
356 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
358 gen_a64_set_pc_im(pc
);
359 gen_exception_internal(excp
);
360 s
->base
.is_jmp
= DISAS_NORETURN
;
363 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
364 uint32_t syndrome
, uint32_t target_el
)
366 gen_a64_set_pc_im(pc
);
367 gen_exception(excp
, syndrome
, target_el
);
368 s
->base
.is_jmp
= DISAS_NORETURN
;
371 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
375 gen_a64_set_pc_im(s
->pc_curr
);
376 tcg_syn
= tcg_const_i32(syndrome
);
377 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
378 tcg_temp_free_i32(tcg_syn
);
379 s
->base
.is_jmp
= DISAS_NORETURN
;
382 static void gen_step_complete_exception(DisasContext
*s
)
384 /* We just completed step of an insn. Move from Active-not-pending
385 * to Active-pending, and then also take the swstep exception.
386 * This corresponds to making the (IMPDEF) choice to prioritize
387 * swstep exceptions over asynchronous exceptions taken to an exception
388 * level where debug is disabled. This choice has the advantage that
389 * we do not need to maintain internal state corresponding to the
390 * ISV/EX syndrome bits between completion of the step and generation
391 * of the exception, and our syndrome information is always correct.
394 gen_swstep_exception(s
, 1, s
->is_ldex
);
395 s
->base
.is_jmp
= DISAS_NORETURN
;
398 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
400 /* No direct tb linking with singlestep (either QEMU's or the ARM
401 * debug architecture kind) or deterministic io
403 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
404 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
408 #ifndef CONFIG_USER_ONLY
409 /* Only link tbs from inside the same guest page */
410 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
418 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
420 const TranslationBlock
*tb
;
423 if (use_goto_tb(s
, n
, dest
)) {
425 gen_a64_set_pc_im(dest
);
426 tcg_gen_exit_tb(tb
, n
);
427 s
->base
.is_jmp
= DISAS_NORETURN
;
429 gen_a64_set_pc_im(dest
);
431 gen_step_complete_exception(s
);
432 } else if (s
->base
.singlestep_enabled
) {
433 gen_exception_internal(EXCP_DEBUG
);
435 tcg_gen_lookup_and_goto_ptr();
436 s
->base
.is_jmp
= DISAS_NORETURN
;
441 void unallocated_encoding(DisasContext
*s
)
443 /* Unallocated and reserved encodings are uncategorized */
444 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
445 default_exception_el(s
));
448 static void init_tmp_a64_array(DisasContext
*s
)
450 #ifdef CONFIG_DEBUG_TCG
451 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
453 s
->tmp_a64_count
= 0;
456 static void free_tmp_a64(DisasContext
*s
)
459 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
460 tcg_temp_free_i64(s
->tmp_a64
[i
]);
462 init_tmp_a64_array(s
);
465 TCGv_i64
new_tmp_a64(DisasContext
*s
)
467 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
468 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
471 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
473 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
474 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
477 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
479 TCGv_i64 t
= new_tmp_a64(s
);
480 tcg_gen_movi_i64(t
, 0);
485 * Register access functions
487 * These functions are used for directly accessing a register in where
488 * changes to the final register value are likely to be made. If you
489 * need to use a register for temporary calculation (e.g. index type
490 * operations) use the read_* form.
492 * B1.2.1 Register mappings
494 * In instruction register encoding 31 can refer to ZR (zero register) or
495 * the SP (stack pointer) depending on context. In QEMU's case we map SP
496 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
497 * This is the point of the _sp forms.
499 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
502 return new_tmp_a64_zero(s
);
508 /* register access for when 31 == SP */
509 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
514 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
515 * representing the register contents. This TCGv is an auto-freed
516 * temporary so it need not be explicitly freed, and may be modified.
518 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
520 TCGv_i64 v
= new_tmp_a64(s
);
523 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
525 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
528 tcg_gen_movi_i64(v
, 0);
533 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
535 TCGv_i64 v
= new_tmp_a64(s
);
537 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
539 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
544 /* Return the offset into CPUARMState of a slice (from
545 * the least significant end) of FP register Qn (ie
547 * (Note that this is not the same mapping as for A32; see cpu.h)
549 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
551 return vec_reg_offset(s
, regno
, 0, size
);
554 /* Offset of the high half of the 128 bit vector Qn */
555 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
557 return vec_reg_offset(s
, regno
, 1, MO_64
);
560 /* Convenience accessors for reading and writing single and double
561 * FP registers. Writing clears the upper parts of the associated
562 * 128 bit vector register, as required by the architecture.
563 * Note that unlike the GP register accessors, the values returned
564 * by the read functions must be manually freed.
566 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
568 TCGv_i64 v
= tcg_temp_new_i64();
570 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
574 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
576 TCGv_i32 v
= tcg_temp_new_i32();
578 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
582 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
584 TCGv_i32 v
= tcg_temp_new_i32();
586 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
590 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
591 * If SVE is not enabled, then there are only 128 bits in the vector.
593 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
595 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
596 unsigned vsz
= vec_full_reg_size(s
);
598 /* Nop move, with side effect of clearing the tail. */
599 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
602 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
604 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
606 tcg_gen_st_i64(v
, cpu_env
, ofs
);
607 clear_vec_high(s
, false, reg
);
610 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
612 TCGv_i64 tmp
= tcg_temp_new_i64();
614 tcg_gen_extu_i32_i64(tmp
, v
);
615 write_fp_dreg(s
, reg
, tmp
);
616 tcg_temp_free_i64(tmp
);
619 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
620 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
621 GVecGen2Fn
*gvec_fn
, int vece
)
623 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
624 is_q
? 16 : 8, vec_full_reg_size(s
));
627 /* Expand a 2-operand + immediate AdvSIMD vector operation using
628 * an expander function.
630 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
631 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
633 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
634 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
637 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
638 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
639 GVecGen3Fn
*gvec_fn
, int vece
)
641 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
642 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
645 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
646 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
647 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
649 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
650 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
651 is_q
? 16 : 8, vec_full_reg_size(s
));
654 /* Expand a 2-operand operation using an out-of-line helper. */
655 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
656 int rn
, int data
, gen_helper_gvec_2
*fn
)
658 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
659 vec_full_reg_offset(s
, rn
),
660 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
663 /* Expand a 3-operand operation using an out-of-line helper. */
664 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
665 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
667 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
668 vec_full_reg_offset(s
, rn
),
669 vec_full_reg_offset(s
, rm
),
670 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
673 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
674 * an out-of-line helper.
676 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
677 int rm
, bool is_fp16
, int data
,
678 gen_helper_gvec_3_ptr
*fn
)
680 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
681 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
682 vec_full_reg_offset(s
, rn
),
683 vec_full_reg_offset(s
, rm
), fpst
,
684 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
685 tcg_temp_free_ptr(fpst
);
688 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
689 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
690 int rm
, gen_helper_gvec_3_ptr
*fn
)
692 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
694 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
695 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
696 vec_full_reg_offset(s
, rn
),
697 vec_full_reg_offset(s
, rm
), qc_ptr
,
698 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
699 tcg_temp_free_ptr(qc_ptr
);
702 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
703 * than the 32 bit equivalent.
705 static inline void gen_set_NZ64(TCGv_i64 result
)
707 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
708 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
711 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
712 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
715 gen_set_NZ64(result
);
717 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
718 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
720 tcg_gen_movi_i32(cpu_CF
, 0);
721 tcg_gen_movi_i32(cpu_VF
, 0);
724 /* dest = T0 + T1; compute C, N, V and Z flags */
725 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
728 TCGv_i64 result
, flag
, tmp
;
729 result
= tcg_temp_new_i64();
730 flag
= tcg_temp_new_i64();
731 tmp
= tcg_temp_new_i64();
733 tcg_gen_movi_i64(tmp
, 0);
734 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
736 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
738 gen_set_NZ64(result
);
740 tcg_gen_xor_i64(flag
, result
, t0
);
741 tcg_gen_xor_i64(tmp
, t0
, t1
);
742 tcg_gen_andc_i64(flag
, flag
, tmp
);
743 tcg_temp_free_i64(tmp
);
744 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
746 tcg_gen_mov_i64(dest
, result
);
747 tcg_temp_free_i64(result
);
748 tcg_temp_free_i64(flag
);
750 /* 32 bit arithmetic */
751 TCGv_i32 t0_32
= tcg_temp_new_i32();
752 TCGv_i32 t1_32
= tcg_temp_new_i32();
753 TCGv_i32 tmp
= tcg_temp_new_i32();
755 tcg_gen_movi_i32(tmp
, 0);
756 tcg_gen_extrl_i64_i32(t0_32
, t0
);
757 tcg_gen_extrl_i64_i32(t1_32
, t1
);
758 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
759 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
760 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
761 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
762 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
763 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
765 tcg_temp_free_i32(tmp
);
766 tcg_temp_free_i32(t0_32
);
767 tcg_temp_free_i32(t1_32
);
771 /* dest = T0 - T1; compute C, N, V and Z flags */
772 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
775 /* 64 bit arithmetic */
776 TCGv_i64 result
, flag
, tmp
;
778 result
= tcg_temp_new_i64();
779 flag
= tcg_temp_new_i64();
780 tcg_gen_sub_i64(result
, t0
, t1
);
782 gen_set_NZ64(result
);
784 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
785 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
787 tcg_gen_xor_i64(flag
, result
, t0
);
788 tmp
= tcg_temp_new_i64();
789 tcg_gen_xor_i64(tmp
, t0
, t1
);
790 tcg_gen_and_i64(flag
, flag
, tmp
);
791 tcg_temp_free_i64(tmp
);
792 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
793 tcg_gen_mov_i64(dest
, result
);
794 tcg_temp_free_i64(flag
);
795 tcg_temp_free_i64(result
);
797 /* 32 bit arithmetic */
798 TCGv_i32 t0_32
= tcg_temp_new_i32();
799 TCGv_i32 t1_32
= tcg_temp_new_i32();
802 tcg_gen_extrl_i64_i32(t0_32
, t0
);
803 tcg_gen_extrl_i64_i32(t1_32
, t1
);
804 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
805 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
806 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
807 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
808 tmp
= tcg_temp_new_i32();
809 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
810 tcg_temp_free_i32(t0_32
);
811 tcg_temp_free_i32(t1_32
);
812 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
813 tcg_temp_free_i32(tmp
);
814 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
818 /* dest = T0 + T1 + CF; do not compute flags. */
819 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
821 TCGv_i64 flag
= tcg_temp_new_i64();
822 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
823 tcg_gen_add_i64(dest
, t0
, t1
);
824 tcg_gen_add_i64(dest
, dest
, flag
);
825 tcg_temp_free_i64(flag
);
828 tcg_gen_ext32u_i64(dest
, dest
);
832 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
833 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
836 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
837 result
= tcg_temp_new_i64();
838 cf_64
= tcg_temp_new_i64();
839 vf_64
= tcg_temp_new_i64();
840 tmp
= tcg_const_i64(0);
842 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
843 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
844 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
845 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
846 gen_set_NZ64(result
);
848 tcg_gen_xor_i64(vf_64
, result
, t0
);
849 tcg_gen_xor_i64(tmp
, t0
, t1
);
850 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
851 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
853 tcg_gen_mov_i64(dest
, result
);
855 tcg_temp_free_i64(tmp
);
856 tcg_temp_free_i64(vf_64
);
857 tcg_temp_free_i64(cf_64
);
858 tcg_temp_free_i64(result
);
860 TCGv_i32 t0_32
, t1_32
, tmp
;
861 t0_32
= tcg_temp_new_i32();
862 t1_32
= tcg_temp_new_i32();
863 tmp
= tcg_const_i32(0);
865 tcg_gen_extrl_i64_i32(t0_32
, t0
);
866 tcg_gen_extrl_i64_i32(t1_32
, t1
);
867 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
868 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
870 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
871 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
872 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
873 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
874 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
876 tcg_temp_free_i32(tmp
);
877 tcg_temp_free_i32(t1_32
);
878 tcg_temp_free_i32(t0_32
);
883 * Load/Store generators
887 * Store from GPR register to memory.
889 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
890 TCGv_i64 tcg_addr
, int size
, int memidx
,
892 unsigned int iss_srt
,
893 bool iss_sf
, bool iss_ar
)
896 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
901 syn
= syn_data_abort_with_iss(0,
907 0, 0, 0, 0, 0, false);
908 disas_set_insn_syndrome(s
, syn
);
912 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
913 TCGv_i64 tcg_addr
, int size
,
915 unsigned int iss_srt
,
916 bool iss_sf
, bool iss_ar
)
918 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
919 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
923 * Load from memory to GPR register
925 static void do_gpr_ld_memidx(DisasContext
*s
,
926 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
927 int size
, bool is_signed
,
928 bool extend
, int memidx
,
929 bool iss_valid
, unsigned int iss_srt
,
930 bool iss_sf
, bool iss_ar
)
932 MemOp memop
= s
->be_data
+ size
;
940 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
942 if (extend
&& is_signed
) {
944 tcg_gen_ext32u_i64(dest
, dest
);
950 syn
= syn_data_abort_with_iss(0,
956 0, 0, 0, 0, 0, false);
957 disas_set_insn_syndrome(s
, syn
);
961 static void do_gpr_ld(DisasContext
*s
,
962 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
963 int size
, bool is_signed
, bool extend
,
964 bool iss_valid
, unsigned int iss_srt
,
965 bool iss_sf
, bool iss_ar
)
967 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
969 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
973 * Store from FP register to memory
975 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
977 /* This writes the bottom N bits of a 128 bit wide vector to memory */
978 TCGv_i64 tmp
= tcg_temp_new_i64();
979 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
981 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
984 bool be
= s
->be_data
== MO_BE
;
985 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
987 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
988 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
990 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
991 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
993 tcg_temp_free_i64(tcg_hiaddr
);
996 tcg_temp_free_i64(tmp
);
1000 * Load from memory to FP register
1002 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1004 /* This always zero-extends and writes to a full 128 bit wide vector */
1005 TCGv_i64 tmplo
= tcg_temp_new_i64();
1006 TCGv_i64 tmphi
= NULL
;
1009 MemOp memop
= s
->be_data
+ size
;
1010 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1012 bool be
= s
->be_data
== MO_BE
;
1013 TCGv_i64 tcg_hiaddr
;
1015 tmphi
= tcg_temp_new_i64();
1016 tcg_hiaddr
= tcg_temp_new_i64();
1018 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1019 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1021 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1023 tcg_temp_free_i64(tcg_hiaddr
);
1026 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1027 tcg_temp_free_i64(tmplo
);
1030 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1031 tcg_temp_free_i64(tmphi
);
1033 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1037 * Vector load/store helpers.
1039 * The principal difference between this and a FP load is that we don't
1040 * zero extend as we are filling a partial chunk of the vector register.
1041 * These functions don't support 128 bit loads/stores, which would be
1042 * normal load/store operations.
1044 * The _i32 versions are useful when operating on 32 bit quantities
1045 * (eg for floating point single or using Neon helper functions).
1048 /* Get value of an element within a vector register */
1049 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1050 int element
, MemOp memop
)
1052 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1055 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1058 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1061 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1064 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1067 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1070 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1074 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1077 g_assert_not_reached();
1081 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1082 int element
, MemOp memop
)
1084 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1087 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1090 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1093 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1096 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1100 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1103 g_assert_not_reached();
1107 /* Set value of an element within a vector register */
1108 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1109 int element
, MemOp memop
)
1111 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1114 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1117 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1120 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1123 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1126 g_assert_not_reached();
1130 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1131 int destidx
, int element
, MemOp memop
)
1133 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1136 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1139 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1142 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1145 g_assert_not_reached();
1149 /* Store from vector register to memory */
1150 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1151 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1153 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1155 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1156 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1158 tcg_temp_free_i64(tcg_tmp
);
1161 /* Load from memory to vector register */
1162 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1163 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1165 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1167 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1168 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1170 tcg_temp_free_i64(tcg_tmp
);
1173 /* Check that FP/Neon access is enabled. If it is, return
1174 * true. If not, emit code to generate an appropriate exception,
1175 * and return false; the caller should not emit any code for
1176 * the instruction. Note that this check must happen after all
1177 * unallocated-encoding checks (otherwise the syndrome information
1178 * for the resulting exception will be incorrect).
1180 static bool fp_access_check(DisasContext
*s
)
1182 if (s
->fp_excp_el
) {
1183 assert(!s
->fp_access_checked
);
1184 s
->fp_access_checked
= true;
1186 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1187 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1190 s
->fp_access_checked
= true;
1194 /* Check that SVE access is enabled. If it is, return true.
1195 * If not, emit code to generate an appropriate exception and return false.
1197 bool sve_access_check(DisasContext
*s
)
1199 if (s
->sve_excp_el
) {
1200 assert(!s
->sve_access_checked
);
1201 s
->sve_access_checked
= true;
1203 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1204 syn_sve_access_trap(), s
->sve_excp_el
);
1207 s
->sve_access_checked
= true;
1208 return fp_access_check(s
);
1212 * This utility function is for doing register extension with an
1213 * optional shift. You will likely want to pass a temporary for the
1214 * destination register. See DecodeRegExtend() in the ARM ARM.
1216 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1217 int option
, unsigned int shift
)
1219 int extsize
= extract32(option
, 0, 2);
1220 bool is_signed
= extract32(option
, 2, 1);
1225 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1228 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1231 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1234 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1240 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1243 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1246 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1249 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1255 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1259 static inline void gen_check_sp_alignment(DisasContext
*s
)
1261 /* The AArch64 architecture mandates that (if enabled via PSTATE
1262 * or SCTLR bits) there is a check that SP is 16-aligned on every
1263 * SP-relative load or store (with an exception generated if it is not).
1264 * In line with general QEMU practice regarding misaligned accesses,
1265 * we omit these checks for the sake of guest program performance.
1266 * This function is provided as a hook so we can more easily add these
1267 * checks in future (possibly as a "favour catching guest program bugs
1268 * over speed" user selectable option).
1273 * This provides a simple table based table lookup decoder. It is
1274 * intended to be used when the relevant bits for decode are too
1275 * awkwardly placed and switch/if based logic would be confusing and
1276 * deeply nested. Since it's a linear search through the table, tables
1277 * should be kept small.
1279 * It returns the first handler where insn & mask == pattern, or
1280 * NULL if there is no match.
1281 * The table is terminated by an empty mask (i.e. 0)
1283 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1286 const AArch64DecodeTable
*tptr
= table
;
1288 while (tptr
->mask
) {
1289 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1290 return tptr
->disas_fn
;
1298 * The instruction disassembly implemented here matches
1299 * the instruction encoding classifications in chapter C4
1300 * of the ARM Architecture Reference Manual (DDI0487B_a);
1301 * classification names and decode diagrams here should generally
1302 * match up with those in the manual.
1305 /* Unconditional branch (immediate)
1307 * +----+-----------+-------------------------------------+
1308 * | op | 0 0 1 0 1 | imm26 |
1309 * +----+-----------+-------------------------------------+
1311 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1313 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1315 if (insn
& (1U << 31)) {
1316 /* BL Branch with link */
1317 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1320 /* B Branch / BL Branch with link */
1322 gen_goto_tb(s
, 0, addr
);
1325 /* Compare and branch (immediate)
1326 * 31 30 25 24 23 5 4 0
1327 * +----+-------------+----+---------------------+--------+
1328 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1329 * +----+-------------+----+---------------------+--------+
1331 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1333 unsigned int sf
, op
, rt
;
1335 TCGLabel
*label_match
;
1338 sf
= extract32(insn
, 31, 1);
1339 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1340 rt
= extract32(insn
, 0, 5);
1341 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1343 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1344 label_match
= gen_new_label();
1347 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1348 tcg_cmp
, 0, label_match
);
1350 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1351 gen_set_label(label_match
);
1352 gen_goto_tb(s
, 1, addr
);
1355 /* Test and branch (immediate)
1356 * 31 30 25 24 23 19 18 5 4 0
1357 * +----+-------------+----+-------+-------------+------+
1358 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1359 * +----+-------------+----+-------+-------------+------+
1361 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1363 unsigned int bit_pos
, op
, rt
;
1365 TCGLabel
*label_match
;
1368 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1369 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1370 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1371 rt
= extract32(insn
, 0, 5);
1373 tcg_cmp
= tcg_temp_new_i64();
1374 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1375 label_match
= gen_new_label();
1378 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1379 tcg_cmp
, 0, label_match
);
1380 tcg_temp_free_i64(tcg_cmp
);
1381 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1382 gen_set_label(label_match
);
1383 gen_goto_tb(s
, 1, addr
);
1386 /* Conditional branch (immediate)
1387 * 31 25 24 23 5 4 3 0
1388 * +---------------+----+---------------------+----+------+
1389 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1390 * +---------------+----+---------------------+----+------+
1392 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1397 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1398 unallocated_encoding(s
);
1401 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1402 cond
= extract32(insn
, 0, 4);
1406 /* genuinely conditional branches */
1407 TCGLabel
*label_match
= gen_new_label();
1408 arm_gen_test_cc(cond
, label_match
);
1409 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1410 gen_set_label(label_match
);
1411 gen_goto_tb(s
, 1, addr
);
1413 /* 0xe and 0xf are both "always" conditions */
1414 gen_goto_tb(s
, 0, addr
);
1418 /* HINT instruction group, including various allocated HINTs */
1419 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1420 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1422 unsigned int selector
= crm
<< 3 | op2
;
1425 unallocated_encoding(s
);
1430 case 0b00000: /* NOP */
1432 case 0b00011: /* WFI */
1433 s
->base
.is_jmp
= DISAS_WFI
;
1435 case 0b00001: /* YIELD */
1436 /* When running in MTTCG we don't generate jumps to the yield and
1437 * WFE helpers as it won't affect the scheduling of other vCPUs.
1438 * If we wanted to more completely model WFE/SEV so we don't busy
1439 * spin unnecessarily we would need to do something more involved.
1441 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1442 s
->base
.is_jmp
= DISAS_YIELD
;
1445 case 0b00010: /* WFE */
1446 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1447 s
->base
.is_jmp
= DISAS_WFE
;
1450 case 0b00100: /* SEV */
1451 case 0b00101: /* SEVL */
1452 /* we treat all as NOP at least for now */
1454 case 0b00111: /* XPACLRI */
1455 if (s
->pauth_active
) {
1456 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1459 case 0b01000: /* PACIA1716 */
1460 if (s
->pauth_active
) {
1461 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1464 case 0b01010: /* PACIB1716 */
1465 if (s
->pauth_active
) {
1466 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1469 case 0b01100: /* AUTIA1716 */
1470 if (s
->pauth_active
) {
1471 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1474 case 0b01110: /* AUTIB1716 */
1475 if (s
->pauth_active
) {
1476 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1479 case 0b11000: /* PACIAZ */
1480 if (s
->pauth_active
) {
1481 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1482 new_tmp_a64_zero(s
));
1485 case 0b11001: /* PACIASP */
1486 if (s
->pauth_active
) {
1487 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1490 case 0b11010: /* PACIBZ */
1491 if (s
->pauth_active
) {
1492 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1493 new_tmp_a64_zero(s
));
1496 case 0b11011: /* PACIBSP */
1497 if (s
->pauth_active
) {
1498 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1501 case 0b11100: /* AUTIAZ */
1502 if (s
->pauth_active
) {
1503 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1504 new_tmp_a64_zero(s
));
1507 case 0b11101: /* AUTIASP */
1508 if (s
->pauth_active
) {
1509 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1512 case 0b11110: /* AUTIBZ */
1513 if (s
->pauth_active
) {
1514 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1515 new_tmp_a64_zero(s
));
1518 case 0b11111: /* AUTIBSP */
1519 if (s
->pauth_active
) {
1520 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1524 /* default specified as NOP equivalent */
1529 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1531 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1534 /* CLREX, DSB, DMB, ISB */
1535 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1536 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1541 unallocated_encoding(s
);
1552 case 1: /* MBReqTypes_Reads */
1553 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1555 case 2: /* MBReqTypes_Writes */
1556 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1558 default: /* MBReqTypes_All */
1559 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1565 /* We need to break the TB after this insn to execute
1566 * a self-modified code correctly and also to take
1567 * any pending interrupts immediately.
1570 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1574 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1575 goto do_unallocated
;
1578 * TODO: There is no speculation barrier opcode for TCG;
1579 * MB and end the TB instead.
1581 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1582 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1587 unallocated_encoding(s
);
1592 static void gen_xaflag(void)
1594 TCGv_i32 z
= tcg_temp_new_i32();
1596 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1605 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1606 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1609 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1610 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1612 /* (!C & Z) << 31 -> -(Z & ~C) */
1613 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1614 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1617 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1619 tcg_temp_free_i32(z
);
1622 static void gen_axflag(void)
1624 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1625 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1627 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1628 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1630 tcg_gen_movi_i32(cpu_NF
, 0);
1631 tcg_gen_movi_i32(cpu_VF
, 0);
1634 /* MSR (immediate) - move immediate to processor state field */
1635 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1636 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1639 int op
= op1
<< 3 | op2
;
1641 /* End the TB by default, chaining is ok. */
1642 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1645 case 0x00: /* CFINV */
1646 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1647 goto do_unallocated
;
1649 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1650 s
->base
.is_jmp
= DISAS_NEXT
;
1653 case 0x01: /* XAFlag */
1654 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1655 goto do_unallocated
;
1658 s
->base
.is_jmp
= DISAS_NEXT
;
1661 case 0x02: /* AXFlag */
1662 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1663 goto do_unallocated
;
1666 s
->base
.is_jmp
= DISAS_NEXT
;
1669 case 0x03: /* UAO */
1670 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1671 goto do_unallocated
;
1674 set_pstate_bits(PSTATE_UAO
);
1676 clear_pstate_bits(PSTATE_UAO
);
1678 t1
= tcg_const_i32(s
->current_el
);
1679 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1680 tcg_temp_free_i32(t1
);
1683 case 0x04: /* PAN */
1684 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1685 goto do_unallocated
;
1688 set_pstate_bits(PSTATE_PAN
);
1690 clear_pstate_bits(PSTATE_PAN
);
1692 t1
= tcg_const_i32(s
->current_el
);
1693 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1694 tcg_temp_free_i32(t1
);
1697 case 0x05: /* SPSel */
1698 if (s
->current_el
== 0) {
1699 goto do_unallocated
;
1701 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1702 gen_helper_msr_i_spsel(cpu_env
, t1
);
1703 tcg_temp_free_i32(t1
);
1706 case 0x19: /* SSBS */
1707 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1708 goto do_unallocated
;
1711 set_pstate_bits(PSTATE_SSBS
);
1713 clear_pstate_bits(PSTATE_SSBS
);
1715 /* Don't need to rebuild hflags since SSBS is a nop */
1718 case 0x1a: /* DIT */
1719 if (!dc_isar_feature(aa64_dit
, s
)) {
1720 goto do_unallocated
;
1723 set_pstate_bits(PSTATE_DIT
);
1725 clear_pstate_bits(PSTATE_DIT
);
1727 /* There's no need to rebuild hflags because DIT is a nop */
1730 case 0x1e: /* DAIFSet */
1731 t1
= tcg_const_i32(crm
);
1732 gen_helper_msr_i_daifset(cpu_env
, t1
);
1733 tcg_temp_free_i32(t1
);
1736 case 0x1f: /* DAIFClear */
1737 t1
= tcg_const_i32(crm
);
1738 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1739 tcg_temp_free_i32(t1
);
1740 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1741 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1744 case 0x1c: /* TCO */
1745 if (dc_isar_feature(aa64_mte
, s
)) {
1746 /* Full MTE is enabled -- set the TCO bit as directed. */
1748 set_pstate_bits(PSTATE_TCO
);
1750 clear_pstate_bits(PSTATE_TCO
);
1752 t1
= tcg_const_i32(s
->current_el
);
1753 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1754 tcg_temp_free_i32(t1
);
1755 /* Many factors, including TCO, go into MTE_ACTIVE. */
1756 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1757 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1758 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1759 s
->base
.is_jmp
= DISAS_NEXT
;
1761 goto do_unallocated
;
1767 unallocated_encoding(s
);
1772 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1774 TCGv_i32 tmp
= tcg_temp_new_i32();
1775 TCGv_i32 nzcv
= tcg_temp_new_i32();
1777 /* build bit 31, N */
1778 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1779 /* build bit 30, Z */
1780 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1781 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1782 /* build bit 29, C */
1783 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1784 /* build bit 28, V */
1785 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1786 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1787 /* generate result */
1788 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1790 tcg_temp_free_i32(nzcv
);
1791 tcg_temp_free_i32(tmp
);
1794 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1796 TCGv_i32 nzcv
= tcg_temp_new_i32();
1798 /* take NZCV from R[t] */
1799 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1802 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1804 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1805 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1807 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1808 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1810 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1811 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1812 tcg_temp_free_i32(nzcv
);
1815 /* MRS - move from system register
1816 * MSR (register) - move to system register
1819 * These are all essentially the same insn in 'read' and 'write'
1820 * versions, with varying op0 fields.
1822 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1823 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1824 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1826 const ARMCPRegInfo
*ri
;
1829 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1830 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1831 crn
, crm
, op0
, op1
, op2
));
1834 /* Unknown register; this might be a guest error or a QEMU
1835 * unimplemented feature.
1837 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1838 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1839 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1840 unallocated_encoding(s
);
1844 /* Check access permissions */
1845 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1846 unallocated_encoding(s
);
1851 /* Emit code to perform further access permissions checks at
1852 * runtime; this may result in an exception.
1855 TCGv_i32 tcg_syn
, tcg_isread
;
1858 gen_a64_set_pc_im(s
->pc_curr
);
1859 tmpptr
= tcg_const_ptr(ri
);
1860 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1861 tcg_syn
= tcg_const_i32(syndrome
);
1862 tcg_isread
= tcg_const_i32(isread
);
1863 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1864 tcg_temp_free_ptr(tmpptr
);
1865 tcg_temp_free_i32(tcg_syn
);
1866 tcg_temp_free_i32(tcg_isread
);
1867 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1869 * The readfn or writefn might raise an exception;
1870 * synchronize the CPU state in case it does.
1872 gen_a64_set_pc_im(s
->pc_curr
);
1875 /* Handle special cases first */
1876 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1880 tcg_rt
= cpu_reg(s
, rt
);
1882 gen_get_nzcv(tcg_rt
);
1884 gen_set_nzcv(tcg_rt
);
1887 case ARM_CP_CURRENTEL
:
1888 /* Reads as current EL value from pstate, which is
1889 * guaranteed to be constant by the tb flags.
1891 tcg_rt
= cpu_reg(s
, rt
);
1892 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1895 /* Writes clear the aligned block of memory which rt points into. */
1896 if (s
->mte_active
[0]) {
1900 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1901 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1902 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1903 t_desc
= tcg_const_i32(desc
);
1905 tcg_rt
= new_tmp_a64(s
);
1906 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1907 tcg_temp_free_i32(t_desc
);
1909 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1911 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1915 TCGv_i64 clean_addr
, tag
;
1918 * DC_GVA, like DC_ZVA, requires that we supply the original
1919 * pointer for an invalid page. Probe that address first.
1921 tcg_rt
= cpu_reg(s
, rt
);
1922 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1923 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1926 /* Extract the tag from the register to match STZGM. */
1927 tag
= tcg_temp_new_i64();
1928 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1929 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1930 tcg_temp_free_i64(tag
);
1934 case ARM_CP_DC_GZVA
:
1936 TCGv_i64 clean_addr
, tag
;
1938 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1939 tcg_rt
= cpu_reg(s
, rt
);
1940 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1941 gen_helper_dc_zva(cpu_env
, clean_addr
);
1944 /* Extract the tag from the register to match STZGM. */
1945 tag
= tcg_temp_new_i64();
1946 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1947 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1948 tcg_temp_free_i64(tag
);
1955 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1957 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1961 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1965 tcg_rt
= cpu_reg(s
, rt
);
1968 if (ri
->type
& ARM_CP_CONST
) {
1969 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1970 } else if (ri
->readfn
) {
1972 tmpptr
= tcg_const_ptr(ri
);
1973 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1974 tcg_temp_free_ptr(tmpptr
);
1976 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1979 if (ri
->type
& ARM_CP_CONST
) {
1980 /* If not forbidden by access permissions, treat as WI */
1982 } else if (ri
->writefn
) {
1984 tmpptr
= tcg_const_ptr(ri
);
1985 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1986 tcg_temp_free_ptr(tmpptr
);
1988 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1992 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1993 /* I/O operations must end the TB here (whether read or write) */
1994 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1996 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1998 * A write to any coprocessor regiser that ends a TB
1999 * must rebuild the hflags for the next TB.
2001 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
2002 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
2003 tcg_temp_free_i32(tcg_el
);
2005 * We default to ending the TB on a coprocessor register write,
2006 * but allow this to be suppressed by the register definition
2007 * (usually only necessary to work around guest bugs).
2009 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2014 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2015 * +---------------------+---+-----+-----+-------+-------+-----+------+
2016 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2017 * +---------------------+---+-----+-----+-------+-------+-----+------+
2019 static void disas_system(DisasContext
*s
, uint32_t insn
)
2021 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2022 l
= extract32(insn
, 21, 1);
2023 op0
= extract32(insn
, 19, 2);
2024 op1
= extract32(insn
, 16, 3);
2025 crn
= extract32(insn
, 12, 4);
2026 crm
= extract32(insn
, 8, 4);
2027 op2
= extract32(insn
, 5, 3);
2028 rt
= extract32(insn
, 0, 5);
2031 if (l
|| rt
!= 31) {
2032 unallocated_encoding(s
);
2036 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2037 handle_hint(s
, insn
, op1
, op2
, crm
);
2039 case 3: /* CLREX, DSB, DMB, ISB */
2040 handle_sync(s
, insn
, op1
, op2
, crm
);
2042 case 4: /* MSR (immediate) */
2043 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2046 unallocated_encoding(s
);
2051 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2054 /* Exception generation
2056 * 31 24 23 21 20 5 4 2 1 0
2057 * +-----------------+-----+------------------------+-----+----+
2058 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2059 * +-----------------------+------------------------+----------+
2061 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2063 int opc
= extract32(insn
, 21, 3);
2064 int op2_ll
= extract32(insn
, 0, 5);
2065 int imm16
= extract32(insn
, 5, 16);
2070 /* For SVC, HVC and SMC we advance the single-step state
2071 * machine before taking the exception. This is architecturally
2072 * mandated, to ensure that single-stepping a system call
2073 * instruction works properly.
2078 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2079 syn_aa64_svc(imm16
), default_exception_el(s
));
2082 if (s
->current_el
== 0) {
2083 unallocated_encoding(s
);
2086 /* The pre HVC helper handles cases when HVC gets trapped
2087 * as an undefined insn by runtime configuration.
2089 gen_a64_set_pc_im(s
->pc_curr
);
2090 gen_helper_pre_hvc(cpu_env
);
2092 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2093 syn_aa64_hvc(imm16
), 2);
2096 if (s
->current_el
== 0) {
2097 unallocated_encoding(s
);
2100 gen_a64_set_pc_im(s
->pc_curr
);
2101 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2102 gen_helper_pre_smc(cpu_env
, tmp
);
2103 tcg_temp_free_i32(tmp
);
2105 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2106 syn_aa64_smc(imm16
), 3);
2109 unallocated_encoding(s
);
2115 unallocated_encoding(s
);
2119 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2123 unallocated_encoding(s
);
2126 /* HLT. This has two purposes.
2127 * Architecturally, it is an external halting debug instruction.
2128 * Since QEMU doesn't implement external debug, we treat this as
2129 * it is required for halting debug disabled: it will UNDEF.
2130 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2132 if (semihosting_enabled() && imm16
== 0xf000) {
2133 #ifndef CONFIG_USER_ONLY
2134 /* In system mode, don't allow userspace access to semihosting,
2135 * to provide some semblance of security (and for consistency
2136 * with our 32-bit semihosting).
2138 if (s
->current_el
== 0) {
2139 unsupported_encoding(s
, insn
);
2143 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2145 unsupported_encoding(s
, insn
);
2149 if (op2_ll
< 1 || op2_ll
> 3) {
2150 unallocated_encoding(s
);
2153 /* DCPS1, DCPS2, DCPS3 */
2154 unsupported_encoding(s
, insn
);
2157 unallocated_encoding(s
);
2162 /* Unconditional branch (register)
2163 * 31 25 24 21 20 16 15 10 9 5 4 0
2164 * +---------------+-------+-------+-------+------+-------+
2165 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2166 * +---------------+-------+-------+-------+------+-------+
2168 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2170 unsigned int opc
, op2
, op3
, rn
, op4
;
2171 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2175 opc
= extract32(insn
, 21, 4);
2176 op2
= extract32(insn
, 16, 5);
2177 op3
= extract32(insn
, 10, 6);
2178 rn
= extract32(insn
, 5, 5);
2179 op4
= extract32(insn
, 0, 5);
2182 goto do_unallocated
;
2194 goto do_unallocated
;
2196 dst
= cpu_reg(s
, rn
);
2201 if (!dc_isar_feature(aa64_pauth
, s
)) {
2202 goto do_unallocated
;
2206 if (rn
!= 0x1f || op4
!= 0x1f) {
2207 goto do_unallocated
;
2210 modifier
= cpu_X
[31];
2212 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2214 goto do_unallocated
;
2216 modifier
= new_tmp_a64_zero(s
);
2218 if (s
->pauth_active
) {
2219 dst
= new_tmp_a64(s
);
2221 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2223 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2226 dst
= cpu_reg(s
, rn
);
2231 goto do_unallocated
;
2233 gen_a64_set_pc(s
, dst
);
2234 /* BLR also needs to load return address */
2236 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2242 if (!dc_isar_feature(aa64_pauth
, s
)) {
2243 goto do_unallocated
;
2245 if ((op3
& ~1) != 2) {
2246 goto do_unallocated
;
2248 btype_mod
= opc
& 1;
2249 if (s
->pauth_active
) {
2250 dst
= new_tmp_a64(s
);
2251 modifier
= cpu_reg_sp(s
, op4
);
2253 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2255 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2258 dst
= cpu_reg(s
, rn
);
2260 gen_a64_set_pc(s
, dst
);
2261 /* BLRAA also needs to load return address */
2263 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2268 if (s
->current_el
== 0) {
2269 goto do_unallocated
;
2274 goto do_unallocated
;
2276 dst
= tcg_temp_new_i64();
2277 tcg_gen_ld_i64(dst
, cpu_env
,
2278 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2281 case 2: /* ERETAA */
2282 case 3: /* ERETAB */
2283 if (!dc_isar_feature(aa64_pauth
, s
)) {
2284 goto do_unallocated
;
2286 if (rn
!= 0x1f || op4
!= 0x1f) {
2287 goto do_unallocated
;
2289 dst
= tcg_temp_new_i64();
2290 tcg_gen_ld_i64(dst
, cpu_env
,
2291 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2292 if (s
->pauth_active
) {
2293 modifier
= cpu_X
[31];
2295 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2297 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2303 goto do_unallocated
;
2305 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2309 gen_helper_exception_return(cpu_env
, dst
);
2310 tcg_temp_free_i64(dst
);
2311 /* Must exit loop to check un-masked IRQs */
2312 s
->base
.is_jmp
= DISAS_EXIT
;
2316 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2317 goto do_unallocated
;
2319 unsupported_encoding(s
, insn
);
2325 unallocated_encoding(s
);
2329 switch (btype_mod
) {
2331 if (dc_isar_feature(aa64_bti
, s
)) {
2332 /* BR to {x16,x17} or !guard -> 1, else 3. */
2333 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2338 if (dc_isar_feature(aa64_bti
, s
)) {
2339 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2344 default: /* RET or none of the above. */
2345 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2349 s
->base
.is_jmp
= DISAS_JUMP
;
2352 /* Branches, exception generating and system instructions */
2353 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2355 switch (extract32(insn
, 25, 7)) {
2356 case 0x0a: case 0x0b:
2357 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2358 disas_uncond_b_imm(s
, insn
);
2360 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2361 disas_comp_b_imm(s
, insn
);
2363 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2364 disas_test_b_imm(s
, insn
);
2366 case 0x2a: /* Conditional branch (immediate) */
2367 disas_cond_b_imm(s
, insn
);
2369 case 0x6a: /* Exception generation / System */
2370 if (insn
& (1 << 24)) {
2371 if (extract32(insn
, 22, 2) == 0) {
2372 disas_system(s
, insn
);
2374 unallocated_encoding(s
);
2380 case 0x6b: /* Unconditional branch (register) */
2381 disas_uncond_b_reg(s
, insn
);
2384 unallocated_encoding(s
);
2390 * Load/Store exclusive instructions are implemented by remembering
2391 * the value/address loaded, and seeing if these are the same
2392 * when the store is performed. This is not actually the architecturally
2393 * mandated semantics, but it works for typical guest code sequences
2394 * and avoids having to monitor regular stores.
2396 * The store exclusive uses the atomic cmpxchg primitives to avoid
2397 * races in multi-threaded linux-user and when MTTCG softmmu is
2400 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2401 TCGv_i64 addr
, int size
, bool is_pair
)
2403 int idx
= get_mem_index(s
);
2404 MemOp memop
= s
->be_data
;
2406 g_assert(size
<= 3);
2408 g_assert(size
>= 2);
2410 /* The pair must be single-copy atomic for the doubleword. */
2411 memop
|= MO_64
| MO_ALIGN
;
2412 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2413 if (s
->be_data
== MO_LE
) {
2414 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2415 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2417 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2418 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2421 /* The pair must be single-copy atomic for *each* doubleword, not
2422 the entire quadword, however it must be quadword aligned. */
2424 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2425 memop
| MO_ALIGN_16
);
2427 TCGv_i64 addr2
= tcg_temp_new_i64();
2428 tcg_gen_addi_i64(addr2
, addr
, 8);
2429 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2430 tcg_temp_free_i64(addr2
);
2432 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2433 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2436 memop
|= size
| MO_ALIGN
;
2437 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2438 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2440 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2443 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2444 TCGv_i64 addr
, int size
, int is_pair
)
2446 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2447 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2450 * [addr + datasize] = {Rt2};
2456 * env->exclusive_addr = -1;
2458 TCGLabel
*fail_label
= gen_new_label();
2459 TCGLabel
*done_label
= gen_new_label();
2462 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2464 tmp
= tcg_temp_new_i64();
2467 if (s
->be_data
== MO_LE
) {
2468 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2470 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2472 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2473 cpu_exclusive_val
, tmp
,
2475 MO_64
| MO_ALIGN
| s
->be_data
);
2476 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2477 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2478 if (!HAVE_CMPXCHG128
) {
2479 gen_helper_exit_atomic(cpu_env
);
2480 s
->base
.is_jmp
= DISAS_NORETURN
;
2481 } else if (s
->be_data
== MO_LE
) {
2482 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2487 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2492 } else if (s
->be_data
== MO_LE
) {
2493 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2494 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2496 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2497 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2500 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2501 cpu_reg(s
, rt
), get_mem_index(s
),
2502 size
| MO_ALIGN
| s
->be_data
);
2503 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2505 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2506 tcg_temp_free_i64(tmp
);
2507 tcg_gen_br(done_label
);
2509 gen_set_label(fail_label
);
2510 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2511 gen_set_label(done_label
);
2512 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2515 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2518 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2519 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2520 int memidx
= get_mem_index(s
);
2521 TCGv_i64 clean_addr
;
2524 gen_check_sp_alignment(s
);
2526 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2527 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2528 size
| MO_ALIGN
| s
->be_data
);
2531 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2534 TCGv_i64 s1
= cpu_reg(s
, rs
);
2535 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2536 TCGv_i64 t1
= cpu_reg(s
, rt
);
2537 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2538 TCGv_i64 clean_addr
;
2539 int memidx
= get_mem_index(s
);
2542 gen_check_sp_alignment(s
);
2545 /* This is a single atomic access, despite the "pair". */
2546 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2549 TCGv_i64 cmp
= tcg_temp_new_i64();
2550 TCGv_i64 val
= tcg_temp_new_i64();
2552 if (s
->be_data
== MO_LE
) {
2553 tcg_gen_concat32_i64(val
, t1
, t2
);
2554 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2556 tcg_gen_concat32_i64(val
, t2
, t1
);
2557 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2560 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2561 MO_64
| MO_ALIGN
| s
->be_data
);
2562 tcg_temp_free_i64(val
);
2564 if (s
->be_data
== MO_LE
) {
2565 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2567 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2569 tcg_temp_free_i64(cmp
);
2570 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2571 if (HAVE_CMPXCHG128
) {
2572 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2573 if (s
->be_data
== MO_LE
) {
2574 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2575 clean_addr
, t1
, t2
);
2577 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2578 clean_addr
, t1
, t2
);
2580 tcg_temp_free_i32(tcg_rs
);
2582 gen_helper_exit_atomic(cpu_env
);
2583 s
->base
.is_jmp
= DISAS_NORETURN
;
2586 TCGv_i64 d1
= tcg_temp_new_i64();
2587 TCGv_i64 d2
= tcg_temp_new_i64();
2588 TCGv_i64 a2
= tcg_temp_new_i64();
2589 TCGv_i64 c1
= tcg_temp_new_i64();
2590 TCGv_i64 c2
= tcg_temp_new_i64();
2591 TCGv_i64 zero
= tcg_const_i64(0);
2593 /* Load the two words, in memory order. */
2594 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2595 MO_64
| MO_ALIGN_16
| s
->be_data
);
2596 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2597 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2599 /* Compare the two words, also in memory order. */
2600 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2601 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2602 tcg_gen_and_i64(c2
, c2
, c1
);
2604 /* If compare equal, write back new data, else write back old data. */
2605 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2606 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2607 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2608 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2609 tcg_temp_free_i64(a2
);
2610 tcg_temp_free_i64(c1
);
2611 tcg_temp_free_i64(c2
);
2612 tcg_temp_free_i64(zero
);
2614 /* Write back the data from memory to Rs. */
2615 tcg_gen_mov_i64(s1
, d1
);
2616 tcg_gen_mov_i64(s2
, d2
);
2617 tcg_temp_free_i64(d1
);
2618 tcg_temp_free_i64(d2
);
2622 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2623 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2625 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2627 int opc0
= extract32(opc
, 0, 1);
2631 regsize
= opc0
? 32 : 64;
2633 regsize
= size
== 3 ? 64 : 32;
2635 return regsize
== 64;
2638 /* Load/store exclusive
2640 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2641 * +-----+-------------+----+---+----+------+----+-------+------+------+
2642 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2643 * +-----+-------------+----+---+----+------+----+-------+------+------+
2645 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2646 * L: 0 -> store, 1 -> load
2647 * o2: 0 -> exclusive, 1 -> not
2648 * o1: 0 -> single register, 1 -> register pair
2649 * o0: 1 -> load-acquire/store-release, 0 -> not
2651 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2653 int rt
= extract32(insn
, 0, 5);
2654 int rn
= extract32(insn
, 5, 5);
2655 int rt2
= extract32(insn
, 10, 5);
2656 int rs
= extract32(insn
, 16, 5);
2657 int is_lasr
= extract32(insn
, 15, 1);
2658 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2659 int size
= extract32(insn
, 30, 2);
2660 TCGv_i64 clean_addr
;
2662 switch (o2_L_o1_o0
) {
2663 case 0x0: /* STXR */
2664 case 0x1: /* STLXR */
2666 gen_check_sp_alignment(s
);
2669 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2671 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2672 true, rn
!= 31, size
);
2673 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2676 case 0x4: /* LDXR */
2677 case 0x5: /* LDAXR */
2679 gen_check_sp_alignment(s
);
2681 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2682 false, rn
!= 31, size
);
2684 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2686 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2690 case 0x8: /* STLLR */
2691 if (!dc_isar_feature(aa64_lor
, s
)) {
2694 /* StoreLORelease is the same as Store-Release for QEMU. */
2696 case 0x9: /* STLR */
2697 /* Generate ISS for non-exclusive accesses including LASR. */
2699 gen_check_sp_alignment(s
);
2701 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2702 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2703 true, rn
!= 31, size
);
2704 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2705 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2708 case 0xc: /* LDLAR */
2709 if (!dc_isar_feature(aa64_lor
, s
)) {
2712 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2714 case 0xd: /* LDAR */
2715 /* Generate ISS for non-exclusive accesses including LASR. */
2717 gen_check_sp_alignment(s
);
2719 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2720 false, rn
!= 31, size
);
2721 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2722 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2723 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2726 case 0x2: case 0x3: /* CASP / STXP */
2727 if (size
& 2) { /* STXP / STLXP */
2729 gen_check_sp_alignment(s
);
2732 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2734 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2735 true, rn
!= 31, size
);
2736 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2740 && ((rt
| rs
) & 1) == 0
2741 && dc_isar_feature(aa64_atomics
, s
)) {
2743 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2748 case 0x6: case 0x7: /* CASPA / LDXP */
2749 if (size
& 2) { /* LDXP / LDAXP */
2751 gen_check_sp_alignment(s
);
2753 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2754 false, rn
!= 31, size
);
2756 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2758 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2763 && ((rt
| rs
) & 1) == 0
2764 && dc_isar_feature(aa64_atomics
, s
)) {
2765 /* CASPA / CASPAL */
2766 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2772 case 0xb: /* CASL */
2773 case 0xe: /* CASA */
2774 case 0xf: /* CASAL */
2775 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2776 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2781 unallocated_encoding(s
);
2785 * Load register (literal)
2787 * 31 30 29 27 26 25 24 23 5 4 0
2788 * +-----+-------+---+-----+-------------------+-------+
2789 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2790 * +-----+-------+---+-----+-------------------+-------+
2792 * V: 1 -> vector (simd/fp)
2793 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2794 * 10-> 32 bit signed, 11 -> prefetch
2795 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2797 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2799 int rt
= extract32(insn
, 0, 5);
2800 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2801 bool is_vector
= extract32(insn
, 26, 1);
2802 int opc
= extract32(insn
, 30, 2);
2803 bool is_signed
= false;
2805 TCGv_i64 tcg_rt
, clean_addr
;
2809 unallocated_encoding(s
);
2813 if (!fp_access_check(s
)) {
2818 /* PRFM (literal) : prefetch */
2821 size
= 2 + extract32(opc
, 0, 1);
2822 is_signed
= extract32(opc
, 1, 1);
2825 tcg_rt
= cpu_reg(s
, rt
);
2827 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2829 do_fp_ld(s
, rt
, clean_addr
, size
);
2831 /* Only unsigned 32bit loads target 32bit registers. */
2832 bool iss_sf
= opc
!= 0;
2834 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2835 true, rt
, iss_sf
, false);
2837 tcg_temp_free_i64(clean_addr
);
2841 * LDNP (Load Pair - non-temporal hint)
2842 * LDP (Load Pair - non vector)
2843 * LDPSW (Load Pair Signed Word - non vector)
2844 * STNP (Store Pair - non-temporal hint)
2845 * STP (Store Pair - non vector)
2846 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2847 * LDP (Load Pair of SIMD&FP)
2848 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2849 * STP (Store Pair of SIMD&FP)
2851 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2852 * +-----+-------+---+---+-------+---+-----------------------------+
2853 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2854 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2856 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2858 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2859 * V: 0 -> GPR, 1 -> Vector
2860 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2861 * 10 -> signed offset, 11 -> pre-index
2862 * L: 0 -> Store 1 -> Load
2864 * Rt, Rt2 = GPR or SIMD registers to be stored
2865 * Rn = general purpose register containing address
2866 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2868 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2870 int rt
= extract32(insn
, 0, 5);
2871 int rn
= extract32(insn
, 5, 5);
2872 int rt2
= extract32(insn
, 10, 5);
2873 uint64_t offset
= sextract64(insn
, 15, 7);
2874 int index
= extract32(insn
, 23, 2);
2875 bool is_vector
= extract32(insn
, 26, 1);
2876 bool is_load
= extract32(insn
, 22, 1);
2877 int opc
= extract32(insn
, 30, 2);
2879 bool is_signed
= false;
2880 bool postindex
= false;
2882 bool set_tag
= false;
2884 TCGv_i64 clean_addr
, dirty_addr
;
2889 unallocated_encoding(s
);
2895 } else if (opc
== 1 && !is_load
) {
2897 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2898 unallocated_encoding(s
);
2904 size
= 2 + extract32(opc
, 1, 1);
2905 is_signed
= extract32(opc
, 0, 1);
2906 if (!is_load
&& is_signed
) {
2907 unallocated_encoding(s
);
2913 case 1: /* post-index */
2918 /* signed offset with "non-temporal" hint. Since we don't emulate
2919 * caches we don't care about hints to the cache system about
2920 * data access patterns, and handle this identically to plain
2924 /* There is no non-temporal-hint version of LDPSW */
2925 unallocated_encoding(s
);
2930 case 2: /* signed offset, rn not updated */
2933 case 3: /* pre-index */
2939 if (is_vector
&& !fp_access_check(s
)) {
2943 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2946 gen_check_sp_alignment(s
);
2949 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2951 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2957 * TODO: We could rely on the stores below, at least for
2958 * system mode, if we arrange to add MO_ALIGN_16.
2960 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2961 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2962 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2964 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2968 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2969 (wback
|| rn
!= 31) && !set_tag
,
2974 do_fp_ld(s
, rt
, clean_addr
, size
);
2976 do_fp_st(s
, rt
, clean_addr
, size
);
2978 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2980 do_fp_ld(s
, rt2
, clean_addr
, size
);
2982 do_fp_st(s
, rt2
, clean_addr
, size
);
2985 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2986 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2989 TCGv_i64 tmp
= tcg_temp_new_i64();
2991 /* Do not modify tcg_rt before recognizing any exception
2992 * from the second load.
2994 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2995 false, 0, false, false);
2996 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2997 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2998 false, 0, false, false);
3000 tcg_gen_mov_i64(tcg_rt
, tmp
);
3001 tcg_temp_free_i64(tmp
);
3003 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3004 false, 0, false, false);
3005 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3006 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
3007 false, 0, false, false);
3013 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3015 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3020 * Load/store (immediate post-indexed)
3021 * Load/store (immediate pre-indexed)
3022 * Load/store (unscaled immediate)
3024 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
3025 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3026 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3027 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3029 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3031 * V = 0 -> non-vector
3032 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3033 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3035 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3041 int rn
= extract32(insn
, 5, 5);
3042 int imm9
= sextract32(insn
, 12, 9);
3043 int idx
= extract32(insn
, 10, 2);
3044 bool is_signed
= false;
3045 bool is_store
= false;
3046 bool is_extended
= false;
3047 bool is_unpriv
= (idx
== 2);
3048 bool iss_valid
= !is_vector
;
3053 TCGv_i64 clean_addr
, dirty_addr
;
3056 size
|= (opc
& 2) << 1;
3057 if (size
> 4 || is_unpriv
) {
3058 unallocated_encoding(s
);
3061 is_store
= ((opc
& 1) == 0);
3062 if (!fp_access_check(s
)) {
3066 if (size
== 3 && opc
== 2) {
3067 /* PRFM - prefetch */
3069 unallocated_encoding(s
);
3074 if (opc
== 3 && size
> 1) {
3075 unallocated_encoding(s
);
3078 is_store
= (opc
== 0);
3079 is_signed
= extract32(opc
, 1, 1);
3080 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3098 g_assert_not_reached();
3102 gen_check_sp_alignment(s
);
3105 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3107 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3110 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3111 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3112 writeback
|| rn
!= 31,
3113 size
, is_unpriv
, memidx
);
3117 do_fp_st(s
, rt
, clean_addr
, size
);
3119 do_fp_ld(s
, rt
, clean_addr
, size
);
3122 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3123 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3126 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3127 iss_valid
, rt
, iss_sf
, false);
3129 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
3130 is_signed
, is_extended
, memidx
,
3131 iss_valid
, rt
, iss_sf
, false);
3136 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3138 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3140 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3145 * Load/store (register offset)
3147 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3148 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3149 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3150 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3153 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3154 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3156 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3157 * opc<0>: 0 -> store, 1 -> load
3158 * V: 1 -> vector/simd
3159 * opt: extend encoding (see DecodeRegExtend)
3160 * S: if S=1 then scale (essentially index by sizeof(size))
3161 * Rt: register to transfer into/out of
3162 * Rn: address register or SP for base
3163 * Rm: offset register or ZR for offset
3165 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3171 int rn
= extract32(insn
, 5, 5);
3172 int shift
= extract32(insn
, 12, 1);
3173 int rm
= extract32(insn
, 16, 5);
3174 int opt
= extract32(insn
, 13, 3);
3175 bool is_signed
= false;
3176 bool is_store
= false;
3177 bool is_extended
= false;
3179 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3181 if (extract32(opt
, 1, 1) == 0) {
3182 unallocated_encoding(s
);
3187 size
|= (opc
& 2) << 1;
3189 unallocated_encoding(s
);
3192 is_store
= !extract32(opc
, 0, 1);
3193 if (!fp_access_check(s
)) {
3197 if (size
== 3 && opc
== 2) {
3198 /* PRFM - prefetch */
3201 if (opc
== 3 && size
> 1) {
3202 unallocated_encoding(s
);
3205 is_store
= (opc
== 0);
3206 is_signed
= extract32(opc
, 1, 1);
3207 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3211 gen_check_sp_alignment(s
);
3213 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3215 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3216 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3218 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3219 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3223 do_fp_st(s
, rt
, clean_addr
, size
);
3225 do_fp_ld(s
, rt
, clean_addr
, size
);
3228 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3229 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3231 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3232 true, rt
, iss_sf
, false);
3234 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3235 is_signed
, is_extended
,
3236 true, rt
, iss_sf
, false);
3242 * Load/store (unsigned immediate)
3244 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3245 * +----+-------+---+-----+-----+------------+-------+------+
3246 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3247 * +----+-------+---+-----+-----+------------+-------+------+
3250 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3251 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3253 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3254 * opc<0>: 0 -> store, 1 -> load
3255 * Rn: base address register (inc SP)
3256 * Rt: target register
3258 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3264 int rn
= extract32(insn
, 5, 5);
3265 unsigned int imm12
= extract32(insn
, 10, 12);
3266 unsigned int offset
;
3268 TCGv_i64 clean_addr
, dirty_addr
;
3271 bool is_signed
= false;
3272 bool is_extended
= false;
3275 size
|= (opc
& 2) << 1;
3277 unallocated_encoding(s
);
3280 is_store
= !extract32(opc
, 0, 1);
3281 if (!fp_access_check(s
)) {
3285 if (size
== 3 && opc
== 2) {
3286 /* PRFM - prefetch */
3289 if (opc
== 3 && size
> 1) {
3290 unallocated_encoding(s
);
3293 is_store
= (opc
== 0);
3294 is_signed
= extract32(opc
, 1, 1);
3295 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3299 gen_check_sp_alignment(s
);
3301 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3302 offset
= imm12
<< size
;
3303 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3304 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3308 do_fp_st(s
, rt
, clean_addr
, size
);
3310 do_fp_ld(s
, rt
, clean_addr
, size
);
3313 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3314 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3316 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3317 true, rt
, iss_sf
, false);
3319 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3320 true, rt
, iss_sf
, false);
3325 /* Atomic memory operations
3327 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3328 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3329 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3330 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3332 * Rt: the result register
3333 * Rn: base address or SP
3334 * Rs: the source register for the operation
3335 * V: vector flag (always 0 as of v8.3)
3339 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3340 int size
, int rt
, bool is_vector
)
3342 int rs
= extract32(insn
, 16, 5);
3343 int rn
= extract32(insn
, 5, 5);
3344 int o3_opc
= extract32(insn
, 12, 4);
3345 bool r
= extract32(insn
, 22, 1);
3346 bool a
= extract32(insn
, 23, 1);
3347 TCGv_i64 tcg_rs
, clean_addr
;
3348 AtomicThreeOpFn
*fn
= NULL
;
3350 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3351 unallocated_encoding(s
);
3355 case 000: /* LDADD */
3356 fn
= tcg_gen_atomic_fetch_add_i64
;
3358 case 001: /* LDCLR */
3359 fn
= tcg_gen_atomic_fetch_and_i64
;
3361 case 002: /* LDEOR */
3362 fn
= tcg_gen_atomic_fetch_xor_i64
;
3364 case 003: /* LDSET */
3365 fn
= tcg_gen_atomic_fetch_or_i64
;
3367 case 004: /* LDSMAX */
3368 fn
= tcg_gen_atomic_fetch_smax_i64
;
3370 case 005: /* LDSMIN */
3371 fn
= tcg_gen_atomic_fetch_smin_i64
;
3373 case 006: /* LDUMAX */
3374 fn
= tcg_gen_atomic_fetch_umax_i64
;
3376 case 007: /* LDUMIN */
3377 fn
= tcg_gen_atomic_fetch_umin_i64
;
3380 fn
= tcg_gen_atomic_xchg_i64
;
3382 case 014: /* LDAPR, LDAPRH, LDAPRB */
3383 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3384 rs
!= 31 || a
!= 1 || r
!= 0) {
3385 unallocated_encoding(s
);
3390 unallocated_encoding(s
);
3395 gen_check_sp_alignment(s
);
3397 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3399 if (o3_opc
== 014) {
3401 * LDAPR* are a special case because they are a simple load, not a
3402 * fetch-and-do-something op.
3403 * The architectural consistency requirements here are weaker than
3404 * full load-acquire (we only need "load-acquire processor consistent"),
3405 * but we choose to implement them as full LDAQ.
3407 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3408 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3409 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3413 tcg_rs
= read_cpu_reg(s
, rs
, true);
3415 if (o3_opc
== 1) { /* LDCLR */
3416 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3419 /* The tcg atomic primitives are all full barriers. Therefore we
3420 * can ignore the Acquire and Release bits of this instruction.
3422 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3423 s
->be_data
| size
| MO_ALIGN
);
3427 * PAC memory operations
3429 * 31 30 27 26 24 22 21 12 11 10 5 0
3430 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3431 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3432 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3434 * Rt: the result register
3435 * Rn: base address or SP
3436 * V: vector flag (always 0 as of v8.3)
3437 * M: clear for key DA, set for key DB
3438 * W: pre-indexing flag
3441 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3442 int size
, int rt
, bool is_vector
)
3444 int rn
= extract32(insn
, 5, 5);
3445 bool is_wback
= extract32(insn
, 11, 1);
3446 bool use_key_a
= !extract32(insn
, 23, 1);
3448 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3450 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3451 unallocated_encoding(s
);
3456 gen_check_sp_alignment(s
);
3458 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3460 if (s
->pauth_active
) {
3462 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3463 new_tmp_a64_zero(s
));
3465 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3466 new_tmp_a64_zero(s
));
3470 /* Form the 10-bit signed, scaled offset. */
3471 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3472 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3473 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3475 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3476 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3477 is_wback
|| rn
!= 31, size
);
3479 tcg_rt
= cpu_reg(s
, rt
);
3480 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3481 /* extend */ false, /* iss_valid */ !is_wback
,
3482 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3485 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3490 * LDAPR/STLR (unscaled immediate)
3492 * 31 30 24 22 21 12 10 5 0
3493 * +------+-------------+-----+---+--------+-----+----+-----+
3494 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3495 * +------+-------------+-----+---+--------+-----+----+-----+
3497 * Rt: source or destination register
3499 * imm9: unscaled immediate offset
3500 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3501 * size: size of load/store
3503 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3505 int rt
= extract32(insn
, 0, 5);
3506 int rn
= extract32(insn
, 5, 5);
3507 int offset
= sextract32(insn
, 12, 9);
3508 int opc
= extract32(insn
, 22, 2);
3509 int size
= extract32(insn
, 30, 2);
3510 TCGv_i64 clean_addr
, dirty_addr
;
3511 bool is_store
= false;
3512 bool is_signed
= false;
3513 bool extend
= false;
3516 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3517 unallocated_encoding(s
);
3522 case 0: /* STLURB */
3525 case 1: /* LDAPUR* */
3527 case 2: /* LDAPURS* 64-bit variant */
3529 unallocated_encoding(s
);
3534 case 3: /* LDAPURS* 32-bit variant */
3536 unallocated_encoding(s
);
3540 extend
= true; /* zero-extend 32->64 after signed load */
3543 g_assert_not_reached();
3546 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3549 gen_check_sp_alignment(s
);
3552 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3553 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3554 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3557 /* Store-Release semantics */
3558 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3559 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3562 * Load-AcquirePC semantics; we implement as the slightly more
3563 * restrictive Load-Acquire.
3565 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3566 true, rt
, iss_sf
, true);
3567 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3571 /* Load/store register (all forms) */
3572 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3574 int rt
= extract32(insn
, 0, 5);
3575 int opc
= extract32(insn
, 22, 2);
3576 bool is_vector
= extract32(insn
, 26, 1);
3577 int size
= extract32(insn
, 30, 2);
3579 switch (extract32(insn
, 24, 2)) {
3581 if (extract32(insn
, 21, 1) == 0) {
3582 /* Load/store register (unscaled immediate)
3583 * Load/store immediate pre/post-indexed
3584 * Load/store register unprivileged
3586 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3589 switch (extract32(insn
, 10, 2)) {
3591 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3594 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3597 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3602 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3605 unallocated_encoding(s
);
3608 /* AdvSIMD load/store multiple structures
3610 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3611 * +---+---+---------------+---+-------------+--------+------+------+------+
3612 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3613 * +---+---+---------------+---+-------------+--------+------+------+------+
3615 * AdvSIMD load/store multiple structures (post-indexed)
3617 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3618 * +---+---+---------------+---+---+---------+--------+------+------+------+
3619 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3620 * +---+---+---------------+---+---+---------+--------+------+------+------+
3622 * Rt: first (or only) SIMD&FP register to be transferred
3623 * Rn: base address or SP
3624 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3626 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3628 int rt
= extract32(insn
, 0, 5);
3629 int rn
= extract32(insn
, 5, 5);
3630 int rm
= extract32(insn
, 16, 5);
3631 int size
= extract32(insn
, 10, 2);
3632 int opcode
= extract32(insn
, 12, 4);
3633 bool is_store
= !extract32(insn
, 22, 1);
3634 bool is_postidx
= extract32(insn
, 23, 1);
3635 bool is_q
= extract32(insn
, 30, 1);
3636 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3637 MemOp endian
= s
->be_data
;
3639 int total
; /* total bytes */
3640 int elements
; /* elements per vector */
3641 int rpt
; /* num iterations */
3642 int selem
; /* structure elements */
3645 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3646 unallocated_encoding(s
);
3650 if (!is_postidx
&& rm
!= 0) {
3651 unallocated_encoding(s
);
3655 /* From the shared decode logic */
3686 unallocated_encoding(s
);
3690 if (size
== 3 && !is_q
&& selem
!= 1) {
3692 unallocated_encoding(s
);
3696 if (!fp_access_check(s
)) {
3701 gen_check_sp_alignment(s
);
3704 /* For our purposes, bytes are always little-endian. */
3709 total
= rpt
* selem
* (is_q
? 16 : 8);
3710 tcg_rn
= cpu_reg_sp(s
, rn
);
3713 * Issue the MTE check vs the logical repeat count, before we
3714 * promote consecutive little-endian elements below.
3716 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3720 * Consecutive little-endian elements from a single register
3721 * can be promoted to a larger little-endian operation.
3723 if (selem
== 1 && endian
== MO_LE
) {
3726 elements
= (is_q
? 16 : 8) >> size
;
3728 tcg_ebytes
= tcg_const_i64(1 << size
);
3729 for (r
= 0; r
< rpt
; r
++) {
3731 for (e
= 0; e
< elements
; e
++) {
3733 for (xs
= 0; xs
< selem
; xs
++) {
3734 int tt
= (rt
+ r
+ xs
) % 32;
3736 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3738 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3740 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3744 tcg_temp_free_i64(tcg_ebytes
);
3747 /* For non-quad operations, setting a slice of the low
3748 * 64 bits of the register clears the high 64 bits (in
3749 * the ARM ARM pseudocode this is implicit in the fact
3750 * that 'rval' is a 64 bit wide variable).
3751 * For quad operations, we might still need to zero the
3754 for (r
= 0; r
< rpt
* selem
; r
++) {
3755 int tt
= (rt
+ r
) % 32;
3756 clear_vec_high(s
, is_q
, tt
);
3762 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3764 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3769 /* AdvSIMD load/store single structure
3771 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3772 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3773 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3774 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3776 * AdvSIMD load/store single structure (post-indexed)
3778 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3779 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3780 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3781 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3783 * Rt: first (or only) SIMD&FP register to be transferred
3784 * Rn: base address or SP
3785 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3786 * index = encoded in Q:S:size dependent on size
3788 * lane_size = encoded in R, opc
3789 * transfer width = encoded in opc, S, size
3791 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3793 int rt
= extract32(insn
, 0, 5);
3794 int rn
= extract32(insn
, 5, 5);
3795 int rm
= extract32(insn
, 16, 5);
3796 int size
= extract32(insn
, 10, 2);
3797 int S
= extract32(insn
, 12, 1);
3798 int opc
= extract32(insn
, 13, 3);
3799 int R
= extract32(insn
, 21, 1);
3800 int is_load
= extract32(insn
, 22, 1);
3801 int is_postidx
= extract32(insn
, 23, 1);
3802 int is_q
= extract32(insn
, 30, 1);
3804 int scale
= extract32(opc
, 1, 2);
3805 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3806 bool replicate
= false;
3807 int index
= is_q
<< 3 | S
<< 2 | size
;
3809 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3811 if (extract32(insn
, 31, 1)) {
3812 unallocated_encoding(s
);
3815 if (!is_postidx
&& rm
!= 0) {
3816 unallocated_encoding(s
);
3822 if (!is_load
|| S
) {
3823 unallocated_encoding(s
);
3832 if (extract32(size
, 0, 1)) {
3833 unallocated_encoding(s
);
3839 if (extract32(size
, 1, 1)) {
3840 unallocated_encoding(s
);
3843 if (!extract32(size
, 0, 1)) {
3847 unallocated_encoding(s
);
3855 g_assert_not_reached();
3858 if (!fp_access_check(s
)) {
3863 gen_check_sp_alignment(s
);
3866 total
= selem
<< scale
;
3867 tcg_rn
= cpu_reg_sp(s
, rn
);
3869 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3872 tcg_ebytes
= tcg_const_i64(1 << scale
);
3873 for (xs
= 0; xs
< selem
; xs
++) {
3875 /* Load and replicate to all elements */
3876 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3878 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3879 get_mem_index(s
), s
->be_data
+ scale
);
3880 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3881 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3883 tcg_temp_free_i64(tcg_tmp
);
3885 /* Load/store one element per register */
3887 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3889 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3892 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3895 tcg_temp_free_i64(tcg_ebytes
);
3899 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3901 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3907 * Load/Store memory tags
3909 * 31 30 29 24 22 21 12 10 5 0
3910 * +-----+-------------+-----+---+------+-----+------+------+
3911 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3912 * +-----+-------------+-----+---+------+-----+------+------+
3914 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3916 int rt
= extract32(insn
, 0, 5);
3917 int rn
= extract32(insn
, 5, 5);
3918 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3919 int op2
= extract32(insn
, 10, 2);
3920 int op1
= extract32(insn
, 22, 2);
3921 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3923 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3925 /* We checked insn bits [29:24,21] in the caller. */
3926 if (extract32(insn
, 30, 2) != 3) {
3927 goto do_unallocated
;
3931 * @index is a tri-state variable which has 3 states:
3932 * < 0 : post-index, writeback
3933 * = 0 : signed offset
3934 * > 0 : pre-index, writeback
3943 if (s
->current_el
== 0 || offset
!= 0) {
3944 goto do_unallocated
;
3946 is_mult
= is_zero
= true;
3966 if (s
->current_el
== 0 || offset
!= 0) {
3967 goto do_unallocated
;
3975 is_pair
= is_zero
= true;
3979 if (s
->current_el
== 0 || offset
!= 0) {
3980 goto do_unallocated
;
3982 is_mult
= is_load
= true;
3988 unallocated_encoding(s
);
3993 ? !dc_isar_feature(aa64_mte
, s
)
3994 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
3995 goto do_unallocated
;
3999 gen_check_sp_alignment(s
);
4002 addr
= read_cpu_reg_sp(s
, rn
, true);
4004 /* pre-index or signed offset */
4005 tcg_gen_addi_i64(addr
, addr
, offset
);
4009 tcg_rt
= cpu_reg(s
, rt
);
4012 int size
= 4 << s
->dcz_blocksize
;
4015 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
4018 * The non-tags portion of STZGM is mostly like DC_ZVA,
4019 * except the alignment happens before the access.
4021 clean_addr
= clean_data_tbi(s
, addr
);
4022 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4023 gen_helper_dc_zva(cpu_env
, clean_addr
);
4024 } else if (s
->ata
) {
4026 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4028 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4031 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4032 int size
= 4 << GMID_EL1_BS
;
4034 clean_addr
= clean_data_tbi(s
, addr
);
4035 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4036 gen_probe_access(s
, clean_addr
, acc
, size
);
4039 /* The result tags are zeros. */
4040 tcg_gen_movi_i64(tcg_rt
, 0);
4047 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4048 tcg_rt
= cpu_reg(s
, rt
);
4050 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4052 clean_addr
= clean_data_tbi(s
, addr
);
4053 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4054 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4057 tcg_rt
= cpu_reg_sp(s
, rt
);
4060 * For STG and ST2G, we need to check alignment and probe memory.
4061 * TODO: For STZG and STZ2G, we could rely on the stores below,
4062 * at least for system mode; user-only won't enforce alignment.
4065 gen_helper_st2g_stub(cpu_env
, addr
);
4067 gen_helper_stg_stub(cpu_env
, addr
);
4069 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4071 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4073 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4077 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4079 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4085 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4086 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4087 int mem_index
= get_mem_index(s
);
4088 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4090 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4091 MO_Q
| MO_ALIGN_16
);
4092 for (i
= 8; i
< n
; i
+= 8) {
4093 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4094 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_Q
);
4096 tcg_temp_free_i64(tcg_zero
);
4100 /* pre-index or post-index */
4103 tcg_gen_addi_i64(addr
, addr
, offset
);
4105 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4109 /* Loads and stores */
4110 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4112 switch (extract32(insn
, 24, 6)) {
4113 case 0x08: /* Load/store exclusive */
4114 disas_ldst_excl(s
, insn
);
4116 case 0x18: case 0x1c: /* Load register (literal) */
4117 disas_ld_lit(s
, insn
);
4119 case 0x28: case 0x29:
4120 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4121 disas_ldst_pair(s
, insn
);
4123 case 0x38: case 0x39:
4124 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4125 disas_ldst_reg(s
, insn
);
4127 case 0x0c: /* AdvSIMD load/store multiple structures */
4128 disas_ldst_multiple_struct(s
, insn
);
4130 case 0x0d: /* AdvSIMD load/store single structure */
4131 disas_ldst_single_struct(s
, insn
);
4134 if (extract32(insn
, 21, 1) != 0) {
4135 disas_ldst_tag(s
, insn
);
4136 } else if (extract32(insn
, 10, 2) == 0) {
4137 disas_ldst_ldapr_stlr(s
, insn
);
4139 unallocated_encoding(s
);
4143 unallocated_encoding(s
);
4148 /* PC-rel. addressing
4149 * 31 30 29 28 24 23 5 4 0
4150 * +----+-------+-----------+-------------------+------+
4151 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4152 * +----+-------+-----------+-------------------+------+
4154 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4156 unsigned int page
, rd
;
4160 page
= extract32(insn
, 31, 1);
4161 /* SignExtend(immhi:immlo) -> offset */
4162 offset
= sextract64(insn
, 5, 19);
4163 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4164 rd
= extract32(insn
, 0, 5);
4168 /* ADRP (page based) */
4173 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4177 * Add/subtract (immediate)
4179 * 31 30 29 28 23 22 21 10 9 5 4 0
4180 * +--+--+--+-------------+--+-------------+-----+-----+
4181 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4182 * +--+--+--+-------------+--+-------------+-----+-----+
4184 * sf: 0 -> 32bit, 1 -> 64bit
4185 * op: 0 -> add , 1 -> sub
4187 * sh: 1 -> LSL imm by 12
4189 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4191 int rd
= extract32(insn
, 0, 5);
4192 int rn
= extract32(insn
, 5, 5);
4193 uint64_t imm
= extract32(insn
, 10, 12);
4194 bool shift
= extract32(insn
, 22, 1);
4195 bool setflags
= extract32(insn
, 29, 1);
4196 bool sub_op
= extract32(insn
, 30, 1);
4197 bool is_64bit
= extract32(insn
, 31, 1);
4199 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4200 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4201 TCGv_i64 tcg_result
;
4207 tcg_result
= tcg_temp_new_i64();
4210 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4212 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4215 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4217 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4219 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4221 tcg_temp_free_i64(tcg_imm
);
4225 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4227 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4230 tcg_temp_free_i64(tcg_result
);
4234 * Add/subtract (immediate, with tags)
4236 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4237 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4238 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4239 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4241 * op: 0 -> add, 1 -> sub
4243 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4245 int rd
= extract32(insn
, 0, 5);
4246 int rn
= extract32(insn
, 5, 5);
4247 int uimm4
= extract32(insn
, 10, 4);
4248 int uimm6
= extract32(insn
, 16, 6);
4249 bool sub_op
= extract32(insn
, 30, 1);
4250 TCGv_i64 tcg_rn
, tcg_rd
;
4253 /* Test all of sf=1, S=0, o2=0, o3=0. */
4254 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4255 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4256 unallocated_encoding(s
);
4260 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4265 tcg_rn
= cpu_reg_sp(s
, rn
);
4266 tcg_rd
= cpu_reg_sp(s
, rd
);
4269 TCGv_i32 offset
= tcg_const_i32(imm
);
4270 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4272 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4273 tcg_temp_free_i32(tag_offset
);
4274 tcg_temp_free_i32(offset
);
4276 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4277 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4281 /* The input should be a value in the bottom e bits (with higher
4282 * bits zero); returns that value replicated into every element
4283 * of size e in a 64 bit integer.
4285 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4295 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4296 static inline uint64_t bitmask64(unsigned int length
)
4298 assert(length
> 0 && length
<= 64);
4299 return ~0ULL >> (64 - length
);
4302 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4303 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4304 * value (ie should cause a guest UNDEF exception), and true if they are
4305 * valid, in which case the decoded bit pattern is written to result.
4307 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4308 unsigned int imms
, unsigned int immr
)
4311 unsigned e
, levels
, s
, r
;
4314 assert(immn
< 2 && imms
< 64 && immr
< 64);
4316 /* The bit patterns we create here are 64 bit patterns which
4317 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4318 * 64 bits each. Each element contains the same value: a run
4319 * of between 1 and e-1 non-zero bits, rotated within the
4320 * element by between 0 and e-1 bits.
4322 * The element size and run length are encoded into immn (1 bit)
4323 * and imms (6 bits) as follows:
4324 * 64 bit elements: immn = 1, imms = <length of run - 1>
4325 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4326 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4327 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4328 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4329 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4330 * Notice that immn = 0, imms = 11111x is the only combination
4331 * not covered by one of the above options; this is reserved.
4332 * Further, <length of run - 1> all-ones is a reserved pattern.
4334 * In all cases the rotation is by immr % e (and immr is 6 bits).
4337 /* First determine the element size */
4338 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4340 /* This is the immn == 0, imms == 0x11111x case */
4350 /* <length of run - 1> mustn't be all-ones. */
4354 /* Create the value of one element: s+1 set bits rotated
4355 * by r within the element (which is e bits wide)...
4357 mask
= bitmask64(s
+ 1);
4359 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4360 mask
&= bitmask64(e
);
4362 /* ...then replicate the element over the whole 64 bit value */
4363 mask
= bitfield_replicate(mask
, e
);
4368 /* Logical (immediate)
4369 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4370 * +----+-----+-------------+---+------+------+------+------+
4371 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4372 * +----+-----+-------------+---+------+------+------+------+
4374 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4376 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4377 TCGv_i64 tcg_rd
, tcg_rn
;
4379 bool is_and
= false;
4381 sf
= extract32(insn
, 31, 1);
4382 opc
= extract32(insn
, 29, 2);
4383 is_n
= extract32(insn
, 22, 1);
4384 immr
= extract32(insn
, 16, 6);
4385 imms
= extract32(insn
, 10, 6);
4386 rn
= extract32(insn
, 5, 5);
4387 rd
= extract32(insn
, 0, 5);
4390 unallocated_encoding(s
);
4394 if (opc
== 0x3) { /* ANDS */
4395 tcg_rd
= cpu_reg(s
, rd
);
4397 tcg_rd
= cpu_reg_sp(s
, rd
);
4399 tcg_rn
= cpu_reg(s
, rn
);
4401 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4402 /* some immediate field values are reserved */
4403 unallocated_encoding(s
);
4408 wmask
&= 0xffffffff;
4412 case 0x3: /* ANDS */
4414 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4418 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4421 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4424 assert(FALSE
); /* must handle all above */
4428 if (!sf
&& !is_and
) {
4429 /* zero extend final result; we know we can skip this for AND
4430 * since the immediate had the high 32 bits clear.
4432 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4435 if (opc
== 3) { /* ANDS */
4436 gen_logic_CC(sf
, tcg_rd
);
4441 * Move wide (immediate)
4443 * 31 30 29 28 23 22 21 20 5 4 0
4444 * +--+-----+-------------+-----+----------------+------+
4445 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4446 * +--+-----+-------------+-----+----------------+------+
4448 * sf: 0 -> 32 bit, 1 -> 64 bit
4449 * opc: 00 -> N, 10 -> Z, 11 -> K
4450 * hw: shift/16 (0,16, and sf only 32, 48)
4452 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4454 int rd
= extract32(insn
, 0, 5);
4455 uint64_t imm
= extract32(insn
, 5, 16);
4456 int sf
= extract32(insn
, 31, 1);
4457 int opc
= extract32(insn
, 29, 2);
4458 int pos
= extract32(insn
, 21, 2) << 4;
4459 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4462 if (!sf
&& (pos
>= 32)) {
4463 unallocated_encoding(s
);
4477 tcg_gen_movi_i64(tcg_rd
, imm
);
4480 tcg_imm
= tcg_const_i64(imm
);
4481 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4482 tcg_temp_free_i64(tcg_imm
);
4484 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4488 unallocated_encoding(s
);
4494 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4495 * +----+-----+-------------+---+------+------+------+------+
4496 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4497 * +----+-----+-------------+---+------+------+------+------+
4499 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4501 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4502 TCGv_i64 tcg_rd
, tcg_tmp
;
4504 sf
= extract32(insn
, 31, 1);
4505 opc
= extract32(insn
, 29, 2);
4506 n
= extract32(insn
, 22, 1);
4507 ri
= extract32(insn
, 16, 6);
4508 si
= extract32(insn
, 10, 6);
4509 rn
= extract32(insn
, 5, 5);
4510 rd
= extract32(insn
, 0, 5);
4511 bitsize
= sf
? 64 : 32;
4513 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4514 unallocated_encoding(s
);
4518 tcg_rd
= cpu_reg(s
, rd
);
4520 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4521 to be smaller than bitsize, we'll never reference data outside the
4522 low 32-bits anyway. */
4523 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4525 /* Recognize simple(r) extractions. */
4527 /* Wd<s-r:0> = Wn<s:r> */
4528 len
= (si
- ri
) + 1;
4529 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4530 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4532 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4533 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4536 /* opc == 1, BFXIL fall through to deposit */
4537 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4540 /* Handle the ri > si case with a deposit
4541 * Wd<32+s-r,32-r> = Wn<s:0>
4544 pos
= (bitsize
- ri
) & (bitsize
- 1);
4547 if (opc
== 0 && len
< ri
) {
4548 /* SBFM: sign extend the destination field from len to fill
4549 the balance of the word. Let the deposit below insert all
4550 of those sign bits. */
4551 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4555 if (opc
== 1) { /* BFM, BFXIL */
4556 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4558 /* SBFM or UBFM: We start with zero, and we haven't modified
4559 any bits outside bitsize, therefore the zero-extension
4560 below is unneeded. */
4561 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4566 if (!sf
) { /* zero extend final result */
4567 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4572 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4573 * +----+------+-------------+---+----+------+--------+------+------+
4574 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4575 * +----+------+-------------+---+----+------+--------+------+------+
4577 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4579 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4581 sf
= extract32(insn
, 31, 1);
4582 n
= extract32(insn
, 22, 1);
4583 rm
= extract32(insn
, 16, 5);
4584 imm
= extract32(insn
, 10, 6);
4585 rn
= extract32(insn
, 5, 5);
4586 rd
= extract32(insn
, 0, 5);
4587 op21
= extract32(insn
, 29, 2);
4588 op0
= extract32(insn
, 21, 1);
4589 bitsize
= sf
? 64 : 32;
4591 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4592 unallocated_encoding(s
);
4594 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4596 tcg_rd
= cpu_reg(s
, rd
);
4598 if (unlikely(imm
== 0)) {
4599 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4600 * so an extract from bit 0 is a special case.
4603 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4605 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4608 tcg_rm
= cpu_reg(s
, rm
);
4609 tcg_rn
= cpu_reg(s
, rn
);
4612 /* Specialization to ROR happens in EXTRACT2. */
4613 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4615 TCGv_i32 t0
= tcg_temp_new_i32();
4617 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4619 tcg_gen_rotri_i32(t0
, t0
, imm
);
4621 TCGv_i32 t1
= tcg_temp_new_i32();
4622 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4623 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4624 tcg_temp_free_i32(t1
);
4626 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4627 tcg_temp_free_i32(t0
);
4633 /* Data processing - immediate */
4634 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4636 switch (extract32(insn
, 23, 6)) {
4637 case 0x20: case 0x21: /* PC-rel. addressing */
4638 disas_pc_rel_adr(s
, insn
);
4640 case 0x22: /* Add/subtract (immediate) */
4641 disas_add_sub_imm(s
, insn
);
4643 case 0x23: /* Add/subtract (immediate, with tags) */
4644 disas_add_sub_imm_with_tags(s
, insn
);
4646 case 0x24: /* Logical (immediate) */
4647 disas_logic_imm(s
, insn
);
4649 case 0x25: /* Move wide (immediate) */
4650 disas_movw_imm(s
, insn
);
4652 case 0x26: /* Bitfield */
4653 disas_bitfield(s
, insn
);
4655 case 0x27: /* Extract */
4656 disas_extract(s
, insn
);
4659 unallocated_encoding(s
);
4664 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4665 * Note that it is the caller's responsibility to ensure that the
4666 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4667 * mandated semantics for out of range shifts.
4669 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4670 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4672 switch (shift_type
) {
4673 case A64_SHIFT_TYPE_LSL
:
4674 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4676 case A64_SHIFT_TYPE_LSR
:
4677 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4679 case A64_SHIFT_TYPE_ASR
:
4681 tcg_gen_ext32s_i64(dst
, src
);
4683 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4685 case A64_SHIFT_TYPE_ROR
:
4687 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4690 t0
= tcg_temp_new_i32();
4691 t1
= tcg_temp_new_i32();
4692 tcg_gen_extrl_i64_i32(t0
, src
);
4693 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4694 tcg_gen_rotr_i32(t0
, t0
, t1
);
4695 tcg_gen_extu_i32_i64(dst
, t0
);
4696 tcg_temp_free_i32(t0
);
4697 tcg_temp_free_i32(t1
);
4701 assert(FALSE
); /* all shift types should be handled */
4705 if (!sf
) { /* zero extend final result */
4706 tcg_gen_ext32u_i64(dst
, dst
);
4710 /* Shift a TCGv src by immediate, put result in dst.
4711 * The shift amount must be in range (this should always be true as the
4712 * relevant instructions will UNDEF on bad shift immediates).
4714 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4715 enum a64_shift_type shift_type
, unsigned int shift_i
)
4717 assert(shift_i
< (sf
? 64 : 32));
4720 tcg_gen_mov_i64(dst
, src
);
4722 TCGv_i64 shift_const
;
4724 shift_const
= tcg_const_i64(shift_i
);
4725 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4726 tcg_temp_free_i64(shift_const
);
4730 /* Logical (shifted register)
4731 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4732 * +----+-----+-----------+-------+---+------+--------+------+------+
4733 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4734 * +----+-----+-----------+-------+---+------+--------+------+------+
4736 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4738 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4739 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4741 sf
= extract32(insn
, 31, 1);
4742 opc
= extract32(insn
, 29, 2);
4743 shift_type
= extract32(insn
, 22, 2);
4744 invert
= extract32(insn
, 21, 1);
4745 rm
= extract32(insn
, 16, 5);
4746 shift_amount
= extract32(insn
, 10, 6);
4747 rn
= extract32(insn
, 5, 5);
4748 rd
= extract32(insn
, 0, 5);
4750 if (!sf
&& (shift_amount
& (1 << 5))) {
4751 unallocated_encoding(s
);
4755 tcg_rd
= cpu_reg(s
, rd
);
4757 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4758 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4759 * register-register MOV and MVN, so it is worth special casing.
4761 tcg_rm
= cpu_reg(s
, rm
);
4763 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4765 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4769 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4771 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4777 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4780 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4783 tcg_rn
= cpu_reg(s
, rn
);
4785 switch (opc
| (invert
<< 2)) {
4788 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4791 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4794 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4798 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4801 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4804 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4812 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4816 gen_logic_CC(sf
, tcg_rd
);
4821 * Add/subtract (extended register)
4823 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4824 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4825 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4826 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4828 * sf: 0 -> 32bit, 1 -> 64bit
4829 * op: 0 -> add , 1 -> sub
4832 * option: extension type (see DecodeRegExtend)
4833 * imm3: optional shift to Rm
4835 * Rd = Rn + LSL(extend(Rm), amount)
4837 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4839 int rd
= extract32(insn
, 0, 5);
4840 int rn
= extract32(insn
, 5, 5);
4841 int imm3
= extract32(insn
, 10, 3);
4842 int option
= extract32(insn
, 13, 3);
4843 int rm
= extract32(insn
, 16, 5);
4844 int opt
= extract32(insn
, 22, 2);
4845 bool setflags
= extract32(insn
, 29, 1);
4846 bool sub_op
= extract32(insn
, 30, 1);
4847 bool sf
= extract32(insn
, 31, 1);
4849 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4851 TCGv_i64 tcg_result
;
4853 if (imm3
> 4 || opt
!= 0) {
4854 unallocated_encoding(s
);
4858 /* non-flag setting ops may use SP */
4860 tcg_rd
= cpu_reg_sp(s
, rd
);
4862 tcg_rd
= cpu_reg(s
, rd
);
4864 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4866 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4867 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4869 tcg_result
= tcg_temp_new_i64();
4873 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4875 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4879 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4881 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4886 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4888 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4891 tcg_temp_free_i64(tcg_result
);
4895 * Add/subtract (shifted register)
4897 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4898 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4899 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4900 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4902 * sf: 0 -> 32bit, 1 -> 64bit
4903 * op: 0 -> add , 1 -> sub
4905 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4906 * imm6: Shift amount to apply to Rm before the add/sub
4908 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4910 int rd
= extract32(insn
, 0, 5);
4911 int rn
= extract32(insn
, 5, 5);
4912 int imm6
= extract32(insn
, 10, 6);
4913 int rm
= extract32(insn
, 16, 5);
4914 int shift_type
= extract32(insn
, 22, 2);
4915 bool setflags
= extract32(insn
, 29, 1);
4916 bool sub_op
= extract32(insn
, 30, 1);
4917 bool sf
= extract32(insn
, 31, 1);
4919 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4920 TCGv_i64 tcg_rn
, tcg_rm
;
4921 TCGv_i64 tcg_result
;
4923 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4924 unallocated_encoding(s
);
4928 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4929 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4931 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4933 tcg_result
= tcg_temp_new_i64();
4937 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4939 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4943 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4945 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4950 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4952 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4955 tcg_temp_free_i64(tcg_result
);
4958 /* Data-processing (3 source)
4960 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4961 * +--+------+-----------+------+------+----+------+------+------+
4962 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4963 * +--+------+-----------+------+------+----+------+------+------+
4965 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4967 int rd
= extract32(insn
, 0, 5);
4968 int rn
= extract32(insn
, 5, 5);
4969 int ra
= extract32(insn
, 10, 5);
4970 int rm
= extract32(insn
, 16, 5);
4971 int op_id
= (extract32(insn
, 29, 3) << 4) |
4972 (extract32(insn
, 21, 3) << 1) |
4973 extract32(insn
, 15, 1);
4974 bool sf
= extract32(insn
, 31, 1);
4975 bool is_sub
= extract32(op_id
, 0, 1);
4976 bool is_high
= extract32(op_id
, 2, 1);
4977 bool is_signed
= false;
4982 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4984 case 0x42: /* SMADDL */
4985 case 0x43: /* SMSUBL */
4986 case 0x44: /* SMULH */
4989 case 0x0: /* MADD (32bit) */
4990 case 0x1: /* MSUB (32bit) */
4991 case 0x40: /* MADD (64bit) */
4992 case 0x41: /* MSUB (64bit) */
4993 case 0x4a: /* UMADDL */
4994 case 0x4b: /* UMSUBL */
4995 case 0x4c: /* UMULH */
4998 unallocated_encoding(s
);
5003 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
5004 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5005 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5006 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
5009 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5011 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5014 tcg_temp_free_i64(low_bits
);
5018 tcg_op1
= tcg_temp_new_i64();
5019 tcg_op2
= tcg_temp_new_i64();
5020 tcg_tmp
= tcg_temp_new_i64();
5023 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
5024 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5027 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5028 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5030 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5031 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5035 if (ra
== 31 && !is_sub
) {
5036 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5037 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5039 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5041 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5043 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5048 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5051 tcg_temp_free_i64(tcg_op1
);
5052 tcg_temp_free_i64(tcg_op2
);
5053 tcg_temp_free_i64(tcg_tmp
);
5056 /* Add/subtract (with carry)
5057 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5058 * +--+--+--+------------------------+------+-------------+------+-----+
5059 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5060 * +--+--+--+------------------------+------+-------------+------+-----+
5063 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5065 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5066 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5068 sf
= extract32(insn
, 31, 1);
5069 op
= extract32(insn
, 30, 1);
5070 setflags
= extract32(insn
, 29, 1);
5071 rm
= extract32(insn
, 16, 5);
5072 rn
= extract32(insn
, 5, 5);
5073 rd
= extract32(insn
, 0, 5);
5075 tcg_rd
= cpu_reg(s
, rd
);
5076 tcg_rn
= cpu_reg(s
, rn
);
5079 tcg_y
= new_tmp_a64(s
);
5080 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5082 tcg_y
= cpu_reg(s
, rm
);
5086 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5088 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5093 * Rotate right into flags
5094 * 31 30 29 21 15 10 5 4 0
5095 * +--+--+--+-----------------+--------+-----------+------+--+------+
5096 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5097 * +--+--+--+-----------------+--------+-----------+------+--+------+
5099 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5101 int mask
= extract32(insn
, 0, 4);
5102 int o2
= extract32(insn
, 4, 1);
5103 int rn
= extract32(insn
, 5, 5);
5104 int imm6
= extract32(insn
, 15, 6);
5105 int sf_op_s
= extract32(insn
, 29, 3);
5109 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5110 unallocated_encoding(s
);
5114 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5115 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5117 nzcv
= tcg_temp_new_i32();
5118 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5120 if (mask
& 8) { /* N */
5121 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5123 if (mask
& 4) { /* Z */
5124 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5125 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5127 if (mask
& 2) { /* C */
5128 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5130 if (mask
& 1) { /* V */
5131 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5134 tcg_temp_free_i32(nzcv
);
5138 * Evaluate into flags
5139 * 31 30 29 21 15 14 10 5 4 0
5140 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5141 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5142 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5144 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5146 int o3_mask
= extract32(insn
, 0, 5);
5147 int rn
= extract32(insn
, 5, 5);
5148 int o2
= extract32(insn
, 15, 6);
5149 int sz
= extract32(insn
, 14, 1);
5150 int sf_op_s
= extract32(insn
, 29, 3);
5154 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5155 !dc_isar_feature(aa64_condm_4
, s
)) {
5156 unallocated_encoding(s
);
5159 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5161 tmp
= tcg_temp_new_i32();
5162 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5163 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5164 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5165 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5166 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5167 tcg_temp_free_i32(tmp
);
5170 /* Conditional compare (immediate / register)
5171 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5172 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5173 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5174 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5177 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5179 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5180 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5181 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5184 if (!extract32(insn
, 29, 1)) {
5185 unallocated_encoding(s
);
5188 if (insn
& (1 << 10 | 1 << 4)) {
5189 unallocated_encoding(s
);
5192 sf
= extract32(insn
, 31, 1);
5193 op
= extract32(insn
, 30, 1);
5194 is_imm
= extract32(insn
, 11, 1);
5195 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5196 cond
= extract32(insn
, 12, 4);
5197 rn
= extract32(insn
, 5, 5);
5198 nzcv
= extract32(insn
, 0, 4);
5200 /* Set T0 = !COND. */
5201 tcg_t0
= tcg_temp_new_i32();
5202 arm_test_cc(&c
, cond
);
5203 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5206 /* Load the arguments for the new comparison. */
5208 tcg_y
= new_tmp_a64(s
);
5209 tcg_gen_movi_i64(tcg_y
, y
);
5211 tcg_y
= cpu_reg(s
, y
);
5213 tcg_rn
= cpu_reg(s
, rn
);
5215 /* Set the flags for the new comparison. */
5216 tcg_tmp
= tcg_temp_new_i64();
5218 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5220 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5222 tcg_temp_free_i64(tcg_tmp
);
5224 /* If COND was false, force the flags to #nzcv. Compute two masks
5225 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5226 * For tcg hosts that support ANDC, we can make do with just T1.
5227 * In either case, allow the tcg optimizer to delete any unused mask.
5229 tcg_t1
= tcg_temp_new_i32();
5230 tcg_t2
= tcg_temp_new_i32();
5231 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5232 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5234 if (nzcv
& 8) { /* N */
5235 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5237 if (TCG_TARGET_HAS_andc_i32
) {
5238 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5240 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5243 if (nzcv
& 4) { /* Z */
5244 if (TCG_TARGET_HAS_andc_i32
) {
5245 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5247 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5250 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5252 if (nzcv
& 2) { /* C */
5253 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5255 if (TCG_TARGET_HAS_andc_i32
) {
5256 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5258 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5261 if (nzcv
& 1) { /* V */
5262 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5264 if (TCG_TARGET_HAS_andc_i32
) {
5265 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5267 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5270 tcg_temp_free_i32(tcg_t0
);
5271 tcg_temp_free_i32(tcg_t1
);
5272 tcg_temp_free_i32(tcg_t2
);
5275 /* Conditional select
5276 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5277 * +----+----+---+-----------------+------+------+-----+------+------+
5278 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5279 * +----+----+---+-----------------+------+------+-----+------+------+
5281 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5283 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5284 TCGv_i64 tcg_rd
, zero
;
5287 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5288 /* S == 1 or op2<1> == 1 */
5289 unallocated_encoding(s
);
5292 sf
= extract32(insn
, 31, 1);
5293 else_inv
= extract32(insn
, 30, 1);
5294 rm
= extract32(insn
, 16, 5);
5295 cond
= extract32(insn
, 12, 4);
5296 else_inc
= extract32(insn
, 10, 1);
5297 rn
= extract32(insn
, 5, 5);
5298 rd
= extract32(insn
, 0, 5);
5300 tcg_rd
= cpu_reg(s
, rd
);
5302 a64_test_cc(&c
, cond
);
5303 zero
= tcg_const_i64(0);
5305 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5307 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5309 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5312 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5313 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5314 if (else_inv
&& else_inc
) {
5315 tcg_gen_neg_i64(t_false
, t_false
);
5316 } else if (else_inv
) {
5317 tcg_gen_not_i64(t_false
, t_false
);
5318 } else if (else_inc
) {
5319 tcg_gen_addi_i64(t_false
, t_false
, 1);
5321 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5324 tcg_temp_free_i64(zero
);
5328 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5332 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5333 unsigned int rn
, unsigned int rd
)
5335 TCGv_i64 tcg_rd
, tcg_rn
;
5336 tcg_rd
= cpu_reg(s
, rd
);
5337 tcg_rn
= cpu_reg(s
, rn
);
5340 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5342 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5343 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5344 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5345 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5346 tcg_temp_free_i32(tcg_tmp32
);
5350 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5351 unsigned int rn
, unsigned int rd
)
5353 TCGv_i64 tcg_rd
, tcg_rn
;
5354 tcg_rd
= cpu_reg(s
, rd
);
5355 tcg_rn
= cpu_reg(s
, rn
);
5358 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5360 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5361 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5362 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5363 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5364 tcg_temp_free_i32(tcg_tmp32
);
5368 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5369 unsigned int rn
, unsigned int rd
)
5371 TCGv_i64 tcg_rd
, tcg_rn
;
5372 tcg_rd
= cpu_reg(s
, rd
);
5373 tcg_rn
= cpu_reg(s
, rn
);
5376 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5378 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5379 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5380 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5381 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5382 tcg_temp_free_i32(tcg_tmp32
);
5386 /* REV with sf==1, opcode==3 ("REV64") */
5387 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5388 unsigned int rn
, unsigned int rd
)
5391 unallocated_encoding(s
);
5394 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5397 /* REV with sf==0, opcode==2
5398 * REV32 (sf==1, opcode==2)
5400 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5401 unsigned int rn
, unsigned int rd
)
5403 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5406 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5407 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5409 /* bswap32_i64 requires zero high word */
5410 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
5411 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
5412 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
5413 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
5414 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5416 tcg_temp_free_i64(tcg_tmp
);
5418 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
5419 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
5423 /* REV16 (opcode==1) */
5424 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5425 unsigned int rn
, unsigned int rd
)
5427 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5428 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5429 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5430 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5432 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5433 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5434 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5435 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5436 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5438 tcg_temp_free_i64(mask
);
5439 tcg_temp_free_i64(tcg_tmp
);
5442 /* Data-processing (1 source)
5443 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5444 * +----+---+---+-----------------+---------+--------+------+------+
5445 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5446 * +----+---+---+-----------------+---------+--------+------+------+
5448 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5450 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5453 if (extract32(insn
, 29, 1)) {
5454 unallocated_encoding(s
);
5458 sf
= extract32(insn
, 31, 1);
5459 opcode
= extract32(insn
, 10, 6);
5460 opcode2
= extract32(insn
, 16, 5);
5461 rn
= extract32(insn
, 5, 5);
5462 rd
= extract32(insn
, 0, 5);
5464 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5466 switch (MAP(sf
, opcode2
, opcode
)) {
5467 case MAP(0, 0x00, 0x00): /* RBIT */
5468 case MAP(1, 0x00, 0x00):
5469 handle_rbit(s
, sf
, rn
, rd
);
5471 case MAP(0, 0x00, 0x01): /* REV16 */
5472 case MAP(1, 0x00, 0x01):
5473 handle_rev16(s
, sf
, rn
, rd
);
5475 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5476 case MAP(1, 0x00, 0x02):
5477 handle_rev32(s
, sf
, rn
, rd
);
5479 case MAP(1, 0x00, 0x03): /* REV64 */
5480 handle_rev64(s
, sf
, rn
, rd
);
5482 case MAP(0, 0x00, 0x04): /* CLZ */
5483 case MAP(1, 0x00, 0x04):
5484 handle_clz(s
, sf
, rn
, rd
);
5486 case MAP(0, 0x00, 0x05): /* CLS */
5487 case MAP(1, 0x00, 0x05):
5488 handle_cls(s
, sf
, rn
, rd
);
5490 case MAP(1, 0x01, 0x00): /* PACIA */
5491 if (s
->pauth_active
) {
5492 tcg_rd
= cpu_reg(s
, rd
);
5493 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5494 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5495 goto do_unallocated
;
5498 case MAP(1, 0x01, 0x01): /* PACIB */
5499 if (s
->pauth_active
) {
5500 tcg_rd
= cpu_reg(s
, rd
);
5501 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5502 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5503 goto do_unallocated
;
5506 case MAP(1, 0x01, 0x02): /* PACDA */
5507 if (s
->pauth_active
) {
5508 tcg_rd
= cpu_reg(s
, rd
);
5509 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5510 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5511 goto do_unallocated
;
5514 case MAP(1, 0x01, 0x03): /* PACDB */
5515 if (s
->pauth_active
) {
5516 tcg_rd
= cpu_reg(s
, rd
);
5517 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5518 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5519 goto do_unallocated
;
5522 case MAP(1, 0x01, 0x04): /* AUTIA */
5523 if (s
->pauth_active
) {
5524 tcg_rd
= cpu_reg(s
, rd
);
5525 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5526 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5527 goto do_unallocated
;
5530 case MAP(1, 0x01, 0x05): /* AUTIB */
5531 if (s
->pauth_active
) {
5532 tcg_rd
= cpu_reg(s
, rd
);
5533 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5534 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5535 goto do_unallocated
;
5538 case MAP(1, 0x01, 0x06): /* AUTDA */
5539 if (s
->pauth_active
) {
5540 tcg_rd
= cpu_reg(s
, rd
);
5541 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5542 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5543 goto do_unallocated
;
5546 case MAP(1, 0x01, 0x07): /* AUTDB */
5547 if (s
->pauth_active
) {
5548 tcg_rd
= cpu_reg(s
, rd
);
5549 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5550 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5551 goto do_unallocated
;
5554 case MAP(1, 0x01, 0x08): /* PACIZA */
5555 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5556 goto do_unallocated
;
5557 } else if (s
->pauth_active
) {
5558 tcg_rd
= cpu_reg(s
, rd
);
5559 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5562 case MAP(1, 0x01, 0x09): /* PACIZB */
5563 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5564 goto do_unallocated
;
5565 } else if (s
->pauth_active
) {
5566 tcg_rd
= cpu_reg(s
, rd
);
5567 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5570 case MAP(1, 0x01, 0x0a): /* PACDZA */
5571 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5572 goto do_unallocated
;
5573 } else if (s
->pauth_active
) {
5574 tcg_rd
= cpu_reg(s
, rd
);
5575 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5578 case MAP(1, 0x01, 0x0b): /* PACDZB */
5579 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5580 goto do_unallocated
;
5581 } else if (s
->pauth_active
) {
5582 tcg_rd
= cpu_reg(s
, rd
);
5583 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5586 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5587 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5588 goto do_unallocated
;
5589 } else if (s
->pauth_active
) {
5590 tcg_rd
= cpu_reg(s
, rd
);
5591 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5594 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5595 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5596 goto do_unallocated
;
5597 } else if (s
->pauth_active
) {
5598 tcg_rd
= cpu_reg(s
, rd
);
5599 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5602 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5603 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5604 goto do_unallocated
;
5605 } else if (s
->pauth_active
) {
5606 tcg_rd
= cpu_reg(s
, rd
);
5607 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5610 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5611 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5612 goto do_unallocated
;
5613 } else if (s
->pauth_active
) {
5614 tcg_rd
= cpu_reg(s
, rd
);
5615 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5618 case MAP(1, 0x01, 0x10): /* XPACI */
5619 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5620 goto do_unallocated
;
5621 } else if (s
->pauth_active
) {
5622 tcg_rd
= cpu_reg(s
, rd
);
5623 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5626 case MAP(1, 0x01, 0x11): /* XPACD */
5627 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5628 goto do_unallocated
;
5629 } else if (s
->pauth_active
) {
5630 tcg_rd
= cpu_reg(s
, rd
);
5631 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5636 unallocated_encoding(s
);
5643 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5644 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5646 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5647 tcg_rd
= cpu_reg(s
, rd
);
5649 if (!sf
&& is_signed
) {
5650 tcg_n
= new_tmp_a64(s
);
5651 tcg_m
= new_tmp_a64(s
);
5652 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5653 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5655 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5656 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5660 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5662 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5665 if (!sf
) { /* zero extend final result */
5666 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5670 /* LSLV, LSRV, ASRV, RORV */
5671 static void handle_shift_reg(DisasContext
*s
,
5672 enum a64_shift_type shift_type
, unsigned int sf
,
5673 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5675 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5676 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5677 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5679 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5680 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5681 tcg_temp_free_i64(tcg_shift
);
5684 /* CRC32[BHWX], CRC32C[BHWX] */
5685 static void handle_crc32(DisasContext
*s
,
5686 unsigned int sf
, unsigned int sz
, bool crc32c
,
5687 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5689 TCGv_i64 tcg_acc
, tcg_val
;
5692 if (!dc_isar_feature(aa64_crc32
, s
)
5693 || (sf
== 1 && sz
!= 3)
5694 || (sf
== 0 && sz
== 3)) {
5695 unallocated_encoding(s
);
5700 tcg_val
= cpu_reg(s
, rm
);
5714 g_assert_not_reached();
5716 tcg_val
= new_tmp_a64(s
);
5717 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5720 tcg_acc
= cpu_reg(s
, rn
);
5721 tcg_bytes
= tcg_const_i32(1 << sz
);
5724 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5726 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5729 tcg_temp_free_i32(tcg_bytes
);
5732 /* Data-processing (2 source)
5733 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5734 * +----+---+---+-----------------+------+--------+------+------+
5735 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5736 * +----+---+---+-----------------+------+--------+------+------+
5738 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5740 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5741 sf
= extract32(insn
, 31, 1);
5742 setflag
= extract32(insn
, 29, 1);
5743 rm
= extract32(insn
, 16, 5);
5744 opcode
= extract32(insn
, 10, 6);
5745 rn
= extract32(insn
, 5, 5);
5746 rd
= extract32(insn
, 0, 5);
5748 if (setflag
&& opcode
!= 0) {
5749 unallocated_encoding(s
);
5754 case 0: /* SUBP(S) */
5755 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5756 goto do_unallocated
;
5758 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5760 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5761 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5762 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5763 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5764 tcg_d
= cpu_reg(s
, rd
);
5767 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5769 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5774 handle_div(s
, false, sf
, rm
, rn
, rd
);
5777 handle_div(s
, true, sf
, rm
, rn
, rd
);
5780 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5781 goto do_unallocated
;
5784 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5785 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5787 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5792 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5793 goto do_unallocated
;
5795 TCGv_i64 t1
= tcg_const_i64(1);
5796 TCGv_i64 t2
= tcg_temp_new_i64();
5798 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5799 tcg_gen_shl_i64(t1
, t1
, t2
);
5800 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5802 tcg_temp_free_i64(t1
);
5803 tcg_temp_free_i64(t2
);
5807 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5810 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5813 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5816 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5818 case 12: /* PACGA */
5819 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5820 goto do_unallocated
;
5822 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5823 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5832 case 23: /* CRC32 */
5834 int sz
= extract32(opcode
, 0, 2);
5835 bool crc32c
= extract32(opcode
, 2, 1);
5836 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5841 unallocated_encoding(s
);
5847 * Data processing - register
5848 * 31 30 29 28 25 21 20 16 10 0
5849 * +--+---+--+---+-------+-----+-------+-------+---------+
5850 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5851 * +--+---+--+---+-------+-----+-------+-------+---------+
5853 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5855 int op0
= extract32(insn
, 30, 1);
5856 int op1
= extract32(insn
, 28, 1);
5857 int op2
= extract32(insn
, 21, 4);
5858 int op3
= extract32(insn
, 10, 6);
5863 /* Add/sub (extended register) */
5864 disas_add_sub_ext_reg(s
, insn
);
5866 /* Add/sub (shifted register) */
5867 disas_add_sub_reg(s
, insn
);
5870 /* Logical (shifted register) */
5871 disas_logic_reg(s
, insn
);
5879 case 0x00: /* Add/subtract (with carry) */
5880 disas_adc_sbc(s
, insn
);
5883 case 0x01: /* Rotate right into flags */
5885 disas_rotate_right_into_flags(s
, insn
);
5888 case 0x02: /* Evaluate into flags */
5892 disas_evaluate_into_flags(s
, insn
);
5896 goto do_unallocated
;
5900 case 0x2: /* Conditional compare */
5901 disas_cc(s
, insn
); /* both imm and reg forms */
5904 case 0x4: /* Conditional select */
5905 disas_cond_select(s
, insn
);
5908 case 0x6: /* Data-processing */
5909 if (op0
) { /* (1 source) */
5910 disas_data_proc_1src(s
, insn
);
5911 } else { /* (2 source) */
5912 disas_data_proc_2src(s
, insn
);
5915 case 0x8 ... 0xf: /* (3 source) */
5916 disas_data_proc_3src(s
, insn
);
5921 unallocated_encoding(s
);
5926 static void handle_fp_compare(DisasContext
*s
, int size
,
5927 unsigned int rn
, unsigned int rm
,
5928 bool cmp_with_zero
, bool signal_all_nans
)
5930 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5931 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5933 if (size
== MO_64
) {
5934 TCGv_i64 tcg_vn
, tcg_vm
;
5936 tcg_vn
= read_fp_dreg(s
, rn
);
5937 if (cmp_with_zero
) {
5938 tcg_vm
= tcg_const_i64(0);
5940 tcg_vm
= read_fp_dreg(s
, rm
);
5942 if (signal_all_nans
) {
5943 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5945 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5947 tcg_temp_free_i64(tcg_vn
);
5948 tcg_temp_free_i64(tcg_vm
);
5950 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5951 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5953 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5954 if (cmp_with_zero
) {
5955 tcg_gen_movi_i32(tcg_vm
, 0);
5957 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5962 if (signal_all_nans
) {
5963 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5965 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5969 if (signal_all_nans
) {
5970 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5972 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5976 g_assert_not_reached();
5979 tcg_temp_free_i32(tcg_vn
);
5980 tcg_temp_free_i32(tcg_vm
);
5983 tcg_temp_free_ptr(fpst
);
5985 gen_set_nzcv(tcg_flags
);
5987 tcg_temp_free_i64(tcg_flags
);
5990 /* Floating point compare
5991 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5992 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5993 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5994 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5996 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5998 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
6001 mos
= extract32(insn
, 29, 3);
6002 type
= extract32(insn
, 22, 2);
6003 rm
= extract32(insn
, 16, 5);
6004 op
= extract32(insn
, 14, 2);
6005 rn
= extract32(insn
, 5, 5);
6006 opc
= extract32(insn
, 3, 2);
6007 op2r
= extract32(insn
, 0, 3);
6009 if (mos
|| op
|| op2r
) {
6010 unallocated_encoding(s
);
6023 if (dc_isar_feature(aa64_fp16
, s
)) {
6028 unallocated_encoding(s
);
6032 if (!fp_access_check(s
)) {
6036 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6039 /* Floating point conditional compare
6040 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6041 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6042 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6043 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6045 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6047 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6049 TCGLabel
*label_continue
= NULL
;
6052 mos
= extract32(insn
, 29, 3);
6053 type
= extract32(insn
, 22, 2);
6054 rm
= extract32(insn
, 16, 5);
6055 cond
= extract32(insn
, 12, 4);
6056 rn
= extract32(insn
, 5, 5);
6057 op
= extract32(insn
, 4, 1);
6058 nzcv
= extract32(insn
, 0, 4);
6061 unallocated_encoding(s
);
6074 if (dc_isar_feature(aa64_fp16
, s
)) {
6079 unallocated_encoding(s
);
6083 if (!fp_access_check(s
)) {
6087 if (cond
< 0x0e) { /* not always */
6088 TCGLabel
*label_match
= gen_new_label();
6089 label_continue
= gen_new_label();
6090 arm_gen_test_cc(cond
, label_match
);
6092 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6093 gen_set_nzcv(tcg_flags
);
6094 tcg_temp_free_i64(tcg_flags
);
6095 tcg_gen_br(label_continue
);
6096 gen_set_label(label_match
);
6099 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6102 gen_set_label(label_continue
);
6106 /* Floating point conditional select
6107 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6108 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6109 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6110 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6112 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6114 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6115 TCGv_i64 t_true
, t_false
, t_zero
;
6119 mos
= extract32(insn
, 29, 3);
6120 type
= extract32(insn
, 22, 2);
6121 rm
= extract32(insn
, 16, 5);
6122 cond
= extract32(insn
, 12, 4);
6123 rn
= extract32(insn
, 5, 5);
6124 rd
= extract32(insn
, 0, 5);
6127 unallocated_encoding(s
);
6140 if (dc_isar_feature(aa64_fp16
, s
)) {
6145 unallocated_encoding(s
);
6149 if (!fp_access_check(s
)) {
6153 /* Zero extend sreg & hreg inputs to 64 bits now. */
6154 t_true
= tcg_temp_new_i64();
6155 t_false
= tcg_temp_new_i64();
6156 read_vec_element(s
, t_true
, rn
, 0, sz
);
6157 read_vec_element(s
, t_false
, rm
, 0, sz
);
6159 a64_test_cc(&c
, cond
);
6160 t_zero
= tcg_const_i64(0);
6161 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6162 tcg_temp_free_i64(t_zero
);
6163 tcg_temp_free_i64(t_false
);
6166 /* Note that sregs & hregs write back zeros to the high bits,
6167 and we've already done the zero-extension. */
6168 write_fp_dreg(s
, rd
, t_true
);
6169 tcg_temp_free_i64(t_true
);
6172 /* Floating-point data-processing (1 source) - half precision */
6173 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6175 TCGv_ptr fpst
= NULL
;
6176 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6177 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6180 case 0x0: /* FMOV */
6181 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6183 case 0x1: /* FABS */
6184 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6186 case 0x2: /* FNEG */
6187 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6189 case 0x3: /* FSQRT */
6190 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6191 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6193 case 0x8: /* FRINTN */
6194 case 0x9: /* FRINTP */
6195 case 0xa: /* FRINTM */
6196 case 0xb: /* FRINTZ */
6197 case 0xc: /* FRINTA */
6199 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6200 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6202 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6203 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6205 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6206 tcg_temp_free_i32(tcg_rmode
);
6209 case 0xe: /* FRINTX */
6210 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6211 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6213 case 0xf: /* FRINTI */
6214 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6215 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6221 write_fp_sreg(s
, rd
, tcg_res
);
6224 tcg_temp_free_ptr(fpst
);
6226 tcg_temp_free_i32(tcg_op
);
6227 tcg_temp_free_i32(tcg_res
);
6230 /* Floating-point data-processing (1 source) - single precision */
6231 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6233 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6234 TCGv_i32 tcg_op
, tcg_res
;
6238 tcg_op
= read_fp_sreg(s
, rn
);
6239 tcg_res
= tcg_temp_new_i32();
6242 case 0x0: /* FMOV */
6243 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6245 case 0x1: /* FABS */
6246 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6248 case 0x2: /* FNEG */
6249 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6251 case 0x3: /* FSQRT */
6252 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6254 case 0x8: /* FRINTN */
6255 case 0x9: /* FRINTP */
6256 case 0xa: /* FRINTM */
6257 case 0xb: /* FRINTZ */
6258 case 0xc: /* FRINTA */
6259 rmode
= arm_rmode_to_sf(opcode
& 7);
6260 gen_fpst
= gen_helper_rints
;
6262 case 0xe: /* FRINTX */
6263 gen_fpst
= gen_helper_rints_exact
;
6265 case 0xf: /* FRINTI */
6266 gen_fpst
= gen_helper_rints
;
6268 case 0x10: /* FRINT32Z */
6269 rmode
= float_round_to_zero
;
6270 gen_fpst
= gen_helper_frint32_s
;
6272 case 0x11: /* FRINT32X */
6273 gen_fpst
= gen_helper_frint32_s
;
6275 case 0x12: /* FRINT64Z */
6276 rmode
= float_round_to_zero
;
6277 gen_fpst
= gen_helper_frint64_s
;
6279 case 0x13: /* FRINT64X */
6280 gen_fpst
= gen_helper_frint64_s
;
6283 g_assert_not_reached();
6286 fpst
= fpstatus_ptr(FPST_FPCR
);
6288 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6289 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6290 gen_fpst(tcg_res
, tcg_op
, fpst
);
6291 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6292 tcg_temp_free_i32(tcg_rmode
);
6294 gen_fpst(tcg_res
, tcg_op
, fpst
);
6296 tcg_temp_free_ptr(fpst
);
6299 write_fp_sreg(s
, rd
, tcg_res
);
6300 tcg_temp_free_i32(tcg_op
);
6301 tcg_temp_free_i32(tcg_res
);
6304 /* Floating-point data-processing (1 source) - double precision */
6305 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6307 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6308 TCGv_i64 tcg_op
, tcg_res
;
6313 case 0x0: /* FMOV */
6314 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6318 tcg_op
= read_fp_dreg(s
, rn
);
6319 tcg_res
= tcg_temp_new_i64();
6322 case 0x1: /* FABS */
6323 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6325 case 0x2: /* FNEG */
6326 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6328 case 0x3: /* FSQRT */
6329 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6331 case 0x8: /* FRINTN */
6332 case 0x9: /* FRINTP */
6333 case 0xa: /* FRINTM */
6334 case 0xb: /* FRINTZ */
6335 case 0xc: /* FRINTA */
6336 rmode
= arm_rmode_to_sf(opcode
& 7);
6337 gen_fpst
= gen_helper_rintd
;
6339 case 0xe: /* FRINTX */
6340 gen_fpst
= gen_helper_rintd_exact
;
6342 case 0xf: /* FRINTI */
6343 gen_fpst
= gen_helper_rintd
;
6345 case 0x10: /* FRINT32Z */
6346 rmode
= float_round_to_zero
;
6347 gen_fpst
= gen_helper_frint32_d
;
6349 case 0x11: /* FRINT32X */
6350 gen_fpst
= gen_helper_frint32_d
;
6352 case 0x12: /* FRINT64Z */
6353 rmode
= float_round_to_zero
;
6354 gen_fpst
= gen_helper_frint64_d
;
6356 case 0x13: /* FRINT64X */
6357 gen_fpst
= gen_helper_frint64_d
;
6360 g_assert_not_reached();
6363 fpst
= fpstatus_ptr(FPST_FPCR
);
6365 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6366 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6367 gen_fpst(tcg_res
, tcg_op
, fpst
);
6368 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6369 tcg_temp_free_i32(tcg_rmode
);
6371 gen_fpst(tcg_res
, tcg_op
, fpst
);
6373 tcg_temp_free_ptr(fpst
);
6376 write_fp_dreg(s
, rd
, tcg_res
);
6377 tcg_temp_free_i64(tcg_op
);
6378 tcg_temp_free_i64(tcg_res
);
6381 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6382 int rd
, int rn
, int dtype
, int ntype
)
6387 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6389 /* Single to double */
6390 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6391 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6392 write_fp_dreg(s
, rd
, tcg_rd
);
6393 tcg_temp_free_i64(tcg_rd
);
6395 /* Single to half */
6396 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6397 TCGv_i32 ahp
= get_ahp_flag();
6398 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6400 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6401 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6402 write_fp_sreg(s
, rd
, tcg_rd
);
6403 tcg_temp_free_i32(tcg_rd
);
6404 tcg_temp_free_i32(ahp
);
6405 tcg_temp_free_ptr(fpst
);
6407 tcg_temp_free_i32(tcg_rn
);
6412 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6413 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6415 /* Double to single */
6416 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6418 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6419 TCGv_i32 ahp
= get_ahp_flag();
6420 /* Double to half */
6421 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6422 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6423 tcg_temp_free_ptr(fpst
);
6424 tcg_temp_free_i32(ahp
);
6426 write_fp_sreg(s
, rd
, tcg_rd
);
6427 tcg_temp_free_i32(tcg_rd
);
6428 tcg_temp_free_i64(tcg_rn
);
6433 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6434 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6435 TCGv_i32 tcg_ahp
= get_ahp_flag();
6436 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6438 /* Half to single */
6439 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6440 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6441 write_fp_sreg(s
, rd
, tcg_rd
);
6442 tcg_temp_free_i32(tcg_rd
);
6444 /* Half to double */
6445 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6446 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6447 write_fp_dreg(s
, rd
, tcg_rd
);
6448 tcg_temp_free_i64(tcg_rd
);
6450 tcg_temp_free_i32(tcg_rn
);
6451 tcg_temp_free_ptr(tcg_fpst
);
6452 tcg_temp_free_i32(tcg_ahp
);
6460 /* Floating point data-processing (1 source)
6461 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6462 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6463 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6464 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6466 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6468 int mos
= extract32(insn
, 29, 3);
6469 int type
= extract32(insn
, 22, 2);
6470 int opcode
= extract32(insn
, 15, 6);
6471 int rn
= extract32(insn
, 5, 5);
6472 int rd
= extract32(insn
, 0, 5);
6475 unallocated_encoding(s
);
6480 case 0x4: case 0x5: case 0x7:
6482 /* FCVT between half, single and double precision */
6483 int dtype
= extract32(opcode
, 0, 2);
6484 if (type
== 2 || dtype
== type
) {
6485 unallocated_encoding(s
);
6488 if (!fp_access_check(s
)) {
6492 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6496 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6497 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6498 unallocated_encoding(s
);
6505 /* 32-to-32 and 64-to-64 ops */
6508 if (!fp_access_check(s
)) {
6511 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6514 if (!fp_access_check(s
)) {
6517 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6520 if (!dc_isar_feature(aa64_fp16
, s
)) {
6521 unallocated_encoding(s
);
6525 if (!fp_access_check(s
)) {
6528 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6531 unallocated_encoding(s
);
6536 unallocated_encoding(s
);
6541 /* Floating-point data-processing (2 source) - single precision */
6542 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6543 int rd
, int rn
, int rm
)
6550 tcg_res
= tcg_temp_new_i32();
6551 fpst
= fpstatus_ptr(FPST_FPCR
);
6552 tcg_op1
= read_fp_sreg(s
, rn
);
6553 tcg_op2
= read_fp_sreg(s
, rm
);
6556 case 0x0: /* FMUL */
6557 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6559 case 0x1: /* FDIV */
6560 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6562 case 0x2: /* FADD */
6563 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6565 case 0x3: /* FSUB */
6566 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6568 case 0x4: /* FMAX */
6569 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6571 case 0x5: /* FMIN */
6572 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6574 case 0x6: /* FMAXNM */
6575 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6577 case 0x7: /* FMINNM */
6578 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6580 case 0x8: /* FNMUL */
6581 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6582 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6586 write_fp_sreg(s
, rd
, tcg_res
);
6588 tcg_temp_free_ptr(fpst
);
6589 tcg_temp_free_i32(tcg_op1
);
6590 tcg_temp_free_i32(tcg_op2
);
6591 tcg_temp_free_i32(tcg_res
);
6594 /* Floating-point data-processing (2 source) - double precision */
6595 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6596 int rd
, int rn
, int rm
)
6603 tcg_res
= tcg_temp_new_i64();
6604 fpst
= fpstatus_ptr(FPST_FPCR
);
6605 tcg_op1
= read_fp_dreg(s
, rn
);
6606 tcg_op2
= read_fp_dreg(s
, rm
);
6609 case 0x0: /* FMUL */
6610 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6612 case 0x1: /* FDIV */
6613 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6615 case 0x2: /* FADD */
6616 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6618 case 0x3: /* FSUB */
6619 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6621 case 0x4: /* FMAX */
6622 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6624 case 0x5: /* FMIN */
6625 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6627 case 0x6: /* FMAXNM */
6628 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6630 case 0x7: /* FMINNM */
6631 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6633 case 0x8: /* FNMUL */
6634 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6635 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6639 write_fp_dreg(s
, rd
, tcg_res
);
6641 tcg_temp_free_ptr(fpst
);
6642 tcg_temp_free_i64(tcg_op1
);
6643 tcg_temp_free_i64(tcg_op2
);
6644 tcg_temp_free_i64(tcg_res
);
6647 /* Floating-point data-processing (2 source) - half precision */
6648 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6649 int rd
, int rn
, int rm
)
6656 tcg_res
= tcg_temp_new_i32();
6657 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6658 tcg_op1
= read_fp_hreg(s
, rn
);
6659 tcg_op2
= read_fp_hreg(s
, rm
);
6662 case 0x0: /* FMUL */
6663 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6665 case 0x1: /* FDIV */
6666 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6668 case 0x2: /* FADD */
6669 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6671 case 0x3: /* FSUB */
6672 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6674 case 0x4: /* FMAX */
6675 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6677 case 0x5: /* FMIN */
6678 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6680 case 0x6: /* FMAXNM */
6681 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6683 case 0x7: /* FMINNM */
6684 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6686 case 0x8: /* FNMUL */
6687 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6688 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6691 g_assert_not_reached();
6694 write_fp_sreg(s
, rd
, tcg_res
);
6696 tcg_temp_free_ptr(fpst
);
6697 tcg_temp_free_i32(tcg_op1
);
6698 tcg_temp_free_i32(tcg_op2
);
6699 tcg_temp_free_i32(tcg_res
);
6702 /* Floating point data-processing (2 source)
6703 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6704 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6705 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6706 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6708 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6710 int mos
= extract32(insn
, 29, 3);
6711 int type
= extract32(insn
, 22, 2);
6712 int rd
= extract32(insn
, 0, 5);
6713 int rn
= extract32(insn
, 5, 5);
6714 int rm
= extract32(insn
, 16, 5);
6715 int opcode
= extract32(insn
, 12, 4);
6717 if (opcode
> 8 || mos
) {
6718 unallocated_encoding(s
);
6724 if (!fp_access_check(s
)) {
6727 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6730 if (!fp_access_check(s
)) {
6733 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6736 if (!dc_isar_feature(aa64_fp16
, s
)) {
6737 unallocated_encoding(s
);
6740 if (!fp_access_check(s
)) {
6743 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6746 unallocated_encoding(s
);
6750 /* Floating-point data-processing (3 source) - single precision */
6751 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6752 int rd
, int rn
, int rm
, int ra
)
6754 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6755 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6756 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6758 tcg_op1
= read_fp_sreg(s
, rn
);
6759 tcg_op2
= read_fp_sreg(s
, rm
);
6760 tcg_op3
= read_fp_sreg(s
, ra
);
6762 /* These are fused multiply-add, and must be done as one
6763 * floating point operation with no rounding between the
6764 * multiplication and addition steps.
6765 * NB that doing the negations here as separate steps is
6766 * correct : an input NaN should come out with its sign bit
6767 * flipped if it is a negated-input.
6770 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6774 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6777 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6779 write_fp_sreg(s
, rd
, tcg_res
);
6781 tcg_temp_free_ptr(fpst
);
6782 tcg_temp_free_i32(tcg_op1
);
6783 tcg_temp_free_i32(tcg_op2
);
6784 tcg_temp_free_i32(tcg_op3
);
6785 tcg_temp_free_i32(tcg_res
);
6788 /* Floating-point data-processing (3 source) - double precision */
6789 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6790 int rd
, int rn
, int rm
, int ra
)
6792 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6793 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6794 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6796 tcg_op1
= read_fp_dreg(s
, rn
);
6797 tcg_op2
= read_fp_dreg(s
, rm
);
6798 tcg_op3
= read_fp_dreg(s
, ra
);
6800 /* These are fused multiply-add, and must be done as one
6801 * floating point operation with no rounding between the
6802 * multiplication and addition steps.
6803 * NB that doing the negations here as separate steps is
6804 * correct : an input NaN should come out with its sign bit
6805 * flipped if it is a negated-input.
6808 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6812 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6815 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6817 write_fp_dreg(s
, rd
, tcg_res
);
6819 tcg_temp_free_ptr(fpst
);
6820 tcg_temp_free_i64(tcg_op1
);
6821 tcg_temp_free_i64(tcg_op2
);
6822 tcg_temp_free_i64(tcg_op3
);
6823 tcg_temp_free_i64(tcg_res
);
6826 /* Floating-point data-processing (3 source) - half precision */
6827 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6828 int rd
, int rn
, int rm
, int ra
)
6830 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6831 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6832 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6834 tcg_op1
= read_fp_hreg(s
, rn
);
6835 tcg_op2
= read_fp_hreg(s
, rm
);
6836 tcg_op3
= read_fp_hreg(s
, ra
);
6838 /* These are fused multiply-add, and must be done as one
6839 * floating point operation with no rounding between the
6840 * multiplication and addition steps.
6841 * NB that doing the negations here as separate steps is
6842 * correct : an input NaN should come out with its sign bit
6843 * flipped if it is a negated-input.
6846 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6850 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6853 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6855 write_fp_sreg(s
, rd
, tcg_res
);
6857 tcg_temp_free_ptr(fpst
);
6858 tcg_temp_free_i32(tcg_op1
);
6859 tcg_temp_free_i32(tcg_op2
);
6860 tcg_temp_free_i32(tcg_op3
);
6861 tcg_temp_free_i32(tcg_res
);
6864 /* Floating point data-processing (3 source)
6865 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6866 * +---+---+---+-----------+------+----+------+----+------+------+------+
6867 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6868 * +---+---+---+-----------+------+----+------+----+------+------+------+
6870 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6872 int mos
= extract32(insn
, 29, 3);
6873 int type
= extract32(insn
, 22, 2);
6874 int rd
= extract32(insn
, 0, 5);
6875 int rn
= extract32(insn
, 5, 5);
6876 int ra
= extract32(insn
, 10, 5);
6877 int rm
= extract32(insn
, 16, 5);
6878 bool o0
= extract32(insn
, 15, 1);
6879 bool o1
= extract32(insn
, 21, 1);
6882 unallocated_encoding(s
);
6888 if (!fp_access_check(s
)) {
6891 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6894 if (!fp_access_check(s
)) {
6897 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6900 if (!dc_isar_feature(aa64_fp16
, s
)) {
6901 unallocated_encoding(s
);
6904 if (!fp_access_check(s
)) {
6907 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6910 unallocated_encoding(s
);
6914 /* Floating point immediate
6915 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6916 * +---+---+---+-----------+------+---+------------+-------+------+------+
6917 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6918 * +---+---+---+-----------+------+---+------------+-------+------+------+
6920 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6922 int rd
= extract32(insn
, 0, 5);
6923 int imm5
= extract32(insn
, 5, 5);
6924 int imm8
= extract32(insn
, 13, 8);
6925 int type
= extract32(insn
, 22, 2);
6926 int mos
= extract32(insn
, 29, 3);
6932 unallocated_encoding(s
);
6945 if (dc_isar_feature(aa64_fp16
, s
)) {
6950 unallocated_encoding(s
);
6954 if (!fp_access_check(s
)) {
6958 imm
= vfp_expand_imm(sz
, imm8
);
6960 tcg_res
= tcg_const_i64(imm
);
6961 write_fp_dreg(s
, rd
, tcg_res
);
6962 tcg_temp_free_i64(tcg_res
);
6965 /* Handle floating point <=> fixed point conversions. Note that we can
6966 * also deal with fp <=> integer conversions as a special case (scale == 64)
6967 * OPTME: consider handling that special case specially or at least skipping
6968 * the call to scalbn in the helpers for zero shifts.
6970 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6971 bool itof
, int rmode
, int scale
, int sf
, int type
)
6973 bool is_signed
= !(opcode
& 1);
6974 TCGv_ptr tcg_fpstatus
;
6975 TCGv_i32 tcg_shift
, tcg_single
;
6976 TCGv_i64 tcg_double
;
6978 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
6980 tcg_shift
= tcg_const_i32(64 - scale
);
6983 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6985 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6988 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6990 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6993 tcg_int
= tcg_extend
;
6997 case 1: /* float64 */
6998 tcg_double
= tcg_temp_new_i64();
7000 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
7001 tcg_shift
, tcg_fpstatus
);
7003 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
7004 tcg_shift
, tcg_fpstatus
);
7006 write_fp_dreg(s
, rd
, tcg_double
);
7007 tcg_temp_free_i64(tcg_double
);
7010 case 0: /* float32 */
7011 tcg_single
= tcg_temp_new_i32();
7013 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
7014 tcg_shift
, tcg_fpstatus
);
7016 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
7017 tcg_shift
, tcg_fpstatus
);
7019 write_fp_sreg(s
, rd
, tcg_single
);
7020 tcg_temp_free_i32(tcg_single
);
7023 case 3: /* float16 */
7024 tcg_single
= tcg_temp_new_i32();
7026 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
7027 tcg_shift
, tcg_fpstatus
);
7029 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7030 tcg_shift
, tcg_fpstatus
);
7032 write_fp_sreg(s
, rd
, tcg_single
);
7033 tcg_temp_free_i32(tcg_single
);
7037 g_assert_not_reached();
7040 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7043 if (extract32(opcode
, 2, 1)) {
7044 /* There are too many rounding modes to all fit into rmode,
7045 * so FCVTA[US] is a special case.
7047 rmode
= FPROUNDING_TIEAWAY
;
7050 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7052 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7055 case 1: /* float64 */
7056 tcg_double
= read_fp_dreg(s
, rn
);
7059 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7060 tcg_shift
, tcg_fpstatus
);
7062 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7063 tcg_shift
, tcg_fpstatus
);
7067 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7068 tcg_shift
, tcg_fpstatus
);
7070 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7071 tcg_shift
, tcg_fpstatus
);
7075 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7077 tcg_temp_free_i64(tcg_double
);
7080 case 0: /* float32 */
7081 tcg_single
= read_fp_sreg(s
, rn
);
7084 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7085 tcg_shift
, tcg_fpstatus
);
7087 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7088 tcg_shift
, tcg_fpstatus
);
7091 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7093 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7094 tcg_shift
, tcg_fpstatus
);
7096 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7097 tcg_shift
, tcg_fpstatus
);
7099 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7100 tcg_temp_free_i32(tcg_dest
);
7102 tcg_temp_free_i32(tcg_single
);
7105 case 3: /* float16 */
7106 tcg_single
= read_fp_sreg(s
, rn
);
7109 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7110 tcg_shift
, tcg_fpstatus
);
7112 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7113 tcg_shift
, tcg_fpstatus
);
7116 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7118 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7119 tcg_shift
, tcg_fpstatus
);
7121 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7122 tcg_shift
, tcg_fpstatus
);
7124 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7125 tcg_temp_free_i32(tcg_dest
);
7127 tcg_temp_free_i32(tcg_single
);
7131 g_assert_not_reached();
7134 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7135 tcg_temp_free_i32(tcg_rmode
);
7138 tcg_temp_free_ptr(tcg_fpstatus
);
7139 tcg_temp_free_i32(tcg_shift
);
7142 /* Floating point <-> fixed point conversions
7143 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7144 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7145 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7146 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7148 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7150 int rd
= extract32(insn
, 0, 5);
7151 int rn
= extract32(insn
, 5, 5);
7152 int scale
= extract32(insn
, 10, 6);
7153 int opcode
= extract32(insn
, 16, 3);
7154 int rmode
= extract32(insn
, 19, 2);
7155 int type
= extract32(insn
, 22, 2);
7156 bool sbit
= extract32(insn
, 29, 1);
7157 bool sf
= extract32(insn
, 31, 1);
7160 if (sbit
|| (!sf
&& scale
< 32)) {
7161 unallocated_encoding(s
);
7166 case 0: /* float32 */
7167 case 1: /* float64 */
7169 case 3: /* float16 */
7170 if (dc_isar_feature(aa64_fp16
, s
)) {
7175 unallocated_encoding(s
);
7179 switch ((rmode
<< 3) | opcode
) {
7180 case 0x2: /* SCVTF */
7181 case 0x3: /* UCVTF */
7184 case 0x18: /* FCVTZS */
7185 case 0x19: /* FCVTZU */
7189 unallocated_encoding(s
);
7193 if (!fp_access_check(s
)) {
7197 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7200 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7202 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7203 * without conversion.
7207 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7213 tmp
= tcg_temp_new_i64();
7214 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7215 write_fp_dreg(s
, rd
, tmp
);
7216 tcg_temp_free_i64(tmp
);
7220 write_fp_dreg(s
, rd
, tcg_rn
);
7223 /* 64 bit to top half. */
7224 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7225 clear_vec_high(s
, true, rd
);
7229 tmp
= tcg_temp_new_i64();
7230 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7231 write_fp_dreg(s
, rd
, tmp
);
7232 tcg_temp_free_i64(tmp
);
7235 g_assert_not_reached();
7238 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7243 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7247 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7250 /* 64 bits from top half */
7251 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7255 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7258 g_assert_not_reached();
7263 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7265 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7266 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7268 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7270 tcg_temp_free_ptr(fpstatus
);
7272 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7273 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7274 tcg_gen_movi_i32(cpu_CF
, 0);
7275 tcg_gen_movi_i32(cpu_NF
, 0);
7276 tcg_gen_movi_i32(cpu_VF
, 0);
7278 tcg_temp_free_i64(t
);
7281 /* Floating point <-> integer conversions
7282 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7283 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7284 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7285 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7287 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7289 int rd
= extract32(insn
, 0, 5);
7290 int rn
= extract32(insn
, 5, 5);
7291 int opcode
= extract32(insn
, 16, 3);
7292 int rmode
= extract32(insn
, 19, 2);
7293 int type
= extract32(insn
, 22, 2);
7294 bool sbit
= extract32(insn
, 29, 1);
7295 bool sf
= extract32(insn
, 31, 1);
7299 goto do_unallocated
;
7307 case 4: /* FCVTAS */
7308 case 5: /* FCVTAU */
7310 goto do_unallocated
;
7313 case 0: /* FCVT[NPMZ]S */
7314 case 1: /* FCVT[NPMZ]U */
7316 case 0: /* float32 */
7317 case 1: /* float64 */
7319 case 3: /* float16 */
7320 if (!dc_isar_feature(aa64_fp16
, s
)) {
7321 goto do_unallocated
;
7325 goto do_unallocated
;
7327 if (!fp_access_check(s
)) {
7330 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7334 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7335 case 0b01100110: /* FMOV half <-> 32-bit int */
7337 case 0b11100110: /* FMOV half <-> 64-bit int */
7339 if (!dc_isar_feature(aa64_fp16
, s
)) {
7340 goto do_unallocated
;
7343 case 0b00000110: /* FMOV 32-bit */
7345 case 0b10100110: /* FMOV 64-bit */
7347 case 0b11001110: /* FMOV top half of 128-bit */
7349 if (!fp_access_check(s
)) {
7353 handle_fmov(s
, rd
, rn
, type
, itof
);
7356 case 0b00111110: /* FJCVTZS */
7357 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7358 goto do_unallocated
;
7359 } else if (fp_access_check(s
)) {
7360 handle_fjcvtzs(s
, rd
, rn
);
7366 unallocated_encoding(s
);
7373 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7374 * 31 30 29 28 25 24 0
7375 * +---+---+---+---------+-----------------------------+
7376 * | | 0 | | 1 1 1 1 | |
7377 * +---+---+---+---------+-----------------------------+
7379 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7381 if (extract32(insn
, 24, 1)) {
7382 /* Floating point data-processing (3 source) */
7383 disas_fp_3src(s
, insn
);
7384 } else if (extract32(insn
, 21, 1) == 0) {
7385 /* Floating point to fixed point conversions */
7386 disas_fp_fixed_conv(s
, insn
);
7388 switch (extract32(insn
, 10, 2)) {
7390 /* Floating point conditional compare */
7391 disas_fp_ccomp(s
, insn
);
7394 /* Floating point data-processing (2 source) */
7395 disas_fp_2src(s
, insn
);
7398 /* Floating point conditional select */
7399 disas_fp_csel(s
, insn
);
7402 switch (ctz32(extract32(insn
, 12, 4))) {
7403 case 0: /* [15:12] == xxx1 */
7404 /* Floating point immediate */
7405 disas_fp_imm(s
, insn
);
7407 case 1: /* [15:12] == xx10 */
7408 /* Floating point compare */
7409 disas_fp_compare(s
, insn
);
7411 case 2: /* [15:12] == x100 */
7412 /* Floating point data-processing (1 source) */
7413 disas_fp_1src(s
, insn
);
7415 case 3: /* [15:12] == 1000 */
7416 unallocated_encoding(s
);
7418 default: /* [15:12] == 0000 */
7419 /* Floating point <-> integer conversions */
7420 disas_fp_int_conv(s
, insn
);
7428 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7431 /* Extract 64 bits from the middle of two concatenated 64 bit
7432 * vector register slices left:right. The extracted bits start
7433 * at 'pos' bits into the right (least significant) side.
7434 * We return the result in tcg_right, and guarantee not to
7437 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7438 assert(pos
> 0 && pos
< 64);
7440 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7441 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7442 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7444 tcg_temp_free_i64(tcg_tmp
);
7448 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7449 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7450 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7451 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7453 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7455 int is_q
= extract32(insn
, 30, 1);
7456 int op2
= extract32(insn
, 22, 2);
7457 int imm4
= extract32(insn
, 11, 4);
7458 int rm
= extract32(insn
, 16, 5);
7459 int rn
= extract32(insn
, 5, 5);
7460 int rd
= extract32(insn
, 0, 5);
7461 int pos
= imm4
<< 3;
7462 TCGv_i64 tcg_resl
, tcg_resh
;
7464 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7465 unallocated_encoding(s
);
7469 if (!fp_access_check(s
)) {
7473 tcg_resh
= tcg_temp_new_i64();
7474 tcg_resl
= tcg_temp_new_i64();
7476 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7477 * either extracting 128 bits from a 128:128 concatenation, or
7478 * extracting 64 bits from a 64:64 concatenation.
7481 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7483 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7484 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7492 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7493 EltPosns
*elt
= eltposns
;
7500 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7502 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7505 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7506 tcg_hh
= tcg_temp_new_i64();
7507 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7508 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7509 tcg_temp_free_i64(tcg_hh
);
7513 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7514 tcg_temp_free_i64(tcg_resl
);
7516 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7518 tcg_temp_free_i64(tcg_resh
);
7519 clear_vec_high(s
, is_q
, rd
);
7523 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7524 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7525 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7526 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7528 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7530 int op2
= extract32(insn
, 22, 2);
7531 int is_q
= extract32(insn
, 30, 1);
7532 int rm
= extract32(insn
, 16, 5);
7533 int rn
= extract32(insn
, 5, 5);
7534 int rd
= extract32(insn
, 0, 5);
7535 int is_tbx
= extract32(insn
, 12, 1);
7536 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7539 unallocated_encoding(s
);
7543 if (!fp_access_check(s
)) {
7547 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7548 vec_full_reg_offset(s
, rm
), cpu_env
,
7549 is_q
? 16 : 8, vec_full_reg_size(s
),
7550 (len
<< 6) | (is_tbx
<< 5) | rn
,
7551 gen_helper_simd_tblx
);
7555 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7556 * +---+---+-------------+------+---+------+---+------------------+------+
7557 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7558 * +---+---+-------------+------+---+------+---+------------------+------+
7560 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7562 int rd
= extract32(insn
, 0, 5);
7563 int rn
= extract32(insn
, 5, 5);
7564 int rm
= extract32(insn
, 16, 5);
7565 int size
= extract32(insn
, 22, 2);
7566 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7567 * bit 2 indicates 1 vs 2 variant of the insn.
7569 int opcode
= extract32(insn
, 12, 2);
7570 bool part
= extract32(insn
, 14, 1);
7571 bool is_q
= extract32(insn
, 30, 1);
7572 int esize
= 8 << size
;
7574 int datasize
= is_q
? 128 : 64;
7575 int elements
= datasize
/ esize
;
7576 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7578 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7579 unallocated_encoding(s
);
7583 if (!fp_access_check(s
)) {
7587 tcg_resl
= tcg_const_i64(0);
7588 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7589 tcg_res
= tcg_temp_new_i64();
7591 for (i
= 0; i
< elements
; i
++) {
7593 case 1: /* UZP1/2 */
7595 int midpoint
= elements
/ 2;
7597 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7599 read_vec_element(s
, tcg_res
, rm
,
7600 2 * (i
- midpoint
) + part
, size
);
7604 case 2: /* TRN1/2 */
7606 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7608 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7611 case 3: /* ZIP1/2 */
7613 int base
= part
* elements
/ 2;
7615 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7617 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7622 g_assert_not_reached();
7627 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7628 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7630 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7631 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7635 tcg_temp_free_i64(tcg_res
);
7637 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7638 tcg_temp_free_i64(tcg_resl
);
7641 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7642 tcg_temp_free_i64(tcg_resh
);
7644 clear_vec_high(s
, is_q
, rd
);
7648 * do_reduction_op helper
7650 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7651 * important for correct NaN propagation that we do these
7652 * operations in exactly the order specified by the pseudocode.
7654 * This is a recursive function, TCG temps should be freed by the
7655 * calling function once it is done with the values.
7657 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7658 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7660 if (esize
== size
) {
7662 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7665 /* We should have one register left here */
7666 assert(ctpop8(vmap
) == 1);
7667 element
= ctz32(vmap
);
7668 assert(element
< 8);
7670 tcg_elem
= tcg_temp_new_i32();
7671 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7674 int bits
= size
/ 2;
7675 int shift
= ctpop8(vmap
) / 2;
7676 int vmap_lo
= (vmap
>> shift
) & vmap
;
7677 int vmap_hi
= (vmap
& ~vmap_lo
);
7678 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7680 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7681 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7682 tcg_res
= tcg_temp_new_i32();
7685 case 0x0c: /* fmaxnmv half-precision */
7686 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7688 case 0x0f: /* fmaxv half-precision */
7689 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7691 case 0x1c: /* fminnmv half-precision */
7692 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7694 case 0x1f: /* fminv half-precision */
7695 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7697 case 0x2c: /* fmaxnmv */
7698 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7700 case 0x2f: /* fmaxv */
7701 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7703 case 0x3c: /* fminnmv */
7704 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7706 case 0x3f: /* fminv */
7707 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7710 g_assert_not_reached();
7713 tcg_temp_free_i32(tcg_hi
);
7714 tcg_temp_free_i32(tcg_lo
);
7719 /* AdvSIMD across lanes
7720 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7721 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7722 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7723 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7725 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7727 int rd
= extract32(insn
, 0, 5);
7728 int rn
= extract32(insn
, 5, 5);
7729 int size
= extract32(insn
, 22, 2);
7730 int opcode
= extract32(insn
, 12, 5);
7731 bool is_q
= extract32(insn
, 30, 1);
7732 bool is_u
= extract32(insn
, 29, 1);
7734 bool is_min
= false;
7738 TCGv_i64 tcg_res
, tcg_elt
;
7741 case 0x1b: /* ADDV */
7743 unallocated_encoding(s
);
7747 case 0x3: /* SADDLV, UADDLV */
7748 case 0xa: /* SMAXV, UMAXV */
7749 case 0x1a: /* SMINV, UMINV */
7750 if (size
== 3 || (size
== 2 && !is_q
)) {
7751 unallocated_encoding(s
);
7755 case 0xc: /* FMAXNMV, FMINNMV */
7756 case 0xf: /* FMAXV, FMINV */
7757 /* Bit 1 of size field encodes min vs max and the actual size
7758 * depends on the encoding of the U bit. If not set (and FP16
7759 * enabled) then we do half-precision float instead of single
7762 is_min
= extract32(size
, 1, 1);
7764 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7766 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7767 unallocated_encoding(s
);
7774 unallocated_encoding(s
);
7778 if (!fp_access_check(s
)) {
7783 elements
= (is_q
? 128 : 64) / esize
;
7785 tcg_res
= tcg_temp_new_i64();
7786 tcg_elt
= tcg_temp_new_i64();
7788 /* These instructions operate across all lanes of a vector
7789 * to produce a single result. We can guarantee that a 64
7790 * bit intermediate is sufficient:
7791 * + for [US]ADDLV the maximum element size is 32 bits, and
7792 * the result type is 64 bits
7793 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7794 * same as the element size, which is 32 bits at most
7795 * For the integer operations we can choose to work at 64
7796 * or 32 bits and truncate at the end; for simplicity
7797 * we use 64 bits always. The floating point
7798 * ops do require 32 bit intermediates, though.
7801 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7803 for (i
= 1; i
< elements
; i
++) {
7804 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7807 case 0x03: /* SADDLV / UADDLV */
7808 case 0x1b: /* ADDV */
7809 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7811 case 0x0a: /* SMAXV / UMAXV */
7813 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7815 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7818 case 0x1a: /* SMINV / UMINV */
7820 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7822 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7826 g_assert_not_reached();
7831 /* Floating point vector reduction ops which work across 32
7832 * bit (single) or 16 bit (half-precision) intermediates.
7833 * Note that correct NaN propagation requires that we do these
7834 * operations in exactly the order specified by the pseudocode.
7836 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7837 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7838 int vmap
= (1 << elements
) - 1;
7839 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7840 (is_q
? 128 : 64), vmap
, fpst
);
7841 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7842 tcg_temp_free_i32(tcg_res32
);
7843 tcg_temp_free_ptr(fpst
);
7846 tcg_temp_free_i64(tcg_elt
);
7848 /* Now truncate the result to the width required for the final output */
7849 if (opcode
== 0x03) {
7850 /* SADDLV, UADDLV: result is 2*esize */
7856 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7859 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7862 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7867 g_assert_not_reached();
7870 write_fp_dreg(s
, rd
, tcg_res
);
7871 tcg_temp_free_i64(tcg_res
);
7874 /* DUP (Element, Vector)
7876 * 31 30 29 21 20 16 15 10 9 5 4 0
7877 * +---+---+-------------------+--------+-------------+------+------+
7878 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7879 * +---+---+-------------------+--------+-------------+------+------+
7881 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7883 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7886 int size
= ctz32(imm5
);
7889 if (size
> 3 || (size
== 3 && !is_q
)) {
7890 unallocated_encoding(s
);
7894 if (!fp_access_check(s
)) {
7898 index
= imm5
>> (size
+ 1);
7899 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7900 vec_reg_offset(s
, rn
, index
, size
),
7901 is_q
? 16 : 8, vec_full_reg_size(s
));
7904 /* DUP (element, scalar)
7905 * 31 21 20 16 15 10 9 5 4 0
7906 * +-----------------------+--------+-------------+------+------+
7907 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7908 * +-----------------------+--------+-------------+------+------+
7910 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7913 int size
= ctz32(imm5
);
7918 unallocated_encoding(s
);
7922 if (!fp_access_check(s
)) {
7926 index
= imm5
>> (size
+ 1);
7928 /* This instruction just extracts the specified element and
7929 * zero-extends it into the bottom of the destination register.
7931 tmp
= tcg_temp_new_i64();
7932 read_vec_element(s
, tmp
, rn
, index
, size
);
7933 write_fp_dreg(s
, rd
, tmp
);
7934 tcg_temp_free_i64(tmp
);
7939 * 31 30 29 21 20 16 15 10 9 5 4 0
7940 * +---+---+-------------------+--------+-------------+------+------+
7941 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7942 * +---+---+-------------------+--------+-------------+------+------+
7944 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7946 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7949 int size
= ctz32(imm5
);
7950 uint32_t dofs
, oprsz
, maxsz
;
7952 if (size
> 3 || ((size
== 3) && !is_q
)) {
7953 unallocated_encoding(s
);
7957 if (!fp_access_check(s
)) {
7961 dofs
= vec_full_reg_offset(s
, rd
);
7962 oprsz
= is_q
? 16 : 8;
7963 maxsz
= vec_full_reg_size(s
);
7965 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7970 * 31 21 20 16 15 14 11 10 9 5 4 0
7971 * +-----------------------+--------+------------+---+------+------+
7972 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7973 * +-----------------------+--------+------------+---+------+------+
7975 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7976 * index: encoded in imm5<4:size+1>
7978 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7981 int size
= ctz32(imm5
);
7982 int src_index
, dst_index
;
7986 unallocated_encoding(s
);
7990 if (!fp_access_check(s
)) {
7994 dst_index
= extract32(imm5
, 1+size
, 5);
7995 src_index
= extract32(imm4
, size
, 4);
7997 tmp
= tcg_temp_new_i64();
7999 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8000 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8002 tcg_temp_free_i64(tmp
);
8004 /* INS is considered a 128-bit write for SVE. */
8005 clear_vec_high(s
, true, rd
);
8011 * 31 21 20 16 15 10 9 5 4 0
8012 * +-----------------------+--------+-------------+------+------+
8013 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8014 * +-----------------------+--------+-------------+------+------+
8016 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8017 * index: encoded in imm5<4:size+1>
8019 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8021 int size
= ctz32(imm5
);
8025 unallocated_encoding(s
);
8029 if (!fp_access_check(s
)) {
8033 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8034 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8036 /* INS is considered a 128-bit write for SVE. */
8037 clear_vec_high(s
, true, rd
);
8044 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8045 * +---+---+-------------------+--------+-------------+------+------+
8046 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8047 * +---+---+-------------------+--------+-------------+------+------+
8049 * U: unsigned when set
8050 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8052 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8053 int rn
, int rd
, int imm5
)
8055 int size
= ctz32(imm5
);
8059 /* Check for UnallocatedEncodings */
8061 if (size
> 2 || (size
== 2 && !is_q
)) {
8062 unallocated_encoding(s
);
8067 || (size
< 3 && is_q
)
8068 || (size
== 3 && !is_q
)) {
8069 unallocated_encoding(s
);
8074 if (!fp_access_check(s
)) {
8078 element
= extract32(imm5
, 1+size
, 4);
8080 tcg_rd
= cpu_reg(s
, rd
);
8081 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8082 if (is_signed
&& !is_q
) {
8083 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8088 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8089 * +---+---+----+-----------------+------+---+------+---+------+------+
8090 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8091 * +---+---+----+-----------------+------+---+------+---+------+------+
8093 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8095 int rd
= extract32(insn
, 0, 5);
8096 int rn
= extract32(insn
, 5, 5);
8097 int imm4
= extract32(insn
, 11, 4);
8098 int op
= extract32(insn
, 29, 1);
8099 int is_q
= extract32(insn
, 30, 1);
8100 int imm5
= extract32(insn
, 16, 5);
8105 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8107 unallocated_encoding(s
);
8112 /* DUP (element - vector) */
8113 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8117 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8122 handle_simd_insg(s
, rd
, rn
, imm5
);
8124 unallocated_encoding(s
);
8129 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8130 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8133 unallocated_encoding(s
);
8139 /* AdvSIMD modified immediate
8140 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8141 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8142 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8143 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8145 * There are a number of operations that can be carried out here:
8146 * MOVI - move (shifted) imm into register
8147 * MVNI - move inverted (shifted) imm into register
8148 * ORR - bitwise OR of (shifted) imm with register
8149 * BIC - bitwise clear of (shifted) imm with register
8150 * With ARMv8.2 we also have:
8151 * FMOV half-precision
8153 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8155 int rd
= extract32(insn
, 0, 5);
8156 int cmode
= extract32(insn
, 12, 4);
8157 int cmode_3_1
= extract32(cmode
, 1, 3);
8158 int cmode_0
= extract32(cmode
, 0, 1);
8159 int o2
= extract32(insn
, 11, 1);
8160 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8161 bool is_neg
= extract32(insn
, 29, 1);
8162 bool is_q
= extract32(insn
, 30, 1);
8165 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8166 /* Check for FMOV (vector, immediate) - half-precision */
8167 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8168 unallocated_encoding(s
);
8173 if (!fp_access_check(s
)) {
8177 /* See AdvSIMDExpandImm() in ARM ARM */
8178 switch (cmode_3_1
) {
8179 case 0: /* Replicate(Zeros(24):imm8, 2) */
8180 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
8181 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
8182 case 3: /* Replicate(imm8:Zeros(24), 2) */
8184 int shift
= cmode_3_1
* 8;
8185 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
8188 case 4: /* Replicate(Zeros(8):imm8, 4) */
8189 case 5: /* Replicate(imm8:Zeros(8), 4) */
8191 int shift
= (cmode_3_1
& 0x1) * 8;
8192 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
8197 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
8198 imm
= (abcdefgh
<< 16) | 0xffff;
8200 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
8201 imm
= (abcdefgh
<< 8) | 0xff;
8203 imm
= bitfield_replicate(imm
, 32);
8206 if (!cmode_0
&& !is_neg
) {
8207 imm
= bitfield_replicate(abcdefgh
, 8);
8208 } else if (!cmode_0
&& is_neg
) {
8211 for (i
= 0; i
< 8; i
++) {
8212 if ((abcdefgh
) & (1 << i
)) {
8213 imm
|= 0xffULL
<< (i
* 8);
8216 } else if (cmode_0
) {
8218 imm
= (abcdefgh
& 0x3f) << 48;
8219 if (abcdefgh
& 0x80) {
8220 imm
|= 0x8000000000000000ULL
;
8222 if (abcdefgh
& 0x40) {
8223 imm
|= 0x3fc0000000000000ULL
;
8225 imm
|= 0x4000000000000000ULL
;
8229 /* FMOV (vector, immediate) - half-precision */
8230 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8231 /* now duplicate across the lanes */
8232 imm
= bitfield_replicate(imm
, 16);
8234 imm
= (abcdefgh
& 0x3f) << 19;
8235 if (abcdefgh
& 0x80) {
8238 if (abcdefgh
& 0x40) {
8249 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
8250 g_assert_not_reached();
8253 if (cmode_3_1
!= 7 && is_neg
) {
8257 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8258 /* MOVI or MVNI, with MVNI negation handled above. */
8259 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8260 vec_full_reg_size(s
), imm
);
8262 /* ORR or BIC, with BIC negation to AND handled above. */
8264 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8266 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8271 /* AdvSIMD scalar copy
8272 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8273 * +-----+----+-----------------+------+---+------+---+------+------+
8274 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8275 * +-----+----+-----------------+------+---+------+---+------+------+
8277 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8279 int rd
= extract32(insn
, 0, 5);
8280 int rn
= extract32(insn
, 5, 5);
8281 int imm4
= extract32(insn
, 11, 4);
8282 int imm5
= extract32(insn
, 16, 5);
8283 int op
= extract32(insn
, 29, 1);
8285 if (op
!= 0 || imm4
!= 0) {
8286 unallocated_encoding(s
);
8290 /* DUP (element, scalar) */
8291 handle_simd_dupes(s
, rd
, rn
, imm5
);
8294 /* AdvSIMD scalar pairwise
8295 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8296 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8297 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8298 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8300 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8302 int u
= extract32(insn
, 29, 1);
8303 int size
= extract32(insn
, 22, 2);
8304 int opcode
= extract32(insn
, 12, 5);
8305 int rn
= extract32(insn
, 5, 5);
8306 int rd
= extract32(insn
, 0, 5);
8309 /* For some ops (the FP ones), size[1] is part of the encoding.
8310 * For ADDP strictly it is not but size[1] is always 1 for valid
8313 opcode
|= (extract32(size
, 1, 1) << 5);
8316 case 0x3b: /* ADDP */
8317 if (u
|| size
!= 3) {
8318 unallocated_encoding(s
);
8321 if (!fp_access_check(s
)) {
8327 case 0xc: /* FMAXNMP */
8328 case 0xd: /* FADDP */
8329 case 0xf: /* FMAXP */
8330 case 0x2c: /* FMINNMP */
8331 case 0x2f: /* FMINP */
8332 /* FP op, size[0] is 32 or 64 bit*/
8334 if (!dc_isar_feature(aa64_fp16
, s
)) {
8335 unallocated_encoding(s
);
8341 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8344 if (!fp_access_check(s
)) {
8348 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8351 unallocated_encoding(s
);
8355 if (size
== MO_64
) {
8356 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8357 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8358 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8360 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8361 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8364 case 0x3b: /* ADDP */
8365 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8367 case 0xc: /* FMAXNMP */
8368 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8370 case 0xd: /* FADDP */
8371 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8373 case 0xf: /* FMAXP */
8374 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8376 case 0x2c: /* FMINNMP */
8377 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8379 case 0x2f: /* FMINP */
8380 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8383 g_assert_not_reached();
8386 write_fp_dreg(s
, rd
, tcg_res
);
8388 tcg_temp_free_i64(tcg_op1
);
8389 tcg_temp_free_i64(tcg_op2
);
8390 tcg_temp_free_i64(tcg_res
);
8392 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8393 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8394 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8396 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8397 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8399 if (size
== MO_16
) {
8401 case 0xc: /* FMAXNMP */
8402 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8404 case 0xd: /* FADDP */
8405 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8407 case 0xf: /* FMAXP */
8408 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8410 case 0x2c: /* FMINNMP */
8411 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8413 case 0x2f: /* FMINP */
8414 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8417 g_assert_not_reached();
8421 case 0xc: /* FMAXNMP */
8422 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8424 case 0xd: /* FADDP */
8425 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8427 case 0xf: /* FMAXP */
8428 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8430 case 0x2c: /* FMINNMP */
8431 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8433 case 0x2f: /* FMINP */
8434 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8437 g_assert_not_reached();
8441 write_fp_sreg(s
, rd
, tcg_res
);
8443 tcg_temp_free_i32(tcg_op1
);
8444 tcg_temp_free_i32(tcg_op2
);
8445 tcg_temp_free_i32(tcg_res
);
8449 tcg_temp_free_ptr(fpst
);
8454 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8456 * This code is handles the common shifting code and is used by both
8457 * the vector and scalar code.
8459 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8460 TCGv_i64 tcg_rnd
, bool accumulate
,
8461 bool is_u
, int size
, int shift
)
8463 bool extended_result
= false;
8464 bool round
= tcg_rnd
!= NULL
;
8466 TCGv_i64 tcg_src_hi
;
8468 if (round
&& size
== 3) {
8469 extended_result
= true;
8470 ext_lshift
= 64 - shift
;
8471 tcg_src_hi
= tcg_temp_new_i64();
8472 } else if (shift
== 64) {
8473 if (!accumulate
&& is_u
) {
8474 /* result is zero */
8475 tcg_gen_movi_i64(tcg_res
, 0);
8480 /* Deal with the rounding step */
8482 if (extended_result
) {
8483 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8485 /* take care of sign extending tcg_res */
8486 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8487 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8488 tcg_src
, tcg_src_hi
,
8491 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8495 tcg_temp_free_i64(tcg_zero
);
8497 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8501 /* Now do the shift right */
8502 if (round
&& extended_result
) {
8503 /* extended case, >64 bit precision required */
8504 if (ext_lshift
== 0) {
8505 /* special case, only high bits matter */
8506 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8508 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8509 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8510 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8515 /* essentially shifting in 64 zeros */
8516 tcg_gen_movi_i64(tcg_src
, 0);
8518 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8522 /* effectively extending the sign-bit */
8523 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8525 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8531 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8533 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8536 if (extended_result
) {
8537 tcg_temp_free_i64(tcg_src_hi
);
8541 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8542 static void handle_scalar_simd_shri(DisasContext
*s
,
8543 bool is_u
, int immh
, int immb
,
8544 int opcode
, int rn
, int rd
)
8547 int immhb
= immh
<< 3 | immb
;
8548 int shift
= 2 * (8 << size
) - immhb
;
8549 bool accumulate
= false;
8551 bool insert
= false;
8556 if (!extract32(immh
, 3, 1)) {
8557 unallocated_encoding(s
);
8561 if (!fp_access_check(s
)) {
8566 case 0x02: /* SSRA / USRA (accumulate) */
8569 case 0x04: /* SRSHR / URSHR (rounding) */
8572 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8573 accumulate
= round
= true;
8575 case 0x08: /* SRI */
8581 uint64_t round_const
= 1ULL << (shift
- 1);
8582 tcg_round
= tcg_const_i64(round_const
);
8587 tcg_rn
= read_fp_dreg(s
, rn
);
8588 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8591 /* shift count same as element size is valid but does nothing;
8592 * special case to avoid potential shift by 64.
8594 int esize
= 8 << size
;
8595 if (shift
!= esize
) {
8596 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8597 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8600 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8601 accumulate
, is_u
, size
, shift
);
8604 write_fp_dreg(s
, rd
, tcg_rd
);
8606 tcg_temp_free_i64(tcg_rn
);
8607 tcg_temp_free_i64(tcg_rd
);
8609 tcg_temp_free_i64(tcg_round
);
8613 /* SHL/SLI - Scalar shift left */
8614 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8615 int immh
, int immb
, int opcode
,
8618 int size
= 32 - clz32(immh
) - 1;
8619 int immhb
= immh
<< 3 | immb
;
8620 int shift
= immhb
- (8 << size
);
8624 if (!extract32(immh
, 3, 1)) {
8625 unallocated_encoding(s
);
8629 if (!fp_access_check(s
)) {
8633 tcg_rn
= read_fp_dreg(s
, rn
);
8634 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8637 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8639 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8642 write_fp_dreg(s
, rd
, tcg_rd
);
8644 tcg_temp_free_i64(tcg_rn
);
8645 tcg_temp_free_i64(tcg_rd
);
8648 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8649 * (signed/unsigned) narrowing */
8650 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8651 bool is_u_shift
, bool is_u_narrow
,
8652 int immh
, int immb
, int opcode
,
8655 int immhb
= immh
<< 3 | immb
;
8656 int size
= 32 - clz32(immh
) - 1;
8657 int esize
= 8 << size
;
8658 int shift
= (2 * esize
) - immhb
;
8659 int elements
= is_scalar
? 1 : (64 / esize
);
8660 bool round
= extract32(opcode
, 0, 1);
8661 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8662 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8663 TCGv_i32 tcg_rd_narrowed
;
8666 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8667 { gen_helper_neon_narrow_sat_s8
,
8668 gen_helper_neon_unarrow_sat8
},
8669 { gen_helper_neon_narrow_sat_s16
,
8670 gen_helper_neon_unarrow_sat16
},
8671 { gen_helper_neon_narrow_sat_s32
,
8672 gen_helper_neon_unarrow_sat32
},
8675 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8676 gen_helper_neon_narrow_sat_u8
,
8677 gen_helper_neon_narrow_sat_u16
,
8678 gen_helper_neon_narrow_sat_u32
,
8681 NeonGenNarrowEnvFn
*narrowfn
;
8687 if (extract32(immh
, 3, 1)) {
8688 unallocated_encoding(s
);
8692 if (!fp_access_check(s
)) {
8697 narrowfn
= unsigned_narrow_fns
[size
];
8699 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8702 tcg_rn
= tcg_temp_new_i64();
8703 tcg_rd
= tcg_temp_new_i64();
8704 tcg_rd_narrowed
= tcg_temp_new_i32();
8705 tcg_final
= tcg_const_i64(0);
8708 uint64_t round_const
= 1ULL << (shift
- 1);
8709 tcg_round
= tcg_const_i64(round_const
);
8714 for (i
= 0; i
< elements
; i
++) {
8715 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8716 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8717 false, is_u_shift
, size
+1, shift
);
8718 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8719 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8720 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8724 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8726 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8730 tcg_temp_free_i64(tcg_round
);
8732 tcg_temp_free_i64(tcg_rn
);
8733 tcg_temp_free_i64(tcg_rd
);
8734 tcg_temp_free_i32(tcg_rd_narrowed
);
8735 tcg_temp_free_i64(tcg_final
);
8737 clear_vec_high(s
, is_q
, rd
);
8740 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8741 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8742 bool src_unsigned
, bool dst_unsigned
,
8743 int immh
, int immb
, int rn
, int rd
)
8745 int immhb
= immh
<< 3 | immb
;
8746 int size
= 32 - clz32(immh
) - 1;
8747 int shift
= immhb
- (8 << size
);
8751 assert(!(scalar
&& is_q
));
8754 if (!is_q
&& extract32(immh
, 3, 1)) {
8755 unallocated_encoding(s
);
8759 /* Since we use the variable-shift helpers we must
8760 * replicate the shift count into each element of
8761 * the tcg_shift value.
8765 shift
|= shift
<< 8;
8768 shift
|= shift
<< 16;
8774 g_assert_not_reached();
8778 if (!fp_access_check(s
)) {
8783 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8784 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8785 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8786 { NULL
, gen_helper_neon_qshl_u64
},
8788 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8789 int maxpass
= is_q
? 2 : 1;
8791 for (pass
= 0; pass
< maxpass
; pass
++) {
8792 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8794 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8795 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8796 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8798 tcg_temp_free_i64(tcg_op
);
8800 tcg_temp_free_i64(tcg_shift
);
8801 clear_vec_high(s
, is_q
, rd
);
8803 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8804 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8806 { gen_helper_neon_qshl_s8
,
8807 gen_helper_neon_qshl_s16
,
8808 gen_helper_neon_qshl_s32
},
8809 { gen_helper_neon_qshlu_s8
,
8810 gen_helper_neon_qshlu_s16
,
8811 gen_helper_neon_qshlu_s32
}
8813 { NULL
, NULL
, NULL
},
8814 { gen_helper_neon_qshl_u8
,
8815 gen_helper_neon_qshl_u16
,
8816 gen_helper_neon_qshl_u32
}
8819 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8820 MemOp memop
= scalar
? size
: MO_32
;
8821 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8823 for (pass
= 0; pass
< maxpass
; pass
++) {
8824 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8826 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8827 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8831 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8834 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8839 g_assert_not_reached();
8841 write_fp_sreg(s
, rd
, tcg_op
);
8843 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8846 tcg_temp_free_i32(tcg_op
);
8848 tcg_temp_free_i32(tcg_shift
);
8851 clear_vec_high(s
, is_q
, rd
);
8856 /* Common vector code for handling integer to FP conversion */
8857 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8858 int elements
, int is_signed
,
8859 int fracbits
, int size
)
8861 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8862 TCGv_i32 tcg_shift
= NULL
;
8864 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8867 if (fracbits
|| size
== MO_64
) {
8868 tcg_shift
= tcg_const_i32(fracbits
);
8871 if (size
== MO_64
) {
8872 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8873 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8875 for (pass
= 0; pass
< elements
; pass
++) {
8876 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8879 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8880 tcg_shift
, tcg_fpst
);
8882 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8883 tcg_shift
, tcg_fpst
);
8885 if (elements
== 1) {
8886 write_fp_dreg(s
, rd
, tcg_double
);
8888 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8892 tcg_temp_free_i64(tcg_int64
);
8893 tcg_temp_free_i64(tcg_double
);
8896 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8897 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8899 for (pass
= 0; pass
< elements
; pass
++) {
8900 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8906 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8907 tcg_shift
, tcg_fpst
);
8909 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8910 tcg_shift
, tcg_fpst
);
8914 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8916 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8923 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8924 tcg_shift
, tcg_fpst
);
8926 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8927 tcg_shift
, tcg_fpst
);
8931 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8933 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8938 g_assert_not_reached();
8941 if (elements
== 1) {
8942 write_fp_sreg(s
, rd
, tcg_float
);
8944 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8948 tcg_temp_free_i32(tcg_int32
);
8949 tcg_temp_free_i32(tcg_float
);
8952 tcg_temp_free_ptr(tcg_fpst
);
8954 tcg_temp_free_i32(tcg_shift
);
8957 clear_vec_high(s
, elements
<< size
== 16, rd
);
8960 /* UCVTF/SCVTF - Integer to FP conversion */
8961 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8962 bool is_q
, bool is_u
,
8963 int immh
, int immb
, int opcode
,
8966 int size
, elements
, fracbits
;
8967 int immhb
= immh
<< 3 | immb
;
8971 if (!is_scalar
&& !is_q
) {
8972 unallocated_encoding(s
);
8975 } else if (immh
& 4) {
8977 } else if (immh
& 2) {
8979 if (!dc_isar_feature(aa64_fp16
, s
)) {
8980 unallocated_encoding(s
);
8984 /* immh == 0 would be a failure of the decode logic */
8985 g_assert(immh
== 1);
8986 unallocated_encoding(s
);
8993 elements
= (8 << is_q
) >> size
;
8995 fracbits
= (16 << size
) - immhb
;
8997 if (!fp_access_check(s
)) {
9001 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
9004 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
9005 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
9006 bool is_q
, bool is_u
,
9007 int immh
, int immb
, int rn
, int rd
)
9009 int immhb
= immh
<< 3 | immb
;
9010 int pass
, size
, fracbits
;
9011 TCGv_ptr tcg_fpstatus
;
9012 TCGv_i32 tcg_rmode
, tcg_shift
;
9016 if (!is_scalar
&& !is_q
) {
9017 unallocated_encoding(s
);
9020 } else if (immh
& 0x4) {
9022 } else if (immh
& 0x2) {
9024 if (!dc_isar_feature(aa64_fp16
, s
)) {
9025 unallocated_encoding(s
);
9029 /* Should have split out AdvSIMD modified immediate earlier. */
9031 unallocated_encoding(s
);
9035 if (!fp_access_check(s
)) {
9039 assert(!(is_scalar
&& is_q
));
9041 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9042 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9043 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9044 fracbits
= (16 << size
) - immhb
;
9045 tcg_shift
= tcg_const_i32(fracbits
);
9047 if (size
== MO_64
) {
9048 int maxpass
= is_scalar
? 1 : 2;
9050 for (pass
= 0; pass
< maxpass
; pass
++) {
9051 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9053 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9055 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9057 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9059 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9060 tcg_temp_free_i64(tcg_op
);
9062 clear_vec_high(s
, is_q
, rd
);
9064 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9065 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9070 fn
= gen_helper_vfp_touhh
;
9072 fn
= gen_helper_vfp_toshh
;
9077 fn
= gen_helper_vfp_touls
;
9079 fn
= gen_helper_vfp_tosls
;
9083 g_assert_not_reached();
9086 for (pass
= 0; pass
< maxpass
; pass
++) {
9087 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9089 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9090 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9092 write_fp_sreg(s
, rd
, tcg_op
);
9094 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9096 tcg_temp_free_i32(tcg_op
);
9099 clear_vec_high(s
, is_q
, rd
);
9103 tcg_temp_free_ptr(tcg_fpstatus
);
9104 tcg_temp_free_i32(tcg_shift
);
9105 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9106 tcg_temp_free_i32(tcg_rmode
);
9109 /* AdvSIMD scalar shift by immediate
9110 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9111 * +-----+---+-------------+------+------+--------+---+------+------+
9112 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9113 * +-----+---+-------------+------+------+--------+---+------+------+
9115 * This is the scalar version so it works on a fixed sized registers
9117 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9119 int rd
= extract32(insn
, 0, 5);
9120 int rn
= extract32(insn
, 5, 5);
9121 int opcode
= extract32(insn
, 11, 5);
9122 int immb
= extract32(insn
, 16, 3);
9123 int immh
= extract32(insn
, 19, 4);
9124 bool is_u
= extract32(insn
, 29, 1);
9127 unallocated_encoding(s
);
9132 case 0x08: /* SRI */
9134 unallocated_encoding(s
);
9138 case 0x00: /* SSHR / USHR */
9139 case 0x02: /* SSRA / USRA */
9140 case 0x04: /* SRSHR / URSHR */
9141 case 0x06: /* SRSRA / URSRA */
9142 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9144 case 0x0a: /* SHL / SLI */
9145 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9147 case 0x1c: /* SCVTF, UCVTF */
9148 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9151 case 0x10: /* SQSHRUN, SQSHRUN2 */
9152 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9154 unallocated_encoding(s
);
9157 handle_vec_simd_sqshrn(s
, true, false, false, true,
9158 immh
, immb
, opcode
, rn
, rd
);
9160 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9161 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9162 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9163 immh
, immb
, opcode
, rn
, rd
);
9165 case 0xc: /* SQSHLU */
9167 unallocated_encoding(s
);
9170 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9172 case 0xe: /* SQSHL, UQSHL */
9173 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9175 case 0x1f: /* FCVTZS, FCVTZU */
9176 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9179 unallocated_encoding(s
);
9184 /* AdvSIMD scalar three different
9185 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9186 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9187 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9188 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9190 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9192 bool is_u
= extract32(insn
, 29, 1);
9193 int size
= extract32(insn
, 22, 2);
9194 int opcode
= extract32(insn
, 12, 4);
9195 int rm
= extract32(insn
, 16, 5);
9196 int rn
= extract32(insn
, 5, 5);
9197 int rd
= extract32(insn
, 0, 5);
9200 unallocated_encoding(s
);
9205 case 0x9: /* SQDMLAL, SQDMLAL2 */
9206 case 0xb: /* SQDMLSL, SQDMLSL2 */
9207 case 0xd: /* SQDMULL, SQDMULL2 */
9208 if (size
== 0 || size
== 3) {
9209 unallocated_encoding(s
);
9214 unallocated_encoding(s
);
9218 if (!fp_access_check(s
)) {
9223 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9224 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9225 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9227 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9228 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9230 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9231 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9234 case 0xd: /* SQDMULL, SQDMULL2 */
9236 case 0xb: /* SQDMLSL, SQDMLSL2 */
9237 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9239 case 0x9: /* SQDMLAL, SQDMLAL2 */
9240 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9241 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9245 g_assert_not_reached();
9248 write_fp_dreg(s
, rd
, tcg_res
);
9250 tcg_temp_free_i64(tcg_op1
);
9251 tcg_temp_free_i64(tcg_op2
);
9252 tcg_temp_free_i64(tcg_res
);
9254 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9255 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9256 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9258 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9259 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9262 case 0xd: /* SQDMULL, SQDMULL2 */
9264 case 0xb: /* SQDMLSL, SQDMLSL2 */
9265 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9267 case 0x9: /* SQDMLAL, SQDMLAL2 */
9269 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9270 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9271 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9273 tcg_temp_free_i64(tcg_op3
);
9277 g_assert_not_reached();
9280 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9281 write_fp_dreg(s
, rd
, tcg_res
);
9283 tcg_temp_free_i32(tcg_op1
);
9284 tcg_temp_free_i32(tcg_op2
);
9285 tcg_temp_free_i64(tcg_res
);
9289 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9290 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9292 /* Handle 64x64->64 opcodes which are shared between the scalar
9293 * and vector 3-same groups. We cover every opcode where size == 3
9294 * is valid in either the three-reg-same (integer, not pairwise)
9295 * or scalar-three-reg-same groups.
9300 case 0x1: /* SQADD */
9302 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9304 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9307 case 0x5: /* SQSUB */
9309 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9311 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9314 case 0x6: /* CMGT, CMHI */
9315 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9316 * We implement this using setcond (test) and then negating.
9318 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9320 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9321 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9323 case 0x7: /* CMGE, CMHS */
9324 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9326 case 0x11: /* CMTST, CMEQ */
9331 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9333 case 0x8: /* SSHL, USHL */
9335 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9337 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9340 case 0x9: /* SQSHL, UQSHL */
9342 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9344 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9347 case 0xa: /* SRSHL, URSHL */
9349 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9351 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9354 case 0xb: /* SQRSHL, UQRSHL */
9356 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9358 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9361 case 0x10: /* ADD, SUB */
9363 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9365 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9369 g_assert_not_reached();
9373 /* Handle the 3-same-operands float operations; shared by the scalar
9374 * and vector encodings. The caller must filter out any encodings
9375 * not allocated for the encoding it is dealing with.
9377 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9378 int fpopcode
, int rd
, int rn
, int rm
)
9381 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9383 for (pass
= 0; pass
< elements
; pass
++) {
9386 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9387 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9388 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9390 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9391 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9394 case 0x39: /* FMLS */
9395 /* As usual for ARM, separate negation for fused multiply-add */
9396 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9398 case 0x19: /* FMLA */
9399 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9400 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9403 case 0x18: /* FMAXNM */
9404 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9406 case 0x1a: /* FADD */
9407 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9409 case 0x1b: /* FMULX */
9410 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9412 case 0x1c: /* FCMEQ */
9413 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9415 case 0x1e: /* FMAX */
9416 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9418 case 0x1f: /* FRECPS */
9419 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9421 case 0x38: /* FMINNM */
9422 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9424 case 0x3a: /* FSUB */
9425 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9427 case 0x3e: /* FMIN */
9428 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9430 case 0x3f: /* FRSQRTS */
9431 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9433 case 0x5b: /* FMUL */
9434 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9436 case 0x5c: /* FCMGE */
9437 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9439 case 0x5d: /* FACGE */
9440 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9442 case 0x5f: /* FDIV */
9443 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9445 case 0x7a: /* FABD */
9446 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9447 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9449 case 0x7c: /* FCMGT */
9450 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9452 case 0x7d: /* FACGT */
9453 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9456 g_assert_not_reached();
9459 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9461 tcg_temp_free_i64(tcg_res
);
9462 tcg_temp_free_i64(tcg_op1
);
9463 tcg_temp_free_i64(tcg_op2
);
9466 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9467 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9468 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9470 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9471 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9474 case 0x39: /* FMLS */
9475 /* As usual for ARM, separate negation for fused multiply-add */
9476 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9478 case 0x19: /* FMLA */
9479 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9480 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9483 case 0x1a: /* FADD */
9484 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9486 case 0x1b: /* FMULX */
9487 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9489 case 0x1c: /* FCMEQ */
9490 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9492 case 0x1e: /* FMAX */
9493 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9495 case 0x1f: /* FRECPS */
9496 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9498 case 0x18: /* FMAXNM */
9499 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9501 case 0x38: /* FMINNM */
9502 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9504 case 0x3a: /* FSUB */
9505 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9507 case 0x3e: /* FMIN */
9508 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9510 case 0x3f: /* FRSQRTS */
9511 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9513 case 0x5b: /* FMUL */
9514 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9516 case 0x5c: /* FCMGE */
9517 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9519 case 0x5d: /* FACGE */
9520 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9522 case 0x5f: /* FDIV */
9523 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9525 case 0x7a: /* FABD */
9526 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9527 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9529 case 0x7c: /* FCMGT */
9530 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9532 case 0x7d: /* FACGT */
9533 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9536 g_assert_not_reached();
9539 if (elements
== 1) {
9540 /* scalar single so clear high part */
9541 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9543 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9544 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9545 tcg_temp_free_i64(tcg_tmp
);
9547 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9550 tcg_temp_free_i32(tcg_res
);
9551 tcg_temp_free_i32(tcg_op1
);
9552 tcg_temp_free_i32(tcg_op2
);
9556 tcg_temp_free_ptr(fpst
);
9558 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9561 /* AdvSIMD scalar three same
9562 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9563 * +-----+---+-----------+------+---+------+--------+---+------+------+
9564 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9565 * +-----+---+-----------+------+---+------+--------+---+------+------+
9567 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9569 int rd
= extract32(insn
, 0, 5);
9570 int rn
= extract32(insn
, 5, 5);
9571 int opcode
= extract32(insn
, 11, 5);
9572 int rm
= extract32(insn
, 16, 5);
9573 int size
= extract32(insn
, 22, 2);
9574 bool u
= extract32(insn
, 29, 1);
9577 if (opcode
>= 0x18) {
9578 /* Floating point: U, size[1] and opcode indicate operation */
9579 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9581 case 0x1b: /* FMULX */
9582 case 0x1f: /* FRECPS */
9583 case 0x3f: /* FRSQRTS */
9584 case 0x5d: /* FACGE */
9585 case 0x7d: /* FACGT */
9586 case 0x1c: /* FCMEQ */
9587 case 0x5c: /* FCMGE */
9588 case 0x7c: /* FCMGT */
9589 case 0x7a: /* FABD */
9592 unallocated_encoding(s
);
9596 if (!fp_access_check(s
)) {
9600 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9605 case 0x1: /* SQADD, UQADD */
9606 case 0x5: /* SQSUB, UQSUB */
9607 case 0x9: /* SQSHL, UQSHL */
9608 case 0xb: /* SQRSHL, UQRSHL */
9610 case 0x8: /* SSHL, USHL */
9611 case 0xa: /* SRSHL, URSHL */
9612 case 0x6: /* CMGT, CMHI */
9613 case 0x7: /* CMGE, CMHS */
9614 case 0x11: /* CMTST, CMEQ */
9615 case 0x10: /* ADD, SUB (vector) */
9617 unallocated_encoding(s
);
9621 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9622 if (size
!= 1 && size
!= 2) {
9623 unallocated_encoding(s
);
9628 unallocated_encoding(s
);
9632 if (!fp_access_check(s
)) {
9636 tcg_rd
= tcg_temp_new_i64();
9639 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9640 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9642 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9643 tcg_temp_free_i64(tcg_rn
);
9644 tcg_temp_free_i64(tcg_rm
);
9646 /* Do a single operation on the lowest element in the vector.
9647 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9648 * no side effects for all these operations.
9649 * OPTME: special-purpose helpers would avoid doing some
9650 * unnecessary work in the helper for the 8 and 16 bit cases.
9652 NeonGenTwoOpEnvFn
*genenvfn
;
9653 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9654 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9655 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9657 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9658 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9661 case 0x1: /* SQADD, UQADD */
9663 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9664 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9665 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9666 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9668 genenvfn
= fns
[size
][u
];
9671 case 0x5: /* SQSUB, UQSUB */
9673 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9674 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9675 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9676 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9678 genenvfn
= fns
[size
][u
];
9681 case 0x9: /* SQSHL, UQSHL */
9683 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9684 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9685 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9686 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9688 genenvfn
= fns
[size
][u
];
9691 case 0xb: /* SQRSHL, UQRSHL */
9693 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9694 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9695 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9696 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9698 genenvfn
= fns
[size
][u
];
9701 case 0x16: /* SQDMULH, SQRDMULH */
9703 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9704 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9705 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9707 assert(size
== 1 || size
== 2);
9708 genenvfn
= fns
[size
- 1][u
];
9712 g_assert_not_reached();
9715 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9716 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9717 tcg_temp_free_i32(tcg_rd32
);
9718 tcg_temp_free_i32(tcg_rn
);
9719 tcg_temp_free_i32(tcg_rm
);
9722 write_fp_dreg(s
, rd
, tcg_rd
);
9724 tcg_temp_free_i64(tcg_rd
);
9727 /* AdvSIMD scalar three same FP16
9728 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9729 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9730 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9731 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9732 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9733 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9735 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9738 int rd
= extract32(insn
, 0, 5);
9739 int rn
= extract32(insn
, 5, 5);
9740 int opcode
= extract32(insn
, 11, 3);
9741 int rm
= extract32(insn
, 16, 5);
9742 bool u
= extract32(insn
, 29, 1);
9743 bool a
= extract32(insn
, 23, 1);
9744 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9751 case 0x03: /* FMULX */
9752 case 0x04: /* FCMEQ (reg) */
9753 case 0x07: /* FRECPS */
9754 case 0x0f: /* FRSQRTS */
9755 case 0x14: /* FCMGE (reg) */
9756 case 0x15: /* FACGE */
9757 case 0x1a: /* FABD */
9758 case 0x1c: /* FCMGT (reg) */
9759 case 0x1d: /* FACGT */
9762 unallocated_encoding(s
);
9766 if (!dc_isar_feature(aa64_fp16
, s
)) {
9767 unallocated_encoding(s
);
9770 if (!fp_access_check(s
)) {
9774 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9776 tcg_op1
= read_fp_hreg(s
, rn
);
9777 tcg_op2
= read_fp_hreg(s
, rm
);
9778 tcg_res
= tcg_temp_new_i32();
9781 case 0x03: /* FMULX */
9782 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9784 case 0x04: /* FCMEQ (reg) */
9785 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9787 case 0x07: /* FRECPS */
9788 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9790 case 0x0f: /* FRSQRTS */
9791 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9793 case 0x14: /* FCMGE (reg) */
9794 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9796 case 0x15: /* FACGE */
9797 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9799 case 0x1a: /* FABD */
9800 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9801 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9803 case 0x1c: /* FCMGT (reg) */
9804 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9806 case 0x1d: /* FACGT */
9807 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9810 g_assert_not_reached();
9813 write_fp_sreg(s
, rd
, tcg_res
);
9816 tcg_temp_free_i32(tcg_res
);
9817 tcg_temp_free_i32(tcg_op1
);
9818 tcg_temp_free_i32(tcg_op2
);
9819 tcg_temp_free_ptr(fpst
);
9822 /* AdvSIMD scalar three same extra
9823 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9824 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9825 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9826 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9828 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9831 int rd
= extract32(insn
, 0, 5);
9832 int rn
= extract32(insn
, 5, 5);
9833 int opcode
= extract32(insn
, 11, 4);
9834 int rm
= extract32(insn
, 16, 5);
9835 int size
= extract32(insn
, 22, 2);
9836 bool u
= extract32(insn
, 29, 1);
9837 TCGv_i32 ele1
, ele2
, ele3
;
9841 switch (u
* 16 + opcode
) {
9842 case 0x10: /* SQRDMLAH (vector) */
9843 case 0x11: /* SQRDMLSH (vector) */
9844 if (size
!= 1 && size
!= 2) {
9845 unallocated_encoding(s
);
9848 feature
= dc_isar_feature(aa64_rdm
, s
);
9851 unallocated_encoding(s
);
9855 unallocated_encoding(s
);
9858 if (!fp_access_check(s
)) {
9862 /* Do a single operation on the lowest element in the vector.
9863 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9864 * with no side effects for all these operations.
9865 * OPTME: special-purpose helpers would avoid doing some
9866 * unnecessary work in the helper for the 16 bit cases.
9868 ele1
= tcg_temp_new_i32();
9869 ele2
= tcg_temp_new_i32();
9870 ele3
= tcg_temp_new_i32();
9872 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9873 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9874 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9877 case 0x0: /* SQRDMLAH */
9879 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9881 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9884 case 0x1: /* SQRDMLSH */
9886 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9888 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9892 g_assert_not_reached();
9894 tcg_temp_free_i32(ele1
);
9895 tcg_temp_free_i32(ele2
);
9897 res
= tcg_temp_new_i64();
9898 tcg_gen_extu_i32_i64(res
, ele3
);
9899 tcg_temp_free_i32(ele3
);
9901 write_fp_dreg(s
, rd
, res
);
9902 tcg_temp_free_i64(res
);
9905 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9906 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9907 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9909 /* Handle 64->64 opcodes which are shared between the scalar and
9910 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9911 * is valid in either group and also the double-precision fp ops.
9912 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9918 case 0x4: /* CLS, CLZ */
9920 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9922 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9926 /* This opcode is shared with CNT and RBIT but we have earlier
9927 * enforced that size == 3 if and only if this is the NOT insn.
9929 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9931 case 0x7: /* SQABS, SQNEG */
9933 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9935 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9938 case 0xa: /* CMLT */
9939 /* 64 bit integer comparison against zero, result is
9940 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9945 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9946 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9948 case 0x8: /* CMGT, CMGE */
9949 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9951 case 0x9: /* CMEQ, CMLE */
9952 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9954 case 0xb: /* ABS, NEG */
9956 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9958 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9961 case 0x2f: /* FABS */
9962 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9964 case 0x6f: /* FNEG */
9965 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9967 case 0x7f: /* FSQRT */
9968 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9970 case 0x1a: /* FCVTNS */
9971 case 0x1b: /* FCVTMS */
9972 case 0x1c: /* FCVTAS */
9973 case 0x3a: /* FCVTPS */
9974 case 0x3b: /* FCVTZS */
9976 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9977 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9978 tcg_temp_free_i32(tcg_shift
);
9981 case 0x5a: /* FCVTNU */
9982 case 0x5b: /* FCVTMU */
9983 case 0x5c: /* FCVTAU */
9984 case 0x7a: /* FCVTPU */
9985 case 0x7b: /* FCVTZU */
9987 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9988 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9989 tcg_temp_free_i32(tcg_shift
);
9992 case 0x18: /* FRINTN */
9993 case 0x19: /* FRINTM */
9994 case 0x38: /* FRINTP */
9995 case 0x39: /* FRINTZ */
9996 case 0x58: /* FRINTA */
9997 case 0x79: /* FRINTI */
9998 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10000 case 0x59: /* FRINTX */
10001 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10003 case 0x1e: /* FRINT32Z */
10004 case 0x5e: /* FRINT32X */
10005 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10007 case 0x1f: /* FRINT64Z */
10008 case 0x5f: /* FRINT64X */
10009 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10012 g_assert_not_reached();
10016 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
10017 bool is_scalar
, bool is_u
, bool is_q
,
10018 int size
, int rn
, int rd
)
10020 bool is_double
= (size
== MO_64
);
10023 if (!fp_access_check(s
)) {
10027 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
10030 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10031 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10032 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10033 NeonGenTwoDoubleOpFn
*genfn
;
10038 case 0x2e: /* FCMLT (zero) */
10041 case 0x2c: /* FCMGT (zero) */
10042 genfn
= gen_helper_neon_cgt_f64
;
10044 case 0x2d: /* FCMEQ (zero) */
10045 genfn
= gen_helper_neon_ceq_f64
;
10047 case 0x6d: /* FCMLE (zero) */
10050 case 0x6c: /* FCMGE (zero) */
10051 genfn
= gen_helper_neon_cge_f64
;
10054 g_assert_not_reached();
10057 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10058 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10060 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10062 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10064 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10066 tcg_temp_free_i64(tcg_res
);
10067 tcg_temp_free_i64(tcg_zero
);
10068 tcg_temp_free_i64(tcg_op
);
10070 clear_vec_high(s
, !is_scalar
, rd
);
10072 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10073 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10074 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10075 NeonGenTwoSingleOpFn
*genfn
;
10077 int pass
, maxpasses
;
10079 if (size
== MO_16
) {
10081 case 0x2e: /* FCMLT (zero) */
10084 case 0x2c: /* FCMGT (zero) */
10085 genfn
= gen_helper_advsimd_cgt_f16
;
10087 case 0x2d: /* FCMEQ (zero) */
10088 genfn
= gen_helper_advsimd_ceq_f16
;
10090 case 0x6d: /* FCMLE (zero) */
10093 case 0x6c: /* FCMGE (zero) */
10094 genfn
= gen_helper_advsimd_cge_f16
;
10097 g_assert_not_reached();
10101 case 0x2e: /* FCMLT (zero) */
10104 case 0x2c: /* FCMGT (zero) */
10105 genfn
= gen_helper_neon_cgt_f32
;
10107 case 0x2d: /* FCMEQ (zero) */
10108 genfn
= gen_helper_neon_ceq_f32
;
10110 case 0x6d: /* FCMLE (zero) */
10113 case 0x6c: /* FCMGE (zero) */
10114 genfn
= gen_helper_neon_cge_f32
;
10117 g_assert_not_reached();
10124 int vector_size
= 8 << is_q
;
10125 maxpasses
= vector_size
>> size
;
10128 for (pass
= 0; pass
< maxpasses
; pass
++) {
10129 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10131 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10133 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10136 write_fp_sreg(s
, rd
, tcg_res
);
10138 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10141 tcg_temp_free_i32(tcg_res
);
10142 tcg_temp_free_i32(tcg_zero
);
10143 tcg_temp_free_i32(tcg_op
);
10145 clear_vec_high(s
, is_q
, rd
);
10149 tcg_temp_free_ptr(fpst
);
10152 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10153 bool is_scalar
, bool is_u
, bool is_q
,
10154 int size
, int rn
, int rd
)
10156 bool is_double
= (size
== 3);
10157 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10160 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10161 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10164 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10165 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10167 case 0x3d: /* FRECPE */
10168 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10170 case 0x3f: /* FRECPX */
10171 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10173 case 0x7d: /* FRSQRTE */
10174 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10177 g_assert_not_reached();
10179 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10181 tcg_temp_free_i64(tcg_res
);
10182 tcg_temp_free_i64(tcg_op
);
10183 clear_vec_high(s
, !is_scalar
, rd
);
10185 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10186 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10187 int pass
, maxpasses
;
10192 maxpasses
= is_q
? 4 : 2;
10195 for (pass
= 0; pass
< maxpasses
; pass
++) {
10196 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10199 case 0x3c: /* URECPE */
10200 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10202 case 0x3d: /* FRECPE */
10203 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10205 case 0x3f: /* FRECPX */
10206 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10208 case 0x7d: /* FRSQRTE */
10209 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10212 g_assert_not_reached();
10216 write_fp_sreg(s
, rd
, tcg_res
);
10218 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10221 tcg_temp_free_i32(tcg_res
);
10222 tcg_temp_free_i32(tcg_op
);
10224 clear_vec_high(s
, is_q
, rd
);
10227 tcg_temp_free_ptr(fpst
);
10230 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10231 int opcode
, bool u
, bool is_q
,
10232 int size
, int rn
, int rd
)
10234 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10235 * in the source becomes a size element in the destination).
10238 TCGv_i32 tcg_res
[2];
10239 int destelt
= is_q
? 2 : 0;
10240 int passes
= scalar
? 1 : 2;
10243 tcg_res
[1] = tcg_const_i32(0);
10246 for (pass
= 0; pass
< passes
; pass
++) {
10247 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10248 NeonGenNarrowFn
*genfn
= NULL
;
10249 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10252 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10254 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10256 tcg_res
[pass
] = tcg_temp_new_i32();
10259 case 0x12: /* XTN, SQXTUN */
10261 static NeonGenNarrowFn
* const xtnfns
[3] = {
10262 gen_helper_neon_narrow_u8
,
10263 gen_helper_neon_narrow_u16
,
10264 tcg_gen_extrl_i64_i32
,
10266 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10267 gen_helper_neon_unarrow_sat8
,
10268 gen_helper_neon_unarrow_sat16
,
10269 gen_helper_neon_unarrow_sat32
,
10272 genenvfn
= sqxtunfns
[size
];
10274 genfn
= xtnfns
[size
];
10278 case 0x14: /* SQXTN, UQXTN */
10280 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10281 { gen_helper_neon_narrow_sat_s8
,
10282 gen_helper_neon_narrow_sat_u8
},
10283 { gen_helper_neon_narrow_sat_s16
,
10284 gen_helper_neon_narrow_sat_u16
},
10285 { gen_helper_neon_narrow_sat_s32
,
10286 gen_helper_neon_narrow_sat_u32
},
10288 genenvfn
= fns
[size
][u
];
10291 case 0x16: /* FCVTN, FCVTN2 */
10292 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10294 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10296 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10297 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10298 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10299 TCGv_i32 ahp
= get_ahp_flag();
10301 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10302 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10303 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10304 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10305 tcg_temp_free_i32(tcg_lo
);
10306 tcg_temp_free_i32(tcg_hi
);
10307 tcg_temp_free_ptr(fpst
);
10308 tcg_temp_free_i32(ahp
);
10311 case 0x56: /* FCVTXN, FCVTXN2 */
10312 /* 64 bit to 32 bit float conversion
10313 * with von Neumann rounding (round to odd)
10316 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10319 g_assert_not_reached();
10323 genfn(tcg_res
[pass
], tcg_op
);
10324 } else if (genenvfn
) {
10325 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10328 tcg_temp_free_i64(tcg_op
);
10331 for (pass
= 0; pass
< 2; pass
++) {
10332 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10333 tcg_temp_free_i32(tcg_res
[pass
]);
10335 clear_vec_high(s
, is_q
, rd
);
10338 /* Remaining saturating accumulating ops */
10339 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10340 bool is_q
, int size
, int rn
, int rd
)
10342 bool is_double
= (size
== 3);
10345 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10346 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10349 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10350 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10351 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10353 if (is_u
) { /* USQADD */
10354 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10355 } else { /* SUQADD */
10356 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10358 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10360 tcg_temp_free_i64(tcg_rd
);
10361 tcg_temp_free_i64(tcg_rn
);
10362 clear_vec_high(s
, !is_scalar
, rd
);
10364 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10365 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10366 int pass
, maxpasses
;
10371 maxpasses
= is_q
? 4 : 2;
10374 for (pass
= 0; pass
< maxpasses
; pass
++) {
10376 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10377 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10379 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10380 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10383 if (is_u
) { /* USQADD */
10386 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10389 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10392 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10395 g_assert_not_reached();
10397 } else { /* SUQADD */
10400 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10403 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10406 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10409 g_assert_not_reached();
10414 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10415 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10416 tcg_temp_free_i64(tcg_zero
);
10418 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10420 tcg_temp_free_i32(tcg_rd
);
10421 tcg_temp_free_i32(tcg_rn
);
10422 clear_vec_high(s
, is_q
, rd
);
10426 /* AdvSIMD scalar two reg misc
10427 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10428 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10429 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10430 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10432 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10434 int rd
= extract32(insn
, 0, 5);
10435 int rn
= extract32(insn
, 5, 5);
10436 int opcode
= extract32(insn
, 12, 5);
10437 int size
= extract32(insn
, 22, 2);
10438 bool u
= extract32(insn
, 29, 1);
10439 bool is_fcvt
= false;
10441 TCGv_i32 tcg_rmode
;
10442 TCGv_ptr tcg_fpstatus
;
10445 case 0x3: /* USQADD / SUQADD*/
10446 if (!fp_access_check(s
)) {
10449 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10451 case 0x7: /* SQABS / SQNEG */
10453 case 0xa: /* CMLT */
10455 unallocated_encoding(s
);
10459 case 0x8: /* CMGT, CMGE */
10460 case 0x9: /* CMEQ, CMLE */
10461 case 0xb: /* ABS, NEG */
10463 unallocated_encoding(s
);
10467 case 0x12: /* SQXTUN */
10469 unallocated_encoding(s
);
10473 case 0x14: /* SQXTN, UQXTN */
10475 unallocated_encoding(s
);
10478 if (!fp_access_check(s
)) {
10481 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10484 case 0x16 ... 0x1d:
10486 /* Floating point: U, size[1] and opcode indicate operation;
10487 * size[0] indicates single or double precision.
10489 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10490 size
= extract32(size
, 0, 1) ? 3 : 2;
10492 case 0x2c: /* FCMGT (zero) */
10493 case 0x2d: /* FCMEQ (zero) */
10494 case 0x2e: /* FCMLT (zero) */
10495 case 0x6c: /* FCMGE (zero) */
10496 case 0x6d: /* FCMLE (zero) */
10497 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10499 case 0x1d: /* SCVTF */
10500 case 0x5d: /* UCVTF */
10502 bool is_signed
= (opcode
== 0x1d);
10503 if (!fp_access_check(s
)) {
10506 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10509 case 0x3d: /* FRECPE */
10510 case 0x3f: /* FRECPX */
10511 case 0x7d: /* FRSQRTE */
10512 if (!fp_access_check(s
)) {
10515 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10517 case 0x1a: /* FCVTNS */
10518 case 0x1b: /* FCVTMS */
10519 case 0x3a: /* FCVTPS */
10520 case 0x3b: /* FCVTZS */
10521 case 0x5a: /* FCVTNU */
10522 case 0x5b: /* FCVTMU */
10523 case 0x7a: /* FCVTPU */
10524 case 0x7b: /* FCVTZU */
10526 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10528 case 0x1c: /* FCVTAS */
10529 case 0x5c: /* FCVTAU */
10530 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10532 rmode
= FPROUNDING_TIEAWAY
;
10534 case 0x56: /* FCVTXN, FCVTXN2 */
10536 unallocated_encoding(s
);
10539 if (!fp_access_check(s
)) {
10542 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10545 unallocated_encoding(s
);
10550 unallocated_encoding(s
);
10554 if (!fp_access_check(s
)) {
10559 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10560 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10561 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10564 tcg_fpstatus
= NULL
;
10568 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10569 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10571 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10572 write_fp_dreg(s
, rd
, tcg_rd
);
10573 tcg_temp_free_i64(tcg_rd
);
10574 tcg_temp_free_i64(tcg_rn
);
10576 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10577 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10579 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10582 case 0x7: /* SQABS, SQNEG */
10584 NeonGenOneOpEnvFn
*genfn
;
10585 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10586 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10587 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10588 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10590 genfn
= fns
[size
][u
];
10591 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10594 case 0x1a: /* FCVTNS */
10595 case 0x1b: /* FCVTMS */
10596 case 0x1c: /* FCVTAS */
10597 case 0x3a: /* FCVTPS */
10598 case 0x3b: /* FCVTZS */
10600 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10601 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10602 tcg_temp_free_i32(tcg_shift
);
10605 case 0x5a: /* FCVTNU */
10606 case 0x5b: /* FCVTMU */
10607 case 0x5c: /* FCVTAU */
10608 case 0x7a: /* FCVTPU */
10609 case 0x7b: /* FCVTZU */
10611 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10612 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10613 tcg_temp_free_i32(tcg_shift
);
10617 g_assert_not_reached();
10620 write_fp_sreg(s
, rd
, tcg_rd
);
10621 tcg_temp_free_i32(tcg_rd
);
10622 tcg_temp_free_i32(tcg_rn
);
10626 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10627 tcg_temp_free_i32(tcg_rmode
);
10628 tcg_temp_free_ptr(tcg_fpstatus
);
10632 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10633 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10634 int immh
, int immb
, int opcode
, int rn
, int rd
)
10636 int size
= 32 - clz32(immh
) - 1;
10637 int immhb
= immh
<< 3 | immb
;
10638 int shift
= 2 * (8 << size
) - immhb
;
10639 GVecGen2iFn
*gvec_fn
;
10641 if (extract32(immh
, 3, 1) && !is_q
) {
10642 unallocated_encoding(s
);
10645 tcg_debug_assert(size
<= 3);
10647 if (!fp_access_check(s
)) {
10652 case 0x02: /* SSRA / USRA (accumulate) */
10653 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10656 case 0x08: /* SRI */
10657 gvec_fn
= gen_gvec_sri
;
10660 case 0x00: /* SSHR / USHR */
10662 if (shift
== 8 << size
) {
10663 /* Shift count the same size as element size produces zero. */
10664 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10665 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10668 gvec_fn
= tcg_gen_gvec_shri
;
10670 /* Shift count the same size as element size produces all sign. */
10671 if (shift
== 8 << size
) {
10674 gvec_fn
= tcg_gen_gvec_sari
;
10678 case 0x04: /* SRSHR / URSHR (rounding) */
10679 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10682 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10683 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10687 g_assert_not_reached();
10690 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10693 /* SHL/SLI - Vector shift left */
10694 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10695 int immh
, int immb
, int opcode
, int rn
, int rd
)
10697 int size
= 32 - clz32(immh
) - 1;
10698 int immhb
= immh
<< 3 | immb
;
10699 int shift
= immhb
- (8 << size
);
10701 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10702 assert(size
>= 0 && size
<= 3);
10704 if (extract32(immh
, 3, 1) && !is_q
) {
10705 unallocated_encoding(s
);
10709 if (!fp_access_check(s
)) {
10714 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10716 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10720 /* USHLL/SHLL - Vector shift left with widening */
10721 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10722 int immh
, int immb
, int opcode
, int rn
, int rd
)
10724 int size
= 32 - clz32(immh
) - 1;
10725 int immhb
= immh
<< 3 | immb
;
10726 int shift
= immhb
- (8 << size
);
10728 int esize
= 8 << size
;
10729 int elements
= dsize
/esize
;
10730 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10731 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10735 unallocated_encoding(s
);
10739 if (!fp_access_check(s
)) {
10743 /* For the LL variants the store is larger than the load,
10744 * so if rd == rn we would overwrite parts of our input.
10745 * So load everything right now and use shifts in the main loop.
10747 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10749 for (i
= 0; i
< elements
; i
++) {
10750 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10751 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10752 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10753 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10757 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10758 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10759 int immh
, int immb
, int opcode
, int rn
, int rd
)
10761 int immhb
= immh
<< 3 | immb
;
10762 int size
= 32 - clz32(immh
) - 1;
10764 int esize
= 8 << size
;
10765 int elements
= dsize
/esize
;
10766 int shift
= (2 * esize
) - immhb
;
10767 bool round
= extract32(opcode
, 0, 1);
10768 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10769 TCGv_i64 tcg_round
;
10772 if (extract32(immh
, 3, 1)) {
10773 unallocated_encoding(s
);
10777 if (!fp_access_check(s
)) {
10781 tcg_rn
= tcg_temp_new_i64();
10782 tcg_rd
= tcg_temp_new_i64();
10783 tcg_final
= tcg_temp_new_i64();
10784 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10787 uint64_t round_const
= 1ULL << (shift
- 1);
10788 tcg_round
= tcg_const_i64(round_const
);
10793 for (i
= 0; i
< elements
; i
++) {
10794 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10795 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10796 false, true, size
+1, shift
);
10798 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10802 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10804 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10807 tcg_temp_free_i64(tcg_round
);
10809 tcg_temp_free_i64(tcg_rn
);
10810 tcg_temp_free_i64(tcg_rd
);
10811 tcg_temp_free_i64(tcg_final
);
10813 clear_vec_high(s
, is_q
, rd
);
10817 /* AdvSIMD shift by immediate
10818 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10819 * +---+---+---+-------------+------+------+--------+---+------+------+
10820 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10821 * +---+---+---+-------------+------+------+--------+---+------+------+
10823 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10825 int rd
= extract32(insn
, 0, 5);
10826 int rn
= extract32(insn
, 5, 5);
10827 int opcode
= extract32(insn
, 11, 5);
10828 int immb
= extract32(insn
, 16, 3);
10829 int immh
= extract32(insn
, 19, 4);
10830 bool is_u
= extract32(insn
, 29, 1);
10831 bool is_q
= extract32(insn
, 30, 1);
10833 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10837 case 0x08: /* SRI */
10839 unallocated_encoding(s
);
10843 case 0x00: /* SSHR / USHR */
10844 case 0x02: /* SSRA / USRA (accumulate) */
10845 case 0x04: /* SRSHR / URSHR (rounding) */
10846 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10847 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10849 case 0x0a: /* SHL / SLI */
10850 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10852 case 0x10: /* SHRN */
10853 case 0x11: /* RSHRN / SQRSHRUN */
10855 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10858 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10861 case 0x12: /* SQSHRN / UQSHRN */
10862 case 0x13: /* SQRSHRN / UQRSHRN */
10863 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10866 case 0x14: /* SSHLL / USHLL */
10867 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10869 case 0x1c: /* SCVTF / UCVTF */
10870 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10873 case 0xc: /* SQSHLU */
10875 unallocated_encoding(s
);
10878 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10880 case 0xe: /* SQSHL, UQSHL */
10881 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10883 case 0x1f: /* FCVTZS/ FCVTZU */
10884 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10887 unallocated_encoding(s
);
10892 /* Generate code to do a "long" addition or subtraction, ie one done in
10893 * TCGv_i64 on vector lanes twice the width specified by size.
10895 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10896 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10898 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10899 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10900 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10901 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10903 NeonGenTwo64OpFn
*genfn
;
10906 genfn
= fns
[size
][is_sub
];
10907 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10910 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10911 int opcode
, int rd
, int rn
, int rm
)
10913 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10914 TCGv_i64 tcg_res
[2];
10917 tcg_res
[0] = tcg_temp_new_i64();
10918 tcg_res
[1] = tcg_temp_new_i64();
10920 /* Does this op do an adding accumulate, a subtracting accumulate,
10921 * or no accumulate at all?
10939 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10940 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10943 /* size == 2 means two 32x32->64 operations; this is worth special
10944 * casing because we can generally handle it inline.
10947 for (pass
= 0; pass
< 2; pass
++) {
10948 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10949 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10950 TCGv_i64 tcg_passres
;
10951 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10953 int elt
= pass
+ is_q
* 2;
10955 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10956 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10959 tcg_passres
= tcg_res
[pass
];
10961 tcg_passres
= tcg_temp_new_i64();
10965 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10966 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10968 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10969 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10971 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10972 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10974 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10975 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10977 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10978 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10979 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10981 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10982 tcg_temp_free_i64(tcg_tmp1
);
10983 tcg_temp_free_i64(tcg_tmp2
);
10986 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10987 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10988 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10989 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10991 case 9: /* SQDMLAL, SQDMLAL2 */
10992 case 11: /* SQDMLSL, SQDMLSL2 */
10993 case 13: /* SQDMULL, SQDMULL2 */
10994 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10995 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10996 tcg_passres
, tcg_passres
);
10999 g_assert_not_reached();
11002 if (opcode
== 9 || opcode
== 11) {
11003 /* saturating accumulate ops */
11005 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
11007 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
11008 tcg_res
[pass
], tcg_passres
);
11009 } else if (accop
> 0) {
11010 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11011 } else if (accop
< 0) {
11012 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11016 tcg_temp_free_i64(tcg_passres
);
11019 tcg_temp_free_i64(tcg_op1
);
11020 tcg_temp_free_i64(tcg_op2
);
11023 /* size 0 or 1, generally helper functions */
11024 for (pass
= 0; pass
< 2; pass
++) {
11025 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11026 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11027 TCGv_i64 tcg_passres
;
11028 int elt
= pass
+ is_q
* 2;
11030 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
11031 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11034 tcg_passres
= tcg_res
[pass
];
11036 tcg_passres
= tcg_temp_new_i64();
11040 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11041 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11043 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11044 static NeonGenWidenFn
* const widenfns
[2][2] = {
11045 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11046 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11048 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11050 widenfn(tcg_op2_64
, tcg_op2
);
11051 widenfn(tcg_passres
, tcg_op1
);
11052 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11053 tcg_passres
, tcg_op2_64
);
11054 tcg_temp_free_i64(tcg_op2_64
);
11057 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11058 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11061 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11063 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11067 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11069 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11073 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11074 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11075 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11078 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11080 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11084 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11086 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11090 case 9: /* SQDMLAL, SQDMLAL2 */
11091 case 11: /* SQDMLSL, SQDMLSL2 */
11092 case 13: /* SQDMULL, SQDMULL2 */
11094 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11095 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11096 tcg_passres
, tcg_passres
);
11099 g_assert_not_reached();
11101 tcg_temp_free_i32(tcg_op1
);
11102 tcg_temp_free_i32(tcg_op2
);
11105 if (opcode
== 9 || opcode
== 11) {
11106 /* saturating accumulate ops */
11108 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11110 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11114 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11115 tcg_res
[pass
], tcg_passres
);
11117 tcg_temp_free_i64(tcg_passres
);
11122 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11123 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11124 tcg_temp_free_i64(tcg_res
[0]);
11125 tcg_temp_free_i64(tcg_res
[1]);
11128 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11129 int opcode
, int rd
, int rn
, int rm
)
11131 TCGv_i64 tcg_res
[2];
11132 int part
= is_q
? 2 : 0;
11135 for (pass
= 0; pass
< 2; pass
++) {
11136 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11137 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11138 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11139 static NeonGenWidenFn
* const widenfns
[3][2] = {
11140 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11141 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11142 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11144 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11146 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11147 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11148 widenfn(tcg_op2_wide
, tcg_op2
);
11149 tcg_temp_free_i32(tcg_op2
);
11150 tcg_res
[pass
] = tcg_temp_new_i64();
11151 gen_neon_addl(size
, (opcode
== 3),
11152 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11153 tcg_temp_free_i64(tcg_op1
);
11154 tcg_temp_free_i64(tcg_op2_wide
);
11157 for (pass
= 0; pass
< 2; pass
++) {
11158 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11159 tcg_temp_free_i64(tcg_res
[pass
]);
11163 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11165 tcg_gen_addi_i64(in
, in
, 1U << 31);
11166 tcg_gen_extrh_i64_i32(res
, in
);
11169 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11170 int opcode
, int rd
, int rn
, int rm
)
11172 TCGv_i32 tcg_res
[2];
11173 int part
= is_q
? 2 : 0;
11176 for (pass
= 0; pass
< 2; pass
++) {
11177 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11178 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11179 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11180 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11181 { gen_helper_neon_narrow_high_u8
,
11182 gen_helper_neon_narrow_round_high_u8
},
11183 { gen_helper_neon_narrow_high_u16
,
11184 gen_helper_neon_narrow_round_high_u16
},
11185 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11187 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11189 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11190 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11192 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11194 tcg_temp_free_i64(tcg_op1
);
11195 tcg_temp_free_i64(tcg_op2
);
11197 tcg_res
[pass
] = tcg_temp_new_i32();
11198 gennarrow(tcg_res
[pass
], tcg_wideres
);
11199 tcg_temp_free_i64(tcg_wideres
);
11202 for (pass
= 0; pass
< 2; pass
++) {
11203 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11204 tcg_temp_free_i32(tcg_res
[pass
]);
11206 clear_vec_high(s
, is_q
, rd
);
11209 /* AdvSIMD three different
11210 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11211 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11212 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11213 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11215 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11217 /* Instructions in this group fall into three basic classes
11218 * (in each case with the operation working on each element in
11219 * the input vectors):
11220 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11222 * (2) wide 64 x 128 -> 128
11223 * (3) narrowing 128 x 128 -> 64
11224 * Here we do initial decode, catch unallocated cases and
11225 * dispatch to separate functions for each class.
11227 int is_q
= extract32(insn
, 30, 1);
11228 int is_u
= extract32(insn
, 29, 1);
11229 int size
= extract32(insn
, 22, 2);
11230 int opcode
= extract32(insn
, 12, 4);
11231 int rm
= extract32(insn
, 16, 5);
11232 int rn
= extract32(insn
, 5, 5);
11233 int rd
= extract32(insn
, 0, 5);
11236 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11237 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11238 /* 64 x 128 -> 128 */
11240 unallocated_encoding(s
);
11243 if (!fp_access_check(s
)) {
11246 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11248 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11249 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11250 /* 128 x 128 -> 64 */
11252 unallocated_encoding(s
);
11255 if (!fp_access_check(s
)) {
11258 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11260 case 14: /* PMULL, PMULL2 */
11262 unallocated_encoding(s
);
11266 case 0: /* PMULL.P8 */
11267 if (!fp_access_check(s
)) {
11270 /* The Q field specifies lo/hi half input for this insn. */
11271 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11272 gen_helper_neon_pmull_h
);
11275 case 3: /* PMULL.P64 */
11276 if (!dc_isar_feature(aa64_pmull
, s
)) {
11277 unallocated_encoding(s
);
11280 if (!fp_access_check(s
)) {
11283 /* The Q field specifies lo/hi half input for this insn. */
11284 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11285 gen_helper_gvec_pmull_q
);
11289 unallocated_encoding(s
);
11293 case 9: /* SQDMLAL, SQDMLAL2 */
11294 case 11: /* SQDMLSL, SQDMLSL2 */
11295 case 13: /* SQDMULL, SQDMULL2 */
11296 if (is_u
|| size
== 0) {
11297 unallocated_encoding(s
);
11301 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11302 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11303 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11304 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11305 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11306 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11307 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11308 /* 64 x 64 -> 128 */
11310 unallocated_encoding(s
);
11313 if (!fp_access_check(s
)) {
11317 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11320 /* opcode 15 not allocated */
11321 unallocated_encoding(s
);
11326 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11327 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11329 int rd
= extract32(insn
, 0, 5);
11330 int rn
= extract32(insn
, 5, 5);
11331 int rm
= extract32(insn
, 16, 5);
11332 int size
= extract32(insn
, 22, 2);
11333 bool is_u
= extract32(insn
, 29, 1);
11334 bool is_q
= extract32(insn
, 30, 1);
11336 if (!fp_access_check(s
)) {
11340 switch (size
+ 4 * is_u
) {
11342 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11345 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11348 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11351 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11354 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11357 case 5: /* BSL bitwise select */
11358 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11360 case 6: /* BIT, bitwise insert if true */
11361 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11363 case 7: /* BIF, bitwise insert if false */
11364 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11368 g_assert_not_reached();
11372 /* Pairwise op subgroup of C3.6.16.
11374 * This is called directly or via the handle_3same_float for float pairwise
11375 * operations where the opcode and size are calculated differently.
11377 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11378 int size
, int rn
, int rm
, int rd
)
11383 /* Floating point operations need fpst */
11384 if (opcode
>= 0x58) {
11385 fpst
= fpstatus_ptr(FPST_FPCR
);
11390 if (!fp_access_check(s
)) {
11394 /* These operations work on the concatenated rm:rn, with each pair of
11395 * adjacent elements being operated on to produce an element in the result.
11398 TCGv_i64 tcg_res
[2];
11400 for (pass
= 0; pass
< 2; pass
++) {
11401 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11402 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11403 int passreg
= (pass
== 0) ? rn
: rm
;
11405 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11406 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11407 tcg_res
[pass
] = tcg_temp_new_i64();
11410 case 0x17: /* ADDP */
11411 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11413 case 0x58: /* FMAXNMP */
11414 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11416 case 0x5a: /* FADDP */
11417 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11419 case 0x5e: /* FMAXP */
11420 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11422 case 0x78: /* FMINNMP */
11423 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11425 case 0x7e: /* FMINP */
11426 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11429 g_assert_not_reached();
11432 tcg_temp_free_i64(tcg_op1
);
11433 tcg_temp_free_i64(tcg_op2
);
11436 for (pass
= 0; pass
< 2; pass
++) {
11437 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11438 tcg_temp_free_i64(tcg_res
[pass
]);
11441 int maxpass
= is_q
? 4 : 2;
11442 TCGv_i32 tcg_res
[4];
11444 for (pass
= 0; pass
< maxpass
; pass
++) {
11445 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11446 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11447 NeonGenTwoOpFn
*genfn
= NULL
;
11448 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11449 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11451 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11452 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11453 tcg_res
[pass
] = tcg_temp_new_i32();
11456 case 0x17: /* ADDP */
11458 static NeonGenTwoOpFn
* const fns
[3] = {
11459 gen_helper_neon_padd_u8
,
11460 gen_helper_neon_padd_u16
,
11466 case 0x14: /* SMAXP, UMAXP */
11468 static NeonGenTwoOpFn
* const fns
[3][2] = {
11469 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11470 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11471 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11473 genfn
= fns
[size
][u
];
11476 case 0x15: /* SMINP, UMINP */
11478 static NeonGenTwoOpFn
* const fns
[3][2] = {
11479 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11480 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11481 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11483 genfn
= fns
[size
][u
];
11486 /* The FP operations are all on single floats (32 bit) */
11487 case 0x58: /* FMAXNMP */
11488 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11490 case 0x5a: /* FADDP */
11491 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11493 case 0x5e: /* FMAXP */
11494 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11496 case 0x78: /* FMINNMP */
11497 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11499 case 0x7e: /* FMINP */
11500 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11503 g_assert_not_reached();
11506 /* FP ops called directly, otherwise call now */
11508 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11511 tcg_temp_free_i32(tcg_op1
);
11512 tcg_temp_free_i32(tcg_op2
);
11515 for (pass
= 0; pass
< maxpass
; pass
++) {
11516 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11517 tcg_temp_free_i32(tcg_res
[pass
]);
11519 clear_vec_high(s
, is_q
, rd
);
11523 tcg_temp_free_ptr(fpst
);
11527 /* Floating point op subgroup of C3.6.16. */
11528 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11530 /* For floating point ops, the U, size[1] and opcode bits
11531 * together indicate the operation. size[0] indicates single
11534 int fpopcode
= extract32(insn
, 11, 5)
11535 | (extract32(insn
, 23, 1) << 5)
11536 | (extract32(insn
, 29, 1) << 6);
11537 int is_q
= extract32(insn
, 30, 1);
11538 int size
= extract32(insn
, 22, 1);
11539 int rm
= extract32(insn
, 16, 5);
11540 int rn
= extract32(insn
, 5, 5);
11541 int rd
= extract32(insn
, 0, 5);
11543 int datasize
= is_q
? 128 : 64;
11544 int esize
= 32 << size
;
11545 int elements
= datasize
/ esize
;
11547 if (size
== 1 && !is_q
) {
11548 unallocated_encoding(s
);
11552 switch (fpopcode
) {
11553 case 0x58: /* FMAXNMP */
11554 case 0x5a: /* FADDP */
11555 case 0x5e: /* FMAXP */
11556 case 0x78: /* FMINNMP */
11557 case 0x7e: /* FMINP */
11558 if (size
&& !is_q
) {
11559 unallocated_encoding(s
);
11562 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11565 case 0x1b: /* FMULX */
11566 case 0x1f: /* FRECPS */
11567 case 0x3f: /* FRSQRTS */
11568 case 0x5d: /* FACGE */
11569 case 0x7d: /* FACGT */
11570 case 0x19: /* FMLA */
11571 case 0x39: /* FMLS */
11572 case 0x18: /* FMAXNM */
11573 case 0x1a: /* FADD */
11574 case 0x1c: /* FCMEQ */
11575 case 0x1e: /* FMAX */
11576 case 0x38: /* FMINNM */
11577 case 0x3a: /* FSUB */
11578 case 0x3e: /* FMIN */
11579 case 0x5b: /* FMUL */
11580 case 0x5c: /* FCMGE */
11581 case 0x5f: /* FDIV */
11582 case 0x7a: /* FABD */
11583 case 0x7c: /* FCMGT */
11584 if (!fp_access_check(s
)) {
11587 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11590 case 0x1d: /* FMLAL */
11591 case 0x3d: /* FMLSL */
11592 case 0x59: /* FMLAL2 */
11593 case 0x79: /* FMLSL2 */
11594 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11595 unallocated_encoding(s
);
11598 if (fp_access_check(s
)) {
11599 int is_s
= extract32(insn
, 23, 1);
11600 int is_2
= extract32(insn
, 29, 1);
11601 int data
= (is_2
<< 1) | is_s
;
11602 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11603 vec_full_reg_offset(s
, rn
),
11604 vec_full_reg_offset(s
, rm
), cpu_env
,
11605 is_q
? 16 : 8, vec_full_reg_size(s
),
11606 data
, gen_helper_gvec_fmlal_a64
);
11611 unallocated_encoding(s
);
11616 /* Integer op subgroup of C3.6.16. */
11617 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11619 int is_q
= extract32(insn
, 30, 1);
11620 int u
= extract32(insn
, 29, 1);
11621 int size
= extract32(insn
, 22, 2);
11622 int opcode
= extract32(insn
, 11, 5);
11623 int rm
= extract32(insn
, 16, 5);
11624 int rn
= extract32(insn
, 5, 5);
11625 int rd
= extract32(insn
, 0, 5);
11630 case 0x13: /* MUL, PMUL */
11631 if (u
&& size
!= 0) {
11632 unallocated_encoding(s
);
11636 case 0x0: /* SHADD, UHADD */
11637 case 0x2: /* SRHADD, URHADD */
11638 case 0x4: /* SHSUB, UHSUB */
11639 case 0xc: /* SMAX, UMAX */
11640 case 0xd: /* SMIN, UMIN */
11641 case 0xe: /* SABD, UABD */
11642 case 0xf: /* SABA, UABA */
11643 case 0x12: /* MLA, MLS */
11645 unallocated_encoding(s
);
11649 case 0x16: /* SQDMULH, SQRDMULH */
11650 if (size
== 0 || size
== 3) {
11651 unallocated_encoding(s
);
11656 if (size
== 3 && !is_q
) {
11657 unallocated_encoding(s
);
11663 if (!fp_access_check(s
)) {
11668 case 0x01: /* SQADD, UQADD */
11670 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11672 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11675 case 0x05: /* SQSUB, UQSUB */
11677 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11679 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11682 case 0x08: /* SSHL, USHL */
11684 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11686 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11689 case 0x0c: /* SMAX, UMAX */
11691 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11693 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11696 case 0x0d: /* SMIN, UMIN */
11698 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11700 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11703 case 0xe: /* SABD, UABD */
11705 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11707 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11710 case 0xf: /* SABA, UABA */
11712 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11714 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11717 case 0x10: /* ADD, SUB */
11719 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11721 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11724 case 0x13: /* MUL, PMUL */
11725 if (!u
) { /* MUL */
11726 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11727 } else { /* PMUL */
11728 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11731 case 0x12: /* MLA, MLS */
11733 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11735 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11738 case 0x16: /* SQDMULH, SQRDMULH */
11740 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11741 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11742 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11744 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11748 if (!u
) { /* CMTST */
11749 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11753 cond
= TCG_COND_EQ
;
11755 case 0x06: /* CMGT, CMHI */
11756 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11758 case 0x07: /* CMGE, CMHS */
11759 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11761 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11762 vec_full_reg_offset(s
, rn
),
11763 vec_full_reg_offset(s
, rm
),
11764 is_q
? 16 : 8, vec_full_reg_size(s
));
11770 for (pass
= 0; pass
< 2; pass
++) {
11771 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11772 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11773 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11775 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11776 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11778 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11780 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11782 tcg_temp_free_i64(tcg_res
);
11783 tcg_temp_free_i64(tcg_op1
);
11784 tcg_temp_free_i64(tcg_op2
);
11787 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11788 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11789 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11790 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11791 NeonGenTwoOpFn
*genfn
= NULL
;
11792 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11794 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11795 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11798 case 0x0: /* SHADD, UHADD */
11800 static NeonGenTwoOpFn
* const fns
[3][2] = {
11801 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11802 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11803 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11805 genfn
= fns
[size
][u
];
11808 case 0x2: /* SRHADD, URHADD */
11810 static NeonGenTwoOpFn
* const fns
[3][2] = {
11811 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11812 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11813 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11815 genfn
= fns
[size
][u
];
11818 case 0x4: /* SHSUB, UHSUB */
11820 static NeonGenTwoOpFn
* const fns
[3][2] = {
11821 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11822 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11823 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11825 genfn
= fns
[size
][u
];
11828 case 0x9: /* SQSHL, UQSHL */
11830 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11831 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11832 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11833 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11835 genenvfn
= fns
[size
][u
];
11838 case 0xa: /* SRSHL, URSHL */
11840 static NeonGenTwoOpFn
* const fns
[3][2] = {
11841 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11842 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11843 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11845 genfn
= fns
[size
][u
];
11848 case 0xb: /* SQRSHL, UQRSHL */
11850 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11851 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11852 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11853 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11855 genenvfn
= fns
[size
][u
];
11859 g_assert_not_reached();
11863 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11865 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11868 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11870 tcg_temp_free_i32(tcg_res
);
11871 tcg_temp_free_i32(tcg_op1
);
11872 tcg_temp_free_i32(tcg_op2
);
11875 clear_vec_high(s
, is_q
, rd
);
11878 /* AdvSIMD three same
11879 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11880 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11881 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11882 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11884 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11886 int opcode
= extract32(insn
, 11, 5);
11889 case 0x3: /* logic ops */
11890 disas_simd_3same_logic(s
, insn
);
11892 case 0x17: /* ADDP */
11893 case 0x14: /* SMAXP, UMAXP */
11894 case 0x15: /* SMINP, UMINP */
11896 /* Pairwise operations */
11897 int is_q
= extract32(insn
, 30, 1);
11898 int u
= extract32(insn
, 29, 1);
11899 int size
= extract32(insn
, 22, 2);
11900 int rm
= extract32(insn
, 16, 5);
11901 int rn
= extract32(insn
, 5, 5);
11902 int rd
= extract32(insn
, 0, 5);
11903 if (opcode
== 0x17) {
11904 if (u
|| (size
== 3 && !is_q
)) {
11905 unallocated_encoding(s
);
11910 unallocated_encoding(s
);
11914 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11917 case 0x18 ... 0x31:
11918 /* floating point ops, sz[1] and U are part of opcode */
11919 disas_simd_3same_float(s
, insn
);
11922 disas_simd_3same_int(s
, insn
);
11928 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11930 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11931 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11932 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11933 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11935 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11936 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11939 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11941 int opcode
, fpopcode
;
11942 int is_q
, u
, a
, rm
, rn
, rd
;
11943 int datasize
, elements
;
11946 bool pairwise
= false;
11948 if (!dc_isar_feature(aa64_fp16
, s
)) {
11949 unallocated_encoding(s
);
11953 if (!fp_access_check(s
)) {
11957 /* For these floating point ops, the U, a and opcode bits
11958 * together indicate the operation.
11960 opcode
= extract32(insn
, 11, 3);
11961 u
= extract32(insn
, 29, 1);
11962 a
= extract32(insn
, 23, 1);
11963 is_q
= extract32(insn
, 30, 1);
11964 rm
= extract32(insn
, 16, 5);
11965 rn
= extract32(insn
, 5, 5);
11966 rd
= extract32(insn
, 0, 5);
11968 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11969 datasize
= is_q
? 128 : 64;
11970 elements
= datasize
/ 16;
11972 switch (fpopcode
) {
11973 case 0x10: /* FMAXNMP */
11974 case 0x12: /* FADDP */
11975 case 0x16: /* FMAXP */
11976 case 0x18: /* FMINNMP */
11977 case 0x1e: /* FMINP */
11982 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
11985 int maxpass
= is_q
? 8 : 4;
11986 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11987 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11988 TCGv_i32 tcg_res
[8];
11990 for (pass
= 0; pass
< maxpass
; pass
++) {
11991 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11992 int passelt
= (pass
<< 1) & (maxpass
- 1);
11994 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11995 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11996 tcg_res
[pass
] = tcg_temp_new_i32();
11998 switch (fpopcode
) {
11999 case 0x10: /* FMAXNMP */
12000 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12003 case 0x12: /* FADDP */
12004 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12006 case 0x16: /* FMAXP */
12007 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12009 case 0x18: /* FMINNMP */
12010 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12013 case 0x1e: /* FMINP */
12014 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12017 g_assert_not_reached();
12021 for (pass
= 0; pass
< maxpass
; pass
++) {
12022 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
12023 tcg_temp_free_i32(tcg_res
[pass
]);
12026 tcg_temp_free_i32(tcg_op1
);
12027 tcg_temp_free_i32(tcg_op2
);
12030 for (pass
= 0; pass
< elements
; pass
++) {
12031 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12032 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12033 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12035 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12036 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12038 switch (fpopcode
) {
12039 case 0x0: /* FMAXNM */
12040 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12042 case 0x1: /* FMLA */
12043 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12044 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12047 case 0x2: /* FADD */
12048 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12050 case 0x3: /* FMULX */
12051 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12053 case 0x4: /* FCMEQ */
12054 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12056 case 0x6: /* FMAX */
12057 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12059 case 0x7: /* FRECPS */
12060 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12062 case 0x8: /* FMINNM */
12063 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12065 case 0x9: /* FMLS */
12066 /* As usual for ARM, separate negation for fused multiply-add */
12067 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12068 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12069 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12072 case 0xa: /* FSUB */
12073 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12075 case 0xe: /* FMIN */
12076 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12078 case 0xf: /* FRSQRTS */
12079 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12081 case 0x13: /* FMUL */
12082 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12084 case 0x14: /* FCMGE */
12085 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12087 case 0x15: /* FACGE */
12088 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12090 case 0x17: /* FDIV */
12091 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12093 case 0x1a: /* FABD */
12094 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12095 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12097 case 0x1c: /* FCMGT */
12098 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12100 case 0x1d: /* FACGT */
12101 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12104 fprintf(stderr
, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64
"\n",
12105 __func__
, insn
, fpopcode
, s
->pc_curr
);
12106 g_assert_not_reached();
12109 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12110 tcg_temp_free_i32(tcg_res
);
12111 tcg_temp_free_i32(tcg_op1
);
12112 tcg_temp_free_i32(tcg_op2
);
12116 tcg_temp_free_ptr(fpst
);
12118 clear_vec_high(s
, is_q
, rd
);
12121 /* AdvSIMD three same extra
12122 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12123 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12124 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12125 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12127 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12129 int rd
= extract32(insn
, 0, 5);
12130 int rn
= extract32(insn
, 5, 5);
12131 int opcode
= extract32(insn
, 11, 4);
12132 int rm
= extract32(insn
, 16, 5);
12133 int size
= extract32(insn
, 22, 2);
12134 bool u
= extract32(insn
, 29, 1);
12135 bool is_q
= extract32(insn
, 30, 1);
12139 switch (u
* 16 + opcode
) {
12140 case 0x10: /* SQRDMLAH (vector) */
12141 case 0x11: /* SQRDMLSH (vector) */
12142 if (size
!= 1 && size
!= 2) {
12143 unallocated_encoding(s
);
12146 feature
= dc_isar_feature(aa64_rdm
, s
);
12148 case 0x02: /* SDOT (vector) */
12149 case 0x12: /* UDOT (vector) */
12150 if (size
!= MO_32
) {
12151 unallocated_encoding(s
);
12154 feature
= dc_isar_feature(aa64_dp
, s
);
12156 case 0x18: /* FCMLA, #0 */
12157 case 0x19: /* FCMLA, #90 */
12158 case 0x1a: /* FCMLA, #180 */
12159 case 0x1b: /* FCMLA, #270 */
12160 case 0x1c: /* FCADD, #90 */
12161 case 0x1e: /* FCADD, #270 */
12163 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12164 || (size
== 3 && !is_q
)) {
12165 unallocated_encoding(s
);
12168 feature
= dc_isar_feature(aa64_fcma
, s
);
12171 unallocated_encoding(s
);
12175 unallocated_encoding(s
);
12178 if (!fp_access_check(s
)) {
12183 case 0x0: /* SQRDMLAH (vector) */
12184 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12187 case 0x1: /* SQRDMLSH (vector) */
12188 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12191 case 0x2: /* SDOT / UDOT */
12192 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
12193 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12196 case 0x8: /* FCMLA, #0 */
12197 case 0x9: /* FCMLA, #90 */
12198 case 0xa: /* FCMLA, #180 */
12199 case 0xb: /* FCMLA, #270 */
12200 rot
= extract32(opcode
, 0, 2);
12203 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
12204 gen_helper_gvec_fcmlah
);
12207 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12208 gen_helper_gvec_fcmlas
);
12211 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12212 gen_helper_gvec_fcmlad
);
12215 g_assert_not_reached();
12219 case 0xc: /* FCADD, #90 */
12220 case 0xe: /* FCADD, #270 */
12221 rot
= extract32(opcode
, 1, 1);
12224 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12225 gen_helper_gvec_fcaddh
);
12228 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12229 gen_helper_gvec_fcadds
);
12232 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12233 gen_helper_gvec_fcaddd
);
12236 g_assert_not_reached();
12241 g_assert_not_reached();
12245 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12246 int size
, int rn
, int rd
)
12248 /* Handle 2-reg-misc ops which are widening (so each size element
12249 * in the source becomes a 2*size element in the destination.
12250 * The only instruction like this is FCVTL.
12255 /* 32 -> 64 bit fp conversion */
12256 TCGv_i64 tcg_res
[2];
12257 int srcelt
= is_q
? 2 : 0;
12259 for (pass
= 0; pass
< 2; pass
++) {
12260 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12261 tcg_res
[pass
] = tcg_temp_new_i64();
12263 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12264 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12265 tcg_temp_free_i32(tcg_op
);
12267 for (pass
= 0; pass
< 2; pass
++) {
12268 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12269 tcg_temp_free_i64(tcg_res
[pass
]);
12272 /* 16 -> 32 bit fp conversion */
12273 int srcelt
= is_q
? 4 : 0;
12274 TCGv_i32 tcg_res
[4];
12275 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
12276 TCGv_i32 ahp
= get_ahp_flag();
12278 for (pass
= 0; pass
< 4; pass
++) {
12279 tcg_res
[pass
] = tcg_temp_new_i32();
12281 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12282 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12285 for (pass
= 0; pass
< 4; pass
++) {
12286 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12287 tcg_temp_free_i32(tcg_res
[pass
]);
12290 tcg_temp_free_ptr(fpst
);
12291 tcg_temp_free_i32(ahp
);
12295 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12296 bool is_q
, int size
, int rn
, int rd
)
12298 int op
= (opcode
<< 1) | u
;
12299 int opsz
= op
+ size
;
12300 int grp_size
= 3 - opsz
;
12301 int dsize
= is_q
? 128 : 64;
12305 unallocated_encoding(s
);
12309 if (!fp_access_check(s
)) {
12314 /* Special case bytes, use bswap op on each group of elements */
12315 int groups
= dsize
/ (8 << grp_size
);
12317 for (i
= 0; i
< groups
; i
++) {
12318 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12320 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12321 switch (grp_size
) {
12323 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
12326 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
12329 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12332 g_assert_not_reached();
12334 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12335 tcg_temp_free_i64(tcg_tmp
);
12337 clear_vec_high(s
, is_q
, rd
);
12339 int revmask
= (1 << grp_size
) - 1;
12340 int esize
= 8 << size
;
12341 int elements
= dsize
/ esize
;
12342 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12343 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12344 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12346 for (i
= 0; i
< elements
; i
++) {
12347 int e_rev
= (i
& 0xf) ^ revmask
;
12348 int off
= e_rev
* esize
;
12349 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12351 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12352 tcg_rn
, off
- 64, esize
);
12354 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12357 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12358 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12360 tcg_temp_free_i64(tcg_rd_hi
);
12361 tcg_temp_free_i64(tcg_rd
);
12362 tcg_temp_free_i64(tcg_rn
);
12366 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12367 bool is_q
, int size
, int rn
, int rd
)
12369 /* Implement the pairwise operations from 2-misc:
12370 * SADDLP, UADDLP, SADALP, UADALP.
12371 * These all add pairs of elements in the input to produce a
12372 * double-width result element in the output (possibly accumulating).
12374 bool accum
= (opcode
== 0x6);
12375 int maxpass
= is_q
? 2 : 1;
12377 TCGv_i64 tcg_res
[2];
12380 /* 32 + 32 -> 64 op */
12381 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12383 for (pass
= 0; pass
< maxpass
; pass
++) {
12384 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12385 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12387 tcg_res
[pass
] = tcg_temp_new_i64();
12389 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12390 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12391 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12393 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12394 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12397 tcg_temp_free_i64(tcg_op1
);
12398 tcg_temp_free_i64(tcg_op2
);
12401 for (pass
= 0; pass
< maxpass
; pass
++) {
12402 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12403 NeonGenOne64OpFn
*genfn
;
12404 static NeonGenOne64OpFn
* const fns
[2][2] = {
12405 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12406 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12409 genfn
= fns
[size
][u
];
12411 tcg_res
[pass
] = tcg_temp_new_i64();
12413 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12414 genfn(tcg_res
[pass
], tcg_op
);
12417 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12419 gen_helper_neon_addl_u16(tcg_res
[pass
],
12420 tcg_res
[pass
], tcg_op
);
12422 gen_helper_neon_addl_u32(tcg_res
[pass
],
12423 tcg_res
[pass
], tcg_op
);
12426 tcg_temp_free_i64(tcg_op
);
12430 tcg_res
[1] = tcg_const_i64(0);
12432 for (pass
= 0; pass
< 2; pass
++) {
12433 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12434 tcg_temp_free_i64(tcg_res
[pass
]);
12438 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12440 /* Implement SHLL and SHLL2 */
12442 int part
= is_q
? 2 : 0;
12443 TCGv_i64 tcg_res
[2];
12445 for (pass
= 0; pass
< 2; pass
++) {
12446 static NeonGenWidenFn
* const widenfns
[3] = {
12447 gen_helper_neon_widen_u8
,
12448 gen_helper_neon_widen_u16
,
12449 tcg_gen_extu_i32_i64
,
12451 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12452 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12454 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12455 tcg_res
[pass
] = tcg_temp_new_i64();
12456 widenfn(tcg_res
[pass
], tcg_op
);
12457 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12459 tcg_temp_free_i32(tcg_op
);
12462 for (pass
= 0; pass
< 2; pass
++) {
12463 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12464 tcg_temp_free_i64(tcg_res
[pass
]);
12468 /* AdvSIMD two reg misc
12469 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12470 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12471 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12472 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12474 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12476 int size
= extract32(insn
, 22, 2);
12477 int opcode
= extract32(insn
, 12, 5);
12478 bool u
= extract32(insn
, 29, 1);
12479 bool is_q
= extract32(insn
, 30, 1);
12480 int rn
= extract32(insn
, 5, 5);
12481 int rd
= extract32(insn
, 0, 5);
12482 bool need_fpstatus
= false;
12483 bool need_rmode
= false;
12485 TCGv_i32 tcg_rmode
;
12486 TCGv_ptr tcg_fpstatus
;
12489 case 0x0: /* REV64, REV32 */
12490 case 0x1: /* REV16 */
12491 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12493 case 0x5: /* CNT, NOT, RBIT */
12494 if (u
&& size
== 0) {
12497 } else if (u
&& size
== 1) {
12500 } else if (!u
&& size
== 0) {
12504 unallocated_encoding(s
);
12506 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12507 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12509 unallocated_encoding(s
);
12512 if (!fp_access_check(s
)) {
12516 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12518 case 0x4: /* CLS, CLZ */
12520 unallocated_encoding(s
);
12524 case 0x2: /* SADDLP, UADDLP */
12525 case 0x6: /* SADALP, UADALP */
12527 unallocated_encoding(s
);
12530 if (!fp_access_check(s
)) {
12533 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12535 case 0x13: /* SHLL, SHLL2 */
12536 if (u
== 0 || size
== 3) {
12537 unallocated_encoding(s
);
12540 if (!fp_access_check(s
)) {
12543 handle_shll(s
, is_q
, size
, rn
, rd
);
12545 case 0xa: /* CMLT */
12547 unallocated_encoding(s
);
12551 case 0x8: /* CMGT, CMGE */
12552 case 0x9: /* CMEQ, CMLE */
12553 case 0xb: /* ABS, NEG */
12554 if (size
== 3 && !is_q
) {
12555 unallocated_encoding(s
);
12559 case 0x3: /* SUQADD, USQADD */
12560 if (size
== 3 && !is_q
) {
12561 unallocated_encoding(s
);
12564 if (!fp_access_check(s
)) {
12567 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12569 case 0x7: /* SQABS, SQNEG */
12570 if (size
== 3 && !is_q
) {
12571 unallocated_encoding(s
);
12576 case 0x16 ... 0x1f:
12578 /* Floating point: U, size[1] and opcode indicate operation;
12579 * size[0] indicates single or double precision.
12581 int is_double
= extract32(size
, 0, 1);
12582 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12583 size
= is_double
? 3 : 2;
12585 case 0x2f: /* FABS */
12586 case 0x6f: /* FNEG */
12587 if (size
== 3 && !is_q
) {
12588 unallocated_encoding(s
);
12592 case 0x1d: /* SCVTF */
12593 case 0x5d: /* UCVTF */
12595 bool is_signed
= (opcode
== 0x1d) ? true : false;
12596 int elements
= is_double
? 2 : is_q
? 4 : 2;
12597 if (is_double
&& !is_q
) {
12598 unallocated_encoding(s
);
12601 if (!fp_access_check(s
)) {
12604 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12607 case 0x2c: /* FCMGT (zero) */
12608 case 0x2d: /* FCMEQ (zero) */
12609 case 0x2e: /* FCMLT (zero) */
12610 case 0x6c: /* FCMGE (zero) */
12611 case 0x6d: /* FCMLE (zero) */
12612 if (size
== 3 && !is_q
) {
12613 unallocated_encoding(s
);
12616 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12618 case 0x7f: /* FSQRT */
12619 if (size
== 3 && !is_q
) {
12620 unallocated_encoding(s
);
12624 case 0x1a: /* FCVTNS */
12625 case 0x1b: /* FCVTMS */
12626 case 0x3a: /* FCVTPS */
12627 case 0x3b: /* FCVTZS */
12628 case 0x5a: /* FCVTNU */
12629 case 0x5b: /* FCVTMU */
12630 case 0x7a: /* FCVTPU */
12631 case 0x7b: /* FCVTZU */
12632 need_fpstatus
= true;
12634 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12635 if (size
== 3 && !is_q
) {
12636 unallocated_encoding(s
);
12640 case 0x5c: /* FCVTAU */
12641 case 0x1c: /* FCVTAS */
12642 need_fpstatus
= true;
12644 rmode
= FPROUNDING_TIEAWAY
;
12645 if (size
== 3 && !is_q
) {
12646 unallocated_encoding(s
);
12650 case 0x3c: /* URECPE */
12652 unallocated_encoding(s
);
12656 case 0x3d: /* FRECPE */
12657 case 0x7d: /* FRSQRTE */
12658 if (size
== 3 && !is_q
) {
12659 unallocated_encoding(s
);
12662 if (!fp_access_check(s
)) {
12665 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12667 case 0x56: /* FCVTXN, FCVTXN2 */
12669 unallocated_encoding(s
);
12673 case 0x16: /* FCVTN, FCVTN2 */
12674 /* handle_2misc_narrow does a 2*size -> size operation, but these
12675 * instructions encode the source size rather than dest size.
12677 if (!fp_access_check(s
)) {
12680 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12682 case 0x17: /* FCVTL, FCVTL2 */
12683 if (!fp_access_check(s
)) {
12686 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12688 case 0x18: /* FRINTN */
12689 case 0x19: /* FRINTM */
12690 case 0x38: /* FRINTP */
12691 case 0x39: /* FRINTZ */
12693 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12695 case 0x59: /* FRINTX */
12696 case 0x79: /* FRINTI */
12697 need_fpstatus
= true;
12698 if (size
== 3 && !is_q
) {
12699 unallocated_encoding(s
);
12703 case 0x58: /* FRINTA */
12705 rmode
= FPROUNDING_TIEAWAY
;
12706 need_fpstatus
= true;
12707 if (size
== 3 && !is_q
) {
12708 unallocated_encoding(s
);
12712 case 0x7c: /* URSQRTE */
12714 unallocated_encoding(s
);
12718 case 0x1e: /* FRINT32Z */
12719 case 0x1f: /* FRINT64Z */
12721 rmode
= FPROUNDING_ZERO
;
12723 case 0x5e: /* FRINT32X */
12724 case 0x5f: /* FRINT64X */
12725 need_fpstatus
= true;
12726 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12727 unallocated_encoding(s
);
12732 unallocated_encoding(s
);
12738 unallocated_encoding(s
);
12742 if (!fp_access_check(s
)) {
12746 if (need_fpstatus
|| need_rmode
) {
12747 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12749 tcg_fpstatus
= NULL
;
12752 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12753 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12760 if (u
&& size
== 0) { /* NOT */
12761 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12765 case 0x8: /* CMGT, CMGE */
12767 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12769 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12772 case 0x9: /* CMEQ, CMLE */
12774 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12776 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12779 case 0xa: /* CMLT */
12780 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12783 if (u
) { /* ABS, NEG */
12784 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12786 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12792 /* All 64-bit element operations can be shared with scalar 2misc */
12795 /* Coverity claims (size == 3 && !is_q) has been eliminated
12796 * from all paths leading to here.
12798 tcg_debug_assert(is_q
);
12799 for (pass
= 0; pass
< 2; pass
++) {
12800 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12801 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12803 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12805 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12806 tcg_rmode
, tcg_fpstatus
);
12808 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12810 tcg_temp_free_i64(tcg_res
);
12811 tcg_temp_free_i64(tcg_op
);
12816 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12817 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12818 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12820 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12823 /* Special cases for 32 bit elements */
12825 case 0x4: /* CLS */
12827 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12829 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12832 case 0x7: /* SQABS, SQNEG */
12834 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12836 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12839 case 0x2f: /* FABS */
12840 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12842 case 0x6f: /* FNEG */
12843 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12845 case 0x7f: /* FSQRT */
12846 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12848 case 0x1a: /* FCVTNS */
12849 case 0x1b: /* FCVTMS */
12850 case 0x1c: /* FCVTAS */
12851 case 0x3a: /* FCVTPS */
12852 case 0x3b: /* FCVTZS */
12854 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12855 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12856 tcg_shift
, tcg_fpstatus
);
12857 tcg_temp_free_i32(tcg_shift
);
12860 case 0x5a: /* FCVTNU */
12861 case 0x5b: /* FCVTMU */
12862 case 0x5c: /* FCVTAU */
12863 case 0x7a: /* FCVTPU */
12864 case 0x7b: /* FCVTZU */
12866 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12867 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12868 tcg_shift
, tcg_fpstatus
);
12869 tcg_temp_free_i32(tcg_shift
);
12872 case 0x18: /* FRINTN */
12873 case 0x19: /* FRINTM */
12874 case 0x38: /* FRINTP */
12875 case 0x39: /* FRINTZ */
12876 case 0x58: /* FRINTA */
12877 case 0x79: /* FRINTI */
12878 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12880 case 0x59: /* FRINTX */
12881 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12883 case 0x7c: /* URSQRTE */
12884 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12886 case 0x1e: /* FRINT32Z */
12887 case 0x5e: /* FRINT32X */
12888 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12890 case 0x1f: /* FRINT64Z */
12891 case 0x5f: /* FRINT64X */
12892 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12895 g_assert_not_reached();
12898 /* Use helpers for 8 and 16 bit elements */
12900 case 0x5: /* CNT, RBIT */
12901 /* For these two insns size is part of the opcode specifier
12902 * (handled earlier); they always operate on byte elements.
12905 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12907 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12910 case 0x7: /* SQABS, SQNEG */
12912 NeonGenOneOpEnvFn
*genfn
;
12913 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12914 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12915 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12917 genfn
= fns
[size
][u
];
12918 genfn(tcg_res
, cpu_env
, tcg_op
);
12921 case 0x4: /* CLS, CLZ */
12924 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12926 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12930 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12932 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12937 g_assert_not_reached();
12941 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12943 tcg_temp_free_i32(tcg_res
);
12944 tcg_temp_free_i32(tcg_op
);
12947 clear_vec_high(s
, is_q
, rd
);
12950 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12951 tcg_temp_free_i32(tcg_rmode
);
12953 if (need_fpstatus
) {
12954 tcg_temp_free_ptr(tcg_fpstatus
);
12958 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12960 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12961 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12962 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12963 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12964 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12965 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12967 * This actually covers two groups where scalar access is governed by
12968 * bit 28. A bunch of the instructions (float to integral) only exist
12969 * in the vector form and are un-allocated for the scalar decode. Also
12970 * in the scalar decode Q is always 1.
12972 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12974 int fpop
, opcode
, a
, u
;
12978 bool only_in_vector
= false;
12981 TCGv_i32 tcg_rmode
= NULL
;
12982 TCGv_ptr tcg_fpstatus
= NULL
;
12983 bool need_rmode
= false;
12984 bool need_fpst
= true;
12987 if (!dc_isar_feature(aa64_fp16
, s
)) {
12988 unallocated_encoding(s
);
12992 rd
= extract32(insn
, 0, 5);
12993 rn
= extract32(insn
, 5, 5);
12995 a
= extract32(insn
, 23, 1);
12996 u
= extract32(insn
, 29, 1);
12997 is_scalar
= extract32(insn
, 28, 1);
12998 is_q
= extract32(insn
, 30, 1);
13000 opcode
= extract32(insn
, 12, 5);
13001 fpop
= deposit32(opcode
, 5, 1, a
);
13002 fpop
= deposit32(fpop
, 6, 1, u
);
13005 case 0x1d: /* SCVTF */
13006 case 0x5d: /* UCVTF */
13013 elements
= (is_q
? 8 : 4);
13016 if (!fp_access_check(s
)) {
13019 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13023 case 0x2c: /* FCMGT (zero) */
13024 case 0x2d: /* FCMEQ (zero) */
13025 case 0x2e: /* FCMLT (zero) */
13026 case 0x6c: /* FCMGE (zero) */
13027 case 0x6d: /* FCMLE (zero) */
13028 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13030 case 0x3d: /* FRECPE */
13031 case 0x3f: /* FRECPX */
13033 case 0x18: /* FRINTN */
13035 only_in_vector
= true;
13036 rmode
= FPROUNDING_TIEEVEN
;
13038 case 0x19: /* FRINTM */
13040 only_in_vector
= true;
13041 rmode
= FPROUNDING_NEGINF
;
13043 case 0x38: /* FRINTP */
13045 only_in_vector
= true;
13046 rmode
= FPROUNDING_POSINF
;
13048 case 0x39: /* FRINTZ */
13050 only_in_vector
= true;
13051 rmode
= FPROUNDING_ZERO
;
13053 case 0x58: /* FRINTA */
13055 only_in_vector
= true;
13056 rmode
= FPROUNDING_TIEAWAY
;
13058 case 0x59: /* FRINTX */
13059 case 0x79: /* FRINTI */
13060 only_in_vector
= true;
13061 /* current rounding mode */
13063 case 0x1a: /* FCVTNS */
13065 rmode
= FPROUNDING_TIEEVEN
;
13067 case 0x1b: /* FCVTMS */
13069 rmode
= FPROUNDING_NEGINF
;
13071 case 0x1c: /* FCVTAS */
13073 rmode
= FPROUNDING_TIEAWAY
;
13075 case 0x3a: /* FCVTPS */
13077 rmode
= FPROUNDING_POSINF
;
13079 case 0x3b: /* FCVTZS */
13081 rmode
= FPROUNDING_ZERO
;
13083 case 0x5a: /* FCVTNU */
13085 rmode
= FPROUNDING_TIEEVEN
;
13087 case 0x5b: /* FCVTMU */
13089 rmode
= FPROUNDING_NEGINF
;
13091 case 0x5c: /* FCVTAU */
13093 rmode
= FPROUNDING_TIEAWAY
;
13095 case 0x7a: /* FCVTPU */
13097 rmode
= FPROUNDING_POSINF
;
13099 case 0x7b: /* FCVTZU */
13101 rmode
= FPROUNDING_ZERO
;
13103 case 0x2f: /* FABS */
13104 case 0x6f: /* FNEG */
13107 case 0x7d: /* FRSQRTE */
13108 case 0x7f: /* FSQRT (vector) */
13111 fprintf(stderr
, "%s: insn 0x%04x fpop 0x%2x\n", __func__
, insn
, fpop
);
13112 g_assert_not_reached();
13116 /* Check additional constraints for the scalar encoding */
13119 unallocated_encoding(s
);
13122 /* FRINTxx is only in the vector form */
13123 if (only_in_vector
) {
13124 unallocated_encoding(s
);
13129 if (!fp_access_check(s
)) {
13133 if (need_rmode
|| need_fpst
) {
13134 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
13138 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13139 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13143 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13144 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13147 case 0x1a: /* FCVTNS */
13148 case 0x1b: /* FCVTMS */
13149 case 0x1c: /* FCVTAS */
13150 case 0x3a: /* FCVTPS */
13151 case 0x3b: /* FCVTZS */
13152 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13154 case 0x3d: /* FRECPE */
13155 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13157 case 0x3f: /* FRECPX */
13158 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13160 case 0x5a: /* FCVTNU */
13161 case 0x5b: /* FCVTMU */
13162 case 0x5c: /* FCVTAU */
13163 case 0x7a: /* FCVTPU */
13164 case 0x7b: /* FCVTZU */
13165 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13167 case 0x6f: /* FNEG */
13168 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13170 case 0x7d: /* FRSQRTE */
13171 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13174 g_assert_not_reached();
13177 /* limit any sign extension going on */
13178 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13179 write_fp_sreg(s
, rd
, tcg_res
);
13181 tcg_temp_free_i32(tcg_res
);
13182 tcg_temp_free_i32(tcg_op
);
13184 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13185 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13186 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13188 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13191 case 0x1a: /* FCVTNS */
13192 case 0x1b: /* FCVTMS */
13193 case 0x1c: /* FCVTAS */
13194 case 0x3a: /* FCVTPS */
13195 case 0x3b: /* FCVTZS */
13196 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13198 case 0x3d: /* FRECPE */
13199 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13201 case 0x5a: /* FCVTNU */
13202 case 0x5b: /* FCVTMU */
13203 case 0x5c: /* FCVTAU */
13204 case 0x7a: /* FCVTPU */
13205 case 0x7b: /* FCVTZU */
13206 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13208 case 0x18: /* FRINTN */
13209 case 0x19: /* FRINTM */
13210 case 0x38: /* FRINTP */
13211 case 0x39: /* FRINTZ */
13212 case 0x58: /* FRINTA */
13213 case 0x79: /* FRINTI */
13214 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13216 case 0x59: /* FRINTX */
13217 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13219 case 0x2f: /* FABS */
13220 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13222 case 0x6f: /* FNEG */
13223 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13225 case 0x7d: /* FRSQRTE */
13226 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13228 case 0x7f: /* FSQRT */
13229 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13232 g_assert_not_reached();
13235 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13237 tcg_temp_free_i32(tcg_res
);
13238 tcg_temp_free_i32(tcg_op
);
13241 clear_vec_high(s
, is_q
, rd
);
13245 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13246 tcg_temp_free_i32(tcg_rmode
);
13249 if (tcg_fpstatus
) {
13250 tcg_temp_free_ptr(tcg_fpstatus
);
13254 /* AdvSIMD scalar x indexed element
13255 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13256 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13257 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13258 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13259 * AdvSIMD vector x indexed element
13260 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13261 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13262 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13263 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13265 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13267 /* This encoding has two kinds of instruction:
13268 * normal, where we perform elt x idxelt => elt for each
13269 * element in the vector
13270 * long, where we perform elt x idxelt and generate a result of
13271 * double the width of the input element
13272 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13274 bool is_scalar
= extract32(insn
, 28, 1);
13275 bool is_q
= extract32(insn
, 30, 1);
13276 bool u
= extract32(insn
, 29, 1);
13277 int size
= extract32(insn
, 22, 2);
13278 int l
= extract32(insn
, 21, 1);
13279 int m
= extract32(insn
, 20, 1);
13280 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13281 int rm
= extract32(insn
, 16, 4);
13282 int opcode
= extract32(insn
, 12, 4);
13283 int h
= extract32(insn
, 11, 1);
13284 int rn
= extract32(insn
, 5, 5);
13285 int rd
= extract32(insn
, 0, 5);
13286 bool is_long
= false;
13288 bool is_fp16
= false;
13292 switch (16 * u
+ opcode
) {
13293 case 0x08: /* MUL */
13294 case 0x10: /* MLA */
13295 case 0x14: /* MLS */
13297 unallocated_encoding(s
);
13301 case 0x02: /* SMLAL, SMLAL2 */
13302 case 0x12: /* UMLAL, UMLAL2 */
13303 case 0x06: /* SMLSL, SMLSL2 */
13304 case 0x16: /* UMLSL, UMLSL2 */
13305 case 0x0a: /* SMULL, SMULL2 */
13306 case 0x1a: /* UMULL, UMULL2 */
13308 unallocated_encoding(s
);
13313 case 0x03: /* SQDMLAL, SQDMLAL2 */
13314 case 0x07: /* SQDMLSL, SQDMLSL2 */
13315 case 0x0b: /* SQDMULL, SQDMULL2 */
13318 case 0x0c: /* SQDMULH */
13319 case 0x0d: /* SQRDMULH */
13321 case 0x01: /* FMLA */
13322 case 0x05: /* FMLS */
13323 case 0x09: /* FMUL */
13324 case 0x19: /* FMULX */
13327 case 0x1d: /* SQRDMLAH */
13328 case 0x1f: /* SQRDMLSH */
13329 if (!dc_isar_feature(aa64_rdm
, s
)) {
13330 unallocated_encoding(s
);
13334 case 0x0e: /* SDOT */
13335 case 0x1e: /* UDOT */
13336 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13337 unallocated_encoding(s
);
13341 case 0x11: /* FCMLA #0 */
13342 case 0x13: /* FCMLA #90 */
13343 case 0x15: /* FCMLA #180 */
13344 case 0x17: /* FCMLA #270 */
13345 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13346 unallocated_encoding(s
);
13351 case 0x00: /* FMLAL */
13352 case 0x04: /* FMLSL */
13353 case 0x18: /* FMLAL2 */
13354 case 0x1c: /* FMLSL2 */
13355 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13356 unallocated_encoding(s
);
13360 /* is_fp, but we pass cpu_env not fp_status. */
13363 unallocated_encoding(s
);
13368 case 1: /* normal fp */
13369 /* convert insn encoded size to MemOp size */
13371 case 0: /* half-precision */
13375 case MO_32
: /* single precision */
13376 case MO_64
: /* double precision */
13379 unallocated_encoding(s
);
13384 case 2: /* complex fp */
13385 /* Each indexable element is a complex pair. */
13390 unallocated_encoding(s
);
13398 unallocated_encoding(s
);
13403 default: /* integer */
13407 unallocated_encoding(s
);
13412 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13413 unallocated_encoding(s
);
13417 /* Given MemOp size, adjust register and indexing. */
13420 index
= h
<< 2 | l
<< 1 | m
;
13423 index
= h
<< 1 | l
;
13428 unallocated_encoding(s
);
13435 g_assert_not_reached();
13438 if (!fp_access_check(s
)) {
13443 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13448 switch (16 * u
+ opcode
) {
13449 case 0x0e: /* SDOT */
13450 case 0x1e: /* UDOT */
13451 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13452 u
? gen_helper_gvec_udot_idx_b
13453 : gen_helper_gvec_sdot_idx_b
);
13455 case 0x11: /* FCMLA #0 */
13456 case 0x13: /* FCMLA #90 */
13457 case 0x15: /* FCMLA #180 */
13458 case 0x17: /* FCMLA #270 */
13460 int rot
= extract32(insn
, 13, 2);
13461 int data
= (index
<< 2) | rot
;
13462 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13463 vec_full_reg_offset(s
, rn
),
13464 vec_full_reg_offset(s
, rm
), fpst
,
13465 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13467 ? gen_helper_gvec_fcmlas_idx
13468 : gen_helper_gvec_fcmlah_idx
);
13469 tcg_temp_free_ptr(fpst
);
13473 case 0x00: /* FMLAL */
13474 case 0x04: /* FMLSL */
13475 case 0x18: /* FMLAL2 */
13476 case 0x1c: /* FMLSL2 */
13478 int is_s
= extract32(opcode
, 2, 1);
13480 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13481 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13482 vec_full_reg_offset(s
, rn
),
13483 vec_full_reg_offset(s
, rm
), cpu_env
,
13484 is_q
? 16 : 8, vec_full_reg_size(s
),
13485 data
, gen_helper_gvec_fmlal_idx_a64
);
13489 case 0x08: /* MUL */
13490 if (!is_long
&& !is_scalar
) {
13491 static gen_helper_gvec_3
* const fns
[3] = {
13492 gen_helper_gvec_mul_idx_h
,
13493 gen_helper_gvec_mul_idx_s
,
13494 gen_helper_gvec_mul_idx_d
,
13496 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13497 vec_full_reg_offset(s
, rn
),
13498 vec_full_reg_offset(s
, rm
),
13499 is_q
? 16 : 8, vec_full_reg_size(s
),
13500 index
, fns
[size
- 1]);
13505 case 0x10: /* MLA */
13506 if (!is_long
&& !is_scalar
) {
13507 static gen_helper_gvec_4
* const fns
[3] = {
13508 gen_helper_gvec_mla_idx_h
,
13509 gen_helper_gvec_mla_idx_s
,
13510 gen_helper_gvec_mla_idx_d
,
13512 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13513 vec_full_reg_offset(s
, rn
),
13514 vec_full_reg_offset(s
, rm
),
13515 vec_full_reg_offset(s
, rd
),
13516 is_q
? 16 : 8, vec_full_reg_size(s
),
13517 index
, fns
[size
- 1]);
13522 case 0x14: /* MLS */
13523 if (!is_long
&& !is_scalar
) {
13524 static gen_helper_gvec_4
* const fns
[3] = {
13525 gen_helper_gvec_mls_idx_h
,
13526 gen_helper_gvec_mls_idx_s
,
13527 gen_helper_gvec_mls_idx_d
,
13529 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13530 vec_full_reg_offset(s
, rn
),
13531 vec_full_reg_offset(s
, rm
),
13532 vec_full_reg_offset(s
, rd
),
13533 is_q
? 16 : 8, vec_full_reg_size(s
),
13534 index
, fns
[size
- 1]);
13541 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13544 assert(is_fp
&& is_q
&& !is_long
);
13546 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13548 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13549 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13550 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13552 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13554 switch (16 * u
+ opcode
) {
13555 case 0x05: /* FMLS */
13556 /* As usual for ARM, separate negation for fused multiply-add */
13557 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13559 case 0x01: /* FMLA */
13560 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13561 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13563 case 0x09: /* FMUL */
13564 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13566 case 0x19: /* FMULX */
13567 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13570 g_assert_not_reached();
13573 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13574 tcg_temp_free_i64(tcg_op
);
13575 tcg_temp_free_i64(tcg_res
);
13578 tcg_temp_free_i64(tcg_idx
);
13579 clear_vec_high(s
, !is_scalar
, rd
);
13580 } else if (!is_long
) {
13581 /* 32 bit floating point, or 16 or 32 bit integer.
13582 * For the 16 bit scalar case we use the usual Neon helpers and
13583 * rely on the fact that 0 op 0 == 0 with no side effects.
13585 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13586 int pass
, maxpasses
;
13591 maxpasses
= is_q
? 4 : 2;
13594 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13596 if (size
== 1 && !is_scalar
) {
13597 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13598 * the index into both halves of the 32 bit tcg_idx and then use
13599 * the usual Neon helpers.
13601 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13604 for (pass
= 0; pass
< maxpasses
; pass
++) {
13605 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13606 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13608 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13610 switch (16 * u
+ opcode
) {
13611 case 0x08: /* MUL */
13612 case 0x10: /* MLA */
13613 case 0x14: /* MLS */
13615 static NeonGenTwoOpFn
* const fns
[2][2] = {
13616 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13617 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13619 NeonGenTwoOpFn
*genfn
;
13620 bool is_sub
= opcode
== 0x4;
13623 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13625 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13627 if (opcode
== 0x8) {
13630 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13631 genfn
= fns
[size
- 1][is_sub
];
13632 genfn(tcg_res
, tcg_op
, tcg_res
);
13635 case 0x05: /* FMLS */
13636 case 0x01: /* FMLA */
13637 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13638 is_scalar
? size
: MO_32
);
13641 if (opcode
== 0x5) {
13642 /* As usual for ARM, separate negation for fused
13644 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13647 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13650 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13655 if (opcode
== 0x5) {
13656 /* As usual for ARM, separate negation for
13657 * fused multiply-add */
13658 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13660 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13664 g_assert_not_reached();
13667 case 0x09: /* FMUL */
13671 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13674 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13679 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13682 g_assert_not_reached();
13685 case 0x19: /* FMULX */
13689 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13692 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13697 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13700 g_assert_not_reached();
13703 case 0x0c: /* SQDMULH */
13705 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13708 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13712 case 0x0d: /* SQRDMULH */
13714 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13717 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13721 case 0x1d: /* SQRDMLAH */
13722 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13723 is_scalar
? size
: MO_32
);
13725 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13726 tcg_op
, tcg_idx
, tcg_res
);
13728 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13729 tcg_op
, tcg_idx
, tcg_res
);
13732 case 0x1f: /* SQRDMLSH */
13733 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13734 is_scalar
? size
: MO_32
);
13736 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13737 tcg_op
, tcg_idx
, tcg_res
);
13739 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13740 tcg_op
, tcg_idx
, tcg_res
);
13744 g_assert_not_reached();
13748 write_fp_sreg(s
, rd
, tcg_res
);
13750 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13753 tcg_temp_free_i32(tcg_op
);
13754 tcg_temp_free_i32(tcg_res
);
13757 tcg_temp_free_i32(tcg_idx
);
13758 clear_vec_high(s
, is_q
, rd
);
13760 /* long ops: 16x16->32 or 32x32->64 */
13761 TCGv_i64 tcg_res
[2];
13763 bool satop
= extract32(opcode
, 0, 1);
13764 MemOp memop
= MO_32
;
13771 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13773 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13775 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13776 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13777 TCGv_i64 tcg_passres
;
13783 passelt
= pass
+ (is_q
* 2);
13786 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13788 tcg_res
[pass
] = tcg_temp_new_i64();
13790 if (opcode
== 0xa || opcode
== 0xb) {
13791 /* Non-accumulating ops */
13792 tcg_passres
= tcg_res
[pass
];
13794 tcg_passres
= tcg_temp_new_i64();
13797 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13798 tcg_temp_free_i64(tcg_op
);
13801 /* saturating, doubling */
13802 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13803 tcg_passres
, tcg_passres
);
13806 if (opcode
== 0xa || opcode
== 0xb) {
13810 /* Accumulating op: handle accumulate step */
13811 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13814 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13815 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13817 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13818 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13820 case 0x7: /* SQDMLSL, SQDMLSL2 */
13821 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13823 case 0x3: /* SQDMLAL, SQDMLAL2 */
13824 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13829 g_assert_not_reached();
13831 tcg_temp_free_i64(tcg_passres
);
13833 tcg_temp_free_i64(tcg_idx
);
13835 clear_vec_high(s
, !is_scalar
, rd
);
13837 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13840 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13843 /* The simplest way to handle the 16x16 indexed ops is to
13844 * duplicate the index into both halves of the 32 bit tcg_idx
13845 * and then use the usual Neon helpers.
13847 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13850 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13851 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13852 TCGv_i64 tcg_passres
;
13855 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13857 read_vec_element_i32(s
, tcg_op
, rn
,
13858 pass
+ (is_q
* 2), MO_32
);
13861 tcg_res
[pass
] = tcg_temp_new_i64();
13863 if (opcode
== 0xa || opcode
== 0xb) {
13864 /* Non-accumulating ops */
13865 tcg_passres
= tcg_res
[pass
];
13867 tcg_passres
= tcg_temp_new_i64();
13870 if (memop
& MO_SIGN
) {
13871 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13873 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13876 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13877 tcg_passres
, tcg_passres
);
13879 tcg_temp_free_i32(tcg_op
);
13881 if (opcode
== 0xa || opcode
== 0xb) {
13885 /* Accumulating op: handle accumulate step */
13886 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13889 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13890 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13893 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13894 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13897 case 0x7: /* SQDMLSL, SQDMLSL2 */
13898 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13900 case 0x3: /* SQDMLAL, SQDMLAL2 */
13901 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13906 g_assert_not_reached();
13908 tcg_temp_free_i64(tcg_passres
);
13910 tcg_temp_free_i32(tcg_idx
);
13913 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13918 tcg_res
[1] = tcg_const_i64(0);
13921 for (pass
= 0; pass
< 2; pass
++) {
13922 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13923 tcg_temp_free_i64(tcg_res
[pass
]);
13928 tcg_temp_free_ptr(fpst
);
13933 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13934 * +-----------------+------+-----------+--------+-----+------+------+
13935 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13936 * +-----------------+------+-----------+--------+-----+------+------+
13938 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13940 int size
= extract32(insn
, 22, 2);
13941 int opcode
= extract32(insn
, 12, 5);
13942 int rn
= extract32(insn
, 5, 5);
13943 int rd
= extract32(insn
, 0, 5);
13945 gen_helper_gvec_2
*genfn2
= NULL
;
13946 gen_helper_gvec_3
*genfn3
= NULL
;
13948 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13949 unallocated_encoding(s
);
13954 case 0x4: /* AESE */
13956 genfn3
= gen_helper_crypto_aese
;
13958 case 0x6: /* AESMC */
13960 genfn2
= gen_helper_crypto_aesmc
;
13962 case 0x5: /* AESD */
13964 genfn3
= gen_helper_crypto_aese
;
13966 case 0x7: /* AESIMC */
13968 genfn2
= gen_helper_crypto_aesmc
;
13971 unallocated_encoding(s
);
13975 if (!fp_access_check(s
)) {
13979 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13981 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13985 /* Crypto three-reg SHA
13986 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13987 * +-----------------+------+---+------+---+--------+-----+------+------+
13988 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13989 * +-----------------+------+---+------+---+--------+-----+------+------+
13991 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13993 int size
= extract32(insn
, 22, 2);
13994 int opcode
= extract32(insn
, 12, 3);
13995 int rm
= extract32(insn
, 16, 5);
13996 int rn
= extract32(insn
, 5, 5);
13997 int rd
= extract32(insn
, 0, 5);
13998 gen_helper_gvec_3
*genfn
;
14002 unallocated_encoding(s
);
14007 case 0: /* SHA1C */
14008 genfn
= gen_helper_crypto_sha1c
;
14009 feature
= dc_isar_feature(aa64_sha1
, s
);
14011 case 1: /* SHA1P */
14012 genfn
= gen_helper_crypto_sha1p
;
14013 feature
= dc_isar_feature(aa64_sha1
, s
);
14015 case 2: /* SHA1M */
14016 genfn
= gen_helper_crypto_sha1m
;
14017 feature
= dc_isar_feature(aa64_sha1
, s
);
14019 case 3: /* SHA1SU0 */
14020 genfn
= gen_helper_crypto_sha1su0
;
14021 feature
= dc_isar_feature(aa64_sha1
, s
);
14023 case 4: /* SHA256H */
14024 genfn
= gen_helper_crypto_sha256h
;
14025 feature
= dc_isar_feature(aa64_sha256
, s
);
14027 case 5: /* SHA256H2 */
14028 genfn
= gen_helper_crypto_sha256h2
;
14029 feature
= dc_isar_feature(aa64_sha256
, s
);
14031 case 6: /* SHA256SU1 */
14032 genfn
= gen_helper_crypto_sha256su1
;
14033 feature
= dc_isar_feature(aa64_sha256
, s
);
14036 unallocated_encoding(s
);
14041 unallocated_encoding(s
);
14045 if (!fp_access_check(s
)) {
14048 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14051 /* Crypto two-reg SHA
14052 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14053 * +-----------------+------+-----------+--------+-----+------+------+
14054 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14055 * +-----------------+------+-----------+--------+-----+------+------+
14057 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14059 int size
= extract32(insn
, 22, 2);
14060 int opcode
= extract32(insn
, 12, 5);
14061 int rn
= extract32(insn
, 5, 5);
14062 int rd
= extract32(insn
, 0, 5);
14063 gen_helper_gvec_2
*genfn
;
14067 unallocated_encoding(s
);
14072 case 0: /* SHA1H */
14073 feature
= dc_isar_feature(aa64_sha1
, s
);
14074 genfn
= gen_helper_crypto_sha1h
;
14076 case 1: /* SHA1SU1 */
14077 feature
= dc_isar_feature(aa64_sha1
, s
);
14078 genfn
= gen_helper_crypto_sha1su1
;
14080 case 2: /* SHA256SU0 */
14081 feature
= dc_isar_feature(aa64_sha256
, s
);
14082 genfn
= gen_helper_crypto_sha256su0
;
14085 unallocated_encoding(s
);
14090 unallocated_encoding(s
);
14094 if (!fp_access_check(s
)) {
14097 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14100 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14102 tcg_gen_rotli_i64(d
, m
, 1);
14103 tcg_gen_xor_i64(d
, d
, n
);
14106 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14108 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14109 tcg_gen_xor_vec(vece
, d
, d
, n
);
14112 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14113 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14115 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14116 static const GVecGen3 op
= {
14117 .fni8
= gen_rax1_i64
,
14118 .fniv
= gen_rax1_vec
,
14119 .opt_opc
= vecop_list
,
14120 .fno
= gen_helper_crypto_rax1
,
14123 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14126 /* Crypto three-reg SHA512
14127 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14128 * +-----------------------+------+---+---+-----+--------+------+------+
14129 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14130 * +-----------------------+------+---+---+-----+--------+------+------+
14132 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14134 int opcode
= extract32(insn
, 10, 2);
14135 int o
= extract32(insn
, 14, 1);
14136 int rm
= extract32(insn
, 16, 5);
14137 int rn
= extract32(insn
, 5, 5);
14138 int rd
= extract32(insn
, 0, 5);
14140 gen_helper_gvec_3
*oolfn
= NULL
;
14141 GVecGen3Fn
*gvecfn
= NULL
;
14145 case 0: /* SHA512H */
14146 feature
= dc_isar_feature(aa64_sha512
, s
);
14147 oolfn
= gen_helper_crypto_sha512h
;
14149 case 1: /* SHA512H2 */
14150 feature
= dc_isar_feature(aa64_sha512
, s
);
14151 oolfn
= gen_helper_crypto_sha512h2
;
14153 case 2: /* SHA512SU1 */
14154 feature
= dc_isar_feature(aa64_sha512
, s
);
14155 oolfn
= gen_helper_crypto_sha512su1
;
14158 feature
= dc_isar_feature(aa64_sha3
, s
);
14159 gvecfn
= gen_gvec_rax1
;
14162 g_assert_not_reached();
14166 case 0: /* SM3PARTW1 */
14167 feature
= dc_isar_feature(aa64_sm3
, s
);
14168 oolfn
= gen_helper_crypto_sm3partw1
;
14170 case 1: /* SM3PARTW2 */
14171 feature
= dc_isar_feature(aa64_sm3
, s
);
14172 oolfn
= gen_helper_crypto_sm3partw2
;
14174 case 2: /* SM4EKEY */
14175 feature
= dc_isar_feature(aa64_sm4
, s
);
14176 oolfn
= gen_helper_crypto_sm4ekey
;
14179 unallocated_encoding(s
);
14185 unallocated_encoding(s
);
14189 if (!fp_access_check(s
)) {
14194 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14196 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14200 /* Crypto two-reg SHA512
14201 * 31 12 11 10 9 5 4 0
14202 * +-----------------------------------------+--------+------+------+
14203 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14204 * +-----------------------------------------+--------+------+------+
14206 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14208 int opcode
= extract32(insn
, 10, 2);
14209 int rn
= extract32(insn
, 5, 5);
14210 int rd
= extract32(insn
, 0, 5);
14214 case 0: /* SHA512SU0 */
14215 feature
= dc_isar_feature(aa64_sha512
, s
);
14218 feature
= dc_isar_feature(aa64_sm4
, s
);
14221 unallocated_encoding(s
);
14226 unallocated_encoding(s
);
14230 if (!fp_access_check(s
)) {
14235 case 0: /* SHA512SU0 */
14236 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14239 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14242 g_assert_not_reached();
14246 /* Crypto four-register
14247 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14248 * +-------------------+-----+------+---+------+------+------+
14249 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14250 * +-------------------+-----+------+---+------+------+------+
14252 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14254 int op0
= extract32(insn
, 21, 2);
14255 int rm
= extract32(insn
, 16, 5);
14256 int ra
= extract32(insn
, 10, 5);
14257 int rn
= extract32(insn
, 5, 5);
14258 int rd
= extract32(insn
, 0, 5);
14264 feature
= dc_isar_feature(aa64_sha3
, s
);
14266 case 2: /* SM3SS1 */
14267 feature
= dc_isar_feature(aa64_sm3
, s
);
14270 unallocated_encoding(s
);
14275 unallocated_encoding(s
);
14279 if (!fp_access_check(s
)) {
14284 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14287 tcg_op1
= tcg_temp_new_i64();
14288 tcg_op2
= tcg_temp_new_i64();
14289 tcg_op3
= tcg_temp_new_i64();
14290 tcg_res
[0] = tcg_temp_new_i64();
14291 tcg_res
[1] = tcg_temp_new_i64();
14293 for (pass
= 0; pass
< 2; pass
++) {
14294 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14295 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14296 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14300 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14303 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14305 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14307 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14308 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14310 tcg_temp_free_i64(tcg_op1
);
14311 tcg_temp_free_i64(tcg_op2
);
14312 tcg_temp_free_i64(tcg_op3
);
14313 tcg_temp_free_i64(tcg_res
[0]);
14314 tcg_temp_free_i64(tcg_res
[1]);
14316 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14318 tcg_op1
= tcg_temp_new_i32();
14319 tcg_op2
= tcg_temp_new_i32();
14320 tcg_op3
= tcg_temp_new_i32();
14321 tcg_res
= tcg_temp_new_i32();
14322 tcg_zero
= tcg_const_i32(0);
14324 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14325 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14326 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14328 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14329 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14330 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14331 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14333 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14334 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14335 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14336 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14338 tcg_temp_free_i32(tcg_op1
);
14339 tcg_temp_free_i32(tcg_op2
);
14340 tcg_temp_free_i32(tcg_op3
);
14341 tcg_temp_free_i32(tcg_res
);
14342 tcg_temp_free_i32(tcg_zero
);
14347 * 31 21 20 16 15 10 9 5 4 0
14348 * +-----------------------+------+--------+------+------+
14349 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14350 * +-----------------------+------+--------+------+------+
14352 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14354 int rm
= extract32(insn
, 16, 5);
14355 int imm6
= extract32(insn
, 10, 6);
14356 int rn
= extract32(insn
, 5, 5);
14357 int rd
= extract32(insn
, 0, 5);
14358 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
14361 if (!dc_isar_feature(aa64_sha3
, s
)) {
14362 unallocated_encoding(s
);
14366 if (!fp_access_check(s
)) {
14370 tcg_op1
= tcg_temp_new_i64();
14371 tcg_op2
= tcg_temp_new_i64();
14372 tcg_res
[0] = tcg_temp_new_i64();
14373 tcg_res
[1] = tcg_temp_new_i64();
14375 for (pass
= 0; pass
< 2; pass
++) {
14376 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14377 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14379 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
14380 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
14382 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14383 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14385 tcg_temp_free_i64(tcg_op1
);
14386 tcg_temp_free_i64(tcg_op2
);
14387 tcg_temp_free_i64(tcg_res
[0]);
14388 tcg_temp_free_i64(tcg_res
[1]);
14391 /* Crypto three-reg imm2
14392 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14393 * +-----------------------+------+-----+------+--------+------+------+
14394 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14395 * +-----------------------+------+-----+------+--------+------+------+
14397 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14399 static gen_helper_gvec_3
* const fns
[4] = {
14400 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14401 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14403 int opcode
= extract32(insn
, 10, 2);
14404 int imm2
= extract32(insn
, 12, 2);
14405 int rm
= extract32(insn
, 16, 5);
14406 int rn
= extract32(insn
, 5, 5);
14407 int rd
= extract32(insn
, 0, 5);
14409 if (!dc_isar_feature(aa64_sm3
, s
)) {
14410 unallocated_encoding(s
);
14414 if (!fp_access_check(s
)) {
14418 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14421 /* C3.6 Data processing - SIMD, inc Crypto
14423 * As the decode gets a little complex we are using a table based
14424 * approach for this part of the decode.
14426 static const AArch64DecodeTable data_proc_simd
[] = {
14427 /* pattern , mask , fn */
14428 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14429 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14430 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14431 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14432 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14433 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14434 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14435 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14436 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14437 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14438 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14439 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14440 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14441 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14442 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14443 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14444 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14445 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14446 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14447 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14448 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14449 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14450 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14451 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14452 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14453 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14454 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14455 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14456 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14457 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14458 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14459 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14460 { 0x00000000, 0x00000000, NULL
}
14463 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14465 /* Note that this is called with all non-FP cases from
14466 * table C3-6 so it must UNDEF for entries not specifically
14467 * allocated to instructions in that table.
14469 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14473 unallocated_encoding(s
);
14477 /* C3.6 Data processing - SIMD and floating point */
14478 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14480 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14481 disas_data_proc_fp(s
, insn
);
14483 /* SIMD, including crypto */
14484 disas_data_proc_simd(s
, insn
);
14490 * @env: The cpu environment
14491 * @s: The DisasContext
14493 * Return true if the page is guarded.
14495 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14497 uint64_t addr
= s
->base
.pc_first
;
14498 #ifdef CONFIG_USER_ONLY
14499 return page_get_flags(addr
) & PAGE_BTI
;
14501 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14502 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14503 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14506 * We test this immediately after reading an insn, which means
14507 * that any normal page must be in the TLB. The only exception
14508 * would be for executing from flash or device memory, which
14509 * does not retain the TLB entry.
14511 * FIXME: Assume false for those, for now. We could use
14512 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14513 * table entry even for that case.
14515 return (tlb_hit(entry
->addr_code
, addr
) &&
14516 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14521 * btype_destination_ok:
14522 * @insn: The instruction at the branch destination
14523 * @bt: SCTLR_ELx.BT
14524 * @btype: PSTATE.BTYPE, and is non-zero
14526 * On a guarded page, there are a limited number of insns
14527 * that may be present at the branch target:
14528 * - branch target identifiers,
14529 * - paciasp, pacibsp,
14532 * Anything else causes a Branch Target Exception.
14534 * Return true if the branch is compatible, false to raise BTITRAP.
14536 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14538 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14540 switch (extract32(insn
, 5, 7)) {
14541 case 0b011001: /* PACIASP */
14542 case 0b011011: /* PACIBSP */
14544 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14545 * with btype == 3. Otherwise all btype are ok.
14547 return !bt
|| btype
!= 3;
14548 case 0b100000: /* BTI */
14549 /* Not compatible with any btype. */
14551 case 0b100010: /* BTI c */
14552 /* Not compatible with btype == 3 */
14554 case 0b100100: /* BTI j */
14555 /* Not compatible with btype == 2 */
14557 case 0b100110: /* BTI jc */
14558 /* Compatible with any btype. */
14562 switch (insn
& 0xffe0001fu
) {
14563 case 0xd4200000u
: /* BRK */
14564 case 0xd4400000u
: /* HLT */
14565 /* Give priority to the breakpoint exception. */
14572 /* C3.1 A64 instruction index by encoding */
14573 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14577 s
->pc_curr
= s
->base
.pc_next
;
14578 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14580 s
->base
.pc_next
+= 4;
14582 s
->fp_access_checked
= false;
14583 s
->sve_access_checked
= false;
14585 if (dc_isar_feature(aa64_bti
, s
)) {
14586 if (s
->base
.num_insns
== 1) {
14588 * At the first insn of the TB, compute s->guarded_page.
14589 * We delayed computing this until successfully reading
14590 * the first insn of the TB, above. This (mostly) ensures
14591 * that the softmmu tlb entry has been populated, and the
14592 * page table GP bit is available.
14594 * Note that we need to compute this even if btype == 0,
14595 * because this value is used for BR instructions later
14596 * where ENV is not available.
14598 s
->guarded_page
= is_guarded_page(env
, s
);
14600 /* First insn can have btype set to non-zero. */
14601 tcg_debug_assert(s
->btype
>= 0);
14604 * Note that the Branch Target Exception has fairly high
14605 * priority -- below debugging exceptions but above most
14606 * everything else. This allows us to handle this now
14607 * instead of waiting until the insn is otherwise decoded.
14611 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14612 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14613 syn_btitrap(s
->btype
),
14614 default_exception_el(s
));
14618 /* Not the first insn: btype must be 0. */
14619 tcg_debug_assert(s
->btype
== 0);
14623 switch (extract32(insn
, 25, 4)) {
14624 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14625 unallocated_encoding(s
);
14628 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14629 unallocated_encoding(s
);
14632 case 0x8: case 0x9: /* Data processing - immediate */
14633 disas_data_proc_imm(s
, insn
);
14635 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14636 disas_b_exc_sys(s
, insn
);
14641 case 0xe: /* Loads and stores */
14642 disas_ldst(s
, insn
);
14645 case 0xd: /* Data processing - register */
14646 disas_data_proc_reg(s
, insn
);
14649 case 0xf: /* Data processing - SIMD and floating point */
14650 disas_data_proc_simd_fp(s
, insn
);
14653 assert(FALSE
); /* all 15 cases should be handled above */
14657 /* if we allocated any temporaries, free them here */
14661 * After execution of most insns, btype is reset to 0.
14662 * Note that we set btype == -1 when the insn sets btype.
14664 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14669 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14672 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14673 CPUARMState
*env
= cpu
->env_ptr
;
14674 ARMCPU
*arm_cpu
= env_archcpu(env
);
14675 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14676 int bound
, core_mmu_idx
;
14678 dc
->isar
= &arm_cpu
->isar
;
14682 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14683 * there is no secure EL1, so we route exceptions to EL3.
14685 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14686 !arm_el_is_aa64(env
, 3);
14689 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14690 dc
->condexec_mask
= 0;
14691 dc
->condexec_cond
= 0;
14692 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14693 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14694 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14695 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14696 dc
->tcma
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TCMA
);
14697 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14698 #if !defined(CONFIG_USER_ONLY)
14699 dc
->user
= (dc
->current_el
== 0);
14701 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14702 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14703 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14704 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14705 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14706 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14707 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14708 dc
->ata
= FIELD_EX32(tb_flags
, TBFLAG_A64
, ATA
);
14709 dc
->mte_active
[0] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE_ACTIVE
);
14710 dc
->mte_active
[1] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE0_ACTIVE
);
14712 dc
->vec_stride
= 0;
14713 dc
->cp_regs
= arm_cpu
->cp_regs
;
14714 dc
->features
= env
->features
;
14715 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14717 #ifdef CONFIG_USER_ONLY
14718 /* In sve_probe_page, we assume TBI is enabled. */
14719 tcg_debug_assert(dc
->tbid
& 1);
14722 /* Single step state. The code-generation logic here is:
14724 * generate code with no special handling for single-stepping (except
14725 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14726 * this happens anyway because those changes are all system register or
14728 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14729 * emit code for one insn
14730 * emit code to clear PSTATE.SS
14731 * emit code to generate software step exception for completed step
14732 * end TB (as usual for having generated an exception)
14733 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14734 * emit code to generate a software step exception
14737 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14738 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14739 dc
->is_ldex
= false;
14740 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14742 /* Bound the number of insns to execute to those left on the page. */
14743 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14745 /* If architectural single step active, limit to 1. */
14746 if (dc
->ss_active
) {
14749 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14751 init_tmp_a64_array(dc
);
14754 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14758 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14760 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14762 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14763 dc
->insn_start
= tcg_last_op();
14766 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14767 const CPUBreakpoint
*bp
)
14769 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14771 if (bp
->flags
& BP_CPU
) {
14772 gen_a64_set_pc_im(dc
->base
.pc_next
);
14773 gen_helper_check_breakpoints(cpu_env
);
14774 /* End the TB early; it likely won't be executed */
14775 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14777 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14778 /* The address covered by the breakpoint must be
14779 included in [tb->pc, tb->pc + tb->size) in order
14780 to for it to be properly cleared -- thus we
14781 increment the PC here so that the logic setting
14782 tb->size below does the right thing. */
14783 dc
->base
.pc_next
+= 4;
14784 dc
->base
.is_jmp
= DISAS_NORETURN
;
14790 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14792 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14793 CPUARMState
*env
= cpu
->env_ptr
;
14795 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14796 /* Singlestep state is Active-pending.
14797 * If we're in this state at the start of a TB then either
14798 * a) we just took an exception to an EL which is being debugged
14799 * and this is the first insn in the exception handler
14800 * b) debug exceptions were masked and we just unmasked them
14801 * without changing EL (eg by clearing PSTATE.D)
14802 * In either case we're going to take a swstep exception in the
14803 * "did not step an insn" case, and so the syndrome ISV and EX
14804 * bits should be zero.
14806 assert(dc
->base
.num_insns
== 1);
14807 gen_swstep_exception(dc
, 0, 0);
14808 dc
->base
.is_jmp
= DISAS_NORETURN
;
14810 disas_a64_insn(env
, dc
);
14813 translator_loop_temp_check(&dc
->base
);
14816 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14818 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14820 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14821 /* Note that this means single stepping WFI doesn't halt the CPU.
14822 * For conditional branch insns this is harmless unreachable code as
14823 * gen_goto_tb() has already handled emitting the debug exception
14824 * (and thus a tb-jump is not possible when singlestepping).
14826 switch (dc
->base
.is_jmp
) {
14828 gen_a64_set_pc_im(dc
->base
.pc_next
);
14832 if (dc
->base
.singlestep_enabled
) {
14833 gen_exception_internal(EXCP_DEBUG
);
14835 gen_step_complete_exception(dc
);
14838 case DISAS_NORETURN
:
14842 switch (dc
->base
.is_jmp
) {
14844 case DISAS_TOO_MANY
:
14845 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14848 case DISAS_UPDATE_EXIT
:
14849 gen_a64_set_pc_im(dc
->base
.pc_next
);
14852 tcg_gen_exit_tb(NULL
, 0);
14854 case DISAS_UPDATE_NOCHAIN
:
14855 gen_a64_set_pc_im(dc
->base
.pc_next
);
14858 tcg_gen_lookup_and_goto_ptr();
14860 case DISAS_NORETURN
:
14864 gen_a64_set_pc_im(dc
->base
.pc_next
);
14865 gen_helper_wfe(cpu_env
);
14868 gen_a64_set_pc_im(dc
->base
.pc_next
);
14869 gen_helper_yield(cpu_env
);
14873 /* This is a special case because we don't want to just halt the CPU
14874 * if trying to debug across a WFI.
14876 TCGv_i32 tmp
= tcg_const_i32(4);
14878 gen_a64_set_pc_im(dc
->base
.pc_next
);
14879 gen_helper_wfi(cpu_env
, tmp
);
14880 tcg_temp_free_i32(tmp
);
14881 /* The helper doesn't necessarily throw an exception, but we
14882 * must go back to the main loop to check for interrupts anyway.
14884 tcg_gen_exit_tb(NULL
, 0);
14891 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14894 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14896 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14897 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14900 const TranslatorOps aarch64_translator_ops
= {
14901 .init_disas_context
= aarch64_tr_init_disas_context
,
14902 .tb_start
= aarch64_tr_tb_start
,
14903 .insn_start
= aarch64_tr_insn_start
,
14904 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14905 .translate_insn
= aarch64_tr_translate_insn
,
14906 .tb_stop
= aarch64_tr_tb_stop
,
14907 .disas_log
= aarch64_tr_disas_log
,