hw/riscv/virt.c

   1 /*
   2  * QEMU RISC-V VirtIO Board
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * RISC-V machine with 16550a UART and VirtIO MMIO
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "qemu/error-report.h"
  24 #include "qapi/error.h"
  25 #include "hw/hw.h"
  26 #include "hw/boards.h"
  27 #include "hw/loader.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/char/serial.h"
  30 #include "target/riscv/cpu.h"
  31 #include "hw/riscv/riscv_htif.h"
  32 #include "hw/riscv/riscv_hart.h"
  33 #include "hw/riscv/sifive_plic.h"
  34 #include "hw/riscv/sifive_clint.h"
  35 #include "hw/riscv/sifive_test.h"
  36 #include "hw/riscv/virt.h"
  37 #include "chardev/char.h"
  38 #include "sysemu/arch_init.h"
  39 #include "sysemu/device_tree.h"
  40 #include "exec/address-spaces.h"
  41 #include "elf.h"
  42
  43 static const struct MemmapEntry {
  44     hwaddr base;
  45     hwaddr size;
  46 } virt_memmap[] = {
  47     [VIRT_DEBUG] =    {        0x0,      0x100 },
  48     [VIRT_MROM] =     {     0x1000,     0x2000 },
  49     [VIRT_TEST] =     {     0x4000,     0x1000 },
  50     [VIRT_CLINT] =    {  0x2000000,    0x10000 },
  51     [VIRT_PLIC] =     {  0xc000000,  0x4000000 },
  52     [VIRT_UART0] =    { 0x10000000,      0x100 },
  53     [VIRT_VIRTIO] =   { 0x10001000,     0x1000 },
  54     [VIRT_DRAM] =     { 0x80000000,        0x0 },
  55 };
  56
  57 static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
  58 {
  59     int i;
  60     for (i = 0; i < (len >> 2); i++) {
  61         stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
  62     }
  63 }
  64
  65 static uint64_t identity_translate(void *opaque, uint64_t addr)
  66 {
  67     return addr;
  68 }
  69
  70 static uint64_t load_kernel(const char *kernel_filename)
  71 {
  72     uint64_t kernel_entry, kernel_high;
  73
  74     if (load_elf(kernel_filename, identity_translate, NULL,
  75                  &kernel_entry, NULL, &kernel_high,
  76                  0, ELF_MACHINE, 1, 0) < 0) {
  77         error_report("qemu: could not load kernel '%s'", kernel_filename);
  78         exit(1);
  79     }
  80     return kernel_entry;
  81 }
  82
  83 static hwaddr load_initrd(const char *filename, uint64_t mem_size,
  84                           uint64_t kernel_entry, hwaddr *start)
  85 {
  86     int size;
  87
  88     /* We want to put the initrd far enough into RAM that when the
  89      * kernel is uncompressed it will not clobber the initrd. However
  90      * on boards without much RAM we must ensure that we still leave
  91      * enough room for a decent sized initrd, and on boards with large
  92      * amounts of RAM we must avoid the initrd being so far up in RAM
  93      * that it is outside lowmem and inaccessible to the kernel.
  94      * So for boards with less  than 256MB of RAM we put the initrd
  95      * halfway into RAM, and for boards with 256MB of RAM or more we put
  96      * the initrd at 128MB.
  97      */
  98     *start = kernel_entry + MIN(mem_size / 2, 128 * 1024 * 1024);
  99
 100     size = load_ramdisk(filename, *start, mem_size - *start);
 101     if (size == -1) {
 102         size = load_image_targphys(filename, *start, mem_size - *start);
 103         if (size == -1) {
 104             error_report("qemu: could not load ramdisk '%s'", filename);
 105             exit(1);
 106         }
 107     }
 108     return *start + size;
 109 }
 110
 111 static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 112     uint64_t mem_size, const char *cmdline)
 113 {
 114     void *fdt;
 115     int cpu;
 116     uint32_t *cells;
 117     char *nodename;
 118     uint32_t plic_phandle, phandle = 1;
 119     int i;
 120
 121     fdt = s->fdt = create_device_tree(&s->fdt_size);
 122     if (!fdt) {
 123         error_report("create_device_tree() failed");
 124         exit(1);
 125     }
 126
 127     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
 128     qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
 129     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 130     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 131
 132     qemu_fdt_add_subnode(fdt, "/soc");
 133     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 134     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");
 135     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 136     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 137
 138     nodename = g_strdup_printf("/memory@%lx",
 139         (long)memmap[VIRT_DRAM].base);
 140     qemu_fdt_add_subnode(fdt, nodename);
 141     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 142         memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
 143         mem_size >> 32, mem_size);
 144     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 145     g_free(nodename);
 146
 147     qemu_fdt_add_subnode(fdt, "/cpus");
 148     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 149                           SIFIVE_CLINT_TIMEBASE_FREQ);
 150     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 151     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 152
 153     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 154         int cpu_phandle = phandle++;
 155         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 156         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 157         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 158         qemu_fdt_add_subnode(fdt, nodename);
 159         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 160                               VIRT_CLOCK_FREQ);
 161         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 162         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 163         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 164         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 165         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 166         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 167         qemu_fdt_add_subnode(fdt, intc);
 168         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
 169         qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
 170         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 171         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 172         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 173         g_free(isa);
 174         g_free(intc);
 175         g_free(nodename);
 176     }
 177
 178     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 179     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 180         nodename =
 181             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 182         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 183         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 184         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 185         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 186         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 187         g_free(nodename);
 188     }
 189     nodename = g_strdup_printf("/soc/clint@%lx",
 190         (long)memmap[VIRT_CLINT].base);
 191     qemu_fdt_add_subnode(fdt, nodename);
 192     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 193     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 194         0x0, memmap[VIRT_CLINT].base,
 195         0x0, memmap[VIRT_CLINT].size);
 196     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 197         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 198     g_free(cells);
 199     g_free(nodename);
 200
 201     plic_phandle = phandle++;
 202     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 203     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 204         nodename =
 205             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 206         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 207         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 208         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 209         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 210         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 211         g_free(nodename);
 212     }
 213     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 214         (long)memmap[VIRT_PLIC].base);
 215     qemu_fdt_add_subnode(fdt, nodename);
 216     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 217     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 218     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 219     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 220         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 221     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 222         0x0, memmap[VIRT_PLIC].base,
 223         0x0, memmap[VIRT_PLIC].size);
 224     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 225     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 226     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 227     qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
 228     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
 229     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 230     g_free(cells);
 231     g_free(nodename);
 232
 233     for (i = 0; i < VIRTIO_COUNT; i++) {
 234         nodename = g_strdup_printf("/virtio_mmio@%lx",
 235             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
 236         qemu_fdt_add_subnode(fdt, nodename);
 237         qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
 238         qemu_fdt_setprop_cells(fdt, nodename, "reg",
 239             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 240             0x0, memmap[VIRT_VIRTIO].size);
 241         qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 242         qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
 243         g_free(nodename);
 244     }
 245
 246     nodename = g_strdup_printf("/test@%lx",
 247         (long)memmap[VIRT_TEST].base);
 248     qemu_fdt_add_subnode(fdt, nodename);
 249     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
 250     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 251         0x0, memmap[VIRT_TEST].base,
 252         0x0, memmap[VIRT_TEST].size);
 253
 254     nodename = g_strdup_printf("/uart@%lx",
 255         (long)memmap[VIRT_UART0].base);
 256     qemu_fdt_add_subnode(fdt, nodename);
 257     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
 258     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 259         0x0, memmap[VIRT_UART0].base,
 260         0x0, memmap[VIRT_UART0].size);
 261     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
 262         qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 263         qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
 264
 265     qemu_fdt_add_subnode(fdt, "/chosen");
 266     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 267     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 268     g_free(nodename);
 269
 270     return fdt;
 271 }
 272
 273 static void riscv_virt_board_init(MachineState *machine)
 274 {
 275     const struct MemmapEntry *memmap = virt_memmap;
 276
 277     RISCVVirtState *s = g_new0(RISCVVirtState, 1);
 278     MemoryRegion *system_memory = get_system_memory();
 279     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 280     MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 281     char *plic_hart_config;
 282     size_t plic_hart_config_len;
 283     int i;
 284     void *fdt;
 285
 286     /* Initialize SOC */
 287     object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
 288     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
 289                               &error_abort);
 290     object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
 291                             &error_abort);
 292     object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 293                             &error_abort);
 294     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 295                             &error_abort);
 296
 297     /* register system main memory (actual RAM) */
 298     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
 299                            machine->ram_size, &error_fatal);
 300     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
 301         main_mem);
 302
 303     /* create device tree */
 304     fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 305
 306     /* boot rom */
 307     memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom",
 308                            s->fdt_size + 0x2000, &error_fatal);
 309     memory_region_add_subregion(system_memory, 0x0, boot_rom);
 310
 311     if (machine->kernel_filename) {
 312         uint64_t kernel_entry = load_kernel(machine->kernel_filename);
 313
 314         if (machine->initrd_filename) {
 315             hwaddr start;
 316             hwaddr end = load_initrd(machine->initrd_filename,
 317                                      machine->ram_size, kernel_entry,
 318                                      &start);
 319             qemu_fdt_setprop_cell(fdt, "/chosen",
 320                                   "linux,initrd-start", start);
 321             qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 322                                   end);
 323         }
 324     }
 325
 326     /* reset vector */
 327     uint32_t reset_vec[8] = {
 328         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
 329         0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
 330         0xf1402573,                  /*     csrr   a0, mhartid  */
 331 #if defined(TARGET_RISCV32)
 332         0x0182a283,                  /*     lw     t0, 24(t0) */
 333 #elif defined(TARGET_RISCV64)
 334         0x0182b283,                  /*     ld     t0, 24(t0) */
 335 #endif
 336         0x00028067,                  /*     jr     t0 */
 337         0x00000000,
 338         memmap[VIRT_DRAM].base,      /* start: .dword memmap[VIRT_DRAM].base */
 339         0x00000000,
 340                                      /* dtb: */
 341     };
 342
 343     /* copy in the reset vector */
 344     copy_le32_to_phys(memmap[VIRT_MROM].base, reset_vec, sizeof(reset_vec));
 345
 346     /* copy in the device tree */
 347     qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
 348     cpu_physical_memory_write(memmap[VIRT_MROM].base + sizeof(reset_vec),
 349         s->fdt, s->fdt_size);
 350
 351     /* create PLIC hart topology configuration string */
 352     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
 353     plic_hart_config = g_malloc0(plic_hart_config_len);
 354     for (i = 0; i < smp_cpus; i++) {
 355         if (i != 0) {
 356             strncat(plic_hart_config, ",", plic_hart_config_len);
 357         }
 358         strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
 359         plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 360     }
 361
 362     /* MMIO */
 363     s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
 364         plic_hart_config,
 365         VIRT_PLIC_NUM_SOURCES,
 366         VIRT_PLIC_NUM_PRIORITIES,
 367         VIRT_PLIC_PRIORITY_BASE,
 368         VIRT_PLIC_PENDING_BASE,
 369         VIRT_PLIC_ENABLE_BASE,
 370         VIRT_PLIC_ENABLE_STRIDE,
 371         VIRT_PLIC_CONTEXT_BASE,
 372         VIRT_PLIC_CONTEXT_STRIDE,
 373         memmap[VIRT_PLIC].size);
 374     sifive_clint_create(memmap[VIRT_CLINT].base,
 375         memmap[VIRT_CLINT].size, smp_cpus,
 376         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 377     sifive_test_create(memmap[VIRT_TEST].base);
 378
 379     for (i = 0; i < VIRTIO_COUNT; i++) {
 380         sysbus_create_simple("virtio-mmio",
 381             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 382             SIFIVE_PLIC(s->plic)->irqs[VIRTIO_IRQ + i]);
 383     }
 384
 385     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
 386         0, SIFIVE_PLIC(s->plic)->irqs[UART0_IRQ], 399193,
 387         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 388 }
 389
 390 static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev)
 391 {
 392     return 0;
 393 }
 394
 395 static void riscv_virt_board_class_init(ObjectClass *klass, void *data)
 396 {
 397     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 398     k->init = riscv_virt_board_sysbus_device_init;
 399 }
 400
 401 static const TypeInfo riscv_virt_board_device = {
 402     .name          = TYPE_RISCV_VIRT_BOARD,
 403     .parent        = TYPE_SYS_BUS_DEVICE,
 404     .instance_size = sizeof(RISCVVirtState),
 405     .class_init    = riscv_virt_board_class_init,
 406 };
 407
 408 static void riscv_virt_board_machine_init(MachineClass *mc)
 409 {
 410     mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
 411     mc->init = riscv_virt_board_init;
 412     mc->max_cpus = 8; /* hardcoded limit in BBL */
 413 }
 414
 415 DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
 416
 417 static void riscv_virt_board_register_types(void)
 418 {
 419     type_register_static(&riscv_virt_board_device);
 420 }
 421
 422 type_init(riscv_virt_board_register_types);