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ui: remove 'sync' parameter from vnc_update_client
[qemu/ar7.git] / target / mips / translate_init.c
blobc7ba6ee5f9baff883f16002463129106de146cf7
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /*****************************************************************************/
55 /* MIPS CPU definitions */
56 const mips_def_t mips_defs[] =
57 {
58 {
59 .name = "4Kc",
60 .CP0_PRid = 0x00018000,
61 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
62 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
63 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
64 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
65 (0 << CP0C1_CA),
66 .CP0_Config2 = MIPS_CONFIG2,
67 .CP0_Config3 = MIPS_CONFIG3,
68 .CP0_LLAddr_rw_bitmask = 0,
69 .CP0_LLAddr_shift = 4,
70 .SYNCI_Step = 32,
71 .CCRes = 2,
72 .CP0_Status_rw_bitmask = 0x1278FF17,
73 .SEGBITS = 32,
74 .PABITS = 32,
75 .insn_flags = CPU_MIPS32,
76 .mmu_type = MMU_TYPE_R4000,
77 },
78 {
79 .name = "4Km",
80 .CP0_PRid = 0x00018300,
81 /* Config1 implemented, fixed mapping MMU,
82 no virtual icache, uncached coherency. */
83 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
84 .CP0_Config1 = MIPS_CONFIG1 |
85 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
86 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
87 (1 << CP0C1_CA),
88 .CP0_Config2 = MIPS_CONFIG2,
89 .CP0_Config3 = MIPS_CONFIG3,
90 .CP0_LLAddr_rw_bitmask = 0,
91 .CP0_LLAddr_shift = 4,
92 .SYNCI_Step = 32,
93 .CCRes = 2,
94 .CP0_Status_rw_bitmask = 0x1258FF17,
95 .SEGBITS = 32,
96 .PABITS = 32,
97 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
98 .mmu_type = MMU_TYPE_FMT,
99 },
100 {
101 .name = "4KEcR1",
102 .CP0_PRid = 0x00018400,
103 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
104 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
105 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
106 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
107 (0 << CP0C1_CA),
108 .CP0_Config2 = MIPS_CONFIG2,
109 .CP0_Config3 = MIPS_CONFIG3,
110 .CP0_LLAddr_rw_bitmask = 0,
111 .CP0_LLAddr_shift = 4,
112 .SYNCI_Step = 32,
113 .CCRes = 2,
114 .CP0_Status_rw_bitmask = 0x1278FF17,
115 .SEGBITS = 32,
116 .PABITS = 32,
117 .insn_flags = CPU_MIPS32,
118 .mmu_type = MMU_TYPE_R4000,
119 },
120 {
121 .name = "4KEmR1",
122 .CP0_PRid = 0x00018500,
123 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
124 .CP0_Config1 = MIPS_CONFIG1 |
125 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
126 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
127 (1 << CP0C1_CA),
128 .CP0_Config2 = MIPS_CONFIG2,
129 .CP0_Config3 = MIPS_CONFIG3,
130 .CP0_LLAddr_rw_bitmask = 0,
131 .CP0_LLAddr_shift = 4,
132 .SYNCI_Step = 32,
133 .CCRes = 2,
134 .CP0_Status_rw_bitmask = 0x1258FF17,
135 .SEGBITS = 32,
136 .PABITS = 32,
137 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
138 .mmu_type = MMU_TYPE_FMT,
139 },
140 {
141 .name = "4KEc",
142 .CP0_PRid = 0x00019000,
143 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
144 (MMU_TYPE_R4000 << CP0C0_MT),
145 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
146 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
147 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
148 (0 << CP0C1_CA),
149 .CP0_Config2 = MIPS_CONFIG2,
150 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
151 .CP0_LLAddr_rw_bitmask = 0,
152 .CP0_LLAddr_shift = 4,
153 .SYNCI_Step = 32,
154 .CCRes = 2,
155 .CP0_Status_rw_bitmask = 0x1278FF17,
156 .SEGBITS = 32,
157 .PABITS = 32,
158 .insn_flags = CPU_MIPS32R2,
159 .mmu_type = MMU_TYPE_R4000,
160 },
161 {
162 .name = "4KEm",
163 .CP0_PRid = 0x00019100,
164 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
165 (MMU_TYPE_FMT << CP0C0_MT),
166 .CP0_Config1 = MIPS_CONFIG1 |
167 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
168 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
169 (1 << CP0C1_CA),
170 .CP0_Config2 = MIPS_CONFIG2,
171 .CP0_Config3 = MIPS_CONFIG3,
172 .CP0_LLAddr_rw_bitmask = 0,
173 .CP0_LLAddr_shift = 4,
174 .SYNCI_Step = 32,
175 .CCRes = 2,
176 .CP0_Status_rw_bitmask = 0x1258FF17,
177 .SEGBITS = 32,
178 .PABITS = 32,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
180 .mmu_type = MMU_TYPE_FMT,
181 },
182 {
183 .name = "24Kc",
184 .CP0_PRid = 0x00019300,
185 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
186 (MMU_TYPE_R4000 << CP0C0_MT),
187 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
188 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
189 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
190 (1 << CP0C1_CA),
191 .CP0_Config2 = MIPS_CONFIG2,
192 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
193 .CP0_LLAddr_rw_bitmask = 0,
194 .CP0_LLAddr_shift = 4,
195 .SYNCI_Step = 32,
196 .CCRes = 2,
197 /* No DSP implemented. */
198 .CP0_Status_rw_bitmask = 0x1278FF1F,
199 .SEGBITS = 32,
200 .PABITS = 32,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
202 .mmu_type = MMU_TYPE_R4000,
203 },
204 {
205 .name = "24KEc",
206 .CP0_PRid = 0x00019600,
207 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
208 (MMU_TYPE_R4000 << CP0C0_MT),
209 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
210 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
211 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
212 (1 << CP0C1_CA),
213 .CP0_Config2 = MIPS_CONFIG2,
214 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
215 .CP0_LLAddr_rw_bitmask = 0,
216 .CP0_LLAddr_shift = 4,
217 .SYNCI_Step = 32,
218 .CCRes = 2,
219 /* we have a DSP, but no FPU */
220 .CP0_Status_rw_bitmask = 0x1378FF1F,
221 .SEGBITS = 32,
222 .PABITS = 32,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
224 .mmu_type = MMU_TYPE_R4000,
225 },
226 {
227 .name = "24Kf",
228 .CP0_PRid = 0x00019300,
229 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
230 (MMU_TYPE_R4000 << CP0C0_MT),
231 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
232 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
233 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
234 (1 << CP0C1_CA),
235 .CP0_Config2 = MIPS_CONFIG2,
236 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
237 .CP0_LLAddr_rw_bitmask = 0,
238 .CP0_LLAddr_shift = 4,
239 .SYNCI_Step = 32,
240 .CCRes = 2,
241 /* No DSP implemented. */
242 .CP0_Status_rw_bitmask = 0x3678FF1F,
243 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
245 .CP1_fcr31 = 0,
246 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
247 .SEGBITS = 32,
248 .PABITS = 32,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
250 .mmu_type = MMU_TYPE_R4000,
251 },
252 {
253 .name = "34Kf",
254 .CP0_PRid = 0x00019500,
255 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
256 (MMU_TYPE_R4000 << CP0C0_MT),
257 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
258 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
259 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
260 (1 << CP0C1_CA),
261 .CP0_Config2 = MIPS_CONFIG2,
262 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
263 (1 << CP0C3_DSPP),
264 .CP0_LLAddr_rw_bitmask = 0,
265 .CP0_LLAddr_shift = 0,
266 .SYNCI_Step = 32,
267 .CCRes = 2,
268 .CP0_Status_rw_bitmask = 0x3778FF1F,
269 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
270 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
272 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
273 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
274 (0xff << CP0TCSt_TASID),
275 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
277 .CP1_fcr31 = 0,
278 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
279 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
280 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
281 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
282 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
283 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
284 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
285 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
286 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
288 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
289 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
290 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
291 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
292 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
293 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
294 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
295 .SEGBITS = 32,
296 .PABITS = 32,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
298 .mmu_type = MMU_TYPE_R4000,
299 },
300 {
301 .name = "74Kf",
302 .CP0_PRid = 0x00019700,
303 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
304 (MMU_TYPE_R4000 << CP0C0_MT),
305 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
306 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
307 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
308 (1 << CP0C1_CA),
309 .CP0_Config2 = MIPS_CONFIG2,
310 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
311 (1 << CP0C3_VInt),
312 .CP0_LLAddr_rw_bitmask = 0,
313 .CP0_LLAddr_shift = 4,
314 .SYNCI_Step = 32,
315 .CCRes = 2,
316 .CP0_Status_rw_bitmask = 0x3778FF1F,
317 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
319 .CP1_fcr31 = 0,
320 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
321 .SEGBITS = 32,
322 .PABITS = 32,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
324 .mmu_type = MMU_TYPE_R4000,
325 },
326 {
327 .name = "M14K",
328 .CP0_PRid = 0x00019b00,
329 /* Config1 implemented, fixed mapping MMU,
330 no virtual icache, uncached coherency. */
331 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
332 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
333 .CP0_Config1 = MIPS_CONFIG1,
334 .CP0_Config2 = MIPS_CONFIG2,
335 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
336 .CP0_LLAddr_rw_bitmask = 0,
337 .CP0_LLAddr_shift = 4,
338 .SYNCI_Step = 32,
339 .CCRes = 2,
340 .CP0_Status_rw_bitmask = 0x1258FF17,
341 .SEGBITS = 32,
342 .PABITS = 32,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
344 .mmu_type = MMU_TYPE_FMT,
345 },
346 {
347 .name = "M14Kc",
348 /* This is the TLB-based MMU core. */
349 .CP0_PRid = 0x00019c00,
350 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
351 (MMU_TYPE_R4000 << CP0C0_MT),
352 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
353 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
354 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
355 .CP0_Config2 = MIPS_CONFIG2,
356 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
357 .CP0_LLAddr_rw_bitmask = 0,
358 .CP0_LLAddr_shift = 4,
359 .SYNCI_Step = 32,
360 .CCRes = 2,
361 .CP0_Status_rw_bitmask = 0x1278FF17,
362 .SEGBITS = 32,
363 .PABITS = 32,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
365 .mmu_type = MMU_TYPE_R4000,
366 },
367 {
368 /* FIXME:
369 * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
370 * Config4: MMUExtDef
371 * Config5: MRP
372 * FIR(FCR0): Has2008
373 * */
374 .name = "P5600",
375 .CP0_PRid = 0x0001A800,
376 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
377 (MMU_TYPE_R4000 << CP0C0_MT),
378 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
379 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
380 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
381 (1 << CP0C1_PC) | (1 << CP0C1_FP),
382 .CP0_Config2 = MIPS_CONFIG2,
383 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
384 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
385 (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
386 (1 << CP0C3_VInt),
387 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
388 (0x1c << CP0C4_KScrExist),
389 .CP0_Config4_rw_bitmask = 0,
390 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
391 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
392 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
393 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
394 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
395 .CP0_LLAddr_rw_bitmask = 0,
396 .CP0_LLAddr_shift = 0,
397 .SYNCI_Step = 32,
398 .CCRes = 2,
399 .CP0_Status_rw_bitmask = 0x3C68FF1F,
400 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
401 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
402 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
403 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
404 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
406 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
407 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
408 .SEGBITS = 32,
409 .PABITS = 40,
410 .insn_flags = CPU_MIPS32R5 | ASE_MSA,
411 .mmu_type = MMU_TYPE_R4000,
412 },
413 {
414 /* A generic CPU supporting MIPS32 Release 6 ISA.
415 FIXME: Support IEEE 754-2008 FP.
416 Eventually this should be replaced by a real CPU model. */
417 .name = "mips32r6-generic",
418 .CP0_PRid = 0x00010000,
419 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
420 (MMU_TYPE_R4000 << CP0C0_MT),
421 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
422 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
423 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
424 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
425 .CP0_Config2 = MIPS_CONFIG2,
426 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
427 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
428 (1 << CP0C3_RXI) | (1U << CP0C3_M),
429 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
430 (3 << CP0C4_IE) | (1U << CP0C4_M),
431 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
432 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
433 (1 << CP0C5_UFE),
434 .CP0_LLAddr_rw_bitmask = 0,
435 .CP0_LLAddr_shift = 0,
436 .SYNCI_Step = 32,
437 .CCRes = 2,
438 .CP0_Status_rw_bitmask = 0x3058FF1F,
439 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
440 (1U << CP0PG_RIE),
441 .CP0_PageGrain_rw_bitmask = 0,
442 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
444 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
445 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
446 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
447 .SEGBITS = 32,
448 .PABITS = 32,
449 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
450 .mmu_type = MMU_TYPE_R4000,
451 },
452 #if defined(TARGET_MIPS64)
453 {
454 .name = "R4000",
455 .CP0_PRid = 0x00000400,
456 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
457 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
458 /* Note: Config1 is only used internally, the R4000 has only Config0. */
459 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
460 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
461 .CP0_LLAddr_shift = 4,
462 .SYNCI_Step = 16,
463 .CCRes = 2,
464 .CP0_Status_rw_bitmask = 0x3678FFFF,
465 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
466 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
467 .CP1_fcr31 = 0,
468 .CP1_fcr31_rw_bitmask = 0x0183FFFF,
469 .SEGBITS = 40,
470 .PABITS = 36,
471 .insn_flags = CPU_MIPS3,
472 .mmu_type = MMU_TYPE_R4000,
473 },
474 {
475 .name = "VR5432",
476 .CP0_PRid = 0x00005400,
477 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
478 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
479 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
480 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
481 .CP0_LLAddr_shift = 4,
482 .SYNCI_Step = 16,
483 .CCRes = 2,
484 .CP0_Status_rw_bitmask = 0x3678FFFF,
485 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
486 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
487 .CP1_fcr31 = 0,
488 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
489 .SEGBITS = 40,
490 .PABITS = 32,
491 .insn_flags = CPU_VR54XX,
492 .mmu_type = MMU_TYPE_R4000,
493 },
494 {
495 .name = "5Kc",
496 .CP0_PRid = 0x00018100,
497 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
498 (MMU_TYPE_R4000 << CP0C0_MT),
499 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
500 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
501 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
502 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
503 .CP0_Config2 = MIPS_CONFIG2,
504 .CP0_Config3 = MIPS_CONFIG3,
505 .CP0_LLAddr_rw_bitmask = 0,
506 .CP0_LLAddr_shift = 4,
507 .SYNCI_Step = 32,
508 .CCRes = 2,
509 .CP0_Status_rw_bitmask = 0x12F8FFFF,
510 .SEGBITS = 42,
511 .PABITS = 36,
512 .insn_flags = CPU_MIPS64,
513 .mmu_type = MMU_TYPE_R4000,
514 },
515 {
516 .name = "5Kf",
517 .CP0_PRid = 0x00018100,
518 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
519 (MMU_TYPE_R4000 << CP0C0_MT),
520 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
521 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
522 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
523 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
524 .CP0_Config2 = MIPS_CONFIG2,
525 .CP0_Config3 = MIPS_CONFIG3,
526 .CP0_LLAddr_rw_bitmask = 0,
527 .CP0_LLAddr_shift = 4,
528 .SYNCI_Step = 32,
529 .CCRes = 2,
530 .CP0_Status_rw_bitmask = 0x36F8FFFF,
531 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
532 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
533 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
534 .CP1_fcr31 = 0,
535 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
536 .SEGBITS = 42,
537 .PABITS = 36,
538 .insn_flags = CPU_MIPS64,
539 .mmu_type = MMU_TYPE_R4000,
540 },
541 {
542 .name = "20Kc",
543 /* We emulate a later version of the 20Kc, earlier ones had a broken
544 WAIT instruction. */
545 .CP0_PRid = 0x000182a0,
546 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
547 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
548 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
549 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
550 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
551 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
552 .CP0_Config2 = MIPS_CONFIG2,
553 .CP0_Config3 = MIPS_CONFIG3,
554 .CP0_LLAddr_rw_bitmask = 0,
555 .CP0_LLAddr_shift = 0,
556 .SYNCI_Step = 32,
557 .CCRes = 1,
558 .CP0_Status_rw_bitmask = 0x36FBFFFF,
559 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
560 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
561 (1 << FCR0_D) | (1 << FCR0_S) |
562 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
563 .CP1_fcr31 = 0,
564 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
565 .SEGBITS = 40,
566 .PABITS = 36,
567 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
568 .mmu_type = MMU_TYPE_R4000,
569 },
570 {
571 /* A generic CPU providing MIPS64 Release 2 features.
572 FIXME: Eventually this should be replaced by a real CPU model. */
573 .name = "MIPS64R2-generic",
574 .CP0_PRid = 0x00010000,
575 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
576 (MMU_TYPE_R4000 << CP0C0_MT),
577 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
578 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
579 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
580 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
581 .CP0_Config2 = MIPS_CONFIG2,
582 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
583 .CP0_LLAddr_rw_bitmask = 0,
584 .CP0_LLAddr_shift = 0,
585 .SYNCI_Step = 32,
586 .CCRes = 2,
587 .CP0_Status_rw_bitmask = 0x36FBFFFF,
588 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
589 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
590 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
591 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
592 .CP1_fcr31 = 0,
593 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
594 .SEGBITS = 42,
595 .PABITS = 36,
596 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
597 .mmu_type = MMU_TYPE_R4000,
598 },
599 {
600 .name = "5KEc",
601 .CP0_PRid = 0x00018900,
602 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
603 (MMU_TYPE_R4000 << CP0C0_MT),
604 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
605 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
606 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
607 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
608 .CP0_Config2 = MIPS_CONFIG2,
609 .CP0_Config3 = MIPS_CONFIG3,
610 .CP0_LLAddr_rw_bitmask = 0,
611 .CP0_LLAddr_shift = 4,
612 .SYNCI_Step = 32,
613 .CCRes = 2,
614 .CP0_Status_rw_bitmask = 0x12F8FFFF,
615 .SEGBITS = 42,
616 .PABITS = 36,
617 .insn_flags = CPU_MIPS64R2,
618 .mmu_type = MMU_TYPE_R4000,
619 },
620 {
621 .name = "5KEf",
622 .CP0_PRid = 0x00018900,
623 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
624 (MMU_TYPE_R4000 << CP0C0_MT),
625 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
626 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
627 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
628 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
629 .CP0_Config2 = MIPS_CONFIG2,
630 .CP0_Config3 = MIPS_CONFIG3,
631 .CP0_LLAddr_rw_bitmask = 0,
632 .CP0_LLAddr_shift = 4,
633 .SYNCI_Step = 32,
634 .CCRes = 2,
635 .CP0_Status_rw_bitmask = 0x36F8FFFF,
636 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
637 (1 << FCR0_D) | (1 << FCR0_S) |
638 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
639 .SEGBITS = 42,
640 .PABITS = 36,
641 .insn_flags = CPU_MIPS64R2,
642 .mmu_type = MMU_TYPE_R4000,
643 },
644 {
645 .name = "I6400",
646 .CP0_PRid = 0x1A900,
647 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
648 (MMU_TYPE_R4000 << CP0C0_MT),
649 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
650 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
651 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
652 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
653 .CP0_Config2 = MIPS_CONFIG2,
654 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
655 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
656 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
657 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
658 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
659 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
660 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
661 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
662 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
663 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
664 .CP0_LLAddr_rw_bitmask = 0,
665 .CP0_LLAddr_shift = 0,
666 .SYNCI_Step = 32,
667 .CCRes = 2,
668 .CP0_Status_rw_bitmask = 0x30D8FFFF,
669 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
670 (1U << CP0PG_RIE),
671 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
672 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
673 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
674 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
675 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
676 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
677 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
678 .MSAIR = 0x03 << MSAIR_ProcID,
679 .SEGBITS = 48,
680 .PABITS = 48,
681 .insn_flags = CPU_MIPS64R6 | ASE_MSA,
682 .mmu_type = MMU_TYPE_R4000,
683 },
684 {
685 .name = "Loongson-2E",
686 .CP0_PRid = 0x6302,
687 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
688 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
689 (0x1<<5) | (0x1<<4) | (0x1<<1),
690 /* Note: Config1 is only used internally,
691 Loongson-2E has only Config0. */
692 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
693 .SYNCI_Step = 16,
694 .CCRes = 2,
695 .CP0_Status_rw_bitmask = 0x35D0FFFF,
696 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
697 .CP1_fcr31 = 0,
698 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
699 .SEGBITS = 40,
700 .PABITS = 40,
701 .insn_flags = CPU_LOONGSON2E,
702 .mmu_type = MMU_TYPE_R4000,
703 },
704 {
705 .name = "Loongson-2F",
706 .CP0_PRid = 0x6303,
707 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
708 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
709 (0x1<<5) | (0x1<<4) | (0x1<<1),
710 /* Note: Config1 is only used internally,
711 Loongson-2F has only Config0. */
712 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
713 .SYNCI_Step = 16,
714 .CCRes = 2,
715 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
716 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
717 .CP1_fcr31 = 0,
718 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
719 .SEGBITS = 40,
720 .PABITS = 40,
721 .insn_flags = CPU_LOONGSON2F,
722 .mmu_type = MMU_TYPE_R4000,
723 },
724 {
725 /* A generic CPU providing MIPS64 ASE DSP 2 features.
726 FIXME: Eventually this should be replaced by a real CPU model. */
727 .name = "mips64dspr2",
728 .CP0_PRid = 0x00010000,
729 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
730 (MMU_TYPE_R4000 << CP0C0_MT),
731 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
732 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
733 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
734 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
735 .CP0_Config2 = MIPS_CONFIG2,
736 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
737 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
738 .CP0_LLAddr_rw_bitmask = 0,
739 .CP0_LLAddr_shift = 0,
740 .SYNCI_Step = 32,
741 .CCRes = 2,
742 .CP0_Status_rw_bitmask = 0x37FBFFFF,
743 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
744 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
745 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
746 .CP1_fcr31 = 0,
747 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
748 .SEGBITS = 42,
749 .PABITS = 36,
750 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
751 .mmu_type = MMU_TYPE_R4000,
752 },
753
754 #endif
755 };
756 const int mips_defs_number = ARRAY_SIZE(mips_defs);
757
758 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
759 {
760 int i;
761
762 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
763 (*cpu_fprintf)(f, "MIPS '%s'\n",
764 mips_defs[i].name);
765 }
766 }
767
768 #ifndef CONFIG_USER_ONLY
769 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
770 {
771 env->tlb->nb_tlb = 1;
772 env->tlb->map_address = &no_mmu_map_address;
773 }
774
775 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
776 {
777 env->tlb->nb_tlb = 1;
778 env->tlb->map_address = &fixed_mmu_map_address;
779 }
780
781 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
782 {
783 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
784 env->tlb->map_address = &r4k_map_address;
785 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
786 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
787 env->tlb->helper_tlbp = r4k_helper_tlbp;
788 env->tlb->helper_tlbr = r4k_helper_tlbr;
789 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
790 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
791 }
792
793 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
794 {
795 MIPSCPU *cpu = mips_env_get_cpu(env);
796
797 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
798
799 switch (def->mmu_type) {
800 case MMU_TYPE_NONE:
801 no_mmu_init(env, def);
802 break;
803 case MMU_TYPE_R4000:
804 r4k_mmu_init(env, def);
805 break;
806 case MMU_TYPE_FMT:
807 fixed_mmu_init(env, def);
808 break;
809 case MMU_TYPE_R3000:
810 case MMU_TYPE_R6000:
811 case MMU_TYPE_R8000:
812 default:
813 cpu_abort(CPU(cpu), "MMU type not supported\n");
814 }
815 }
816 #endif /* CONFIG_USER_ONLY */
817
818 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
819 {
820 int i;
821
822 for (i = 0; i < MIPS_FPU_MAX; i++)
823 env->fpus[i].fcr0 = def->CP1_fcr0;
824
825 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
826 }
827
828 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
829 {
830 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
831
832 /* MVPConf1 implemented, TLB sharable, no gating storage support,
833 programmable cache partitioning implemented, number of allocatable
834 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
835 implemented, 5 TCs implemented. */
836 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
837 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
838 // TODO: actually do 2 VPEs.
839 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
840 // (0x04 << CP0MVPC0_PTC);
841 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
842 (0x00 << CP0MVPC0_PTC);
843 #if !defined(CONFIG_USER_ONLY)
844 /* Usermode has no TLB support */
845 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
846 #endif
847
848 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
849 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
850 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
851 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
852 (0x1 << CP0MVPC1_PCP1);
853 }
854
855 static void msa_reset(CPUMIPSState *env)
856 {
857 #ifdef CONFIG_USER_ONLY
858 /* MSA access enabled */
859 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
860 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
861 #endif
862
863 /* MSA CSR:
864 - non-signaling floating point exception mode off (NX bit is 0)
865 - Cause, Enables, and Flags are all 0
866 - round to nearest / ties to even (RM bits are 0) */
867 env->active_tc.msacsr = 0;
868
869 restore_msa_fp_status(env);
870
871 /* tininess detected after rounding.*/
872 set_float_detect_tininess(float_tininess_after_rounding,
873 &env->active_tc.msa_fp_status);
874
875 /* clear float_status exception flags */
876 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
877
878 /* clear float_status nan mode */
879 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
880
881 /* set proper signanling bit meaning ("1" means "quiet") */
882 set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
883 }
AR7 emulation for QEMU