?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ui: remove 'sync' parameter from vnc_update_client
[qemu/ar7.git] / target / mips / helper.c
blobea076261afc4e89ffe9cbf056e26b8f7e413a677
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26 #include "hw/mips/cpudevs.h"
27
28 enum {
29 TLBRET_XI = -6,
30 TLBRET_RI = -5,
31 TLBRET_DIRTY = -4,
32 TLBRET_INVALID = -3,
33 TLBRET_NOMATCH = -2,
34 TLBRET_BADADDR = -1,
35 TLBRET_MATCH = 0
36 };
37
38 #if !defined(CONFIG_USER_ONLY)
39
40 /* no MMU emulation */
41 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
42 target_ulong address, int rw, int access_type)
43 {
44 *physical = address;
45 *prot = PAGE_READ | PAGE_WRITE;
46 return TLBRET_MATCH;
47 }
48
49 /* fixed mapping MMU emulation */
50 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
51 target_ulong address, int rw, int access_type)
52 {
53 if (address <= (int32_t)0x7FFFFFFFUL) {
54 if (!(env->CP0_Status & (1 << CP0St_ERL)))
55 *physical = address + 0x40000000UL;
56 else
57 *physical = address;
58 } else if (address <= (int32_t)0xBFFFFFFFUL)
59 *physical = address & 0x1FFFFFFF;
60 else
61 *physical = address;
62
63 *prot = PAGE_READ | PAGE_WRITE;
64 return TLBRET_MATCH;
65 }
66
67 /* MIPS32/MIPS64 R4000-style MMU emulation */
68 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
69 target_ulong address, int rw, int access_type)
70 {
71 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
72 int i;
73
74 for (i = 0; i < env->tlb->tlb_in_use; i++) {
75 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
76 /* 1k pages are not supported. */
77 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
78 target_ulong tag = address & ~mask;
79 target_ulong VPN = tlb->VPN & ~mask;
80 #if defined(TARGET_MIPS64)
81 tag &= env->SEGMask;
82 #endif
83
84 /* Check ASID, virtual page number & size */
85 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
86 /* TLB match */
87 int n = !!(address & mask & ~(mask >> 1));
88 /* Check access rights */
89 if (!(n ? tlb->V1 : tlb->V0)) {
90 return TLBRET_INVALID;
91 }
92 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
93 return TLBRET_XI;
94 }
95 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
96 return TLBRET_RI;
97 }
98 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
99 *physical = tlb->PFN[n] | (address & (mask >> 1));
100 *prot = PAGE_READ;
101 if (n ? tlb->D1 : tlb->D0)
102 *prot |= PAGE_WRITE;
103 return TLBRET_MATCH;
104 }
105 return TLBRET_DIRTY;
106 }
107 }
108 return TLBRET_NOMATCH;
109 }
110
111 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
112 {
113 /*
114 * Interpret access control mode and mmu_idx.
115 * AdE? TLB?
116 * AM K S U E K S U E
117 * UK 0 0 1 1 0 0 - - 0
118 * MK 1 0 1 1 0 1 - - !eu
119 * MSK 2 0 0 1 0 1 1 - !eu
120 * MUSK 3 0 0 0 0 1 1 1 !eu
121 * MUSUK 4 0 0 0 0 0 1 1 0
122 * USK 5 0 0 1 0 0 0 - 0
123 * - 6 - - - - - - - -
124 * UUSK 7 0 0 0 0 0 0 0 0
125 */
126 int32_t adetlb_mask;
127
128 switch (mmu_idx) {
129 case 3 /* ERL */:
130 /* If EU is set, always unmapped */
131 if (eu) {
132 return 0;
133 }
134 /* fall through */
135 case MIPS_HFLAG_KM:
136 /* Never AdE, TLB mapped if AM={1,2,3} */
137 adetlb_mask = 0x70000000;
138 goto check_tlb;
139
140 case MIPS_HFLAG_SM:
141 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
142 adetlb_mask = 0xc0380000;
143 goto check_ade;
144
145 case MIPS_HFLAG_UM:
146 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
147 adetlb_mask = 0xe4180000;
148 /* fall through */
149 check_ade:
150 /* does this AM cause AdE in current execution mode */
151 if ((adetlb_mask << am) < 0) {
152 return TLBRET_BADADDR;
153 }
154 adetlb_mask <<= 8;
155 /* fall through */
156 check_tlb:
157 /* is this AM mapped in current execution mode */
158 return ((adetlb_mask << am) < 0);
159 default:
160 assert(0);
161 return TLBRET_BADADDR;
162 };
163 }
164
165 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
166 int *prot, target_ulong real_address,
167 int rw, int access_type, int mmu_idx,
168 unsigned int am, bool eu,
169 target_ulong segmask,
170 hwaddr physical_base)
171 {
172 int mapped = is_seg_am_mapped(am, eu, mmu_idx);
173
174 if (mapped < 0) {
175 /* is_seg_am_mapped can report TLBRET_BADADDR */
176 return mapped;
177 } else if (mapped) {
178 /* The segment is TLB mapped */
179 return env->tlb->map_address(env, physical, prot, real_address, rw,
180 access_type);
181 } else {
182 /* The segment is unmapped */
183 *physical = physical_base | (real_address & segmask);
184 *prot = PAGE_READ | PAGE_WRITE;
185 return TLBRET_MATCH;
186 }
187 }
188
189 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
190 int *prot, target_ulong real_address,
191 int rw, int access_type, int mmu_idx,
192 uint16_t segctl, target_ulong segmask)
193 {
194 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
195 bool eu = (segctl >> CP0SC_EU) & 1;
196 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
197
198 return get_seg_physical_address(env, physical, prot, real_address, rw,
199 access_type, mmu_idx, am, eu, segmask,
200 pa & ~(hwaddr)segmask);
201 }
202
203 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
204 int *prot, target_ulong real_address,
205 int rw, int access_type, int mmu_idx)
206 {
207 /* User mode can only access useg/xuseg */
208 #if defined(TARGET_MIPS64)
209 int user_mode = mmu_idx == MIPS_HFLAG_UM;
210 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
211 int kernel_mode = !user_mode && !supervisor_mode;
212 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
213 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
214 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
215 #endif
216 int ret = TLBRET_MATCH;
217 /* effective address (modified for KVM T&E kernel segments) */
218 target_ulong address = real_address;
219
220 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
221 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
222 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
223 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
224 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
225
226 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
227 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
228
229 if (mips_um_ksegs_enabled()) {
230 /* KVM T&E adds guest kernel segments in useg */
231 if (real_address >= KVM_KSEG0_BASE) {
232 if (real_address < KVM_KSEG2_BASE) {
233 /* kseg0 */
234 address += KSEG0_BASE - KVM_KSEG0_BASE;
235 } else if (real_address <= USEG_LIMIT) {
236 /* kseg2/3 */
237 address += KSEG2_BASE - KVM_KSEG2_BASE;
238 }
239 }
240 }
241
242 if (address <= USEG_LIMIT) {
243 /* useg */
244 uint16_t segctl;
245
246 if (address >= 0x40000000UL) {
247 segctl = env->CP0_SegCtl2;
248 } else {
249 segctl = env->CP0_SegCtl2 >> 16;
250 }
251 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
252 access_type, mmu_idx, segctl,
253 0x3FFFFFFF);
254 #if defined(TARGET_MIPS64)
255 } else if (address < 0x4000000000000000ULL) {
256 /* xuseg */
257 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
258 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
259 } else {
260 ret = TLBRET_BADADDR;
261 }
262 } else if (address < 0x8000000000000000ULL) {
263 /* xsseg */
264 if ((supervisor_mode || kernel_mode) &&
265 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
266 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
267 } else {
268 ret = TLBRET_BADADDR;
269 }
270 } else if (address < 0xC000000000000000ULL) {
271 /* xkphys */
272 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
273 /* KX/SX/UX bit to check for each xkphys EVA access mode */
274 static const uint8_t am_ksux[8] = {
275 [CP0SC_AM_UK] = (1u << CP0St_KX),
276 [CP0SC_AM_MK] = (1u << CP0St_KX),
277 [CP0SC_AM_MSK] = (1u << CP0St_SX),
278 [CP0SC_AM_MUSK] = (1u << CP0St_UX),
279 [CP0SC_AM_MUSUK] = (1u << CP0St_UX),
280 [CP0SC_AM_USK] = (1u << CP0St_SX),
281 [6] = (1u << CP0St_KX),
282 [CP0SC_AM_UUSK] = (1u << CP0St_UX),
283 };
284 unsigned int am = CP0SC_AM_UK;
285 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
286
287 if (xr & (1 << ((address >> 59) & 0x7))) {
288 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
289 }
290 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */
291 if (env->CP0_Status & am_ksux[am]) {
292 ret = get_seg_physical_address(env, physical, prot,
293 real_address, rw, access_type,
294 mmu_idx, am, false, env->PAMask,
295 0);
296 } else {
297 ret = TLBRET_BADADDR;
298 }
299 } else {
300 ret = TLBRET_BADADDR;
301 }
302 } else if (address < 0xFFFFFFFF80000000ULL) {
303 /* xkseg */
304 if (kernel_mode && KX &&
305 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
306 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
307 } else {
308 ret = TLBRET_BADADDR;
309 }
310 #endif
311 } else if (address < KSEG1_BASE) {
312 /* kseg0 */
313 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
314 access_type, mmu_idx,
315 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
316 } else if (address < KSEG2_BASE) {
317 /* kseg1 */
318 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
319 access_type, mmu_idx,
320 env->CP0_SegCtl1, 0x1FFFFFFF);
321 } else if (address < KSEG3_BASE) {
322 /* sseg (kseg2) */
323 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
324 access_type, mmu_idx,
325 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
326 } else {
327 /* kseg3 */
328 /* XXX: debug segment is not emulated */
329 ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
330 access_type, mmu_idx,
331 env->CP0_SegCtl0, 0x1FFFFFFF);
332 }
333 return ret;
334 }
335
336 void cpu_mips_tlb_flush(CPUMIPSState *env)
337 {
338 MIPSCPU *cpu = mips_env_get_cpu(env);
339
340 /* Flush qemu's TLB and discard all shadowed entries. */
341 tlb_flush(CPU(cpu));
342 env->tlb->tlb_in_use = env->tlb->nb_tlb;
343 }
344
345 /* Called for updates to CP0_Status. */
346 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
347 {
348 int32_t tcstatus, *tcst;
349 uint32_t v = cpu->CP0_Status;
350 uint32_t cu, mx, asid, ksu;
351 uint32_t mask = ((1 << CP0TCSt_TCU3)
352 | (1 << CP0TCSt_TCU2)
353 | (1 << CP0TCSt_TCU1)
354 | (1 << CP0TCSt_TCU0)
355 | (1 << CP0TCSt_TMX)
356 | (3 << CP0TCSt_TKSU)
357 | (0xff << CP0TCSt_TASID));
358
359 cu = (v >> CP0St_CU0) & 0xf;
360 mx = (v >> CP0St_MX) & 0x1;
361 ksu = (v >> CP0St_KSU) & 0x3;
362 asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
363
364 tcstatus = cu << CP0TCSt_TCU0;
365 tcstatus |= mx << CP0TCSt_TMX;
366 tcstatus |= ksu << CP0TCSt_TKSU;
367 tcstatus |= asid;
368
369 if (tc == cpu->current_tc) {
370 tcst = &cpu->active_tc.CP0_TCStatus;
371 } else {
372 tcst = &cpu->tcs[tc].CP0_TCStatus;
373 }
374
375 *tcst &= ~mask;
376 *tcst |= tcstatus;
377 compute_hflags(cpu);
378 }
379
380 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
381 {
382 uint32_t mask = env->CP0_Status_rw_bitmask;
383 target_ulong old = env->CP0_Status;
384
385 if (env->insn_flags & ISA_MIPS32R6) {
386 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
387 #if defined(TARGET_MIPS64)
388 uint32_t ksux = (1 << CP0St_KX) & val;
389 ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
390 ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
391 val = (val & ~(7 << CP0St_UX)) | ksux;
392 #endif
393 if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
394 mask &= ~(3 << CP0St_KSU);
395 }
396 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
397 }
398
399 env->CP0_Status = (old & ~mask) | (val & mask);
400 #if defined(TARGET_MIPS64)
401 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
402 /* Access to at least one of the 64-bit segments has been disabled */
403 tlb_flush(CPU(mips_env_get_cpu(env)));
404 }
405 #endif
406 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
407 sync_c0_status(env, env, env->current_tc);
408 } else {
409 compute_hflags(env);
410 }
411 }
412
413 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
414 {
415 uint32_t mask = 0x00C00300;
416 uint32_t old = env->CP0_Cause;
417 int i;
418
419 if (env->insn_flags & ISA_MIPS32R2) {
420 mask |= 1 << CP0Ca_DC;
421 }
422 if (env->insn_flags & ISA_MIPS32R6) {
423 mask &= ~((1 << CP0Ca_WP) & val);
424 }
425
426 env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
427
428 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
429 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
430 cpu_mips_stop_count(env);
431 } else {
432 cpu_mips_start_count(env);
433 }
434 }
435
436 /* Set/reset software interrupts */
437 for (i = 0 ; i < 2 ; i++) {
438 if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
439 cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
440 }
441 }
442 }
443 #endif
444
445 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
446 int rw, int tlb_error)
447 {
448 CPUState *cs = CPU(mips_env_get_cpu(env));
449 int exception = 0, error_code = 0;
450
451 if (rw == MMU_INST_FETCH) {
452 error_code |= EXCP_INST_NOTAVAIL;
453 }
454
455 switch (tlb_error) {
456 default:
457 case TLBRET_BADADDR:
458 /* Reference to kernel address from user mode or supervisor mode */
459 /* Reference to supervisor address from user mode */
460 if (rw == MMU_DATA_STORE) {
461 exception = EXCP_AdES;
462 } else {
463 exception = EXCP_AdEL;
464 }
465 break;
466 case TLBRET_NOMATCH:
467 /* No TLB match for a mapped address */
468 if (rw == MMU_DATA_STORE) {
469 exception = EXCP_TLBS;
470 } else {
471 exception = EXCP_TLBL;
472 }
473 error_code |= EXCP_TLB_NOMATCH;
474 break;
475 case TLBRET_INVALID:
476 /* TLB match with no valid bit */
477 if (rw == MMU_DATA_STORE) {
478 exception = EXCP_TLBS;
479 } else {
480 exception = EXCP_TLBL;
481 }
482 break;
483 case TLBRET_DIRTY:
484 /* TLB match but 'D' bit is cleared */
485 exception = EXCP_LTLBL;
486 break;
487 case TLBRET_XI:
488 /* Execute-Inhibit Exception */
489 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
490 exception = EXCP_TLBXI;
491 } else {
492 exception = EXCP_TLBL;
493 }
494 break;
495 case TLBRET_RI:
496 /* Read-Inhibit Exception */
497 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
498 exception = EXCP_TLBRI;
499 } else {
500 exception = EXCP_TLBL;
501 }
502 break;
503 }
504 /* Raise exception */
505 env->CP0_BadVAddr = address;
506 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
507 ((address >> 9) & 0x007ffff0);
508 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
509 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
510 (address & (TARGET_PAGE_MASK << 1));
511 #if defined(TARGET_MIPS64)
512 env->CP0_EntryHi &= env->SEGMask;
513 env->CP0_XContext =
514 /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
515 /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
516 /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
517 #endif
518 cs->exception_index = exception;
519 env->error_code = error_code;
520 }
521
522 #if !defined(CONFIG_USER_ONLY)
523 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
524 {
525 MIPSCPU *cpu = MIPS_CPU(cs);
526 CPUMIPSState *env = &cpu->env;
527 hwaddr phys_addr;
528 int prot;
529
530 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT,
531 cpu_mmu_index(env, false)) != 0) {
532 return -1;
533 }
534 return phys_addr;
535 }
536 #endif
537
538 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
539 int mmu_idx)
540 {
541 MIPSCPU *cpu = MIPS_CPU(cs);
542 CPUMIPSState *env = &cpu->env;
543 #if !defined(CONFIG_USER_ONLY)
544 hwaddr physical;
545 int prot;
546 int access_type;
547 #endif
548 int ret = 0;
549
550 #if 0
551 log_cpu_state(cs, 0);
552 #endif
553 qemu_log_mask(CPU_LOG_MMU,
554 "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
555 __func__, env->active_tc.PC, address, rw, mmu_idx);
556
557 /* data access */
558 #if !defined(CONFIG_USER_ONLY)
559 /* XXX: put correct access by using cpu_restore_state()
560 correctly */
561 access_type = ACCESS_INT;
562 ret = get_physical_address(env, &physical, &prot,
563 address, rw, access_type, mmu_idx);
564 switch (ret) {
565 case TLBRET_MATCH:
566 qemu_log_mask(CPU_LOG_MMU,
567 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
568 " prot %d\n", __func__, address, physical, prot);
569 break;
570 default:
571 qemu_log_mask(CPU_LOG_MMU,
572 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
573 ret);
574 break;
575 }
576 if (ret == TLBRET_MATCH) {
577 tlb_set_page(cs, address & TARGET_PAGE_MASK,
578 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
579 mmu_idx, TARGET_PAGE_SIZE);
580 ret = 0;
581 } else if (ret < 0)
582 #endif
583 {
584 raise_mmu_exception(env, address, rw, ret);
585 ret = 1;
586 }
587
588 return ret;
589 }
590
591 #if !defined(CONFIG_USER_ONLY)
592 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
593 {
594 hwaddr physical;
595 int prot;
596 int access_type;
597 int ret = 0;
598
599 /* data access */
600 access_type = ACCESS_INT;
601 ret = get_physical_address(env, &physical, &prot, address, rw, access_type,
602 cpu_mmu_index(env, false));
603 if (ret != TLBRET_MATCH) {
604 raise_mmu_exception(env, address, rw, ret);
605 return -1LL;
606 } else {
607 return physical;
608 }
609 }
610
611 static const char * const excp_names[EXCP_LAST + 1] = {
612 [EXCP_RESET] = "reset",
613 [EXCP_SRESET] = "soft reset",
614 [EXCP_DSS] = "debug single step",
615 [EXCP_DINT] = "debug interrupt",
616 [EXCP_NMI] = "non-maskable interrupt",
617 [EXCP_MCHECK] = "machine check",
618 [EXCP_EXT_INTERRUPT] = "interrupt",
619 [EXCP_DFWATCH] = "deferred watchpoint",
620 [EXCP_DIB] = "debug instruction breakpoint",
621 [EXCP_IWATCH] = "instruction fetch watchpoint",
622 [EXCP_AdEL] = "address error load",
623 [EXCP_AdES] = "address error store",
624 [EXCP_TLBF] = "TLB refill",
625 [EXCP_IBE] = "instruction bus error",
626 [EXCP_DBp] = "debug breakpoint",
627 [EXCP_SYSCALL] = "syscall",
628 [EXCP_BREAK] = "break",
629 [EXCP_CpU] = "coprocessor unusable",
630 [EXCP_RI] = "reserved instruction",
631 [EXCP_OVERFLOW] = "arithmetic overflow",
632 [EXCP_TRAP] = "trap",
633 [EXCP_FPE] = "floating point",
634 [EXCP_DDBS] = "debug data break store",
635 [EXCP_DWATCH] = "data watchpoint",
636 [EXCP_LTLBL] = "TLB modify",
637 [EXCP_TLBL] = "TLB load",
638 [EXCP_TLBS] = "TLB store",
639 [EXCP_DBE] = "data bus error",
640 [EXCP_DDBL] = "debug data break load",
641 [EXCP_THREAD] = "thread",
642 [EXCP_MDMX] = "MDMX",
643 [EXCP_C2E] = "precise coprocessor 2",
644 [EXCP_CACHE] = "cache error",
645 [EXCP_TLBXI] = "TLB execute-inhibit",
646 [EXCP_TLBRI] = "TLB read-inhibit",
647 [EXCP_MSADIS] = "MSA disabled",
648 [EXCP_MSAFPE] = "MSA floating point",
649 };
650 #endif
651
652 target_ulong exception_resume_pc (CPUMIPSState *env)
653 {
654 target_ulong bad_pc;
655 target_ulong isa_mode;
656
657 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
658 bad_pc = env->active_tc.PC | isa_mode;
659 if (env->hflags & MIPS_HFLAG_BMASK) {
660 /* If the exception was raised from a delay slot, come back to
661 the jump. */
662 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
663 }
664
665 return bad_pc;
666 }
667
668 #if !defined(CONFIG_USER_ONLY)
669 static void set_hflags_for_handler (CPUMIPSState *env)
670 {
671 /* Exception handlers are entered in 32-bit mode. */
672 env->hflags &= ~(MIPS_HFLAG_M16);
673 /* ...except that microMIPS lets you choose. */
674 if (env->insn_flags & ASE_MICROMIPS) {
675 env->hflags |= (!!(env->CP0_Config3
676 & (1 << CP0C3_ISA_ON_EXC))
677 << MIPS_HFLAG_M16_SHIFT);
678 }
679 }
680
681 static inline void set_badinstr_registers(CPUMIPSState *env)
682 {
683 if (env->hflags & MIPS_HFLAG_M16) {
684 /* TODO: add BadInstr support for microMIPS */
685 return;
686 }
687 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
688 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
689 }
690 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
691 (env->hflags & MIPS_HFLAG_BMASK)) {
692 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
693 }
694 }
695 #endif
696
697 void mips_cpu_do_interrupt(CPUState *cs)
698 {
699 #if !defined(CONFIG_USER_ONLY)
700 MIPSCPU *cpu = MIPS_CPU(cs);
701 CPUMIPSState *env = &cpu->env;
702 bool update_badinstr = 0;
703 target_ulong offset;
704 int cause = -1;
705 const char *name;
706
707 if (qemu_loglevel_mask(CPU_LOG_INT)
708 && cs->exception_index != EXCP_EXT_INTERRUPT) {
709 if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
710 name = "unknown";
711 } else {
712 name = excp_names[cs->exception_index];
713 }
714
715 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
716 " %s exception\n",
717 __func__, env->active_tc.PC, env->CP0_EPC, name);
718 }
719 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
720 (env->hflags & MIPS_HFLAG_DM)) {
721 cs->exception_index = EXCP_DINT;
722 }
723 offset = 0x180;
724 switch (cs->exception_index) {
725 case EXCP_DSS:
726 env->CP0_Debug |= 1 << CP0DB_DSS;
727 /* Debug single step cannot be raised inside a delay slot and
728 resume will always occur on the next instruction
729 (but we assume the pc has always been updated during
730 code translation). */
731 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
732 goto enter_debug_mode;
733 case EXCP_DINT:
734 env->CP0_Debug |= 1 << CP0DB_DINT;
735 goto set_DEPC;
736 case EXCP_DIB:
737 env->CP0_Debug |= 1 << CP0DB_DIB;
738 goto set_DEPC;
739 case EXCP_DBp:
740 env->CP0_Debug |= 1 << CP0DB_DBp;
741 /* Setup DExcCode - SDBBP instruction */
742 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
743 goto set_DEPC;
744 case EXCP_DDBS:
745 env->CP0_Debug |= 1 << CP0DB_DDBS;
746 goto set_DEPC;
747 case EXCP_DDBL:
748 env->CP0_Debug |= 1 << CP0DB_DDBL;
749 set_DEPC:
750 env->CP0_DEPC = exception_resume_pc(env);
751 env->hflags &= ~MIPS_HFLAG_BMASK;
752 enter_debug_mode:
753 if (env->insn_flags & ISA_MIPS3) {
754 env->hflags |= MIPS_HFLAG_64;
755 if (!(env->insn_flags & ISA_MIPS64R6) ||
756 env->CP0_Status & (1 << CP0St_KX)) {
757 env->hflags &= ~MIPS_HFLAG_AWRAP;
758 }
759 }
760 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
761 env->hflags &= ~(MIPS_HFLAG_KSU);
762 /* EJTAG probe trap enable is not implemented... */
763 if (!(env->CP0_Status & (1 << CP0St_EXL)))
764 env->CP0_Cause &= ~(1U << CP0Ca_BD);
765 env->active_tc.PC = env->exception_base + 0x480;
766 set_hflags_for_handler(env);
767 break;
768 case EXCP_RESET:
769 cpu_reset(CPU(cpu));
770 break;
771 case EXCP_SRESET:
772 env->CP0_Status |= (1 << CP0St_SR);
773 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
774 goto set_error_EPC;
775 case EXCP_NMI:
776 env->CP0_Status |= (1 << CP0St_NMI);
777 set_error_EPC:
778 env->CP0_ErrorEPC = exception_resume_pc(env);
779 env->hflags &= ~MIPS_HFLAG_BMASK;
780 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
781 if (env->insn_flags & ISA_MIPS3) {
782 env->hflags |= MIPS_HFLAG_64;
783 if (!(env->insn_flags & ISA_MIPS64R6) ||
784 env->CP0_Status & (1 << CP0St_KX)) {
785 env->hflags &= ~MIPS_HFLAG_AWRAP;
786 }
787 }
788 env->hflags |= MIPS_HFLAG_CP0;
789 env->hflags &= ~(MIPS_HFLAG_KSU);
790 if (!(env->CP0_Status & (1 << CP0St_EXL)))
791 env->CP0_Cause &= ~(1U << CP0Ca_BD);
792 env->active_tc.PC = env->exception_base;
793 set_hflags_for_handler(env);
794 break;
795 case EXCP_EXT_INTERRUPT:
796 cause = 0;
797 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
798 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
799
800 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
801 offset = 0x200;
802 } else {
803 uint32_t vector = 0;
804 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
805
806 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
807 /* For VEIC mode, the external interrupt controller feeds
808 * the vector through the CP0Cause IP lines. */
809 vector = pending;
810 } else {
811 /* Vectored Interrupts
812 * Mask with Status.IM7-IM0 to get enabled interrupts. */
813 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
814 /* Find the highest-priority interrupt. */
815 while (pending >>= 1) {
816 vector++;
817 }
818 }
819 offset = 0x200 + (vector * (spacing << 5));
820 }
821 }
822 goto set_EPC;
823 case EXCP_LTLBL:
824 cause = 1;
825 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
826 goto set_EPC;
827 case EXCP_TLBL:
828 cause = 2;
829 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
830 if ((env->error_code & EXCP_TLB_NOMATCH) &&
831 !(env->CP0_Status & (1 << CP0St_EXL))) {
832 #if defined(TARGET_MIPS64)
833 int R = env->CP0_BadVAddr >> 62;
834 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
835 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
836
837 if ((R != 0 || UX) && (R != 3 || KX) &&
838 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
839 offset = 0x080;
840 } else {
841 #endif
842 offset = 0x000;
843 #if defined(TARGET_MIPS64)
844 }
845 #endif
846 }
847 goto set_EPC;
848 case EXCP_TLBS:
849 cause = 3;
850 update_badinstr = 1;
851 if ((env->error_code & EXCP_TLB_NOMATCH) &&
852 !(env->CP0_Status & (1 << CP0St_EXL))) {
853 #if defined(TARGET_MIPS64)
854 int R = env->CP0_BadVAddr >> 62;
855 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
856 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
857
858 if ((R != 0 || UX) && (R != 3 || KX) &&
859 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) {
860 offset = 0x080;
861 } else {
862 #endif
863 offset = 0x000;
864 #if defined(TARGET_MIPS64)
865 }
866 #endif
867 }
868 goto set_EPC;
869 case EXCP_AdEL:
870 cause = 4;
871 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
872 goto set_EPC;
873 case EXCP_AdES:
874 cause = 5;
875 update_badinstr = 1;
876 goto set_EPC;
877 case EXCP_IBE:
878 cause = 6;
879 goto set_EPC;
880 case EXCP_DBE:
881 cause = 7;
882 goto set_EPC;
883 case EXCP_SYSCALL:
884 cause = 8;
885 update_badinstr = 1;
886 goto set_EPC;
887 case EXCP_BREAK:
888 cause = 9;
889 update_badinstr = 1;
890 goto set_EPC;
891 case EXCP_RI:
892 cause = 10;
893 update_badinstr = 1;
894 goto set_EPC;
895 case EXCP_CpU:
896 cause = 11;
897 update_badinstr = 1;
898 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
899 (env->error_code << CP0Ca_CE);
900 goto set_EPC;
901 case EXCP_OVERFLOW:
902 cause = 12;
903 update_badinstr = 1;
904 goto set_EPC;
905 case EXCP_TRAP:
906 cause = 13;
907 update_badinstr = 1;
908 goto set_EPC;
909 case EXCP_MSAFPE:
910 cause = 14;
911 update_badinstr = 1;
912 goto set_EPC;
913 case EXCP_FPE:
914 cause = 15;
915 update_badinstr = 1;
916 goto set_EPC;
917 case EXCP_C2E:
918 cause = 18;
919 goto set_EPC;
920 case EXCP_TLBRI:
921 cause = 19;
922 update_badinstr = 1;
923 goto set_EPC;
924 case EXCP_TLBXI:
925 cause = 20;
926 goto set_EPC;
927 case EXCP_MSADIS:
928 cause = 21;
929 update_badinstr = 1;
930 goto set_EPC;
931 case EXCP_MDMX:
932 cause = 22;
933 goto set_EPC;
934 case EXCP_DWATCH:
935 cause = 23;
936 /* XXX: TODO: manage deferred watch exceptions */
937 goto set_EPC;
938 case EXCP_MCHECK:
939 cause = 24;
940 goto set_EPC;
941 case EXCP_THREAD:
942 cause = 25;
943 goto set_EPC;
944 case EXCP_DSPDIS:
945 cause = 26;
946 goto set_EPC;
947 case EXCP_CACHE:
948 cause = 30;
949 offset = 0x100;
950 set_EPC:
951 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
952 env->CP0_EPC = exception_resume_pc(env);
953 if (update_badinstr) {
954 set_badinstr_registers(env);
955 }
956 if (env->hflags & MIPS_HFLAG_BMASK) {
957 env->CP0_Cause |= (1U << CP0Ca_BD);
958 } else {
959 env->CP0_Cause &= ~(1U << CP0Ca_BD);
960 }
961 env->CP0_Status |= (1 << CP0St_EXL);
962 if (env->insn_flags & ISA_MIPS3) {
963 env->hflags |= MIPS_HFLAG_64;
964 if (!(env->insn_flags & ISA_MIPS64R6) ||
965 env->CP0_Status & (1 << CP0St_KX)) {
966 env->hflags &= ~MIPS_HFLAG_AWRAP;
967 }
968 }
969 env->hflags |= MIPS_HFLAG_CP0;
970 env->hflags &= ~(MIPS_HFLAG_KSU);
971 }
972 env->hflags &= ~MIPS_HFLAG_BMASK;
973 if (env->CP0_Status & (1 << CP0St_BEV)) {
974 env->active_tc.PC = env->exception_base + 0x200;
975 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
976 env->CP0_Config5 & (1 << CP0C5_CV))) {
977 /* Force KSeg1 for cache errors */
978 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
979 } else {
980 env->active_tc.PC = env->CP0_EBase & ~0xfff;
981 }
982
983 env->active_tc.PC += offset;
984 set_hflags_for_handler(env);
985 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
986 break;
987 default:
988 abort();
989 }
990 if (qemu_loglevel_mask(CPU_LOG_INT)
991 && cs->exception_index != EXCP_EXT_INTERRUPT) {
992 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
993 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
994 __func__, env->active_tc.PC, env->CP0_EPC, cause,
995 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
996 env->CP0_DEPC);
997 }
998 #endif
999 cs->exception_index = EXCP_NONE;
1000 }
1001
1002 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
1003 {
1004 if (interrupt_request & CPU_INTERRUPT_HARD) {
1005 MIPSCPU *cpu = MIPS_CPU(cs);
1006 CPUMIPSState *env = &cpu->env;
1007
1008 if (cpu_mips_hw_interrupts_enabled(env) &&
1009 cpu_mips_hw_interrupts_pending(env)) {
1010 /* Raise it */
1011 cs->exception_index = EXCP_EXT_INTERRUPT;
1012 env->error_code = 0;
1013 mips_cpu_do_interrupt(cs);
1014 return true;
1015 }
1016 }
1017 return false;
1018 }
1019
1020 #if !defined(CONFIG_USER_ONLY)
1021 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
1022 {
1023 MIPSCPU *cpu = mips_env_get_cpu(env);
1024 CPUState *cs;
1025 r4k_tlb_t *tlb;
1026 target_ulong addr;
1027 target_ulong end;
1028 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
1029 target_ulong mask;
1030
1031 tlb = &env->tlb->mmu.r4k.tlb[idx];
1032 /* The qemu TLB is flushed when the ASID changes, so no need to
1033 flush these entries again. */
1034 if (tlb->G == 0 && tlb->ASID != ASID) {
1035 return;
1036 }
1037
1038 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
1039 /* For tlbwr, we can shadow the discarded entry into
1040 a new (fake) TLB entry, as long as the guest can not
1041 tell that it's there. */
1042 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
1043 env->tlb->tlb_in_use++;
1044 return;
1045 }
1046
1047 /* 1k pages are not supported. */
1048 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1049 if (tlb->V0) {
1050 cs = CPU(cpu);
1051 addr = tlb->VPN & ~mask;
1052 #if defined(TARGET_MIPS64)
1053 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1054 addr |= 0x3FFFFF0000000000ULL;
1055 }
1056 #endif
1057 end = addr | (mask >> 1);
1058 while (addr < end) {
1059 tlb_flush_page(cs, addr);
1060 addr += TARGET_PAGE_SIZE;
1061 }
1062 }
1063 if (tlb->V1) {
1064 cs = CPU(cpu);
1065 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1066 #if defined(TARGET_MIPS64)
1067 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1068 addr |= 0x3FFFFF0000000000ULL;
1069 }
1070 #endif
1071 end = addr | mask;
1072 while (addr - 1 < end) {
1073 tlb_flush_page(cs, addr);
1074 addr += TARGET_PAGE_SIZE;
1075 }
1076 }
1077 }
1078 #endif
1079
1080 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
1081 uint32_t exception,
1082 int error_code,
1083 uintptr_t pc)
1084 {
1085 CPUState *cs = CPU(mips_env_get_cpu(env));
1086
1087 if (exception < EXCP_SC) {
1088 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
1089 __func__, exception, error_code);
1090 }
1091 cs->exception_index = exception;
1092 env->error_code = error_code;
1093
1094 cpu_loop_exit_restore(cs, pc);
1095 }
AR7 emulation for QEMU