?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-lm32: make cpu-qom.h not target specific
[qemu/ar7.git] / target-m68k / translate.c
blobe46356e44c78475728a6f0f7b04458d8e7dfa923
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu/log.h"
26 #include "exec/cpu_ldst.h"
27
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
30
31 #include "trace-tcg.h"
32 #include "exec/log.h"
33
34
35 //#define DEBUG_DISPATCH 1
36
37 /* Fake floating point. */
38 #define tcg_gen_mov_f64 tcg_gen_mov_i64
39 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
40 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
41
42 #define DEFO32(name, offset) static TCGv QREG_##name;
43 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
44 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
45 #include "qregs.def"
46 #undef DEFO32
47 #undef DEFO64
48 #undef DEFF64
49
50 static TCGv_i32 cpu_halted;
51 static TCGv_i32 cpu_exception_index;
52
53 static TCGv_env cpu_env;
54
55 static char cpu_reg_names[3*8*3 + 5*4];
56 static TCGv cpu_dregs[8];
57 static TCGv cpu_aregs[8];
58 static TCGv_i64 cpu_fregs[8];
59 static TCGv_i64 cpu_macc[4];
60
61 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
62 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
63 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
64 #define MACREG(acc) cpu_macc[acc]
65 #define QREG_SP cpu_aregs[7]
66
67 static TCGv NULL_QREG;
68 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
69 /* Used to distinguish stores from bad addressing modes. */
70 static TCGv store_dummy;
71
72 #include "exec/gen-icount.h"
73
74 void m68k_tcg_init(void)
75 {
76 char *p;
77 int i;
78
79 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
80
81 #define DEFO32(name, offset) \
82 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
83 offsetof(CPUM68KState, offset), #name);
84 #define DEFO64(name, offset) \
85 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFF64(name, offset) DEFO64(name, offset)
88 #include "qregs.def"
89 #undef DEFO32
90 #undef DEFO64
91 #undef DEFF64
92
93 cpu_halted = tcg_global_mem_new_i32(cpu_env,
94 -offsetof(M68kCPU, env) +
95 offsetof(CPUState, halted), "HALTED");
96 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
97 -offsetof(M68kCPU, env) +
98 offsetof(CPUState, exception_index),
99 "EXCEPTION");
100
101 p = cpu_reg_names;
102 for (i = 0; i < 8; i++) {
103 sprintf(p, "D%d", i);
104 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
105 offsetof(CPUM68KState, dregs[i]), p);
106 p += 3;
107 sprintf(p, "A%d", i);
108 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
109 offsetof(CPUM68KState, aregs[i]), p);
110 p += 3;
111 sprintf(p, "F%d", i);
112 cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env,
113 offsetof(CPUM68KState, fregs[i]), p);
114 p += 3;
115 }
116 for (i = 0; i < 4; i++) {
117 sprintf(p, "ACC%d", i);
118 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
119 offsetof(CPUM68KState, macc[i]), p);
120 p += 5;
121 }
122
123 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
124 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
125 }
126
127 /* internal defines */
128 typedef struct DisasContext {
129 CPUM68KState *env;
130 target_ulong insn_pc; /* Start of the current instruction. */
131 target_ulong pc;
132 int is_jmp;
133 int cc_op;
134 int user;
135 uint32_t fpcr;
136 struct TranslationBlock *tb;
137 int singlestep_enabled;
138 TCGv_i64 mactmp;
139 int done_mac;
140 } DisasContext;
141
142 #define DISAS_JUMP_NEXT 4
143
144 #if defined(CONFIG_USER_ONLY)
145 #define IS_USER(s) 1
146 #else
147 #define IS_USER(s) s->user
148 #endif
149
150 /* XXX: move that elsewhere */
151 /* ??? Fix exceptions. */
152 static void *gen_throws_exception;
153 #define gen_last_qop NULL
154
155 #define OS_BYTE 0
156 #define OS_WORD 1
157 #define OS_LONG 2
158 #define OS_SINGLE 4
159 #define OS_DOUBLE 5
160
161 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
162
163 #ifdef DEBUG_DISPATCH
164 #define DISAS_INSN(name) \
165 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
166 uint16_t insn); \
167 static void disas_##name(CPUM68KState *env, DisasContext *s, \
168 uint16_t insn) \
169 { \
170 qemu_log("Dispatch " #name "\n"); \
171 real_disas_##name(s, env, insn); \
172 } \
173 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
174 uint16_t insn)
175 #else
176 #define DISAS_INSN(name) \
177 static void disas_##name(CPUM68KState *env, DisasContext *s, \
178 uint16_t insn)
179 #endif
180
181 /* Generate a load from the specified address. Narrow values are
182 sign extended to full register width. */
183 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
184 {
185 TCGv tmp;
186 int index = IS_USER(s);
187 tmp = tcg_temp_new_i32();
188 switch(opsize) {
189 case OS_BYTE:
190 if (sign)
191 tcg_gen_qemu_ld8s(tmp, addr, index);
192 else
193 tcg_gen_qemu_ld8u(tmp, addr, index);
194 break;
195 case OS_WORD:
196 if (sign)
197 tcg_gen_qemu_ld16s(tmp, addr, index);
198 else
199 tcg_gen_qemu_ld16u(tmp, addr, index);
200 break;
201 case OS_LONG:
202 case OS_SINGLE:
203 tcg_gen_qemu_ld32u(tmp, addr, index);
204 break;
205 default:
206 g_assert_not_reached();
207 }
208 gen_throws_exception = gen_last_qop;
209 return tmp;
210 }
211
212 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
213 {
214 TCGv_i64 tmp;
215 int index = IS_USER(s);
216 tmp = tcg_temp_new_i64();
217 tcg_gen_qemu_ldf64(tmp, addr, index);
218 gen_throws_exception = gen_last_qop;
219 return tmp;
220 }
221
222 /* Generate a store. */
223 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
224 {
225 int index = IS_USER(s);
226 switch(opsize) {
227 case OS_BYTE:
228 tcg_gen_qemu_st8(val, addr, index);
229 break;
230 case OS_WORD:
231 tcg_gen_qemu_st16(val, addr, index);
232 break;
233 case OS_LONG:
234 case OS_SINGLE:
235 tcg_gen_qemu_st32(val, addr, index);
236 break;
237 default:
238 g_assert_not_reached();
239 }
240 gen_throws_exception = gen_last_qop;
241 }
242
243 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
244 {
245 int index = IS_USER(s);
246 tcg_gen_qemu_stf64(val, addr, index);
247 gen_throws_exception = gen_last_qop;
248 }
249
250 typedef enum {
251 EA_STORE,
252 EA_LOADU,
253 EA_LOADS
254 } ea_what;
255
256 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
257 otherwise generate a store. */
258 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
259 ea_what what)
260 {
261 if (what == EA_STORE) {
262 gen_store(s, opsize, addr, val);
263 return store_dummy;
264 } else {
265 return gen_load(s, opsize, addr, what == EA_LOADS);
266 }
267 }
268
269 /* Read a 32-bit immediate constant. */
270 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
271 {
272 uint32_t im;
273 im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
274 s->pc += 2;
275 im |= cpu_lduw_code(env, s->pc);
276 s->pc += 2;
277 return im;
278 }
279
280 /* Calculate and address index. */
281 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
282 {
283 TCGv add;
284 int scale;
285
286 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
287 if ((ext & 0x800) == 0) {
288 tcg_gen_ext16s_i32(tmp, add);
289 add = tmp;
290 }
291 scale = (ext >> 9) & 3;
292 if (scale != 0) {
293 tcg_gen_shli_i32(tmp, add, scale);
294 add = tmp;
295 }
296 return add;
297 }
298
299 /* Handle a base + index + displacement effective addresss.
300 A NULL_QREG base means pc-relative. */
301 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
302 {
303 uint32_t offset;
304 uint16_t ext;
305 TCGv add;
306 TCGv tmp;
307 uint32_t bd, od;
308
309 offset = s->pc;
310 ext = cpu_lduw_code(env, s->pc);
311 s->pc += 2;
312
313 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
314 return NULL_QREG;
315
316 if (ext & 0x100) {
317 /* full extension word format */
318 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
319 return NULL_QREG;
320
321 if ((ext & 0x30) > 0x10) {
322 /* base displacement */
323 if ((ext & 0x30) == 0x20) {
324 bd = (int16_t)cpu_lduw_code(env, s->pc);
325 s->pc += 2;
326 } else {
327 bd = read_im32(env, s);
328 }
329 } else {
330 bd = 0;
331 }
332 tmp = tcg_temp_new();
333 if ((ext & 0x44) == 0) {
334 /* pre-index */
335 add = gen_addr_index(ext, tmp);
336 } else {
337 add = NULL_QREG;
338 }
339 if ((ext & 0x80) == 0) {
340 /* base not suppressed */
341 if (IS_NULL_QREG(base)) {
342 base = tcg_const_i32(offset + bd);
343 bd = 0;
344 }
345 if (!IS_NULL_QREG(add)) {
346 tcg_gen_add_i32(tmp, add, base);
347 add = tmp;
348 } else {
349 add = base;
350 }
351 }
352 if (!IS_NULL_QREG(add)) {
353 if (bd != 0) {
354 tcg_gen_addi_i32(tmp, add, bd);
355 add = tmp;
356 }
357 } else {
358 add = tcg_const_i32(bd);
359 }
360 if ((ext & 3) != 0) {
361 /* memory indirect */
362 base = gen_load(s, OS_LONG, add, 0);
363 if ((ext & 0x44) == 4) {
364 add = gen_addr_index(ext, tmp);
365 tcg_gen_add_i32(tmp, add, base);
366 add = tmp;
367 } else {
368 add = base;
369 }
370 if ((ext & 3) > 1) {
371 /* outer displacement */
372 if ((ext & 3) == 2) {
373 od = (int16_t)cpu_lduw_code(env, s->pc);
374 s->pc += 2;
375 } else {
376 od = read_im32(env, s);
377 }
378 } else {
379 od = 0;
380 }
381 if (od != 0) {
382 tcg_gen_addi_i32(tmp, add, od);
383 add = tmp;
384 }
385 }
386 } else {
387 /* brief extension word format */
388 tmp = tcg_temp_new();
389 add = gen_addr_index(ext, tmp);
390 if (!IS_NULL_QREG(base)) {
391 tcg_gen_add_i32(tmp, add, base);
392 if ((int8_t)ext)
393 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
394 } else {
395 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
396 }
397 add = tmp;
398 }
399 return add;
400 }
401
402 /* Update the CPU env CC_OP state. */
403 static inline void gen_flush_cc_op(DisasContext *s)
404 {
405 if (s->cc_op != CC_OP_DYNAMIC)
406 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
407 }
408
409 /* Evaluate all the CC flags. */
410 static inline void gen_flush_flags(DisasContext *s)
411 {
412 if (s->cc_op == CC_OP_FLAGS)
413 return;
414 gen_flush_cc_op(s);
415 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
416 s->cc_op = CC_OP_FLAGS;
417 }
418
419 static void gen_logic_cc(DisasContext *s, TCGv val)
420 {
421 tcg_gen_mov_i32(QREG_CC_DEST, val);
422 s->cc_op = CC_OP_LOGIC;
423 }
424
425 static void gen_update_cc_add(TCGv dest, TCGv src)
426 {
427 tcg_gen_mov_i32(QREG_CC_DEST, dest);
428 tcg_gen_mov_i32(QREG_CC_SRC, src);
429 }
430
431 static inline int opsize_bytes(int opsize)
432 {
433 switch (opsize) {
434 case OS_BYTE: return 1;
435 case OS_WORD: return 2;
436 case OS_LONG: return 4;
437 case OS_SINGLE: return 4;
438 case OS_DOUBLE: return 8;
439 default:
440 g_assert_not_reached();
441 }
442 }
443
444 /* Assign value to a register. If the width is less than the register width
445 only the low part of the register is set. */
446 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
447 {
448 TCGv tmp;
449 switch (opsize) {
450 case OS_BYTE:
451 tcg_gen_andi_i32(reg, reg, 0xffffff00);
452 tmp = tcg_temp_new();
453 tcg_gen_ext8u_i32(tmp, val);
454 tcg_gen_or_i32(reg, reg, tmp);
455 break;
456 case OS_WORD:
457 tcg_gen_andi_i32(reg, reg, 0xffff0000);
458 tmp = tcg_temp_new();
459 tcg_gen_ext16u_i32(tmp, val);
460 tcg_gen_or_i32(reg, reg, tmp);
461 break;
462 case OS_LONG:
463 case OS_SINGLE:
464 tcg_gen_mov_i32(reg, val);
465 break;
466 default:
467 g_assert_not_reached();
468 }
469 }
470
471 /* Sign or zero extend a value. */
472 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
473 {
474 TCGv tmp;
475
476 switch (opsize) {
477 case OS_BYTE:
478 tmp = tcg_temp_new();
479 if (sign)
480 tcg_gen_ext8s_i32(tmp, val);
481 else
482 tcg_gen_ext8u_i32(tmp, val);
483 break;
484 case OS_WORD:
485 tmp = tcg_temp_new();
486 if (sign)
487 tcg_gen_ext16s_i32(tmp, val);
488 else
489 tcg_gen_ext16u_i32(tmp, val);
490 break;
491 case OS_LONG:
492 case OS_SINGLE:
493 tmp = val;
494 break;
495 default:
496 g_assert_not_reached();
497 }
498 return tmp;
499 }
500
501 /* Generate code for an "effective address". Does not adjust the base
502 register for autoincrement addressing modes. */
503 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
504 int opsize)
505 {
506 TCGv reg;
507 TCGv tmp;
508 uint16_t ext;
509 uint32_t offset;
510
511 switch ((insn >> 3) & 7) {
512 case 0: /* Data register direct. */
513 case 1: /* Address register direct. */
514 return NULL_QREG;
515 case 2: /* Indirect register */
516 case 3: /* Indirect postincrement. */
517 return AREG(insn, 0);
518 case 4: /* Indirect predecrememnt. */
519 reg = AREG(insn, 0);
520 tmp = tcg_temp_new();
521 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
522 return tmp;
523 case 5: /* Indirect displacement. */
524 reg = AREG(insn, 0);
525 tmp = tcg_temp_new();
526 ext = cpu_lduw_code(env, s->pc);
527 s->pc += 2;
528 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
529 return tmp;
530 case 6: /* Indirect index + displacement. */
531 reg = AREG(insn, 0);
532 return gen_lea_indexed(env, s, reg);
533 case 7: /* Other */
534 switch (insn & 7) {
535 case 0: /* Absolute short. */
536 offset = cpu_ldsw_code(env, s->pc);
537 s->pc += 2;
538 return tcg_const_i32(offset);
539 case 1: /* Absolute long. */
540 offset = read_im32(env, s);
541 return tcg_const_i32(offset);
542 case 2: /* pc displacement */
543 offset = s->pc;
544 offset += cpu_ldsw_code(env, s->pc);
545 s->pc += 2;
546 return tcg_const_i32(offset);
547 case 3: /* pc index+displacement. */
548 return gen_lea_indexed(env, s, NULL_QREG);
549 case 4: /* Immediate. */
550 default:
551 return NULL_QREG;
552 }
553 }
554 /* Should never happen. */
555 return NULL_QREG;
556 }
557
558 /* Helper function for gen_ea. Reuse the computed address between the
559 for read/write operands. */
560 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
561 uint16_t insn, int opsize, TCGv val,
562 TCGv *addrp, ea_what what)
563 {
564 TCGv tmp;
565
566 if (addrp && what == EA_STORE) {
567 tmp = *addrp;
568 } else {
569 tmp = gen_lea(env, s, insn, opsize);
570 if (IS_NULL_QREG(tmp))
571 return tmp;
572 if (addrp)
573 *addrp = tmp;
574 }
575 return gen_ldst(s, opsize, tmp, val, what);
576 }
577
578 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
579 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
580 ADDRP is non-null for readwrite operands. */
581 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
582 int opsize, TCGv val, TCGv *addrp, ea_what what)
583 {
584 TCGv reg;
585 TCGv result;
586 uint32_t offset;
587
588 switch ((insn >> 3) & 7) {
589 case 0: /* Data register direct. */
590 reg = DREG(insn, 0);
591 if (what == EA_STORE) {
592 gen_partset_reg(opsize, reg, val);
593 return store_dummy;
594 } else {
595 return gen_extend(reg, opsize, what == EA_LOADS);
596 }
597 case 1: /* Address register direct. */
598 reg = AREG(insn, 0);
599 if (what == EA_STORE) {
600 tcg_gen_mov_i32(reg, val);
601 return store_dummy;
602 } else {
603 return gen_extend(reg, opsize, what == EA_LOADS);
604 }
605 case 2: /* Indirect register */
606 reg = AREG(insn, 0);
607 return gen_ldst(s, opsize, reg, val, what);
608 case 3: /* Indirect postincrement. */
609 reg = AREG(insn, 0);
610 result = gen_ldst(s, opsize, reg, val, what);
611 /* ??? This is not exception safe. The instruction may still
612 fault after this point. */
613 if (what == EA_STORE || !addrp)
614 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
615 return result;
616 case 4: /* Indirect predecrememnt. */
617 {
618 TCGv tmp;
619 if (addrp && what == EA_STORE) {
620 tmp = *addrp;
621 } else {
622 tmp = gen_lea(env, s, insn, opsize);
623 if (IS_NULL_QREG(tmp))
624 return tmp;
625 if (addrp)
626 *addrp = tmp;
627 }
628 result = gen_ldst(s, opsize, tmp, val, what);
629 /* ??? This is not exception safe. The instruction may still
630 fault after this point. */
631 if (what == EA_STORE || !addrp) {
632 reg = AREG(insn, 0);
633 tcg_gen_mov_i32(reg, tmp);
634 }
635 }
636 return result;
637 case 5: /* Indirect displacement. */
638 case 6: /* Indirect index + displacement. */
639 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
640 case 7: /* Other */
641 switch (insn & 7) {
642 case 0: /* Absolute short. */
643 case 1: /* Absolute long. */
644 case 2: /* pc displacement */
645 case 3: /* pc index+displacement. */
646 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
647 case 4: /* Immediate. */
648 /* Sign extend values for consistency. */
649 switch (opsize) {
650 case OS_BYTE:
651 if (what == EA_LOADS) {
652 offset = cpu_ldsb_code(env, s->pc + 1);
653 } else {
654 offset = cpu_ldub_code(env, s->pc + 1);
655 }
656 s->pc += 2;
657 break;
658 case OS_WORD:
659 if (what == EA_LOADS) {
660 offset = cpu_ldsw_code(env, s->pc);
661 } else {
662 offset = cpu_lduw_code(env, s->pc);
663 }
664 s->pc += 2;
665 break;
666 case OS_LONG:
667 offset = read_im32(env, s);
668 break;
669 default:
670 g_assert_not_reached();
671 }
672 return tcg_const_i32(offset);
673 default:
674 return NULL_QREG;
675 }
676 }
677 /* Should never happen. */
678 return NULL_QREG;
679 }
680
681 /* This generates a conditional branch, clobbering all temporaries. */
682 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
683 {
684 TCGv tmp;
685
686 /* TODO: Optimize compare/branch pairs rather than always flushing
687 flag state to CC_OP_FLAGS. */
688 gen_flush_flags(s);
689 switch (cond) {
690 case 0: /* T */
691 tcg_gen_br(l1);
692 break;
693 case 1: /* F */
694 break;
695 case 2: /* HI (!C && !Z) */
696 tmp = tcg_temp_new();
697 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
698 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
699 break;
700 case 3: /* LS (C || Z) */
701 tmp = tcg_temp_new();
702 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
703 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
704 break;
705 case 4: /* CC (!C) */
706 tmp = tcg_temp_new();
707 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
708 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
709 break;
710 case 5: /* CS (C) */
711 tmp = tcg_temp_new();
712 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
713 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
714 break;
715 case 6: /* NE (!Z) */
716 tmp = tcg_temp_new();
717 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
718 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
719 break;
720 case 7: /* EQ (Z) */
721 tmp = tcg_temp_new();
722 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
723 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
724 break;
725 case 8: /* VC (!V) */
726 tmp = tcg_temp_new();
727 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
728 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
729 break;
730 case 9: /* VS (V) */
731 tmp = tcg_temp_new();
732 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
733 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
734 break;
735 case 10: /* PL (!N) */
736 tmp = tcg_temp_new();
737 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
738 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
739 break;
740 case 11: /* MI (N) */
741 tmp = tcg_temp_new();
742 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
743 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
744 break;
745 case 12: /* GE (!(N ^ V)) */
746 tmp = tcg_temp_new();
747 assert(CCF_V == (CCF_N >> 2));
748 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
749 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
750 tcg_gen_andi_i32(tmp, tmp, CCF_V);
751 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
752 break;
753 case 13: /* LT (N ^ V) */
754 tmp = tcg_temp_new();
755 assert(CCF_V == (CCF_N >> 2));
756 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
757 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
758 tcg_gen_andi_i32(tmp, tmp, CCF_V);
759 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
760 break;
761 case 14: /* GT (!(Z || (N ^ V))) */
762 tmp = tcg_temp_new();
763 assert(CCF_V == (CCF_N >> 2));
764 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
765 tcg_gen_shri_i32(tmp, tmp, 2);
766 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
767 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
768 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
769 break;
770 case 15: /* LE (Z || (N ^ V)) */
771 tmp = tcg_temp_new();
772 assert(CCF_V == (CCF_N >> 2));
773 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
774 tcg_gen_shri_i32(tmp, tmp, 2);
775 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
776 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
777 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
778 break;
779 default:
780 /* Should ever happen. */
781 abort();
782 }
783 }
784
785 DISAS_INSN(scc)
786 {
787 TCGLabel *l1;
788 int cond;
789 TCGv reg;
790
791 l1 = gen_new_label();
792 cond = (insn >> 8) & 0xf;
793 reg = DREG(insn, 0);
794 tcg_gen_andi_i32(reg, reg, 0xffffff00);
795 /* This is safe because we modify the reg directly, with no other values
796 live. */
797 gen_jmpcc(s, cond ^ 1, l1);
798 tcg_gen_ori_i32(reg, reg, 0xff);
799 gen_set_label(l1);
800 }
801
802 /* Force a TB lookup after an instruction that changes the CPU state. */
803 static void gen_lookup_tb(DisasContext *s)
804 {
805 gen_flush_cc_op(s);
806 tcg_gen_movi_i32(QREG_PC, s->pc);
807 s->is_jmp = DISAS_UPDATE;
808 }
809
810 /* Generate a jump to an immediate address. */
811 static void gen_jmp_im(DisasContext *s, uint32_t dest)
812 {
813 gen_flush_cc_op(s);
814 tcg_gen_movi_i32(QREG_PC, dest);
815 s->is_jmp = DISAS_JUMP;
816 }
817
818 /* Generate a jump to the address in qreg DEST. */
819 static void gen_jmp(DisasContext *s, TCGv dest)
820 {
821 gen_flush_cc_op(s);
822 tcg_gen_mov_i32(QREG_PC, dest);
823 s->is_jmp = DISAS_JUMP;
824 }
825
826 static void gen_exception(DisasContext *s, uint32_t where, int nr)
827 {
828 gen_flush_cc_op(s);
829 gen_jmp_im(s, where);
830 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
831 }
832
833 static inline void gen_addr_fault(DisasContext *s)
834 {
835 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
836 }
837
838 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
839 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
840 op_sign ? EA_LOADS : EA_LOADU); \
841 if (IS_NULL_QREG(result)) { \
842 gen_addr_fault(s); \
843 return; \
844 } \
845 } while (0)
846
847 #define DEST_EA(env, insn, opsize, val, addrp) do { \
848 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
849 if (IS_NULL_QREG(ea_result)) { \
850 gen_addr_fault(s); \
851 return; \
852 } \
853 } while (0)
854
855 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
856 {
857 #ifndef CONFIG_USER_ONLY
858 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
859 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
860 #else
861 return true;
862 #endif
863 }
864
865 /* Generate a jump to an immediate address. */
866 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
867 {
868 if (unlikely(s->singlestep_enabled)) {
869 gen_exception(s, dest, EXCP_DEBUG);
870 } else if (use_goto_tb(s, dest)) {
871 tcg_gen_goto_tb(n);
872 tcg_gen_movi_i32(QREG_PC, dest);
873 tcg_gen_exit_tb((uintptr_t)s->tb + n);
874 } else {
875 gen_jmp_im(s, dest);
876 tcg_gen_exit_tb(0);
877 }
878 s->is_jmp = DISAS_TB_JUMP;
879 }
880
881 DISAS_INSN(undef_mac)
882 {
883 gen_exception(s, s->pc - 2, EXCP_LINEA);
884 }
885
886 DISAS_INSN(undef_fpu)
887 {
888 gen_exception(s, s->pc - 2, EXCP_LINEF);
889 }
890
891 DISAS_INSN(undef)
892 {
893 M68kCPU *cpu = m68k_env_get_cpu(env);
894
895 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
896 cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
897 }
898
899 DISAS_INSN(mulw)
900 {
901 TCGv reg;
902 TCGv tmp;
903 TCGv src;
904 int sign;
905
906 sign = (insn & 0x100) != 0;
907 reg = DREG(insn, 9);
908 tmp = tcg_temp_new();
909 if (sign)
910 tcg_gen_ext16s_i32(tmp, reg);
911 else
912 tcg_gen_ext16u_i32(tmp, reg);
913 SRC_EA(env, src, OS_WORD, sign, NULL);
914 tcg_gen_mul_i32(tmp, tmp, src);
915 tcg_gen_mov_i32(reg, tmp);
916 /* Unlike m68k, coldfire always clears the overflow bit. */
917 gen_logic_cc(s, tmp);
918 }
919
920 DISAS_INSN(divw)
921 {
922 TCGv reg;
923 TCGv tmp;
924 TCGv src;
925 int sign;
926
927 sign = (insn & 0x100) != 0;
928 reg = DREG(insn, 9);
929 if (sign) {
930 tcg_gen_ext16s_i32(QREG_DIV1, reg);
931 } else {
932 tcg_gen_ext16u_i32(QREG_DIV1, reg);
933 }
934 SRC_EA(env, src, OS_WORD, sign, NULL);
935 tcg_gen_mov_i32(QREG_DIV2, src);
936 if (sign) {
937 gen_helper_divs(cpu_env, tcg_const_i32(1));
938 } else {
939 gen_helper_divu(cpu_env, tcg_const_i32(1));
940 }
941
942 tmp = tcg_temp_new();
943 src = tcg_temp_new();
944 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
945 tcg_gen_shli_i32(src, QREG_DIV2, 16);
946 tcg_gen_or_i32(reg, tmp, src);
947 s->cc_op = CC_OP_FLAGS;
948 }
949
950 DISAS_INSN(divl)
951 {
952 TCGv num;
953 TCGv den;
954 TCGv reg;
955 uint16_t ext;
956
957 ext = cpu_lduw_code(env, s->pc);
958 s->pc += 2;
959 if (ext & 0x87f8) {
960 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
961 return;
962 }
963 num = DREG(ext, 12);
964 reg = DREG(ext, 0);
965 tcg_gen_mov_i32(QREG_DIV1, num);
966 SRC_EA(env, den, OS_LONG, 0, NULL);
967 tcg_gen_mov_i32(QREG_DIV2, den);
968 if (ext & 0x0800) {
969 gen_helper_divs(cpu_env, tcg_const_i32(0));
970 } else {
971 gen_helper_divu(cpu_env, tcg_const_i32(0));
972 }
973 if ((ext & 7) == ((ext >> 12) & 7)) {
974 /* div */
975 tcg_gen_mov_i32 (reg, QREG_DIV1);
976 } else {
977 /* rem */
978 tcg_gen_mov_i32 (reg, QREG_DIV2);
979 }
980 s->cc_op = CC_OP_FLAGS;
981 }
982
983 DISAS_INSN(addsub)
984 {
985 TCGv reg;
986 TCGv dest;
987 TCGv src;
988 TCGv tmp;
989 TCGv addr;
990 int add;
991
992 add = (insn & 0x4000) != 0;
993 reg = DREG(insn, 9);
994 dest = tcg_temp_new();
995 if (insn & 0x100) {
996 SRC_EA(env, tmp, OS_LONG, 0, &addr);
997 src = reg;
998 } else {
999 tmp = reg;
1000 SRC_EA(env, src, OS_LONG, 0, NULL);
1001 }
1002 if (add) {
1003 tcg_gen_add_i32(dest, tmp, src);
1004 gen_helper_xflag_lt(QREG_CC_X, dest, src);
1005 s->cc_op = CC_OP_ADD;
1006 } else {
1007 gen_helper_xflag_lt(QREG_CC_X, tmp, src);
1008 tcg_gen_sub_i32(dest, tmp, src);
1009 s->cc_op = CC_OP_SUB;
1010 }
1011 gen_update_cc_add(dest, src);
1012 if (insn & 0x100) {
1013 DEST_EA(env, insn, OS_LONG, dest, &addr);
1014 } else {
1015 tcg_gen_mov_i32(reg, dest);
1016 }
1017 }
1018
1019
1020 /* Reverse the order of the bits in REG. */
1021 DISAS_INSN(bitrev)
1022 {
1023 TCGv reg;
1024 reg = DREG(insn, 0);
1025 gen_helper_bitrev(reg, reg);
1026 }
1027
1028 DISAS_INSN(bitop_reg)
1029 {
1030 int opsize;
1031 int op;
1032 TCGv src1;
1033 TCGv src2;
1034 TCGv tmp;
1035 TCGv addr;
1036 TCGv dest;
1037
1038 if ((insn & 0x38) != 0)
1039 opsize = OS_BYTE;
1040 else
1041 opsize = OS_LONG;
1042 op = (insn >> 6) & 3;
1043 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1044 src2 = DREG(insn, 9);
1045 dest = tcg_temp_new();
1046
1047 gen_flush_flags(s);
1048 tmp = tcg_temp_new();
1049 if (opsize == OS_BYTE)
1050 tcg_gen_andi_i32(tmp, src2, 7);
1051 else
1052 tcg_gen_andi_i32(tmp, src2, 31);
1053 src2 = tmp;
1054 tmp = tcg_temp_new();
1055 tcg_gen_shr_i32(tmp, src1, src2);
1056 tcg_gen_andi_i32(tmp, tmp, 1);
1057 tcg_gen_shli_i32(tmp, tmp, 2);
1058 /* Clear CCF_Z if bit set. */
1059 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1060 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1061
1062 tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);
1063 switch (op) {
1064 case 1: /* bchg */
1065 tcg_gen_xor_i32(dest, src1, tmp);
1066 break;
1067 case 2: /* bclr */
1068 tcg_gen_not_i32(tmp, tmp);
1069 tcg_gen_and_i32(dest, src1, tmp);
1070 break;
1071 case 3: /* bset */
1072 tcg_gen_or_i32(dest, src1, tmp);
1073 break;
1074 default: /* btst */
1075 break;
1076 }
1077 if (op)
1078 DEST_EA(env, insn, opsize, dest, &addr);
1079 }
1080
1081 DISAS_INSN(sats)
1082 {
1083 TCGv reg;
1084 reg = DREG(insn, 0);
1085 gen_flush_flags(s);
1086 gen_helper_sats(reg, reg, QREG_CC_DEST);
1087 gen_logic_cc(s, reg);
1088 }
1089
1090 static void gen_push(DisasContext *s, TCGv val)
1091 {
1092 TCGv tmp;
1093
1094 tmp = tcg_temp_new();
1095 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1096 gen_store(s, OS_LONG, tmp, val);
1097 tcg_gen_mov_i32(QREG_SP, tmp);
1098 }
1099
1100 DISAS_INSN(movem)
1101 {
1102 TCGv addr;
1103 int i;
1104 uint16_t mask;
1105 TCGv reg;
1106 TCGv tmp;
1107 int is_load;
1108
1109 mask = cpu_lduw_code(env, s->pc);
1110 s->pc += 2;
1111 tmp = gen_lea(env, s, insn, OS_LONG);
1112 if (IS_NULL_QREG(tmp)) {
1113 gen_addr_fault(s);
1114 return;
1115 }
1116 addr = tcg_temp_new();
1117 tcg_gen_mov_i32(addr, tmp);
1118 is_load = ((insn & 0x0400) != 0);
1119 for (i = 0; i < 16; i++, mask >>= 1) {
1120 if (mask & 1) {
1121 if (i < 8)
1122 reg = DREG(i, 0);
1123 else
1124 reg = AREG(i, 0);
1125 if (is_load) {
1126 tmp = gen_load(s, OS_LONG, addr, 0);
1127 tcg_gen_mov_i32(reg, tmp);
1128 } else {
1129 gen_store(s, OS_LONG, addr, reg);
1130 }
1131 if (mask != 1)
1132 tcg_gen_addi_i32(addr, addr, 4);
1133 }
1134 }
1135 }
1136
1137 DISAS_INSN(bitop_im)
1138 {
1139 int opsize;
1140 int op;
1141 TCGv src1;
1142 uint32_t mask;
1143 int bitnum;
1144 TCGv tmp;
1145 TCGv addr;
1146
1147 if ((insn & 0x38) != 0)
1148 opsize = OS_BYTE;
1149 else
1150 opsize = OS_LONG;
1151 op = (insn >> 6) & 3;
1152
1153 bitnum = cpu_lduw_code(env, s->pc);
1154 s->pc += 2;
1155 if (bitnum & 0xff00) {
1156 disas_undef(env, s, insn);
1157 return;
1158 }
1159
1160 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1161
1162 gen_flush_flags(s);
1163 if (opsize == OS_BYTE)
1164 bitnum &= 7;
1165 else
1166 bitnum &= 31;
1167 mask = 1 << bitnum;
1168
1169 tmp = tcg_temp_new();
1170 assert (CCF_Z == (1 << 2));
1171 if (bitnum > 2)
1172 tcg_gen_shri_i32(tmp, src1, bitnum - 2);
1173 else if (bitnum < 2)
1174 tcg_gen_shli_i32(tmp, src1, 2 - bitnum);
1175 else
1176 tcg_gen_mov_i32(tmp, src1);
1177 tcg_gen_andi_i32(tmp, tmp, CCF_Z);
1178 /* Clear CCF_Z if bit set. */
1179 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1180 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1181 if (op) {
1182 switch (op) {
1183 case 1: /* bchg */
1184 tcg_gen_xori_i32(tmp, src1, mask);
1185 break;
1186 case 2: /* bclr */
1187 tcg_gen_andi_i32(tmp, src1, ~mask);
1188 break;
1189 case 3: /* bset */
1190 tcg_gen_ori_i32(tmp, src1, mask);
1191 break;
1192 default: /* btst */
1193 break;
1194 }
1195 DEST_EA(env, insn, opsize, tmp, &addr);
1196 }
1197 }
1198
1199 DISAS_INSN(arith_im)
1200 {
1201 int op;
1202 uint32_t im;
1203 TCGv src1;
1204 TCGv dest;
1205 TCGv addr;
1206
1207 op = (insn >> 9) & 7;
1208 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1209 im = read_im32(env, s);
1210 dest = tcg_temp_new();
1211 switch (op) {
1212 case 0: /* ori */
1213 tcg_gen_ori_i32(dest, src1, im);
1214 gen_logic_cc(s, dest);
1215 break;
1216 case 1: /* andi */
1217 tcg_gen_andi_i32(dest, src1, im);
1218 gen_logic_cc(s, dest);
1219 break;
1220 case 2: /* subi */
1221 tcg_gen_mov_i32(dest, src1);
1222 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1223 tcg_gen_subi_i32(dest, dest, im);
1224 gen_update_cc_add(dest, tcg_const_i32(im));
1225 s->cc_op = CC_OP_SUB;
1226 break;
1227 case 3: /* addi */
1228 tcg_gen_mov_i32(dest, src1);
1229 tcg_gen_addi_i32(dest, dest, im);
1230 gen_update_cc_add(dest, tcg_const_i32(im));
1231 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1232 s->cc_op = CC_OP_ADD;
1233 break;
1234 case 5: /* eori */
1235 tcg_gen_xori_i32(dest, src1, im);
1236 gen_logic_cc(s, dest);
1237 break;
1238 case 6: /* cmpi */
1239 tcg_gen_mov_i32(dest, src1);
1240 tcg_gen_subi_i32(dest, dest, im);
1241 gen_update_cc_add(dest, tcg_const_i32(im));
1242 s->cc_op = CC_OP_SUB;
1243 break;
1244 default:
1245 abort();
1246 }
1247 if (op != 6) {
1248 DEST_EA(env, insn, OS_LONG, dest, &addr);
1249 }
1250 }
1251
1252 DISAS_INSN(byterev)
1253 {
1254 TCGv reg;
1255
1256 reg = DREG(insn, 0);
1257 tcg_gen_bswap32_i32(reg, reg);
1258 }
1259
1260 DISAS_INSN(move)
1261 {
1262 TCGv src;
1263 TCGv dest;
1264 int op;
1265 int opsize;
1266
1267 switch (insn >> 12) {
1268 case 1: /* move.b */
1269 opsize = OS_BYTE;
1270 break;
1271 case 2: /* move.l */
1272 opsize = OS_LONG;
1273 break;
1274 case 3: /* move.w */
1275 opsize = OS_WORD;
1276 break;
1277 default:
1278 abort();
1279 }
1280 SRC_EA(env, src, opsize, 1, NULL);
1281 op = (insn >> 6) & 7;
1282 if (op == 1) {
1283 /* movea */
1284 /* The value will already have been sign extended. */
1285 dest = AREG(insn, 9);
1286 tcg_gen_mov_i32(dest, src);
1287 } else {
1288 /* normal move */
1289 uint16_t dest_ea;
1290 dest_ea = ((insn >> 9) & 7) | (op << 3);
1291 DEST_EA(env, dest_ea, opsize, src, NULL);
1292 /* This will be correct because loads sign extend. */
1293 gen_logic_cc(s, src);
1294 }
1295 }
1296
1297 DISAS_INSN(negx)
1298 {
1299 TCGv reg;
1300
1301 gen_flush_flags(s);
1302 reg = DREG(insn, 0);
1303 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1304 }
1305
1306 DISAS_INSN(lea)
1307 {
1308 TCGv reg;
1309 TCGv tmp;
1310
1311 reg = AREG(insn, 9);
1312 tmp = gen_lea(env, s, insn, OS_LONG);
1313 if (IS_NULL_QREG(tmp)) {
1314 gen_addr_fault(s);
1315 return;
1316 }
1317 tcg_gen_mov_i32(reg, tmp);
1318 }
1319
1320 DISAS_INSN(clr)
1321 {
1322 int opsize;
1323
1324 switch ((insn >> 6) & 3) {
1325 case 0: /* clr.b */
1326 opsize = OS_BYTE;
1327 break;
1328 case 1: /* clr.w */
1329 opsize = OS_WORD;
1330 break;
1331 case 2: /* clr.l */
1332 opsize = OS_LONG;
1333 break;
1334 default:
1335 abort();
1336 }
1337 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1338 gen_logic_cc(s, tcg_const_i32(0));
1339 }
1340
1341 static TCGv gen_get_ccr(DisasContext *s)
1342 {
1343 TCGv dest;
1344
1345 gen_flush_flags(s);
1346 dest = tcg_temp_new();
1347 tcg_gen_shli_i32(dest, QREG_CC_X, 4);
1348 tcg_gen_or_i32(dest, dest, QREG_CC_DEST);
1349 return dest;
1350 }
1351
1352 DISAS_INSN(move_from_ccr)
1353 {
1354 TCGv reg;
1355 TCGv ccr;
1356
1357 ccr = gen_get_ccr(s);
1358 reg = DREG(insn, 0);
1359 gen_partset_reg(OS_WORD, reg, ccr);
1360 }
1361
1362 DISAS_INSN(neg)
1363 {
1364 TCGv reg;
1365 TCGv src1;
1366
1367 reg = DREG(insn, 0);
1368 src1 = tcg_temp_new();
1369 tcg_gen_mov_i32(src1, reg);
1370 tcg_gen_neg_i32(reg, src1);
1371 s->cc_op = CC_OP_SUB;
1372 gen_update_cc_add(reg, src1);
1373 gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
1374 s->cc_op = CC_OP_SUB;
1375 }
1376
1377 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1378 {
1379 tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf);
1380 tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4);
1381 if (!ccr_only) {
1382 gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
1383 }
1384 }
1385
1386 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1387 int ccr_only)
1388 {
1389 TCGv tmp;
1390 TCGv reg;
1391
1392 s->cc_op = CC_OP_FLAGS;
1393 if ((insn & 0x38) == 0)
1394 {
1395 tmp = tcg_temp_new();
1396 reg = DREG(insn, 0);
1397 tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
1398 tcg_gen_shri_i32(tmp, reg, 4);
1399 tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
1400 if (!ccr_only) {
1401 gen_helper_set_sr(cpu_env, reg);
1402 }
1403 }
1404 else if ((insn & 0x3f) == 0x3c)
1405 {
1406 uint16_t val;
1407 val = cpu_lduw_code(env, s->pc);
1408 s->pc += 2;
1409 gen_set_sr_im(s, val, ccr_only);
1410 }
1411 else
1412 disas_undef(env, s, insn);
1413 }
1414
1415 DISAS_INSN(move_to_ccr)
1416 {
1417 gen_set_sr(env, s, insn, 1);
1418 }
1419
1420 DISAS_INSN(not)
1421 {
1422 TCGv reg;
1423
1424 reg = DREG(insn, 0);
1425 tcg_gen_not_i32(reg, reg);
1426 gen_logic_cc(s, reg);
1427 }
1428
1429 DISAS_INSN(swap)
1430 {
1431 TCGv src1;
1432 TCGv src2;
1433 TCGv reg;
1434
1435 src1 = tcg_temp_new();
1436 src2 = tcg_temp_new();
1437 reg = DREG(insn, 0);
1438 tcg_gen_shli_i32(src1, reg, 16);
1439 tcg_gen_shri_i32(src2, reg, 16);
1440 tcg_gen_or_i32(reg, src1, src2);
1441 gen_logic_cc(s, reg);
1442 }
1443
1444 DISAS_INSN(pea)
1445 {
1446 TCGv tmp;
1447
1448 tmp = gen_lea(env, s, insn, OS_LONG);
1449 if (IS_NULL_QREG(tmp)) {
1450 gen_addr_fault(s);
1451 return;
1452 }
1453 gen_push(s, tmp);
1454 }
1455
1456 DISAS_INSN(ext)
1457 {
1458 int op;
1459 TCGv reg;
1460 TCGv tmp;
1461
1462 reg = DREG(insn, 0);
1463 op = (insn >> 6) & 7;
1464 tmp = tcg_temp_new();
1465 if (op == 3)
1466 tcg_gen_ext16s_i32(tmp, reg);
1467 else
1468 tcg_gen_ext8s_i32(tmp, reg);
1469 if (op == 2)
1470 gen_partset_reg(OS_WORD, reg, tmp);
1471 else
1472 tcg_gen_mov_i32(reg, tmp);
1473 gen_logic_cc(s, tmp);
1474 }
1475
1476 DISAS_INSN(tst)
1477 {
1478 int opsize;
1479 TCGv tmp;
1480
1481 switch ((insn >> 6) & 3) {
1482 case 0: /* tst.b */
1483 opsize = OS_BYTE;
1484 break;
1485 case 1: /* tst.w */
1486 opsize = OS_WORD;
1487 break;
1488 case 2: /* tst.l */
1489 opsize = OS_LONG;
1490 break;
1491 default:
1492 abort();
1493 }
1494 SRC_EA(env, tmp, opsize, 1, NULL);
1495 gen_logic_cc(s, tmp);
1496 }
1497
1498 DISAS_INSN(pulse)
1499 {
1500 /* Implemented as a NOP. */
1501 }
1502
1503 DISAS_INSN(illegal)
1504 {
1505 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1506 }
1507
1508 /* ??? This should be atomic. */
1509 DISAS_INSN(tas)
1510 {
1511 TCGv dest;
1512 TCGv src1;
1513 TCGv addr;
1514
1515 dest = tcg_temp_new();
1516 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1517 gen_logic_cc(s, src1);
1518 tcg_gen_ori_i32(dest, src1, 0x80);
1519 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1520 }
1521
1522 DISAS_INSN(mull)
1523 {
1524 uint16_t ext;
1525 TCGv reg;
1526 TCGv src1;
1527 TCGv dest;
1528
1529 /* The upper 32 bits of the product are discarded, so
1530 muls.l and mulu.l are functionally equivalent. */
1531 ext = cpu_lduw_code(env, s->pc);
1532 s->pc += 2;
1533 if (ext & 0x87ff) {
1534 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1535 return;
1536 }
1537 reg = DREG(ext, 12);
1538 SRC_EA(env, src1, OS_LONG, 0, NULL);
1539 dest = tcg_temp_new();
1540 tcg_gen_mul_i32(dest, src1, reg);
1541 tcg_gen_mov_i32(reg, dest);
1542 /* Unlike m68k, coldfire always clears the overflow bit. */
1543 gen_logic_cc(s, dest);
1544 }
1545
1546 DISAS_INSN(link)
1547 {
1548 int16_t offset;
1549 TCGv reg;
1550 TCGv tmp;
1551
1552 offset = cpu_ldsw_code(env, s->pc);
1553 s->pc += 2;
1554 reg = AREG(insn, 0);
1555 tmp = tcg_temp_new();
1556 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1557 gen_store(s, OS_LONG, tmp, reg);
1558 if ((insn & 7) != 7)
1559 tcg_gen_mov_i32(reg, tmp);
1560 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1561 }
1562
1563 DISAS_INSN(unlk)
1564 {
1565 TCGv src;
1566 TCGv reg;
1567 TCGv tmp;
1568
1569 src = tcg_temp_new();
1570 reg = AREG(insn, 0);
1571 tcg_gen_mov_i32(src, reg);
1572 tmp = gen_load(s, OS_LONG, src, 0);
1573 tcg_gen_mov_i32(reg, tmp);
1574 tcg_gen_addi_i32(QREG_SP, src, 4);
1575 }
1576
1577 DISAS_INSN(nop)
1578 {
1579 }
1580
1581 DISAS_INSN(rts)
1582 {
1583 TCGv tmp;
1584
1585 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1586 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1587 gen_jmp(s, tmp);
1588 }
1589
1590 DISAS_INSN(jump)
1591 {
1592 TCGv tmp;
1593
1594 /* Load the target address first to ensure correct exception
1595 behavior. */
1596 tmp = gen_lea(env, s, insn, OS_LONG);
1597 if (IS_NULL_QREG(tmp)) {
1598 gen_addr_fault(s);
1599 return;
1600 }
1601 if ((insn & 0x40) == 0) {
1602 /* jsr */
1603 gen_push(s, tcg_const_i32(s->pc));
1604 }
1605 gen_jmp(s, tmp);
1606 }
1607
1608 DISAS_INSN(addsubq)
1609 {
1610 TCGv src1;
1611 TCGv src2;
1612 TCGv dest;
1613 int val;
1614 TCGv addr;
1615
1616 SRC_EA(env, src1, OS_LONG, 0, &addr);
1617 val = (insn >> 9) & 7;
1618 if (val == 0)
1619 val = 8;
1620 dest = tcg_temp_new();
1621 tcg_gen_mov_i32(dest, src1);
1622 if ((insn & 0x38) == 0x08) {
1623 /* Don't update condition codes if the destination is an
1624 address register. */
1625 if (insn & 0x0100) {
1626 tcg_gen_subi_i32(dest, dest, val);
1627 } else {
1628 tcg_gen_addi_i32(dest, dest, val);
1629 }
1630 } else {
1631 src2 = tcg_const_i32(val);
1632 if (insn & 0x0100) {
1633 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1634 tcg_gen_subi_i32(dest, dest, val);
1635 s->cc_op = CC_OP_SUB;
1636 } else {
1637 tcg_gen_addi_i32(dest, dest, val);
1638 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1639 s->cc_op = CC_OP_ADD;
1640 }
1641 gen_update_cc_add(dest, src2);
1642 }
1643 DEST_EA(env, insn, OS_LONG, dest, &addr);
1644 }
1645
1646 DISAS_INSN(tpf)
1647 {
1648 switch (insn & 7) {
1649 case 2: /* One extension word. */
1650 s->pc += 2;
1651 break;
1652 case 3: /* Two extension words. */
1653 s->pc += 4;
1654 break;
1655 case 4: /* No extension words. */
1656 break;
1657 default:
1658 disas_undef(env, s, insn);
1659 }
1660 }
1661
1662 DISAS_INSN(branch)
1663 {
1664 int32_t offset;
1665 uint32_t base;
1666 int op;
1667 TCGLabel *l1;
1668
1669 base = s->pc;
1670 op = (insn >> 8) & 0xf;
1671 offset = (int8_t)insn;
1672 if (offset == 0) {
1673 offset = cpu_ldsw_code(env, s->pc);
1674 s->pc += 2;
1675 } else if (offset == -1) {
1676 offset = read_im32(env, s);
1677 }
1678 if (op == 1) {
1679 /* bsr */
1680 gen_push(s, tcg_const_i32(s->pc));
1681 }
1682 gen_flush_cc_op(s);
1683 if (op > 1) {
1684 /* Bcc */
1685 l1 = gen_new_label();
1686 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1687 gen_jmp_tb(s, 1, base + offset);
1688 gen_set_label(l1);
1689 gen_jmp_tb(s, 0, s->pc);
1690 } else {
1691 /* Unconditional branch. */
1692 gen_jmp_tb(s, 0, base + offset);
1693 }
1694 }
1695
1696 DISAS_INSN(moveq)
1697 {
1698 uint32_t val;
1699
1700 val = (int8_t)insn;
1701 tcg_gen_movi_i32(DREG(insn, 9), val);
1702 gen_logic_cc(s, tcg_const_i32(val));
1703 }
1704
1705 DISAS_INSN(mvzs)
1706 {
1707 int opsize;
1708 TCGv src;
1709 TCGv reg;
1710
1711 if (insn & 0x40)
1712 opsize = OS_WORD;
1713 else
1714 opsize = OS_BYTE;
1715 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1716 reg = DREG(insn, 9);
1717 tcg_gen_mov_i32(reg, src);
1718 gen_logic_cc(s, src);
1719 }
1720
1721 DISAS_INSN(or)
1722 {
1723 TCGv reg;
1724 TCGv dest;
1725 TCGv src;
1726 TCGv addr;
1727
1728 reg = DREG(insn, 9);
1729 dest = tcg_temp_new();
1730 if (insn & 0x100) {
1731 SRC_EA(env, src, OS_LONG, 0, &addr);
1732 tcg_gen_or_i32(dest, src, reg);
1733 DEST_EA(env, insn, OS_LONG, dest, &addr);
1734 } else {
1735 SRC_EA(env, src, OS_LONG, 0, NULL);
1736 tcg_gen_or_i32(dest, src, reg);
1737 tcg_gen_mov_i32(reg, dest);
1738 }
1739 gen_logic_cc(s, dest);
1740 }
1741
1742 DISAS_INSN(suba)
1743 {
1744 TCGv src;
1745 TCGv reg;
1746
1747 SRC_EA(env, src, OS_LONG, 0, NULL);
1748 reg = AREG(insn, 9);
1749 tcg_gen_sub_i32(reg, reg, src);
1750 }
1751
1752 DISAS_INSN(subx)
1753 {
1754 TCGv reg;
1755 TCGv src;
1756
1757 gen_flush_flags(s);
1758 reg = DREG(insn, 9);
1759 src = DREG(insn, 0);
1760 gen_helper_subx_cc(reg, cpu_env, reg, src);
1761 }
1762
1763 DISAS_INSN(mov3q)
1764 {
1765 TCGv src;
1766 int val;
1767
1768 val = (insn >> 9) & 7;
1769 if (val == 0)
1770 val = -1;
1771 src = tcg_const_i32(val);
1772 gen_logic_cc(s, src);
1773 DEST_EA(env, insn, OS_LONG, src, NULL);
1774 }
1775
1776 DISAS_INSN(cmp)
1777 {
1778 int op;
1779 TCGv src;
1780 TCGv reg;
1781 TCGv dest;
1782 int opsize;
1783
1784 op = (insn >> 6) & 3;
1785 switch (op) {
1786 case 0: /* cmp.b */
1787 opsize = OS_BYTE;
1788 s->cc_op = CC_OP_CMPB;
1789 break;
1790 case 1: /* cmp.w */
1791 opsize = OS_WORD;
1792 s->cc_op = CC_OP_CMPW;
1793 break;
1794 case 2: /* cmp.l */
1795 opsize = OS_LONG;
1796 s->cc_op = CC_OP_SUB;
1797 break;
1798 default:
1799 abort();
1800 }
1801 SRC_EA(env, src, opsize, 1, NULL);
1802 reg = DREG(insn, 9);
1803 dest = tcg_temp_new();
1804 tcg_gen_sub_i32(dest, reg, src);
1805 gen_update_cc_add(dest, src);
1806 }
1807
1808 DISAS_INSN(cmpa)
1809 {
1810 int opsize;
1811 TCGv src;
1812 TCGv reg;
1813 TCGv dest;
1814
1815 if (insn & 0x100) {
1816 opsize = OS_LONG;
1817 } else {
1818 opsize = OS_WORD;
1819 }
1820 SRC_EA(env, src, opsize, 1, NULL);
1821 reg = AREG(insn, 9);
1822 dest = tcg_temp_new();
1823 tcg_gen_sub_i32(dest, reg, src);
1824 gen_update_cc_add(dest, src);
1825 s->cc_op = CC_OP_SUB;
1826 }
1827
1828 DISAS_INSN(eor)
1829 {
1830 TCGv src;
1831 TCGv reg;
1832 TCGv dest;
1833 TCGv addr;
1834
1835 SRC_EA(env, src, OS_LONG, 0, &addr);
1836 reg = DREG(insn, 9);
1837 dest = tcg_temp_new();
1838 tcg_gen_xor_i32(dest, src, reg);
1839 gen_logic_cc(s, dest);
1840 DEST_EA(env, insn, OS_LONG, dest, &addr);
1841 }
1842
1843 DISAS_INSN(and)
1844 {
1845 TCGv src;
1846 TCGv reg;
1847 TCGv dest;
1848 TCGv addr;
1849
1850 reg = DREG(insn, 9);
1851 dest = tcg_temp_new();
1852 if (insn & 0x100) {
1853 SRC_EA(env, src, OS_LONG, 0, &addr);
1854 tcg_gen_and_i32(dest, src, reg);
1855 DEST_EA(env, insn, OS_LONG, dest, &addr);
1856 } else {
1857 SRC_EA(env, src, OS_LONG, 0, NULL);
1858 tcg_gen_and_i32(dest, src, reg);
1859 tcg_gen_mov_i32(reg, dest);
1860 }
1861 gen_logic_cc(s, dest);
1862 }
1863
1864 DISAS_INSN(adda)
1865 {
1866 TCGv src;
1867 TCGv reg;
1868
1869 SRC_EA(env, src, OS_LONG, 0, NULL);
1870 reg = AREG(insn, 9);
1871 tcg_gen_add_i32(reg, reg, src);
1872 }
1873
1874 DISAS_INSN(addx)
1875 {
1876 TCGv reg;
1877 TCGv src;
1878
1879 gen_flush_flags(s);
1880 reg = DREG(insn, 9);
1881 src = DREG(insn, 0);
1882 gen_helper_addx_cc(reg, cpu_env, reg, src);
1883 s->cc_op = CC_OP_FLAGS;
1884 }
1885
1886 /* TODO: This could be implemented without helper functions. */
1887 DISAS_INSN(shift_im)
1888 {
1889 TCGv reg;
1890 int tmp;
1891 TCGv shift;
1892
1893 reg = DREG(insn, 0);
1894 tmp = (insn >> 9) & 7;
1895 if (tmp == 0)
1896 tmp = 8;
1897 shift = tcg_const_i32(tmp);
1898 /* No need to flush flags becuse we know we will set C flag. */
1899 if (insn & 0x100) {
1900 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1901 } else {
1902 if (insn & 8) {
1903 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1904 } else {
1905 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1906 }
1907 }
1908 s->cc_op = CC_OP_SHIFT;
1909 }
1910
1911 DISAS_INSN(shift_reg)
1912 {
1913 TCGv reg;
1914 TCGv shift;
1915
1916 reg = DREG(insn, 0);
1917 shift = DREG(insn, 9);
1918 /* Shift by zero leaves C flag unmodified. */
1919 gen_flush_flags(s);
1920 if (insn & 0x100) {
1921 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1922 } else {
1923 if (insn & 8) {
1924 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1925 } else {
1926 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1927 }
1928 }
1929 s->cc_op = CC_OP_SHIFT;
1930 }
1931
1932 DISAS_INSN(ff1)
1933 {
1934 TCGv reg;
1935 reg = DREG(insn, 0);
1936 gen_logic_cc(s, reg);
1937 gen_helper_ff1(reg, reg);
1938 }
1939
1940 static TCGv gen_get_sr(DisasContext *s)
1941 {
1942 TCGv ccr;
1943 TCGv sr;
1944
1945 ccr = gen_get_ccr(s);
1946 sr = tcg_temp_new();
1947 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
1948 tcg_gen_or_i32(sr, sr, ccr);
1949 return sr;
1950 }
1951
1952 DISAS_INSN(strldsr)
1953 {
1954 uint16_t ext;
1955 uint32_t addr;
1956
1957 addr = s->pc - 2;
1958 ext = cpu_lduw_code(env, s->pc);
1959 s->pc += 2;
1960 if (ext != 0x46FC) {
1961 gen_exception(s, addr, EXCP_UNSUPPORTED);
1962 return;
1963 }
1964 ext = cpu_lduw_code(env, s->pc);
1965 s->pc += 2;
1966 if (IS_USER(s) || (ext & SR_S) == 0) {
1967 gen_exception(s, addr, EXCP_PRIVILEGE);
1968 return;
1969 }
1970 gen_push(s, gen_get_sr(s));
1971 gen_set_sr_im(s, ext, 0);
1972 }
1973
1974 DISAS_INSN(move_from_sr)
1975 {
1976 TCGv reg;
1977 TCGv sr;
1978
1979 if (IS_USER(s)) {
1980 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1981 return;
1982 }
1983 sr = gen_get_sr(s);
1984 reg = DREG(insn, 0);
1985 gen_partset_reg(OS_WORD, reg, sr);
1986 }
1987
1988 DISAS_INSN(move_to_sr)
1989 {
1990 if (IS_USER(s)) {
1991 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1992 return;
1993 }
1994 gen_set_sr(env, s, insn, 0);
1995 gen_lookup_tb(s);
1996 }
1997
1998 DISAS_INSN(move_from_usp)
1999 {
2000 if (IS_USER(s)) {
2001 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2002 return;
2003 }
2004 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
2005 offsetof(CPUM68KState, sp[M68K_USP]));
2006 }
2007
2008 DISAS_INSN(move_to_usp)
2009 {
2010 if (IS_USER(s)) {
2011 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2012 return;
2013 }
2014 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
2015 offsetof(CPUM68KState, sp[M68K_USP]));
2016 }
2017
2018 DISAS_INSN(halt)
2019 {
2020 gen_exception(s, s->pc, EXCP_HALT_INSN);
2021 }
2022
2023 DISAS_INSN(stop)
2024 {
2025 uint16_t ext;
2026
2027 if (IS_USER(s)) {
2028 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2029 return;
2030 }
2031
2032 ext = cpu_lduw_code(env, s->pc);
2033 s->pc += 2;
2034
2035 gen_set_sr_im(s, ext, 0);
2036 tcg_gen_movi_i32(cpu_halted, 1);
2037 gen_exception(s, s->pc, EXCP_HLT);
2038 }
2039
2040 DISAS_INSN(rte)
2041 {
2042 if (IS_USER(s)) {
2043 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2044 return;
2045 }
2046 gen_exception(s, s->pc - 2, EXCP_RTE);
2047 }
2048
2049 DISAS_INSN(movec)
2050 {
2051 uint16_t ext;
2052 TCGv reg;
2053
2054 if (IS_USER(s)) {
2055 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2056 return;
2057 }
2058
2059 ext = cpu_lduw_code(env, s->pc);
2060 s->pc += 2;
2061
2062 if (ext & 0x8000) {
2063 reg = AREG(ext, 12);
2064 } else {
2065 reg = DREG(ext, 12);
2066 }
2067 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2068 gen_lookup_tb(s);
2069 }
2070
2071 DISAS_INSN(intouch)
2072 {
2073 if (IS_USER(s)) {
2074 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2075 return;
2076 }
2077 /* ICache fetch. Implement as no-op. */
2078 }
2079
2080 DISAS_INSN(cpushl)
2081 {
2082 if (IS_USER(s)) {
2083 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2084 return;
2085 }
2086 /* Cache push/invalidate. Implement as no-op. */
2087 }
2088
2089 DISAS_INSN(wddata)
2090 {
2091 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2092 }
2093
2094 DISAS_INSN(wdebug)
2095 {
2096 M68kCPU *cpu = m68k_env_get_cpu(env);
2097
2098 if (IS_USER(s)) {
2099 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2100 return;
2101 }
2102 /* TODO: Implement wdebug. */
2103 cpu_abort(CPU(cpu), "WDEBUG not implemented");
2104 }
2105
2106 DISAS_INSN(trap)
2107 {
2108 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2109 }
2110
2111 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2112 immediately before the next FP instruction is executed. */
2113 DISAS_INSN(fpu)
2114 {
2115 uint16_t ext;
2116 int32_t offset;
2117 int opmode;
2118 TCGv_i64 src;
2119 TCGv_i64 dest;
2120 TCGv_i64 res;
2121 TCGv tmp32;
2122 int round;
2123 int set_dest;
2124 int opsize;
2125
2126 ext = cpu_lduw_code(env, s->pc);
2127 s->pc += 2;
2128 opmode = ext & 0x7f;
2129 switch ((ext >> 13) & 7) {
2130 case 0: case 2:
2131 break;
2132 case 1:
2133 goto undef;
2134 case 3: /* fmove out */
2135 src = FREG(ext, 7);
2136 tmp32 = tcg_temp_new_i32();
2137 /* fmove */
2138 /* ??? TODO: Proper behavior on overflow. */
2139 switch ((ext >> 10) & 7) {
2140 case 0:
2141 opsize = OS_LONG;
2142 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2143 break;
2144 case 1:
2145 opsize = OS_SINGLE;
2146 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2147 break;
2148 case 4:
2149 opsize = OS_WORD;
2150 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2151 break;
2152 case 5: /* OS_DOUBLE */
2153 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2154 switch ((insn >> 3) & 7) {
2155 case 2:
2156 case 3:
2157 break;
2158 case 4:
2159 tcg_gen_addi_i32(tmp32, tmp32, -8);
2160 break;
2161 case 5:
2162 offset = cpu_ldsw_code(env, s->pc);
2163 s->pc += 2;
2164 tcg_gen_addi_i32(tmp32, tmp32, offset);
2165 break;
2166 default:
2167 goto undef;
2168 }
2169 gen_store64(s, tmp32, src);
2170 switch ((insn >> 3) & 7) {
2171 case 3:
2172 tcg_gen_addi_i32(tmp32, tmp32, 8);
2173 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2174 break;
2175 case 4:
2176 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2177 break;
2178 }
2179 tcg_temp_free_i32(tmp32);
2180 return;
2181 case 6:
2182 opsize = OS_BYTE;
2183 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2184 break;
2185 default:
2186 goto undef;
2187 }
2188 DEST_EA(env, insn, opsize, tmp32, NULL);
2189 tcg_temp_free_i32(tmp32);
2190 return;
2191 case 4: /* fmove to control register. */
2192 switch ((ext >> 10) & 7) {
2193 case 4: /* FPCR */
2194 /* Not implemented. Ignore writes. */
2195 break;
2196 case 1: /* FPIAR */
2197 case 2: /* FPSR */
2198 default:
2199 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2200 (ext >> 10) & 7);
2201 }
2202 break;
2203 case 5: /* fmove from control register. */
2204 switch ((ext >> 10) & 7) {
2205 case 4: /* FPCR */
2206 /* Not implemented. Always return zero. */
2207 tmp32 = tcg_const_i32(0);
2208 break;
2209 case 1: /* FPIAR */
2210 case 2: /* FPSR */
2211 default:
2212 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2213 (ext >> 10) & 7);
2214 goto undef;
2215 }
2216 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2217 break;
2218 case 6: /* fmovem */
2219 case 7:
2220 {
2221 TCGv addr;
2222 uint16_t mask;
2223 int i;
2224 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2225 goto undef;
2226 tmp32 = gen_lea(env, s, insn, OS_LONG);
2227 if (IS_NULL_QREG(tmp32)) {
2228 gen_addr_fault(s);
2229 return;
2230 }
2231 addr = tcg_temp_new_i32();
2232 tcg_gen_mov_i32(addr, tmp32);
2233 mask = 0x80;
2234 for (i = 0; i < 8; i++) {
2235 if (ext & mask) {
2236 dest = FREG(i, 0);
2237 if (ext & (1 << 13)) {
2238 /* store */
2239 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2240 } else {
2241 /* load */
2242 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2243 }
2244 if (ext & (mask - 1))
2245 tcg_gen_addi_i32(addr, addr, 8);
2246 }
2247 mask >>= 1;
2248 }
2249 tcg_temp_free_i32(addr);
2250 }
2251 return;
2252 }
2253 if (ext & (1 << 14)) {
2254 /* Source effective address. */
2255 switch ((ext >> 10) & 7) {
2256 case 0: opsize = OS_LONG; break;
2257 case 1: opsize = OS_SINGLE; break;
2258 case 4: opsize = OS_WORD; break;
2259 case 5: opsize = OS_DOUBLE; break;
2260 case 6: opsize = OS_BYTE; break;
2261 default:
2262 goto undef;
2263 }
2264 if (opsize == OS_DOUBLE) {
2265 tmp32 = tcg_temp_new_i32();
2266 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2267 switch ((insn >> 3) & 7) {
2268 case 2:
2269 case 3:
2270 break;
2271 case 4:
2272 tcg_gen_addi_i32(tmp32, tmp32, -8);
2273 break;
2274 case 5:
2275 offset = cpu_ldsw_code(env, s->pc);
2276 s->pc += 2;
2277 tcg_gen_addi_i32(tmp32, tmp32, offset);
2278 break;
2279 case 7:
2280 offset = cpu_ldsw_code(env, s->pc);
2281 offset += s->pc - 2;
2282 s->pc += 2;
2283 tcg_gen_addi_i32(tmp32, tmp32, offset);
2284 break;
2285 default:
2286 goto undef;
2287 }
2288 src = gen_load64(s, tmp32);
2289 switch ((insn >> 3) & 7) {
2290 case 3:
2291 tcg_gen_addi_i32(tmp32, tmp32, 8);
2292 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2293 break;
2294 case 4:
2295 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2296 break;
2297 }
2298 tcg_temp_free_i32(tmp32);
2299 } else {
2300 SRC_EA(env, tmp32, opsize, 1, NULL);
2301 src = tcg_temp_new_i64();
2302 switch (opsize) {
2303 case OS_LONG:
2304 case OS_WORD:
2305 case OS_BYTE:
2306 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2307 break;
2308 case OS_SINGLE:
2309 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2310 break;
2311 }
2312 }
2313 } else {
2314 /* Source register. */
2315 src = FREG(ext, 10);
2316 }
2317 dest = FREG(ext, 7);
2318 res = tcg_temp_new_i64();
2319 if (opmode != 0x3a)
2320 tcg_gen_mov_f64(res, dest);
2321 round = 1;
2322 set_dest = 1;
2323 switch (opmode) {
2324 case 0: case 0x40: case 0x44: /* fmove */
2325 tcg_gen_mov_f64(res, src);
2326 break;
2327 case 1: /* fint */
2328 gen_helper_iround_f64(res, cpu_env, src);
2329 round = 0;
2330 break;
2331 case 3: /* fintrz */
2332 gen_helper_itrunc_f64(res, cpu_env, src);
2333 round = 0;
2334 break;
2335 case 4: case 0x41: case 0x45: /* fsqrt */
2336 gen_helper_sqrt_f64(res, cpu_env, src);
2337 break;
2338 case 0x18: case 0x58: case 0x5c: /* fabs */
2339 gen_helper_abs_f64(res, src);
2340 break;
2341 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2342 gen_helper_chs_f64(res, src);
2343 break;
2344 case 0x20: case 0x60: case 0x64: /* fdiv */
2345 gen_helper_div_f64(res, cpu_env, res, src);
2346 break;
2347 case 0x22: case 0x62: case 0x66: /* fadd */
2348 gen_helper_add_f64(res, cpu_env, res, src);
2349 break;
2350 case 0x23: case 0x63: case 0x67: /* fmul */
2351 gen_helper_mul_f64(res, cpu_env, res, src);
2352 break;
2353 case 0x28: case 0x68: case 0x6c: /* fsub */
2354 gen_helper_sub_f64(res, cpu_env, res, src);
2355 break;
2356 case 0x38: /* fcmp */
2357 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2358 set_dest = 0;
2359 round = 0;
2360 break;
2361 case 0x3a: /* ftst */
2362 tcg_gen_mov_f64(res, src);
2363 set_dest = 0;
2364 round = 0;
2365 break;
2366 default:
2367 goto undef;
2368 }
2369 if (ext & (1 << 14)) {
2370 tcg_temp_free_i64(src);
2371 }
2372 if (round) {
2373 if (opmode & 0x40) {
2374 if ((opmode & 0x4) != 0)
2375 round = 0;
2376 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2377 round = 0;
2378 }
2379 }
2380 if (round) {
2381 TCGv tmp = tcg_temp_new_i32();
2382 gen_helper_f64_to_f32(tmp, cpu_env, res);
2383 gen_helper_f32_to_f64(res, cpu_env, tmp);
2384 tcg_temp_free_i32(tmp);
2385 }
2386 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2387 if (set_dest) {
2388 tcg_gen_mov_f64(dest, res);
2389 }
2390 tcg_temp_free_i64(res);
2391 return;
2392 undef:
2393 /* FIXME: Is this right for offset addressing modes? */
2394 s->pc -= 2;
2395 disas_undef_fpu(env, s, insn);
2396 }
2397
2398 DISAS_INSN(fbcc)
2399 {
2400 uint32_t offset;
2401 uint32_t addr;
2402 TCGv flag;
2403 TCGLabel *l1;
2404
2405 addr = s->pc;
2406 offset = cpu_ldsw_code(env, s->pc);
2407 s->pc += 2;
2408 if (insn & (1 << 6)) {
2409 offset = (offset << 16) | cpu_lduw_code(env, s->pc);
2410 s->pc += 2;
2411 }
2412
2413 l1 = gen_new_label();
2414 /* TODO: Raise BSUN exception. */
2415 flag = tcg_temp_new();
2416 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2417 /* Jump to l1 if condition is true. */
2418 switch (insn & 0xf) {
2419 case 0: /* f */
2420 break;
2421 case 1: /* eq (=0) */
2422 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2423 break;
2424 case 2: /* ogt (=1) */
2425 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2426 break;
2427 case 3: /* oge (=0 or =1) */
2428 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2429 break;
2430 case 4: /* olt (=-1) */
2431 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2432 break;
2433 case 5: /* ole (=-1 or =0) */
2434 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2435 break;
2436 case 6: /* ogl (=-1 or =1) */
2437 tcg_gen_andi_i32(flag, flag, 1);
2438 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2439 break;
2440 case 7: /* or (=2) */
2441 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2442 break;
2443 case 8: /* un (<2) */
2444 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2445 break;
2446 case 9: /* ueq (=0 or =2) */
2447 tcg_gen_andi_i32(flag, flag, 1);
2448 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2449 break;
2450 case 10: /* ugt (>0) */
2451 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2452 break;
2453 case 11: /* uge (>=0) */
2454 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2455 break;
2456 case 12: /* ult (=-1 or =2) */
2457 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2458 break;
2459 case 13: /* ule (!=1) */
2460 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2461 break;
2462 case 14: /* ne (!=0) */
2463 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2464 break;
2465 case 15: /* t */
2466 tcg_gen_br(l1);
2467 break;
2468 }
2469 gen_jmp_tb(s, 0, s->pc);
2470 gen_set_label(l1);
2471 gen_jmp_tb(s, 1, addr + offset);
2472 }
2473
2474 DISAS_INSN(frestore)
2475 {
2476 M68kCPU *cpu = m68k_env_get_cpu(env);
2477
2478 /* TODO: Implement frestore. */
2479 cpu_abort(CPU(cpu), "FRESTORE not implemented");
2480 }
2481
2482 DISAS_INSN(fsave)
2483 {
2484 M68kCPU *cpu = m68k_env_get_cpu(env);
2485
2486 /* TODO: Implement fsave. */
2487 cpu_abort(CPU(cpu), "FSAVE not implemented");
2488 }
2489
2490 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2491 {
2492 TCGv tmp = tcg_temp_new();
2493 if (s->env->macsr & MACSR_FI) {
2494 if (upper)
2495 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2496 else
2497 tcg_gen_shli_i32(tmp, val, 16);
2498 } else if (s->env->macsr & MACSR_SU) {
2499 if (upper)
2500 tcg_gen_sari_i32(tmp, val, 16);
2501 else
2502 tcg_gen_ext16s_i32(tmp, val);
2503 } else {
2504 if (upper)
2505 tcg_gen_shri_i32(tmp, val, 16);
2506 else
2507 tcg_gen_ext16u_i32(tmp, val);
2508 }
2509 return tmp;
2510 }
2511
2512 static void gen_mac_clear_flags(void)
2513 {
2514 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2515 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2516 }
2517
2518 DISAS_INSN(mac)
2519 {
2520 TCGv rx;
2521 TCGv ry;
2522 uint16_t ext;
2523 int acc;
2524 TCGv tmp;
2525 TCGv addr;
2526 TCGv loadval;
2527 int dual;
2528 TCGv saved_flags;
2529
2530 if (!s->done_mac) {
2531 s->mactmp = tcg_temp_new_i64();
2532 s->done_mac = 1;
2533 }
2534
2535 ext = cpu_lduw_code(env, s->pc);
2536 s->pc += 2;
2537
2538 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2539 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2540 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2541 disas_undef(env, s, insn);
2542 return;
2543 }
2544 if (insn & 0x30) {
2545 /* MAC with load. */
2546 tmp = gen_lea(env, s, insn, OS_LONG);
2547 addr = tcg_temp_new();
2548 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2549 /* Load the value now to ensure correct exception behavior.
2550 Perform writeback after reading the MAC inputs. */
2551 loadval = gen_load(s, OS_LONG, addr, 0);
2552
2553 acc ^= 1;
2554 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2555 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2556 } else {
2557 loadval = addr = NULL_QREG;
2558 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2559 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2560 }
2561
2562 gen_mac_clear_flags();
2563 #if 0
2564 l1 = -1;
2565 /* Disabled because conditional branches clobber temporary vars. */
2566 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2567 /* Skip the multiply if we know we will ignore it. */
2568 l1 = gen_new_label();
2569 tmp = tcg_temp_new();
2570 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2571 gen_op_jmp_nz32(tmp, l1);
2572 }
2573 #endif
2574
2575 if ((ext & 0x0800) == 0) {
2576 /* Word. */
2577 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2578 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2579 }
2580 if (s->env->macsr & MACSR_FI) {
2581 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2582 } else {
2583 if (s->env->macsr & MACSR_SU)
2584 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2585 else
2586 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2587 switch ((ext >> 9) & 3) {
2588 case 1:
2589 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2590 break;
2591 case 3:
2592 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2593 break;
2594 }
2595 }
2596
2597 if (dual) {
2598 /* Save the overflow flag from the multiply. */
2599 saved_flags = tcg_temp_new();
2600 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2601 } else {
2602 saved_flags = NULL_QREG;
2603 }
2604
2605 #if 0
2606 /* Disabled because conditional branches clobber temporary vars. */
2607 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2608 /* Skip the accumulate if the value is already saturated. */
2609 l1 = gen_new_label();
2610 tmp = tcg_temp_new();
2611 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2612 gen_op_jmp_nz32(tmp, l1);
2613 }
2614 #endif
2615
2616 if (insn & 0x100)
2617 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2618 else
2619 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2620
2621 if (s->env->macsr & MACSR_FI)
2622 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2623 else if (s->env->macsr & MACSR_SU)
2624 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2625 else
2626 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2627
2628 #if 0
2629 /* Disabled because conditional branches clobber temporary vars. */
2630 if (l1 != -1)
2631 gen_set_label(l1);
2632 #endif
2633
2634 if (dual) {
2635 /* Dual accumulate variant. */
2636 acc = (ext >> 2) & 3;
2637 /* Restore the overflow flag from the multiplier. */
2638 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2639 #if 0
2640 /* Disabled because conditional branches clobber temporary vars. */
2641 if ((s->env->macsr & MACSR_OMC) != 0) {
2642 /* Skip the accumulate if the value is already saturated. */
2643 l1 = gen_new_label();
2644 tmp = tcg_temp_new();
2645 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2646 gen_op_jmp_nz32(tmp, l1);
2647 }
2648 #endif
2649 if (ext & 2)
2650 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2651 else
2652 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2653 if (s->env->macsr & MACSR_FI)
2654 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2655 else if (s->env->macsr & MACSR_SU)
2656 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2657 else
2658 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2659 #if 0
2660 /* Disabled because conditional branches clobber temporary vars. */
2661 if (l1 != -1)
2662 gen_set_label(l1);
2663 #endif
2664 }
2665 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2666
2667 if (insn & 0x30) {
2668 TCGv rw;
2669 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2670 tcg_gen_mov_i32(rw, loadval);
2671 /* FIXME: Should address writeback happen with the masked or
2672 unmasked value? */
2673 switch ((insn >> 3) & 7) {
2674 case 3: /* Post-increment. */
2675 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2676 break;
2677 case 4: /* Pre-decrement. */
2678 tcg_gen_mov_i32(AREG(insn, 0), addr);
2679 }
2680 }
2681 }
2682
2683 DISAS_INSN(from_mac)
2684 {
2685 TCGv rx;
2686 TCGv_i64 acc;
2687 int accnum;
2688
2689 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2690 accnum = (insn >> 9) & 3;
2691 acc = MACREG(accnum);
2692 if (s->env->macsr & MACSR_FI) {
2693 gen_helper_get_macf(rx, cpu_env, acc);
2694 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2695 tcg_gen_extrl_i64_i32(rx, acc);
2696 } else if (s->env->macsr & MACSR_SU) {
2697 gen_helper_get_macs(rx, acc);
2698 } else {
2699 gen_helper_get_macu(rx, acc);
2700 }
2701 if (insn & 0x40) {
2702 tcg_gen_movi_i64(acc, 0);
2703 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2704 }
2705 }
2706
2707 DISAS_INSN(move_mac)
2708 {
2709 /* FIXME: This can be done without a helper. */
2710 int src;
2711 TCGv dest;
2712 src = insn & 3;
2713 dest = tcg_const_i32((insn >> 9) & 3);
2714 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2715 gen_mac_clear_flags();
2716 gen_helper_mac_set_flags(cpu_env, dest);
2717 }
2718
2719 DISAS_INSN(from_macsr)
2720 {
2721 TCGv reg;
2722
2723 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2724 tcg_gen_mov_i32(reg, QREG_MACSR);
2725 }
2726
2727 DISAS_INSN(from_mask)
2728 {
2729 TCGv reg;
2730 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2731 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2732 }
2733
2734 DISAS_INSN(from_mext)
2735 {
2736 TCGv reg;
2737 TCGv acc;
2738 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2739 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2740 if (s->env->macsr & MACSR_FI)
2741 gen_helper_get_mac_extf(reg, cpu_env, acc);
2742 else
2743 gen_helper_get_mac_exti(reg, cpu_env, acc);
2744 }
2745
2746 DISAS_INSN(macsr_to_ccr)
2747 {
2748 tcg_gen_movi_i32(QREG_CC_X, 0);
2749 tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
2750 s->cc_op = CC_OP_FLAGS;
2751 }
2752
2753 DISAS_INSN(to_mac)
2754 {
2755 TCGv_i64 acc;
2756 TCGv val;
2757 int accnum;
2758 accnum = (insn >> 9) & 3;
2759 acc = MACREG(accnum);
2760 SRC_EA(env, val, OS_LONG, 0, NULL);
2761 if (s->env->macsr & MACSR_FI) {
2762 tcg_gen_ext_i32_i64(acc, val);
2763 tcg_gen_shli_i64(acc, acc, 8);
2764 } else if (s->env->macsr & MACSR_SU) {
2765 tcg_gen_ext_i32_i64(acc, val);
2766 } else {
2767 tcg_gen_extu_i32_i64(acc, val);
2768 }
2769 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2770 gen_mac_clear_flags();
2771 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2772 }
2773
2774 DISAS_INSN(to_macsr)
2775 {
2776 TCGv val;
2777 SRC_EA(env, val, OS_LONG, 0, NULL);
2778 gen_helper_set_macsr(cpu_env, val);
2779 gen_lookup_tb(s);
2780 }
2781
2782 DISAS_INSN(to_mask)
2783 {
2784 TCGv val;
2785 SRC_EA(env, val, OS_LONG, 0, NULL);
2786 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2787 }
2788
2789 DISAS_INSN(to_mext)
2790 {
2791 TCGv val;
2792 TCGv acc;
2793 SRC_EA(env, val, OS_LONG, 0, NULL);
2794 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2795 if (s->env->macsr & MACSR_FI)
2796 gen_helper_set_mac_extf(cpu_env, val, acc);
2797 else if (s->env->macsr & MACSR_SU)
2798 gen_helper_set_mac_exts(cpu_env, val, acc);
2799 else
2800 gen_helper_set_mac_extu(cpu_env, val, acc);
2801 }
2802
2803 static disas_proc opcode_table[65536];
2804
2805 static void
2806 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2807 {
2808 int i;
2809 int from;
2810 int to;
2811
2812 /* Sanity check. All set bits must be included in the mask. */
2813 if (opcode & ~mask) {
2814 fprintf(stderr,
2815 "qemu internal error: bogus opcode definition %04x/%04x\n",
2816 opcode, mask);
2817 abort();
2818 }
2819 /* This could probably be cleverer. For now just optimize the case where
2820 the top bits are known. */
2821 /* Find the first zero bit in the mask. */
2822 i = 0x8000;
2823 while ((i & mask) != 0)
2824 i >>= 1;
2825 /* Iterate over all combinations of this and lower bits. */
2826 if (i == 0)
2827 i = 1;
2828 else
2829 i <<= 1;
2830 from = opcode & ~(i - 1);
2831 to = from + i;
2832 for (i = from; i < to; i++) {
2833 if ((i & mask) == opcode)
2834 opcode_table[i] = proc;
2835 }
2836 }
2837
2838 /* Register m68k opcode handlers. Order is important.
2839 Later insn override earlier ones. */
2840 void register_m68k_insns (CPUM68KState *env)
2841 {
2842 #define INSN(name, opcode, mask, feature) do { \
2843 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2844 register_opcode(disas_##name, 0x##opcode, 0x##mask); \
2845 } while(0)
2846 INSN(undef, 0000, 0000, CF_ISA_A);
2847 INSN(arith_im, 0080, fff8, CF_ISA_A);
2848 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
2849 INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
2850 INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
2851 INSN(bitop_reg, 0180, f1c0, CF_ISA_A);
2852 INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);
2853 INSN(arith_im, 0280, fff8, CF_ISA_A);
2854 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
2855 INSN(arith_im, 0480, fff8, CF_ISA_A);
2856 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
2857 INSN(arith_im, 0680, fff8, CF_ISA_A);
2858 INSN(bitop_im, 0800, ffc0, CF_ISA_A);
2859 INSN(bitop_im, 0840, ffc0, CF_ISA_A);
2860 INSN(bitop_im, 0880, ffc0, CF_ISA_A);
2861 INSN(bitop_im, 08c0, ffc0, CF_ISA_A);
2862 INSN(arith_im, 0a80, fff8, CF_ISA_A);
2863 INSN(arith_im, 0c00, ff38, CF_ISA_A);
2864 INSN(move, 1000, f000, CF_ISA_A);
2865 INSN(move, 2000, f000, CF_ISA_A);
2866 INSN(move, 3000, f000, CF_ISA_A);
2867 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
2868 INSN(negx, 4080, fff8, CF_ISA_A);
2869 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
2870 INSN(lea, 41c0, f1c0, CF_ISA_A);
2871 INSN(clr, 4200, ff00, CF_ISA_A);
2872 INSN(undef, 42c0, ffc0, CF_ISA_A);
2873 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
2874 INSN(neg, 4480, fff8, CF_ISA_A);
2875 INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);
2876 INSN(not, 4680, fff8, CF_ISA_A);
2877 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
2878 INSN(pea, 4840, ffc0, CF_ISA_A);
2879 INSN(swap, 4840, fff8, CF_ISA_A);
2880 INSN(movem, 48c0, fbc0, CF_ISA_A);
2881 INSN(ext, 4880, fff8, CF_ISA_A);
2882 INSN(ext, 48c0, fff8, CF_ISA_A);
2883 INSN(ext, 49c0, fff8, CF_ISA_A);
2884 INSN(tst, 4a00, ff00, CF_ISA_A);
2885 INSN(tas, 4ac0, ffc0, CF_ISA_B);
2886 INSN(halt, 4ac8, ffff, CF_ISA_A);
2887 INSN(pulse, 4acc, ffff, CF_ISA_A);
2888 INSN(illegal, 4afc, ffff, CF_ISA_A);
2889 INSN(mull, 4c00, ffc0, CF_ISA_A);
2890 INSN(divl, 4c40, ffc0, CF_ISA_A);
2891 INSN(sats, 4c80, fff8, CF_ISA_B);
2892 INSN(trap, 4e40, fff0, CF_ISA_A);
2893 INSN(link, 4e50, fff8, CF_ISA_A);
2894 INSN(unlk, 4e58, fff8, CF_ISA_A);
2895 INSN(move_to_usp, 4e60, fff8, USP);
2896 INSN(move_from_usp, 4e68, fff8, USP);
2897 INSN(nop, 4e71, ffff, CF_ISA_A);
2898 INSN(stop, 4e72, ffff, CF_ISA_A);
2899 INSN(rte, 4e73, ffff, CF_ISA_A);
2900 INSN(rts, 4e75, ffff, CF_ISA_A);
2901 INSN(movec, 4e7b, ffff, CF_ISA_A);
2902 INSN(jump, 4e80, ffc0, CF_ISA_A);
2903 INSN(jump, 4ec0, ffc0, CF_ISA_A);
2904 INSN(addsubq, 5180, f1c0, CF_ISA_A);
2905 INSN(scc, 50c0, f0f8, CF_ISA_A);
2906 INSN(addsubq, 5080, f1c0, CF_ISA_A);
2907 INSN(tpf, 51f8, fff8, CF_ISA_A);
2908
2909 /* Branch instructions. */
2910 INSN(branch, 6000, f000, CF_ISA_A);
2911 /* Disable long branch instructions, then add back the ones we want. */
2912 INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */
2913 INSN(branch, 60ff, f0ff, CF_ISA_B);
2914 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
2915 INSN(branch, 60ff, ffff, BRAL);
2916
2917 INSN(moveq, 7000, f100, CF_ISA_A);
2918 INSN(mvzs, 7100, f100, CF_ISA_B);
2919 INSN(or, 8000, f000, CF_ISA_A);
2920 INSN(divw, 80c0, f0c0, CF_ISA_A);
2921 INSN(addsub, 9000, f000, CF_ISA_A);
2922 INSN(subx, 9180, f1f8, CF_ISA_A);
2923 INSN(suba, 91c0, f1c0, CF_ISA_A);
2924
2925 INSN(undef_mac, a000, f000, CF_ISA_A);
2926 INSN(mac, a000, f100, CF_EMAC);
2927 INSN(from_mac, a180, f9b0, CF_EMAC);
2928 INSN(move_mac, a110, f9fc, CF_EMAC);
2929 INSN(from_macsr,a980, f9f0, CF_EMAC);
2930 INSN(from_mask, ad80, fff0, CF_EMAC);
2931 INSN(from_mext, ab80, fbf0, CF_EMAC);
2932 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
2933 INSN(to_mac, a100, f9c0, CF_EMAC);
2934 INSN(to_macsr, a900, ffc0, CF_EMAC);
2935 INSN(to_mext, ab00, fbc0, CF_EMAC);
2936 INSN(to_mask, ad00, ffc0, CF_EMAC);
2937
2938 INSN(mov3q, a140, f1c0, CF_ISA_B);
2939 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
2940 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
2941 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
2942 INSN(cmp, b080, f1c0, CF_ISA_A);
2943 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
2944 INSN(eor, b180, f1c0, CF_ISA_A);
2945 INSN(and, c000, f000, CF_ISA_A);
2946 INSN(mulw, c0c0, f0c0, CF_ISA_A);
2947 INSN(addsub, d000, f000, CF_ISA_A);
2948 INSN(addx, d180, f1f8, CF_ISA_A);
2949 INSN(adda, d1c0, f1c0, CF_ISA_A);
2950 INSN(shift_im, e080, f0f0, CF_ISA_A);
2951 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
2952 INSN(undef_fpu, f000, f000, CF_ISA_A);
2953 INSN(fpu, f200, ffc0, CF_FPU);
2954 INSN(fbcc, f280, ffc0, CF_FPU);
2955 INSN(frestore, f340, ffc0, CF_FPU);
2956 INSN(fsave, f340, ffc0, CF_FPU);
2957 INSN(intouch, f340, ffc0, CF_ISA_A);
2958 INSN(cpushl, f428, ff38, CF_ISA_A);
2959 INSN(wddata, fb00, ff00, CF_ISA_A);
2960 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
2961 #undef INSN
2962 }
2963
2964 /* ??? Some of this implementation is not exception safe. We should always
2965 write back the result to memory before setting the condition codes. */
2966 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
2967 {
2968 uint16_t insn;
2969
2970 insn = cpu_lduw_code(env, s->pc);
2971 s->pc += 2;
2972
2973 opcode_table[insn](env, s, insn);
2974 }
2975
2976 /* generate intermediate code for basic block 'tb'. */
2977 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
2978 {
2979 M68kCPU *cpu = m68k_env_get_cpu(env);
2980 CPUState *cs = CPU(cpu);
2981 DisasContext dc1, *dc = &dc1;
2982 target_ulong pc_start;
2983 int pc_offset;
2984 int num_insns;
2985 int max_insns;
2986
2987 /* generate intermediate code */
2988 pc_start = tb->pc;
2989
2990 dc->tb = tb;
2991
2992 dc->env = env;
2993 dc->is_jmp = DISAS_NEXT;
2994 dc->pc = pc_start;
2995 dc->cc_op = CC_OP_DYNAMIC;
2996 dc->singlestep_enabled = cs->singlestep_enabled;
2997 dc->fpcr = env->fpcr;
2998 dc->user = (env->sr & SR_S) == 0;
2999 dc->done_mac = 0;
3000 num_insns = 0;
3001 max_insns = tb->cflags & CF_COUNT_MASK;
3002 if (max_insns == 0) {
3003 max_insns = CF_COUNT_MASK;
3004 }
3005 if (max_insns > TCG_MAX_INSNS) {
3006 max_insns = TCG_MAX_INSNS;
3007 }
3008
3009 gen_tb_start(tb);
3010 do {
3011 pc_offset = dc->pc - pc_start;
3012 gen_throws_exception = NULL;
3013 tcg_gen_insn_start(dc->pc);
3014 num_insns++;
3015
3016 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3017 gen_exception(dc, dc->pc, EXCP_DEBUG);
3018 dc->is_jmp = DISAS_JUMP;
3019 /* The address covered by the breakpoint must be included in
3020 [tb->pc, tb->pc + tb->size) in order to for it to be
3021 properly cleared -- thus we increment the PC here so that
3022 the logic setting tb->size below does the right thing. */
3023 dc->pc += 2;
3024 break;
3025 }
3026
3027 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3028 gen_io_start();
3029 }
3030
3031 dc->insn_pc = dc->pc;
3032 disas_m68k_insn(env, dc);
3033 } while (!dc->is_jmp && !tcg_op_buf_full() &&
3034 !cs->singlestep_enabled &&
3035 !singlestep &&
3036 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3037 num_insns < max_insns);
3038
3039 if (tb->cflags & CF_LAST_IO)
3040 gen_io_end();
3041 if (unlikely(cs->singlestep_enabled)) {
3042 /* Make sure the pc is updated, and raise a debug exception. */
3043 if (!dc->is_jmp) {
3044 gen_flush_cc_op(dc);
3045 tcg_gen_movi_i32(QREG_PC, dc->pc);
3046 }
3047 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3048 } else {
3049 switch(dc->is_jmp) {
3050 case DISAS_NEXT:
3051 gen_flush_cc_op(dc);
3052 gen_jmp_tb(dc, 0, dc->pc);
3053 break;
3054 default:
3055 case DISAS_JUMP:
3056 case DISAS_UPDATE:
3057 gen_flush_cc_op(dc);
3058 /* indicate that the hash table must be used to find the next TB */
3059 tcg_gen_exit_tb(0);
3060 break;
3061 case DISAS_TB_JUMP:
3062 /* nothing more to generate */
3063 break;
3064 }
3065 }
3066 gen_tb_end(tb, num_insns);
3067
3068 #ifdef DEBUG_DISAS
3069 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3070 qemu_log("----------------\n");
3071 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3072 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
3073 qemu_log("\n");
3074 }
3075 #endif
3076 tb->size = dc->pc - pc_start;
3077 tb->icount = num_insns;
3078 }
3079
3080 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3081 int flags)
3082 {
3083 M68kCPU *cpu = M68K_CPU(cs);
3084 CPUM68KState *env = &cpu->env;
3085 int i;
3086 uint16_t sr;
3087 CPU_DoubleU u;
3088 for (i = 0; i < 8; i++)
3089 {
3090 u.d = env->fregs[i];
3091 cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3092 i, env->dregs[i], i, env->aregs[i],
3093 i, u.l.upper, u.l.lower, *(double *)&u.d);
3094 }
3095 cpu_fprintf (f, "PC = %08x ", env->pc);
3096 sr = env->sr;
3097 cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-',
3098 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3099 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3100 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3101 }
3102
3103 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
3104 target_ulong *data)
3105 {
3106 env->pc = data[0];
3107 }
AR7 emulation for QEMU