target-xtensa: implement extended L32R
[qemu/ar7.git] / target-xtensa / helper.c
blob074207f5cfcb5f19dfb0888618c8da07cbb800f5
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "gdbstub.h"
31 #include "qemu-common.h"
32 #include "host-utils.h"
33 #if !defined(CONFIG_USER_ONLY)
34 #include "hw/loader.h"
35 #endif
37 void cpu_reset(CPUXtensaState *env)
39 env->exception_taken = 0;
40 env->pc = env->config->exception_vector[EXC_RESET];
41 env->sregs[LITBASE] &= ~1;
42 env->sregs[PS] = 0x1f;
45 static const XtensaConfig core_config[] = {
47 .name = "sample-xtensa-core",
48 .options = -1,
49 .nareg = 64,
50 .ndepc = 1,
51 .excm_level = 16,
52 .exception_vector = {
53 [EXC_RESET] = 0x5fff8000,
54 [EXC_WINDOW_OVERFLOW4] = 0x5fff8400,
55 [EXC_WINDOW_UNDERFLOW4] = 0x5fff8440,
56 [EXC_WINDOW_OVERFLOW8] = 0x5fff8480,
57 [EXC_WINDOW_UNDERFLOW8] = 0x5fff84c0,
58 [EXC_WINDOW_OVERFLOW12] = 0x5fff8500,
59 [EXC_WINDOW_UNDERFLOW12] = 0x5fff8540,
60 [EXC_KERNEL] = 0x5fff861c,
61 [EXC_USER] = 0x5fff863c,
62 [EXC_DOUBLE] = 0x5fff865c,
67 CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
69 static int tcg_inited;
70 CPUXtensaState *env;
71 const XtensaConfig *config = NULL;
72 int i;
74 for (i = 0; i < ARRAY_SIZE(core_config); ++i)
75 if (strcmp(core_config[i].name, cpu_model) == 0) {
76 config = core_config + i;
77 break;
80 if (config == NULL) {
81 return NULL;
84 env = g_malloc0(sizeof(*env));
85 env->config = config;
86 cpu_exec_init(env);
88 if (!tcg_inited) {
89 tcg_inited = 1;
90 xtensa_translate_init();
93 qemu_init_vcpu(env);
94 return env;
98 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
100 int i;
101 cpu_fprintf(f, "Available CPUs:\n");
102 for (i = 0; i < ARRAY_SIZE(core_config); ++i) {
103 cpu_fprintf(f, " %s\n", core_config[i].name);
107 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
109 return addr;
112 void do_interrupt(CPUState *env)
114 switch (env->exception_index) {
115 case EXC_WINDOW_OVERFLOW4:
116 case EXC_WINDOW_UNDERFLOW4:
117 case EXC_WINDOW_OVERFLOW8:
118 case EXC_WINDOW_UNDERFLOW8:
119 case EXC_WINDOW_OVERFLOW12:
120 case EXC_WINDOW_UNDERFLOW12:
121 case EXC_KERNEL:
122 case EXC_USER:
123 case EXC_DOUBLE:
124 if (env->config->exception_vector[env->exception_index]) {
125 env->pc = env->config->exception_vector[env->exception_index];
126 env->exception_taken = 1;
127 } else {
128 qemu_log("%s(pc = %08x) bad exception_index: %d\n",
129 __func__, env->pc, env->exception_index);
131 break;