hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/ppc/mac.h"
  27 #include "hw/ppc/mac_dbdma.h"
  28 #include "sysemu/block-backend.h"
  29 #include "sysemu/dma.h"
  30
  31 #include <hw/ide/internal.h>
  32
  33 /* debug MACIO */
  34 // #define DEBUG_MACIO
  35
  36 #ifdef DEBUG_MACIO
  37 static const int debug_macio = 1;
  38 #else
  39 static const int debug_macio = 0;
  40 #endif
  41
  42 #define MACIO_DPRINTF(fmt, ...) do { \
  43         if (debug_macio) { \
  44             printf(fmt , ## __VA_ARGS__); \
  45         } \
  46     } while (0)
  47
  48
  49 /***********************************************************/
  50 /* MacIO based PowerPC IDE */
  51
  52 #define MACIO_PAGE_SIZE 4096
  53
  54 /*
  55  * Unaligned DMA read/write access functions required for OS X/Darwin which
  56  * don't perform DMA transactions on sector boundaries. These functions are
  57  * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
  58  * easy to remove if the unaligned block APIs are ever exposed.
  59  */
  60
  61 static void pmac_dma_read(BlockBackend *blk,
  62                           int64_t offset, unsigned int bytes,
  63                           void (*cb)(void *opaque, int ret), void *opaque)
  64 {
  65     DBDMA_io *io = opaque;
  66     MACIOIDEState *m = io->opaque;
  67     IDEState *s = idebus_active_if(&m->bus);
  68     dma_addr_t dma_addr, dma_len;
  69     void *mem;
  70     int64_t sector_num;
  71     int nsector;
  72     uint64_t align = BDRV_SECTOR_SIZE;
  73     size_t head_bytes, tail_bytes;
  74
  75     qemu_iovec_destroy(&io->iov);
  76     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
  77
  78     sector_num = (offset >> 9);
  79     nsector = (io->len >> 9);
  80
  81     MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
  82                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
  83                   sector_num, nsector);
  84
  85     dma_addr = io->addr;
  86     dma_len = io->len;
  87     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
  88                          DMA_DIRECTION_FROM_DEVICE);
  89
  90     if (offset & (align - 1)) {
  91         head_bytes = offset & (align - 1);
  92
  93         MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
  94                       "discarding %zu bytes\n", sector_num, head_bytes);
  95
  96         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
  97
  98         bytes += offset & (align - 1);
  99         offset = offset & ~(align - 1);
 100     }
 101
 102     qemu_iovec_add(&io->iov, mem, io->len);
 103
 104     if ((offset + bytes) & (align - 1)) {
 105         tail_bytes = (offset + bytes) & (align - 1);
 106
 107         MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
 108                       "discarding bytes %zu\n", sector_num, tail_bytes);
 109
 110         qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
 111         bytes = ROUND_UP(bytes, align);
 112     }
 113
 114     s->io_buffer_size -= io->len;
 115     s->io_buffer_index += io->len;
 116
 117     io->len = 0;
 118
 119     MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 "  "
 120                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 121
 122     m->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov, (bytes >> 9),
 123                              cb, io);
 124 }
 125
 126 static void pmac_dma_write(BlockBackend *blk,
 127                          int64_t offset, int bytes,
 128                          void (*cb)(void *opaque, int ret), void *opaque)
 129 {
 130     DBDMA_io *io = opaque;
 131     MACIOIDEState *m = io->opaque;
 132     IDEState *s = idebus_active_if(&m->bus);
 133     dma_addr_t dma_addr, dma_len;
 134     void *mem;
 135     int64_t sector_num;
 136     int nsector;
 137     uint64_t align = BDRV_SECTOR_SIZE;
 138     size_t head_bytes, tail_bytes;
 139     bool unaligned_head = false, unaligned_tail = false;
 140
 141     qemu_iovec_destroy(&io->iov);
 142     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
 143
 144     sector_num = (offset >> 9);
 145     nsector = (io->len >> 9);
 146
 147     MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
 148                   "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
 149                   sector_num, nsector);
 150
 151     dma_addr = io->addr;
 152     dma_len = io->len;
 153     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
 154                          DMA_DIRECTION_TO_DEVICE);
 155
 156     if (offset & (align - 1)) {
 157         head_bytes = offset & (align - 1);
 158         sector_num = ((offset & ~(align - 1)) >> 9);
 159
 160         MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
 161                       PRId64 "\n", sector_num);
 162
 163         blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
 164
 165         qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
 166         qemu_iovec_add(&io->iov, mem, io->len);
 167
 168         bytes += offset & (align - 1);
 169         offset = offset & ~(align - 1);
 170
 171         unaligned_head = true;
 172     }
 173
 174     if ((offset + bytes) & (align - 1)) {
 175         tail_bytes = (offset + bytes) & (align - 1);
 176         sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
 177
 178         MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
 179                       PRId64 "\n", sector_num);
 180
 181         blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
 182
 183         if (!unaligned_head) {
 184             qemu_iovec_add(&io->iov, mem, io->len);
 185         }
 186
 187         qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
 188                        align - tail_bytes);
 189
 190         bytes = ROUND_UP(bytes, align);
 191
 192         unaligned_tail = true;
 193     }
 194
 195     if (!unaligned_head && !unaligned_tail) {
 196         qemu_iovec_add(&io->iov, mem, io->len);
 197     }
 198
 199     s->io_buffer_size -= io->len;
 200     s->io_buffer_index += io->len;
 201
 202     io->len = 0;
 203
 204     MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 "  "
 205                   "nsector: %x\n", (offset >> 9), (bytes >> 9));
 206
 207     m->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov, (bytes >> 9),
 208                               cb, io);
 209 }
 210
 211 static void pmac_dma_trim(BlockBackend *blk,
 212                         int64_t offset, int bytes,
 213                         void (*cb)(void *opaque, int ret), void *opaque)
 214 {
 215     DBDMA_io *io = opaque;
 216     MACIOIDEState *m = io->opaque;
 217     IDEState *s = idebus_active_if(&m->bus);
 218     dma_addr_t dma_addr, dma_len;
 219     void *mem;
 220
 221     qemu_iovec_destroy(&io->iov);
 222     qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
 223
 224     dma_addr = io->addr;
 225     dma_len = io->len;
 226     mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
 227                          DMA_DIRECTION_TO_DEVICE);
 228
 229     qemu_iovec_add(&io->iov, mem, io->len);
 230     s->io_buffer_size -= io->len;
 231     s->io_buffer_index += io->len;
 232     io->len = 0;
 233
 234     m->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov, (bytes >> 9),
 235                               cb, io);
 236 }
 237
 238 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
 239 {
 240     DBDMA_io *io = opaque;
 241     MACIOIDEState *m = io->opaque;
 242     IDEState *s = idebus_active_if(&m->bus);
 243     int64_t offset;
 244
 245     MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
 246
 247     if (ret < 0) {
 248         MACIO_DPRINTF("DMA error: %d\n", ret);
 249         ide_atapi_io_error(s, ret);
 250         goto done;
 251     }
 252
 253     if (!m->dma_active) {
 254         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 255                       s->nsector, io->len, s->status);
 256         /* data not ready yet, wait for the channel to get restarted */
 257         io->processing = false;
 258         return;
 259     }
 260
 261     if (s->io_buffer_size <= 0) {
 262         MACIO_DPRINTF("End of IDE transfer\n");
 263         ide_atapi_cmd_ok(s);
 264         m->dma_active = false;
 265         goto done;
 266     }
 267
 268     if (io->len == 0) {
 269         MACIO_DPRINTF("End of DMA transfer\n");
 270         goto done;
 271     }
 272
 273     if (s->lba == -1) {
 274         /* Non-block ATAPI transfer - just copy to RAM */
 275         s->io_buffer_size = MIN(s->io_buffer_size, io->len);
 276         cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
 277         ide_atapi_cmd_ok(s);
 278         m->dma_active = false;
 279         goto done;
 280     }
 281
 282     /* Calculate current offset */
 283     offset = (int64_t)(s->lba << 11) + s->io_buffer_index;
 284
 285     pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
 286     return;
 287
 288 done:
 289     block_acct_done(blk_get_stats(s->blk), &s->acct);
 290     io->dma_end(opaque);
 291
 292     return;
 293 }
 294
 295 static void pmac_ide_transfer_cb(void *opaque, int ret)
 296 {
 297     DBDMA_io *io = opaque;
 298     MACIOIDEState *m = io->opaque;
 299     IDEState *s = idebus_active_if(&m->bus);
 300     int64_t offset;
 301
 302     MACIO_DPRINTF("pmac_ide_transfer_cb\n");
 303
 304     if (ret < 0) {
 305         MACIO_DPRINTF("DMA error: %d\n", ret);
 306         m->aiocb = NULL;
 307         ide_dma_error(s);
 308         goto done;
 309     }
 310
 311     if (!m->dma_active) {
 312         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 313                       s->nsector, io->len, s->status);
 314         /* data not ready yet, wait for the channel to get restarted */
 315         io->processing = false;
 316         return;
 317     }
 318
 319     if (s->io_buffer_size <= 0) {
 320         MACIO_DPRINTF("End of IDE transfer\n");
 321         s->status = READY_STAT | SEEK_STAT;
 322         ide_set_irq(s->bus);
 323         m->dma_active = false;
 324         goto done;
 325     }
 326
 327     if (io->len == 0) {
 328         MACIO_DPRINTF("End of DMA transfer\n");
 329         goto done;
 330     }
 331
 332     /* Calculate number of sectors */
 333     offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
 334
 335     switch (s->dma_cmd) {
 336     case IDE_DMA_READ:
 337         pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 338         break;
 339     case IDE_DMA_WRITE:
 340         pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 341         break;
 342     case IDE_DMA_TRIM:
 343         pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
 344         break;
 345     }
 346
 347     return;
 348
 349 done:
 350     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 351         block_acct_done(blk_get_stats(s->blk), &s->acct);
 352     }
 353     io->dma_end(opaque);
 354 }
 355
 356 static void pmac_ide_transfer(DBDMA_io *io)
 357 {
 358     MACIOIDEState *m = io->opaque;
 359     IDEState *s = idebus_active_if(&m->bus);
 360
 361     MACIO_DPRINTF("\n");
 362
 363     if (s->drive_kind == IDE_CD) {
 364         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 365                          BLOCK_ACCT_READ);
 366
 367         pmac_ide_atapi_transfer_cb(io, 0);
 368         return;
 369     }
 370
 371     switch (s->dma_cmd) {
 372     case IDE_DMA_READ:
 373         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 374                          BLOCK_ACCT_READ);
 375         break;
 376     case IDE_DMA_WRITE:
 377         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 378                          BLOCK_ACCT_WRITE);
 379         break;
 380     default:
 381         break;
 382     }
 383
 384     pmac_ide_transfer_cb(io, 0);
 385 }
 386
 387 static void pmac_ide_flush(DBDMA_io *io)
 388 {
 389     MACIOIDEState *m = io->opaque;
 390
 391     if (m->aiocb) {
 392         blk_drain_all();
 393     }
 394 }
 395
 396 /* PowerMac IDE memory IO */
 397 static void pmac_ide_writeb (void *opaque,
 398                              hwaddr addr, uint32_t val)
 399 {
 400     MACIOIDEState *d = opaque;
 401
 402     addr = (addr & 0xFFF) >> 4;
 403     switch (addr) {
 404     case 1 ... 7:
 405         ide_ioport_write(&d->bus, addr, val);
 406         break;
 407     case 8:
 408     case 22:
 409         ide_cmd_write(&d->bus, 0, val);
 410         break;
 411     default:
 412         break;
 413     }
 414 }
 415
 416 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
 417 {
 418     uint8_t retval;
 419     MACIOIDEState *d = opaque;
 420
 421     addr = (addr & 0xFFF) >> 4;
 422     switch (addr) {
 423     case 1 ... 7:
 424         retval = ide_ioport_read(&d->bus, addr);
 425         break;
 426     case 8:
 427     case 22:
 428         retval = ide_status_read(&d->bus, 0);
 429         break;
 430     default:
 431         retval = 0xFF;
 432         break;
 433     }
 434     return retval;
 435 }
 436
 437 static void pmac_ide_writew (void *opaque,
 438                              hwaddr addr, uint32_t val)
 439 {
 440     MACIOIDEState *d = opaque;
 441
 442     addr = (addr & 0xFFF) >> 4;
 443     val = bswap16(val);
 444     if (addr == 0) {
 445         ide_data_writew(&d->bus, 0, val);
 446     }
 447 }
 448
 449 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
 450 {
 451     uint16_t retval;
 452     MACIOIDEState *d = opaque;
 453
 454     addr = (addr & 0xFFF) >> 4;
 455     if (addr == 0) {
 456         retval = ide_data_readw(&d->bus, 0);
 457     } else {
 458         retval = 0xFFFF;
 459     }
 460     retval = bswap16(retval);
 461     return retval;
 462 }
 463
 464 static void pmac_ide_writel (void *opaque,
 465                              hwaddr addr, uint32_t val)
 466 {
 467     MACIOIDEState *d = opaque;
 468
 469     addr = (addr & 0xFFF) >> 4;
 470     val = bswap32(val);
 471     if (addr == 0) {
 472         ide_data_writel(&d->bus, 0, val);
 473     }
 474 }
 475
 476 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
 477 {
 478     uint32_t retval;
 479     MACIOIDEState *d = opaque;
 480
 481     addr = (addr & 0xFFF) >> 4;
 482     if (addr == 0) {
 483         retval = ide_data_readl(&d->bus, 0);
 484     } else {
 485         retval = 0xFFFFFFFF;
 486     }
 487     retval = bswap32(retval);
 488     return retval;
 489 }
 490
 491 static const MemoryRegionOps pmac_ide_ops = {
 492     .old_mmio = {
 493         .write = {
 494             pmac_ide_writeb,
 495             pmac_ide_writew,
 496             pmac_ide_writel,
 497         },
 498         .read = {
 499             pmac_ide_readb,
 500             pmac_ide_readw,
 501             pmac_ide_readl,
 502         },
 503     },
 504     .endianness = DEVICE_NATIVE_ENDIAN,
 505 };
 506
 507 static const VMStateDescription vmstate_pmac = {
 508     .name = "ide",
 509     .version_id = 3,
 510     .minimum_version_id = 0,
 511     .fields = (VMStateField[]) {
 512         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 513         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 514         VMSTATE_END_OF_LIST()
 515     }
 516 };
 517
 518 static void macio_ide_reset(DeviceState *dev)
 519 {
 520     MACIOIDEState *d = MACIO_IDE(dev);
 521
 522     ide_bus_reset(&d->bus);
 523 }
 524
 525 static int ide_nop_int(IDEDMA *dma, int x)
 526 {
 527     return 0;
 528 }
 529
 530 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
 531 {
 532     return 0;
 533 }
 534
 535 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
 536                             BlockCompletionFunc *cb)
 537 {
 538     MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
 539
 540     s->io_buffer_index = 0;
 541     if (s->drive_kind == IDE_CD) {
 542         s->io_buffer_size = s->packet_transfer_size;
 543     } else {
 544         s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
 545     }
 546
 547     MACIO_DPRINTF("\n\n------------ IDE transfer\n");
 548     MACIO_DPRINTF("buffer_size: %x   buffer_index: %x\n",
 549                   s->io_buffer_size, s->io_buffer_index);
 550     MACIO_DPRINTF("lba: %x    size: %x\n", s->lba, s->io_buffer_size);
 551     MACIO_DPRINTF("-------------------------\n");
 552
 553     m->dma_active = true;
 554     DBDMA_kick(m->dbdma);
 555 }
 556
 557 static const IDEDMAOps dbdma_ops = {
 558     .start_dma      = ide_dbdma_start,
 559     .prepare_buf    = ide_nop_int32,
 560     .rw_buf         = ide_nop_int,
 561 };
 562
 563 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
 564 {
 565     MACIOIDEState *s = MACIO_IDE(dev);
 566
 567     ide_init2(&s->bus, s->irq);
 568
 569     /* Register DMA callbacks */
 570     s->dma.ops = &dbdma_ops;
 571     s->bus.dma = &s->dma;
 572 }
 573
 574 static void macio_ide_initfn(Object *obj)
 575 {
 576     SysBusDevice *d = SYS_BUS_DEVICE(obj);
 577     MACIOIDEState *s = MACIO_IDE(obj);
 578
 579     ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
 580     memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
 581     sysbus_init_mmio(d, &s->mem);
 582     sysbus_init_irq(d, &s->irq);
 583     sysbus_init_irq(d, &s->dma_irq);
 584 }
 585
 586 static void macio_ide_class_init(ObjectClass *oc, void *data)
 587 {
 588     DeviceClass *dc = DEVICE_CLASS(oc);
 589
 590     dc->realize = macio_ide_realizefn;
 591     dc->reset = macio_ide_reset;
 592     dc->vmsd = &vmstate_pmac;
 593 }
 594
 595 static const TypeInfo macio_ide_type_info = {
 596     .name = TYPE_MACIO_IDE,
 597     .parent = TYPE_SYS_BUS_DEVICE,
 598     .instance_size = sizeof(MACIOIDEState),
 599     .instance_init = macio_ide_initfn,
 600     .class_init = macio_ide_class_init,
 601 };
 602
 603 static void macio_ide_register_types(void)
 604 {
 605     type_register_static(&macio_ide_type_info);
 606 }
 607
 608 /* hd_table must contain 2 block drivers */
 609 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
 610 {
 611     int i;
 612
 613     for (i = 0; i < 2; i++) {
 614         if (hd_table[i]) {
 615             ide_create_drive(&s->bus, i, hd_table[i]);
 616         }
 617     }
 618 }
 619
 620 void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
 621 {
 622     s->dbdma = dbdma;
 623     DBDMA_register_channel(dbdma, channel, s->dma_irq,
 624                            pmac_ide_transfer, pmac_ide_flush, s);
 625 }
 626
 627 type_init(macio_ide_register_types)