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cpu-exec: reset BQL after longjmp in cpu_exec_step_atomic
[qemu/ar7.git] / memory.c
blob61d66e444131b46bc0ef2952550c49a5cf9d8367
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/visitor.h"
23 #include "qemu/bitops.h"
24 #include "qemu/error-report.h"
25 #include "qom/object.h"
26 #include "trace-root.h"
27
28 #include "exec/memory-internal.h"
29 #include "exec/ram_addr.h"
30 #include "sysemu/kvm.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/qdev-properties.h"
33 #include "migration/vmstate.h"
34
35 //#define DEBUG_UNASSIGNED
36
37 static unsigned memory_region_transaction_depth;
38 static bool memory_region_update_pending;
39 static bool ioeventfd_update_pending;
40 static bool global_dirty_log = false;
41
42 static QTAILQ_HEAD(, MemoryListener) memory_listeners
43 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
44
45 static QTAILQ_HEAD(, AddressSpace) address_spaces
46 = QTAILQ_HEAD_INITIALIZER(address_spaces);
47
48 static GHashTable *flat_views;
49
50 typedef struct AddrRange AddrRange;
51
52 /*
53 * Note that signed integers are needed for negative offsetting in aliases
54 * (large MemoryRegion::alias_offset).
55 */
56 struct AddrRange {
57 Int128 start;
58 Int128 size;
59 };
60
61 static AddrRange addrrange_make(Int128 start, Int128 size)
62 {
63 return (AddrRange) { start, size };
64 }
65
66 static bool addrrange_equal(AddrRange r1, AddrRange r2)
67 {
68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
69 }
70
71 static Int128 addrrange_end(AddrRange r)
72 {
73 return int128_add(r.start, r.size);
74 }
75
76 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
77 {
78 int128_addto(&range.start, delta);
79 return range;
80 }
81
82 static bool addrrange_contains(AddrRange range, Int128 addr)
83 {
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86 }
87
88 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89 {
90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
92 }
93
94 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95 {
96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
99 }
100
101 enum ListenerDirection { Forward, Reverse };
102
103 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
117 if (_listener->_callback) { \
118 _listener->_callback(_listener, ##_args); \
119 } \
120 } \
121 break; \
122 default: \
123 abort(); \
124 } \
125 } while (0)
126
127 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
128 do { \
129 MemoryListener *_listener; \
130 \
131 switch (_direction) { \
132 case Forward: \
133 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
134 if (_listener->_callback) { \
135 _listener->_callback(_listener, _section, ##_args); \
136 } \
137 } \
138 break; \
139 case Reverse: \
140 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
141 if (_listener->_callback) { \
142 _listener->_callback(_listener, _section, ##_args); \
143 } \
144 } \
145 break; \
146 default: \
147 abort(); \
148 } \
149 } while (0)
150
151 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
152 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
153 do { \
154 MemoryRegionSection mrs = section_from_flat_range(fr, \
155 address_space_to_flatview(as)); \
156 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
157 } while(0)
158
159 struct CoalescedMemoryRange {
160 AddrRange addr;
161 QTAILQ_ENTRY(CoalescedMemoryRange) link;
162 };
163
164 struct MemoryRegionIoeventfd {
165 AddrRange addr;
166 bool match_data;
167 uint64_t data;
168 EventNotifier *e;
169 };
170
171 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
172 MemoryRegionIoeventfd *b)
173 {
174 if (int128_lt(a->addr.start, b->addr.start)) {
175 return true;
176 } else if (int128_gt(a->addr.start, b->addr.start)) {
177 return false;
178 } else if (int128_lt(a->addr.size, b->addr.size)) {
179 return true;
180 } else if (int128_gt(a->addr.size, b->addr.size)) {
181 return false;
182 } else if (a->match_data < b->match_data) {
183 return true;
184 } else if (a->match_data > b->match_data) {
185 return false;
186 } else if (a->match_data) {
187 if (a->data < b->data) {
188 return true;
189 } else if (a->data > b->data) {
190 return false;
191 }
192 }
193 if (a->e < b->e) {
194 return true;
195 } else if (a->e > b->e) {
196 return false;
197 }
198 return false;
199 }
200
201 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
202 MemoryRegionIoeventfd *b)
203 {
204 return !memory_region_ioeventfd_before(a, b)
205 && !memory_region_ioeventfd_before(b, a);
206 }
207
208 /* Range of memory in the global map. Addresses are absolute. */
209 struct FlatRange {
210 MemoryRegion *mr;
211 hwaddr offset_in_region;
212 AddrRange addr;
213 uint8_t dirty_log_mask;
214 bool romd_mode;
215 bool readonly;
216 bool nonvolatile;
217 int has_coalesced_range;
218 };
219
220 #define FOR_EACH_FLAT_RANGE(var, view) \
221 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
222
223 static inline MemoryRegionSection
224 section_from_flat_range(FlatRange *fr, FlatView *fv)
225 {
226 return (MemoryRegionSection) {
227 .mr = fr->mr,
228 .fv = fv,
229 .offset_within_region = fr->offset_in_region,
230 .size = fr->addr.size,
231 .offset_within_address_space = int128_get64(fr->addr.start),
232 .readonly = fr->readonly,
233 .nonvolatile = fr->nonvolatile,
234 };
235 }
236
237 static bool flatrange_equal(FlatRange *a, FlatRange *b)
238 {
239 return a->mr == b->mr
240 && addrrange_equal(a->addr, b->addr)
241 && a->offset_in_region == b->offset_in_region
242 && a->romd_mode == b->romd_mode
243 && a->readonly == b->readonly
244 && a->nonvolatile == b->nonvolatile;
245 }
246
247 static FlatView *flatview_new(MemoryRegion *mr_root)
248 {
249 FlatView *view;
250
251 view = g_new0(FlatView, 1);
252 view->ref = 1;
253 view->root = mr_root;
254 memory_region_ref(mr_root);
255 trace_flatview_new(view, mr_root);
256
257 return view;
258 }
259
260 /* Insert a range into a given position. Caller is responsible for maintaining
261 * sorting order.
262 */
263 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
264 {
265 if (view->nr == view->nr_allocated) {
266 view->nr_allocated = MAX(2 * view->nr, 10);
267 view->ranges = g_realloc(view->ranges,
268 view->nr_allocated * sizeof(*view->ranges));
269 }
270 memmove(view->ranges + pos + 1, view->ranges + pos,
271 (view->nr - pos) * sizeof(FlatRange));
272 view->ranges[pos] = *range;
273 memory_region_ref(range->mr);
274 ++view->nr;
275 }
276
277 static void flatview_destroy(FlatView *view)
278 {
279 int i;
280
281 trace_flatview_destroy(view, view->root);
282 if (view->dispatch) {
283 address_space_dispatch_free(view->dispatch);
284 }
285 for (i = 0; i < view->nr; i++) {
286 memory_region_unref(view->ranges[i].mr);
287 }
288 g_free(view->ranges);
289 memory_region_unref(view->root);
290 g_free(view);
291 }
292
293 static bool flatview_ref(FlatView *view)
294 {
295 return atomic_fetch_inc_nonzero(&view->ref) > 0;
296 }
297
298 void flatview_unref(FlatView *view)
299 {
300 if (atomic_fetch_dec(&view->ref) == 1) {
301 trace_flatview_destroy_rcu(view, view->root);
302 assert(view->root);
303 call_rcu(view, flatview_destroy, rcu);
304 }
305 }
306
307 static bool can_merge(FlatRange *r1, FlatRange *r2)
308 {
309 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
310 && r1->mr == r2->mr
311 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
312 r1->addr.size),
313 int128_make64(r2->offset_in_region))
314 && r1->dirty_log_mask == r2->dirty_log_mask
315 && r1->romd_mode == r2->romd_mode
316 && r1->readonly == r2->readonly
317 && r1->nonvolatile == r2->nonvolatile;
318 }
319
320 /* Attempt to simplify a view by merging adjacent ranges */
321 static void flatview_simplify(FlatView *view)
322 {
323 unsigned i, j;
324
325 i = 0;
326 while (i < view->nr) {
327 j = i + 1;
328 while (j < view->nr
329 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
330 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
331 ++j;
332 }
333 ++i;
334 memmove(&view->ranges[i], &view->ranges[j],
335 (view->nr - j) * sizeof(view->ranges[j]));
336 view->nr -= j - i;
337 }
338 }
339
340 static bool memory_region_big_endian(MemoryRegion *mr)
341 {
342 #ifdef TARGET_WORDS_BIGENDIAN
343 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
344 #else
345 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
346 #endif
347 }
348
349 static bool memory_region_wrong_endianness(MemoryRegion *mr)
350 {
351 #ifdef TARGET_WORDS_BIGENDIAN
352 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
353 #else
354 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
355 #endif
356 }
357
358 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
359 {
360 if (memory_region_wrong_endianness(mr)) {
361 switch (size) {
362 case 1:
363 break;
364 case 2:
365 *data = bswap16(*data);
366 break;
367 case 4:
368 *data = bswap32(*data);
369 break;
370 case 8:
371 *data = bswap64(*data);
372 break;
373 default:
374 abort();
375 }
376 }
377 }
378
379 static inline void memory_region_shift_read_access(uint64_t *value,
380 signed shift,
381 uint64_t mask,
382 uint64_t tmp)
383 {
384 if (shift >= 0) {
385 *value |= (tmp & mask) << shift;
386 } else {
387 *value |= (tmp & mask) >> -shift;
388 }
389 }
390
391 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
392 signed shift,
393 uint64_t mask)
394 {
395 uint64_t tmp;
396
397 if (shift >= 0) {
398 tmp = (*value >> shift) & mask;
399 } else {
400 tmp = (*value << -shift) & mask;
401 }
402
403 return tmp;
404 }
405
406 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
407 {
408 MemoryRegion *root;
409 hwaddr abs_addr = offset;
410
411 abs_addr += mr->addr;
412 for (root = mr; root->container; ) {
413 root = root->container;
414 abs_addr += root->addr;
415 }
416
417 return abs_addr;
418 }
419
420 static int get_cpu_index(void)
421 {
422 if (current_cpu) {
423 return current_cpu->cpu_index;
424 }
425 return -1;
426 }
427
428 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
429 hwaddr addr,
430 uint64_t *value,
431 unsigned size,
432 signed shift,
433 uint64_t mask,
434 MemTxAttrs attrs)
435 {
436 uint64_t tmp;
437
438 tmp = mr->ops->read(mr->opaque, addr, size);
439 if (mr->subpage) {
440 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
441 } else if (mr == &io_mem_notdirty) {
442 /* Accesses to code which has previously been translated into a TB show
443 * up in the MMIO path, as accesses to the io_mem_notdirty
444 * MemoryRegion. */
445 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
446 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
447 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
448 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
449 }
450 memory_region_shift_read_access(value, shift, mask, tmp);
451 return MEMTX_OK;
452 }
453
454 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
455 hwaddr addr,
456 uint64_t *value,
457 unsigned size,
458 signed shift,
459 uint64_t mask,
460 MemTxAttrs attrs)
461 {
462 uint64_t tmp = 0;
463 MemTxResult r;
464
465 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
466 if (mr->subpage) {
467 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
468 } else if (mr == &io_mem_notdirty) {
469 /* Accesses to code which has previously been translated into a TB show
470 * up in the MMIO path, as accesses to the io_mem_notdirty
471 * MemoryRegion. */
472 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
473 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
474 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
475 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
476 }
477 memory_region_shift_read_access(value, shift, mask, tmp);
478 return r;
479 }
480
481 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
482 hwaddr addr,
483 uint64_t *value,
484 unsigned size,
485 signed shift,
486 uint64_t mask,
487 MemTxAttrs attrs)
488 {
489 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
490
491 if (mr->subpage) {
492 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
493 } else if (mr == &io_mem_notdirty) {
494 /* Accesses to code which has previously been translated into a TB show
495 * up in the MMIO path, as accesses to the io_mem_notdirty
496 * MemoryRegion. */
497 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
498 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
499 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
500 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
501 }
502 mr->ops->write(mr->opaque, addr, tmp, size);
503 return MEMTX_OK;
504 }
505
506 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
507 hwaddr addr,
508 uint64_t *value,
509 unsigned size,
510 signed shift,
511 uint64_t mask,
512 MemTxAttrs attrs)
513 {
514 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
515
516 if (mr->subpage) {
517 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
518 } else if (mr == &io_mem_notdirty) {
519 /* Accesses to code which has previously been translated into a TB show
520 * up in the MMIO path, as accesses to the io_mem_notdirty
521 * MemoryRegion. */
522 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
523 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
524 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
525 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
526 }
527 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
528 }
529
530 static MemTxResult access_with_adjusted_size(hwaddr addr,
531 uint64_t *value,
532 unsigned size,
533 unsigned access_size_min,
534 unsigned access_size_max,
535 MemTxResult (*access_fn)
536 (MemoryRegion *mr,
537 hwaddr addr,
538 uint64_t *value,
539 unsigned size,
540 signed shift,
541 uint64_t mask,
542 MemTxAttrs attrs),
543 MemoryRegion *mr,
544 MemTxAttrs attrs)
545 {
546 uint64_t access_mask;
547 unsigned access_size;
548 unsigned i;
549 MemTxResult r = MEMTX_OK;
550
551 if (!access_size_min) {
552 access_size_min = 1;
553 }
554 if (!access_size_max) {
555 access_size_max = 4;
556 }
557
558 /* FIXME: support unaligned access? */
559 access_size = MAX(MIN(size, access_size_max), access_size_min);
560 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
561 if (memory_region_big_endian(mr)) {
562 for (i = 0; i < size; i += access_size) {
563 r |= access_fn(mr, addr + i, value, access_size,
564 (size - access_size - i) * 8, access_mask, attrs);
565 }
566 } else {
567 for (i = 0; i < size; i += access_size) {
568 r |= access_fn(mr, addr + i, value, access_size, i * 8,
569 access_mask, attrs);
570 }
571 }
572 return r;
573 }
574
575 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
576 {
577 AddressSpace *as;
578
579 while (mr->container) {
580 mr = mr->container;
581 }
582 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
583 if (mr == as->root) {
584 return as;
585 }
586 }
587 return NULL;
588 }
589
590 /* Render a memory region into the global view. Ranges in @view obscure
591 * ranges in @mr.
592 */
593 static void render_memory_region(FlatView *view,
594 MemoryRegion *mr,
595 Int128 base,
596 AddrRange clip,
597 bool readonly,
598 bool nonvolatile)
599 {
600 MemoryRegion *subregion;
601 unsigned i;
602 hwaddr offset_in_region;
603 Int128 remain;
604 Int128 now;
605 FlatRange fr;
606 AddrRange tmp;
607
608 if (!mr->enabled) {
609 return;
610 }
611
612 int128_addto(&base, int128_make64(mr->addr));
613 readonly |= mr->readonly;
614 nonvolatile |= mr->nonvolatile;
615
616 tmp = addrrange_make(base, mr->size);
617
618 if (!addrrange_intersects(tmp, clip)) {
619 return;
620 }
621
622 clip = addrrange_intersection(tmp, clip);
623
624 if (mr->alias) {
625 int128_subfrom(&base, int128_make64(mr->alias->addr));
626 int128_subfrom(&base, int128_make64(mr->alias_offset));
627 render_memory_region(view, mr->alias, base, clip,
628 readonly, nonvolatile);
629 return;
630 }
631
632 /* Render subregions in priority order. */
633 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
634 render_memory_region(view, subregion, base, clip,
635 readonly, nonvolatile);
636 }
637
638 if (!mr->terminates) {
639 return;
640 }
641
642 offset_in_region = int128_get64(int128_sub(clip.start, base));
643 base = clip.start;
644 remain = clip.size;
645
646 fr.mr = mr;
647 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
648 fr.romd_mode = mr->romd_mode;
649 fr.readonly = readonly;
650 fr.nonvolatile = nonvolatile;
651 fr.has_coalesced_range = 0;
652
653 /* Render the region itself into any gaps left by the current view. */
654 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
655 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
656 continue;
657 }
658 if (int128_lt(base, view->ranges[i].addr.start)) {
659 now = int128_min(remain,
660 int128_sub(view->ranges[i].addr.start, base));
661 fr.offset_in_region = offset_in_region;
662 fr.addr = addrrange_make(base, now);
663 flatview_insert(view, i, &fr);
664 ++i;
665 int128_addto(&base, now);
666 offset_in_region += int128_get64(now);
667 int128_subfrom(&remain, now);
668 }
669 now = int128_sub(int128_min(int128_add(base, remain),
670 addrrange_end(view->ranges[i].addr)),
671 base);
672 int128_addto(&base, now);
673 offset_in_region += int128_get64(now);
674 int128_subfrom(&remain, now);
675 }
676 if (int128_nz(remain)) {
677 fr.offset_in_region = offset_in_region;
678 fr.addr = addrrange_make(base, remain);
679 flatview_insert(view, i, &fr);
680 }
681 }
682
683 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
684 {
685 while (mr->enabled) {
686 if (mr->alias) {
687 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
688 /* The alias is included in its entirety. Use it as
689 * the "real" root, so that we can share more FlatViews.
690 */
691 mr = mr->alias;
692 continue;
693 }
694 } else if (!mr->terminates) {
695 unsigned int found = 0;
696 MemoryRegion *child, *next = NULL;
697 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
698 if (child->enabled) {
699 if (++found > 1) {
700 next = NULL;
701 break;
702 }
703 if (!child->addr && int128_ge(mr->size, child->size)) {
704 /* A child is included in its entirety. If it's the only
705 * enabled one, use it in the hope of finding an alias down the
706 * way. This will also let us share FlatViews.
707 */
708 next = child;
709 }
710 }
711 }
712 if (found == 0) {
713 return NULL;
714 }
715 if (next) {
716 mr = next;
717 continue;
718 }
719 }
720
721 return mr;
722 }
723
724 return NULL;
725 }
726
727 /* Render a memory topology into a list of disjoint absolute ranges. */
728 static FlatView *generate_memory_topology(MemoryRegion *mr)
729 {
730 int i;
731 FlatView *view;
732
733 view = flatview_new(mr);
734
735 if (mr) {
736 render_memory_region(view, mr, int128_zero(),
737 addrrange_make(int128_zero(), int128_2_64()),
738 false, false);
739 }
740 flatview_simplify(view);
741
742 view->dispatch = address_space_dispatch_new(view);
743 for (i = 0; i < view->nr; i++) {
744 MemoryRegionSection mrs =
745 section_from_flat_range(&view->ranges[i], view);
746 flatview_add_to_dispatch(view, &mrs);
747 }
748 address_space_dispatch_compact(view->dispatch);
749 g_hash_table_replace(flat_views, mr, view);
750
751 return view;
752 }
753
754 static void address_space_add_del_ioeventfds(AddressSpace *as,
755 MemoryRegionIoeventfd *fds_new,
756 unsigned fds_new_nb,
757 MemoryRegionIoeventfd *fds_old,
758 unsigned fds_old_nb)
759 {
760 unsigned iold, inew;
761 MemoryRegionIoeventfd *fd;
762 MemoryRegionSection section;
763
764 /* Generate a symmetric difference of the old and new fd sets, adding
765 * and deleting as necessary.
766 */
767
768 iold = inew = 0;
769 while (iold < fds_old_nb || inew < fds_new_nb) {
770 if (iold < fds_old_nb
771 && (inew == fds_new_nb
772 || memory_region_ioeventfd_before(&fds_old[iold],
773 &fds_new[inew]))) {
774 fd = &fds_old[iold];
775 section = (MemoryRegionSection) {
776 .fv = address_space_to_flatview(as),
777 .offset_within_address_space = int128_get64(fd->addr.start),
778 .size = fd->addr.size,
779 };
780 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
781 fd->match_data, fd->data, fd->e);
782 ++iold;
783 } else if (inew < fds_new_nb
784 && (iold == fds_old_nb
785 || memory_region_ioeventfd_before(&fds_new[inew],
786 &fds_old[iold]))) {
787 fd = &fds_new[inew];
788 section = (MemoryRegionSection) {
789 .fv = address_space_to_flatview(as),
790 .offset_within_address_space = int128_get64(fd->addr.start),
791 .size = fd->addr.size,
792 };
793 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
794 fd->match_data, fd->data, fd->e);
795 ++inew;
796 } else {
797 ++iold;
798 ++inew;
799 }
800 }
801 }
802
803 FlatView *address_space_get_flatview(AddressSpace *as)
804 {
805 FlatView *view;
806
807 rcu_read_lock();
808 do {
809 view = address_space_to_flatview(as);
810 /* If somebody has replaced as->current_map concurrently,
811 * flatview_ref returns false.
812 */
813 } while (!flatview_ref(view));
814 rcu_read_unlock();
815 return view;
816 }
817
818 static void address_space_update_ioeventfds(AddressSpace *as)
819 {
820 FlatView *view;
821 FlatRange *fr;
822 unsigned ioeventfd_nb = 0;
823 MemoryRegionIoeventfd *ioeventfds = NULL;
824 AddrRange tmp;
825 unsigned i;
826
827 view = address_space_get_flatview(as);
828 FOR_EACH_FLAT_RANGE(fr, view) {
829 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
830 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
831 int128_sub(fr->addr.start,
832 int128_make64(fr->offset_in_region)));
833 if (addrrange_intersects(fr->addr, tmp)) {
834 ++ioeventfd_nb;
835 ioeventfds = g_realloc(ioeventfds,
836 ioeventfd_nb * sizeof(*ioeventfds));
837 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
838 ioeventfds[ioeventfd_nb-1].addr = tmp;
839 }
840 }
841 }
842
843 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
844 as->ioeventfds, as->ioeventfd_nb);
845
846 g_free(as->ioeventfds);
847 as->ioeventfds = ioeventfds;
848 as->ioeventfd_nb = ioeventfd_nb;
849 flatview_unref(view);
850 }
851
852 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
853 {
854 if (!fr->has_coalesced_range) {
855 return;
856 }
857
858 if (--fr->has_coalesced_range > 0) {
859 return;
860 }
861
862 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
863 int128_get64(fr->addr.start),
864 int128_get64(fr->addr.size));
865 }
866
867 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
868 {
869 MemoryRegion *mr = fr->mr;
870 CoalescedMemoryRange *cmr;
871 AddrRange tmp;
872
873 if (QTAILQ_EMPTY(&mr->coalesced)) {
874 return;
875 }
876
877 if (fr->has_coalesced_range++) {
878 return;
879 }
880
881 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
882 tmp = addrrange_shift(cmr->addr,
883 int128_sub(fr->addr.start,
884 int128_make64(fr->offset_in_region)));
885 if (!addrrange_intersects(tmp, fr->addr)) {
886 continue;
887 }
888 tmp = addrrange_intersection(tmp, fr->addr);
889 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
890 int128_get64(tmp.start),
891 int128_get64(tmp.size));
892 }
893 }
894
895 static void address_space_update_topology_pass(AddressSpace *as,
896 const FlatView *old_view,
897 const FlatView *new_view,
898 bool adding)
899 {
900 unsigned iold, inew;
901 FlatRange *frold, *frnew;
902
903 /* Generate a symmetric difference of the old and new memory maps.
904 * Kill ranges in the old map, and instantiate ranges in the new map.
905 */
906 iold = inew = 0;
907 while (iold < old_view->nr || inew < new_view->nr) {
908 if (iold < old_view->nr) {
909 frold = &old_view->ranges[iold];
910 } else {
911 frold = NULL;
912 }
913 if (inew < new_view->nr) {
914 frnew = &new_view->ranges[inew];
915 } else {
916 frnew = NULL;
917 }
918
919 if (frold
920 && (!frnew
921 || int128_lt(frold->addr.start, frnew->addr.start)
922 || (int128_eq(frold->addr.start, frnew->addr.start)
923 && !flatrange_equal(frold, frnew)))) {
924 /* In old but not in new, or in both but attributes changed. */
925
926 if (!adding) {
927 flat_range_coalesced_io_del(frold, as);
928 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
929 }
930
931 ++iold;
932 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
933 /* In both and unchanged (except logging may have changed) */
934
935 if (!adding) {
936 flat_range_coalesced_io_del(frold, as);
937 } else {
938 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
939 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
940 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
941 frold->dirty_log_mask,
942 frnew->dirty_log_mask);
943 }
944 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
945 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
946 frold->dirty_log_mask,
947 frnew->dirty_log_mask);
948 }
949 flat_range_coalesced_io_add(frnew, as);
950 }
951
952 ++iold;
953 ++inew;
954 } else {
955 /* In new */
956
957 if (adding) {
958 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
959 flat_range_coalesced_io_add(frnew, as);
960 }
961
962 ++inew;
963 }
964 }
965 }
966
967 static void flatviews_init(void)
968 {
969 static FlatView *empty_view;
970
971 if (flat_views) {
972 return;
973 }
974
975 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
976 (GDestroyNotify) flatview_unref);
977 if (!empty_view) {
978 empty_view = generate_memory_topology(NULL);
979 /* We keep it alive forever in the global variable. */
980 flatview_ref(empty_view);
981 } else {
982 g_hash_table_replace(flat_views, NULL, empty_view);
983 flatview_ref(empty_view);
984 }
985 }
986
987 static void flatviews_reset(void)
988 {
989 AddressSpace *as;
990
991 if (flat_views) {
992 g_hash_table_unref(flat_views);
993 flat_views = NULL;
994 }
995 flatviews_init();
996
997 /* Render unique FVs */
998 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
999 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1000
1001 if (g_hash_table_lookup(flat_views, physmr)) {
1002 continue;
1003 }
1004
1005 generate_memory_topology(physmr);
1006 }
1007 }
1008
1009 static void address_space_set_flatview(AddressSpace *as)
1010 {
1011 FlatView *old_view = address_space_to_flatview(as);
1012 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1013 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1014
1015 assert(new_view);
1016
1017 if (old_view == new_view) {
1018 return;
1019 }
1020
1021 if (old_view) {
1022 flatview_ref(old_view);
1023 }
1024
1025 flatview_ref(new_view);
1026
1027 if (!QTAILQ_EMPTY(&as->listeners)) {
1028 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1029
1030 if (!old_view2) {
1031 old_view2 = &tmpview;
1032 }
1033 address_space_update_topology_pass(as, old_view2, new_view, false);
1034 address_space_update_topology_pass(as, old_view2, new_view, true);
1035 }
1036
1037 /* Writes are protected by the BQL. */
1038 atomic_rcu_set(&as->current_map, new_view);
1039 if (old_view) {
1040 flatview_unref(old_view);
1041 }
1042
1043 /* Note that all the old MemoryRegions are still alive up to this
1044 * point. This relieves most MemoryListeners from the need to
1045 * ref/unref the MemoryRegions they get---unless they use them
1046 * outside the iothread mutex, in which case precise reference
1047 * counting is necessary.
1048 */
1049 if (old_view) {
1050 flatview_unref(old_view);
1051 }
1052 }
1053
1054 static void address_space_update_topology(AddressSpace *as)
1055 {
1056 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1057
1058 flatviews_init();
1059 if (!g_hash_table_lookup(flat_views, physmr)) {
1060 generate_memory_topology(physmr);
1061 }
1062 address_space_set_flatview(as);
1063 }
1064
1065 void memory_region_transaction_begin(void)
1066 {
1067 qemu_flush_coalesced_mmio_buffer();
1068 ++memory_region_transaction_depth;
1069 }
1070
1071 void memory_region_transaction_commit(void)
1072 {
1073 AddressSpace *as;
1074
1075 assert(memory_region_transaction_depth);
1076 assert(qemu_mutex_iothread_locked());
1077
1078 --memory_region_transaction_depth;
1079 if (!memory_region_transaction_depth) {
1080 if (memory_region_update_pending) {
1081 flatviews_reset();
1082
1083 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1084
1085 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1086 address_space_set_flatview(as);
1087 address_space_update_ioeventfds(as);
1088 }
1089 memory_region_update_pending = false;
1090 ioeventfd_update_pending = false;
1091 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1092 } else if (ioeventfd_update_pending) {
1093 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1094 address_space_update_ioeventfds(as);
1095 }
1096 ioeventfd_update_pending = false;
1097 }
1098 }
1099 }
1100
1101 static void memory_region_destructor_none(MemoryRegion *mr)
1102 {
1103 }
1104
1105 static void memory_region_destructor_ram(MemoryRegion *mr)
1106 {
1107 qemu_ram_free(mr->ram_block);
1108 }
1109
1110 static bool memory_region_need_escape(char c)
1111 {
1112 return c == '/' || c == '[' || c == '\\' || c == ']';
1113 }
1114
1115 static char *memory_region_escape_name(const char *name)
1116 {
1117 const char *p;
1118 char *escaped, *q;
1119 uint8_t c;
1120 size_t bytes = 0;
1121
1122 for (p = name; *p; p++) {
1123 bytes += memory_region_need_escape(*p) ? 4 : 1;
1124 }
1125 if (bytes == p - name) {
1126 return g_memdup(name, bytes + 1);
1127 }
1128
1129 escaped = g_malloc(bytes + 1);
1130 for (p = name, q = escaped; *p; p++) {
1131 c = *p;
1132 if (unlikely(memory_region_need_escape(c))) {
1133 *q++ = '\\';
1134 *q++ = 'x';
1135 *q++ = "0123456789abcdef"[c >> 4];
1136 c = "0123456789abcdef"[c & 15];
1137 }
1138 *q++ = c;
1139 }
1140 *q = 0;
1141 return escaped;
1142 }
1143
1144 static void memory_region_do_init(MemoryRegion *mr,
1145 Object *owner,
1146 const char *name,
1147 uint64_t size)
1148 {
1149 mr->size = int128_make64(size);
1150 if (size == UINT64_MAX) {
1151 mr->size = int128_2_64();
1152 }
1153 mr->name = g_strdup(name);
1154 mr->owner = owner;
1155 mr->ram_block = NULL;
1156
1157 if (name) {
1158 char *escaped_name = memory_region_escape_name(name);
1159 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1160
1161 if (!owner) {
1162 owner = container_get(qdev_get_machine(), "/unattached");
1163 }
1164
1165 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1166 object_unref(OBJECT(mr));
1167 g_free(name_array);
1168 g_free(escaped_name);
1169 }
1170 }
1171
1172 void memory_region_init(MemoryRegion *mr,
1173 Object *owner,
1174 const char *name,
1175 uint64_t size)
1176 {
1177 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1178 memory_region_do_init(mr, owner, name, size);
1179 }
1180
1181 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1182 void *opaque, Error **errp)
1183 {
1184 MemoryRegion *mr = MEMORY_REGION(obj);
1185 uint64_t value = mr->addr;
1186
1187 visit_type_uint64(v, name, &value, errp);
1188 }
1189
1190 static void memory_region_get_container(Object *obj, Visitor *v,
1191 const char *name, void *opaque,
1192 Error **errp)
1193 {
1194 MemoryRegion *mr = MEMORY_REGION(obj);
1195 gchar *path = (gchar *)"";
1196
1197 if (mr->container) {
1198 path = object_get_canonical_path(OBJECT(mr->container));
1199 }
1200 visit_type_str(v, name, &path, errp);
1201 if (mr->container) {
1202 g_free(path);
1203 }
1204 }
1205
1206 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1207 const char *part)
1208 {
1209 MemoryRegion *mr = MEMORY_REGION(obj);
1210
1211 return OBJECT(mr->container);
1212 }
1213
1214 static void memory_region_get_priority(Object *obj, Visitor *v,
1215 const char *name, void *opaque,
1216 Error **errp)
1217 {
1218 MemoryRegion *mr = MEMORY_REGION(obj);
1219 int32_t value = mr->priority;
1220
1221 visit_type_int32(v, name, &value, errp);
1222 }
1223
1224 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1225 void *opaque, Error **errp)
1226 {
1227 MemoryRegion *mr = MEMORY_REGION(obj);
1228 uint64_t value = memory_region_size(mr);
1229
1230 visit_type_uint64(v, name, &value, errp);
1231 }
1232
1233 static void memory_region_initfn(Object *obj)
1234 {
1235 MemoryRegion *mr = MEMORY_REGION(obj);
1236 ObjectProperty *op;
1237
1238 mr->ops = &unassigned_mem_ops;
1239 mr->enabled = true;
1240 mr->romd_mode = true;
1241 mr->global_locking = true;
1242 mr->destructor = memory_region_destructor_none;
1243 QTAILQ_INIT(&mr->subregions);
1244 QTAILQ_INIT(&mr->coalesced);
1245
1246 op = object_property_add(OBJECT(mr), "container",
1247 "link<" TYPE_MEMORY_REGION ">",
1248 memory_region_get_container,
1249 NULL, /* memory_region_set_container */
1250 NULL, NULL, &error_abort);
1251 op->resolve = memory_region_resolve_container;
1252
1253 object_property_add(OBJECT(mr), "addr", "uint64",
1254 memory_region_get_addr,
1255 NULL, /* memory_region_set_addr */
1256 NULL, NULL, &error_abort);
1257 object_property_add(OBJECT(mr), "priority", "uint32",
1258 memory_region_get_priority,
1259 NULL, /* memory_region_set_priority */
1260 NULL, NULL, &error_abort);
1261 object_property_add(OBJECT(mr), "size", "uint64",
1262 memory_region_get_size,
1263 NULL, /* memory_region_set_size, */
1264 NULL, NULL, &error_abort);
1265 }
1266
1267 static void iommu_memory_region_initfn(Object *obj)
1268 {
1269 MemoryRegion *mr = MEMORY_REGION(obj);
1270
1271 mr->is_iommu = true;
1272 }
1273
1274 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1275 unsigned size)
1276 {
1277 #ifdef DEBUG_UNASSIGNED
1278 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1279 #endif
1280 if (current_cpu != NULL) {
1281 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1282 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
1283 }
1284 return 0;
1285 }
1286
1287 static void unassigned_mem_write(void *opaque, hwaddr addr,
1288 uint64_t val, unsigned size)
1289 {
1290 #ifdef DEBUG_UNASSIGNED
1291 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1292 #endif
1293 if (current_cpu != NULL) {
1294 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1295 }
1296 }
1297
1298 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1299 unsigned size, bool is_write,
1300 MemTxAttrs attrs)
1301 {
1302 return false;
1303 }
1304
1305 const MemoryRegionOps unassigned_mem_ops = {
1306 .valid.accepts = unassigned_mem_accepts,
1307 .endianness = DEVICE_NATIVE_ENDIAN,
1308 };
1309
1310 static uint64_t memory_region_ram_device_read(void *opaque,
1311 hwaddr addr, unsigned size)
1312 {
1313 MemoryRegion *mr = opaque;
1314 uint64_t data = (uint64_t)~0;
1315
1316 switch (size) {
1317 case 1:
1318 data = *(uint8_t *)(mr->ram_block->host + addr);
1319 break;
1320 case 2:
1321 data = *(uint16_t *)(mr->ram_block->host + addr);
1322 break;
1323 case 4:
1324 data = *(uint32_t *)(mr->ram_block->host + addr);
1325 break;
1326 case 8:
1327 data = *(uint64_t *)(mr->ram_block->host + addr);
1328 break;
1329 }
1330
1331 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1332
1333 return data;
1334 }
1335
1336 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1337 uint64_t data, unsigned size)
1338 {
1339 MemoryRegion *mr = opaque;
1340
1341 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1342
1343 switch (size) {
1344 case 1:
1345 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1346 break;
1347 case 2:
1348 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1349 break;
1350 case 4:
1351 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1352 break;
1353 case 8:
1354 *(uint64_t *)(mr->ram_block->host + addr) = data;
1355 break;
1356 }
1357 }
1358
1359 static const MemoryRegionOps ram_device_mem_ops = {
1360 .read = memory_region_ram_device_read,
1361 .write = memory_region_ram_device_write,
1362 .endianness = DEVICE_HOST_ENDIAN,
1363 .valid = {
1364 .min_access_size = 1,
1365 .max_access_size = 8,
1366 .unaligned = true,
1367 },
1368 .impl = {
1369 .min_access_size = 1,
1370 .max_access_size = 8,
1371 .unaligned = true,
1372 },
1373 };
1374
1375 bool memory_region_access_valid(MemoryRegion *mr,
1376 hwaddr addr,
1377 unsigned size,
1378 bool is_write,
1379 MemTxAttrs attrs)
1380 {
1381 int access_size_min, access_size_max;
1382 int access_size, i;
1383
1384 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1385 return false;
1386 }
1387
1388 if (!mr->ops->valid.accepts) {
1389 return true;
1390 }
1391
1392 access_size_min = mr->ops->valid.min_access_size;
1393 if (!mr->ops->valid.min_access_size) {
1394 access_size_min = 1;
1395 }
1396
1397 access_size_max = mr->ops->valid.max_access_size;
1398 if (!mr->ops->valid.max_access_size) {
1399 access_size_max = 4;
1400 }
1401
1402 access_size = MAX(MIN(size, access_size_max), access_size_min);
1403 for (i = 0; i < size; i += access_size) {
1404 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1405 is_write, attrs)) {
1406 return false;
1407 }
1408 }
1409
1410 return true;
1411 }
1412
1413 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1414 hwaddr addr,
1415 uint64_t *pval,
1416 unsigned size,
1417 MemTxAttrs attrs)
1418 {
1419 *pval = 0;
1420
1421 if (mr->ops->read) {
1422 return access_with_adjusted_size(addr, pval, size,
1423 mr->ops->impl.min_access_size,
1424 mr->ops->impl.max_access_size,
1425 memory_region_read_accessor,
1426 mr, attrs);
1427 } else {
1428 return access_with_adjusted_size(addr, pval, size,
1429 mr->ops->impl.min_access_size,
1430 mr->ops->impl.max_access_size,
1431 memory_region_read_with_attrs_accessor,
1432 mr, attrs);
1433 }
1434 }
1435
1436 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1437 hwaddr addr,
1438 uint64_t *pval,
1439 unsigned size,
1440 MemTxAttrs attrs)
1441 {
1442 MemTxResult r;
1443
1444 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1445 *pval = unassigned_mem_read(mr, addr, size);
1446 return MEMTX_DECODE_ERROR;
1447 }
1448
1449 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1450 adjust_endianness(mr, pval, size);
1451 return r;
1452 }
1453
1454 /* Return true if an eventfd was signalled */
1455 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1456 hwaddr addr,
1457 uint64_t data,
1458 unsigned size,
1459 MemTxAttrs attrs)
1460 {
1461 MemoryRegionIoeventfd ioeventfd = {
1462 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1463 .data = data,
1464 };
1465 unsigned i;
1466
1467 for (i = 0; i < mr->ioeventfd_nb; i++) {
1468 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1469 ioeventfd.e = mr->ioeventfds[i].e;
1470
1471 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1472 event_notifier_set(ioeventfd.e);
1473 return true;
1474 }
1475 }
1476
1477 return false;
1478 }
1479
1480 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1481 hwaddr addr,
1482 uint64_t data,
1483 unsigned size,
1484 MemTxAttrs attrs)
1485 {
1486 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1487 unassigned_mem_write(mr, addr, data, size);
1488 return MEMTX_DECODE_ERROR;
1489 }
1490
1491 adjust_endianness(mr, &data, size);
1492
1493 if ((!kvm_eventfds_enabled()) &&
1494 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1495 return MEMTX_OK;
1496 }
1497
1498 if (mr->ops->write) {
1499 return access_with_adjusted_size(addr, &data, size,
1500 mr->ops->impl.min_access_size,
1501 mr->ops->impl.max_access_size,
1502 memory_region_write_accessor, mr,
1503 attrs);
1504 } else {
1505 return
1506 access_with_adjusted_size(addr, &data, size,
1507 mr->ops->impl.min_access_size,
1508 mr->ops->impl.max_access_size,
1509 memory_region_write_with_attrs_accessor,
1510 mr, attrs);
1511 }
1512 }
1513
1514 void memory_region_init_io(MemoryRegion *mr,
1515 Object *owner,
1516 const MemoryRegionOps *ops,
1517 void *opaque,
1518 const char *name,
1519 uint64_t size)
1520 {
1521 memory_region_init(mr, owner, name, size);
1522 mr->ops = ops ? ops : &unassigned_mem_ops;
1523 mr->opaque = opaque;
1524 mr->terminates = true;
1525 }
1526
1527 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1528 Object *owner,
1529 const char *name,
1530 uint64_t size,
1531 Error **errp)
1532 {
1533 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1534 }
1535
1536 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1537 Object *owner,
1538 const char *name,
1539 uint64_t size,
1540 bool share,
1541 Error **errp)
1542 {
1543 Error *err = NULL;
1544 memory_region_init(mr, owner, name, size);
1545 mr->ram = true;
1546 mr->terminates = true;
1547 mr->destructor = memory_region_destructor_ram;
1548 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1549 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1550 if (err) {
1551 mr->size = int128_zero();
1552 object_unparent(OBJECT(mr));
1553 error_propagate(errp, err);
1554 }
1555 }
1556
1557 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1558 Object *owner,
1559 const char *name,
1560 uint64_t size,
1561 uint64_t max_size,
1562 void (*resized)(const char*,
1563 uint64_t length,
1564 void *host),
1565 Error **errp)
1566 {
1567 Error *err = NULL;
1568 memory_region_init(mr, owner, name, size);
1569 mr->ram = true;
1570 mr->terminates = true;
1571 mr->destructor = memory_region_destructor_ram;
1572 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1573 mr, &err);
1574 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1575 if (err) {
1576 mr->size = int128_zero();
1577 object_unparent(OBJECT(mr));
1578 error_propagate(errp, err);
1579 }
1580 }
1581
1582 #ifdef CONFIG_POSIX
1583 void memory_region_init_ram_from_file(MemoryRegion *mr,
1584 struct Object *owner,
1585 const char *name,
1586 uint64_t size,
1587 uint64_t align,
1588 uint32_t ram_flags,
1589 const char *path,
1590 Error **errp)
1591 {
1592 Error *err = NULL;
1593 memory_region_init(mr, owner, name, size);
1594 mr->ram = true;
1595 mr->terminates = true;
1596 mr->destructor = memory_region_destructor_ram;
1597 mr->align = align;
1598 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1599 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1600 if (err) {
1601 mr->size = int128_zero();
1602 object_unparent(OBJECT(mr));
1603 error_propagate(errp, err);
1604 }
1605 }
1606
1607 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1608 struct Object *owner,
1609 const char *name,
1610 uint64_t size,
1611 bool share,
1612 int fd,
1613 Error **errp)
1614 {
1615 Error *err = NULL;
1616 memory_region_init(mr, owner, name, size);
1617 mr->ram = true;
1618 mr->terminates = true;
1619 mr->destructor = memory_region_destructor_ram;
1620 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1621 share ? RAM_SHARED : 0,
1622 fd, &err);
1623 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1624 if (err) {
1625 mr->size = int128_zero();
1626 object_unparent(OBJECT(mr));
1627 error_propagate(errp, err);
1628 }
1629 }
1630 #endif
1631
1632 void memory_region_init_ram_ptr(MemoryRegion *mr,
1633 Object *owner,
1634 const char *name,
1635 uint64_t size,
1636 void *ptr)
1637 {
1638 memory_region_init(mr, owner, name, size);
1639 mr->ram = true;
1640 mr->terminates = true;
1641 mr->destructor = memory_region_destructor_ram;
1642 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1643
1644 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1645 assert(ptr != NULL);
1646 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1647 }
1648
1649 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1650 Object *owner,
1651 const char *name,
1652 uint64_t size,
1653 void *ptr)
1654 {
1655 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1656 mr->ram_device = true;
1657 mr->ops = &ram_device_mem_ops;
1658 mr->opaque = mr;
1659 }
1660
1661 void memory_region_init_alias(MemoryRegion *mr,
1662 Object *owner,
1663 const char *name,
1664 MemoryRegion *orig,
1665 hwaddr offset,
1666 uint64_t size)
1667 {
1668 memory_region_init(mr, owner, name, size);
1669 mr->alias = orig;
1670 mr->alias_offset = offset;
1671 }
1672
1673 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1674 struct Object *owner,
1675 const char *name,
1676 uint64_t size,
1677 Error **errp)
1678 {
1679 Error *err = NULL;
1680 memory_region_init(mr, owner, name, size);
1681 mr->ram = true;
1682 mr->readonly = true;
1683 mr->terminates = true;
1684 mr->destructor = memory_region_destructor_ram;
1685 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1686 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1687 if (err) {
1688 mr->size = int128_zero();
1689 object_unparent(OBJECT(mr));
1690 error_propagate(errp, err);
1691 }
1692 }
1693
1694 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1695 Object *owner,
1696 const MemoryRegionOps *ops,
1697 void *opaque,
1698 const char *name,
1699 uint64_t size,
1700 Error **errp)
1701 {
1702 Error *err = NULL;
1703 assert(ops);
1704 memory_region_init(mr, owner, name, size);
1705 mr->ops = ops;
1706 mr->opaque = opaque;
1707 mr->terminates = true;
1708 mr->rom_device = true;
1709 mr->destructor = memory_region_destructor_ram;
1710 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1711 if (err) {
1712 mr->size = int128_zero();
1713 object_unparent(OBJECT(mr));
1714 error_propagate(errp, err);
1715 }
1716 }
1717
1718 void memory_region_init_iommu(void *_iommu_mr,
1719 size_t instance_size,
1720 const char *mrtypename,
1721 Object *owner,
1722 const char *name,
1723 uint64_t size)
1724 {
1725 struct IOMMUMemoryRegion *iommu_mr;
1726 struct MemoryRegion *mr;
1727
1728 object_initialize(_iommu_mr, instance_size, mrtypename);
1729 mr = MEMORY_REGION(_iommu_mr);
1730 memory_region_do_init(mr, owner, name, size);
1731 iommu_mr = IOMMU_MEMORY_REGION(mr);
1732 mr->terminates = true; /* then re-forwards */
1733 QLIST_INIT(&iommu_mr->iommu_notify);
1734 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1735 }
1736
1737 static void memory_region_finalize(Object *obj)
1738 {
1739 MemoryRegion *mr = MEMORY_REGION(obj);
1740
1741 assert(!mr->container);
1742
1743 /* We know the region is not visible in any address space (it
1744 * does not have a container and cannot be a root either because
1745 * it has no references, so we can blindly clear mr->enabled.
1746 * memory_region_set_enabled instead could trigger a transaction
1747 * and cause an infinite loop.
1748 */
1749 mr->enabled = false;
1750 memory_region_transaction_begin();
1751 while (!QTAILQ_EMPTY(&mr->subregions)) {
1752 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1753 memory_region_del_subregion(mr, subregion);
1754 }
1755 memory_region_transaction_commit();
1756
1757 mr->destructor(mr);
1758 memory_region_clear_coalescing(mr);
1759 g_free((char *)mr->name);
1760 g_free(mr->ioeventfds);
1761 }
1762
1763 Object *memory_region_owner(MemoryRegion *mr)
1764 {
1765 Object *obj = OBJECT(mr);
1766 return obj->parent;
1767 }
1768
1769 void memory_region_ref(MemoryRegion *mr)
1770 {
1771 /* MMIO callbacks most likely will access data that belongs
1772 * to the owner, hence the need to ref/unref the owner whenever
1773 * the memory region is in use.
1774 *
1775 * The memory region is a child of its owner. As long as the
1776 * owner doesn't call unparent itself on the memory region,
1777 * ref-ing the owner will also keep the memory region alive.
1778 * Memory regions without an owner are supposed to never go away;
1779 * we do not ref/unref them because it slows down DMA sensibly.
1780 */
1781 if (mr && mr->owner) {
1782 object_ref(mr->owner);
1783 }
1784 }
1785
1786 void memory_region_unref(MemoryRegion *mr)
1787 {
1788 if (mr && mr->owner) {
1789 object_unref(mr->owner);
1790 }
1791 }
1792
1793 uint64_t memory_region_size(MemoryRegion *mr)
1794 {
1795 if (int128_eq(mr->size, int128_2_64())) {
1796 return UINT64_MAX;
1797 }
1798 return int128_get64(mr->size);
1799 }
1800
1801 const char *memory_region_name(const MemoryRegion *mr)
1802 {
1803 if (!mr->name) {
1804 ((MemoryRegion *)mr)->name =
1805 object_get_canonical_path_component(OBJECT(mr));
1806 }
1807 return mr->name;
1808 }
1809
1810 bool memory_region_is_ram_device(MemoryRegion *mr)
1811 {
1812 return mr->ram_device;
1813 }
1814
1815 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1816 {
1817 uint8_t mask = mr->dirty_log_mask;
1818 if (global_dirty_log && mr->ram_block) {
1819 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1820 }
1821 return mask;
1822 }
1823
1824 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1825 {
1826 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1827 }
1828
1829 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1830 {
1831 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1832 IOMMUNotifier *iommu_notifier;
1833 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1834
1835 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1836 flags |= iommu_notifier->notifier_flags;
1837 }
1838
1839 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1840 imrc->notify_flag_changed(iommu_mr,
1841 iommu_mr->iommu_notify_flags,
1842 flags);
1843 }
1844
1845 iommu_mr->iommu_notify_flags = flags;
1846 }
1847
1848 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1849 IOMMUNotifier *n)
1850 {
1851 IOMMUMemoryRegion *iommu_mr;
1852
1853 if (mr->alias) {
1854 memory_region_register_iommu_notifier(mr->alias, n);
1855 return;
1856 }
1857
1858 /* We need to register for at least one bitfield */
1859 iommu_mr = IOMMU_MEMORY_REGION(mr);
1860 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1861 assert(n->start <= n->end);
1862 assert(n->iommu_idx >= 0 &&
1863 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1864
1865 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1866 memory_region_update_iommu_notify_flags(iommu_mr);
1867 }
1868
1869 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1870 {
1871 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1872
1873 if (imrc->get_min_page_size) {
1874 return imrc->get_min_page_size(iommu_mr);
1875 }
1876 return TARGET_PAGE_SIZE;
1877 }
1878
1879 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1880 {
1881 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1882 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1883 hwaddr addr, granularity;
1884 IOMMUTLBEntry iotlb;
1885
1886 /* If the IOMMU has its own replay callback, override */
1887 if (imrc->replay) {
1888 imrc->replay(iommu_mr, n);
1889 return;
1890 }
1891
1892 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1893
1894 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1895 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1896 if (iotlb.perm != IOMMU_NONE) {
1897 n->notify(n, &iotlb);
1898 }
1899
1900 /* if (2^64 - MR size) < granularity, it's possible to get an
1901 * infinite loop here. This should catch such a wraparound */
1902 if ((addr + granularity) < addr) {
1903 break;
1904 }
1905 }
1906 }
1907
1908 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1909 {
1910 IOMMUNotifier *notifier;
1911
1912 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1913 memory_region_iommu_replay(iommu_mr, notifier);
1914 }
1915 }
1916
1917 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1918 IOMMUNotifier *n)
1919 {
1920 IOMMUMemoryRegion *iommu_mr;
1921
1922 if (mr->alias) {
1923 memory_region_unregister_iommu_notifier(mr->alias, n);
1924 return;
1925 }
1926 QLIST_REMOVE(n, node);
1927 iommu_mr = IOMMU_MEMORY_REGION(mr);
1928 memory_region_update_iommu_notify_flags(iommu_mr);
1929 }
1930
1931 void memory_region_notify_one(IOMMUNotifier *notifier,
1932 IOMMUTLBEntry *entry)
1933 {
1934 IOMMUNotifierFlag request_flags;
1935
1936 /*
1937 * Skip the notification if the notification does not overlap
1938 * with registered range.
1939 */
1940 if (notifier->start > entry->iova + entry->addr_mask ||
1941 notifier->end < entry->iova) {
1942 return;
1943 }
1944
1945 if (entry->perm & IOMMU_RW) {
1946 request_flags = IOMMU_NOTIFIER_MAP;
1947 } else {
1948 request_flags = IOMMU_NOTIFIER_UNMAP;
1949 }
1950
1951 if (notifier->notifier_flags & request_flags) {
1952 notifier->notify(notifier, entry);
1953 }
1954 }
1955
1956 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1957 int iommu_idx,
1958 IOMMUTLBEntry entry)
1959 {
1960 IOMMUNotifier *iommu_notifier;
1961
1962 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1963
1964 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1965 if (iommu_notifier->iommu_idx == iommu_idx) {
1966 memory_region_notify_one(iommu_notifier, &entry);
1967 }
1968 }
1969 }
1970
1971 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1972 enum IOMMUMemoryRegionAttr attr,
1973 void *data)
1974 {
1975 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1976
1977 if (!imrc->get_attr) {
1978 return -EINVAL;
1979 }
1980
1981 return imrc->get_attr(iommu_mr, attr, data);
1982 }
1983
1984 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1985 MemTxAttrs attrs)
1986 {
1987 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1988
1989 if (!imrc->attrs_to_index) {
1990 return 0;
1991 }
1992
1993 return imrc->attrs_to_index(iommu_mr, attrs);
1994 }
1995
1996 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1997 {
1998 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1999
2000 if (!imrc->num_indexes) {
2001 return 1;
2002 }
2003
2004 return imrc->num_indexes(iommu_mr);
2005 }
2006
2007 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2008 {
2009 uint8_t mask = 1 << client;
2010 uint8_t old_logging;
2011
2012 assert(client == DIRTY_MEMORY_VGA);
2013 old_logging = mr->vga_logging_count;
2014 mr->vga_logging_count += log ? 1 : -1;
2015 if (!!old_logging == !!mr->vga_logging_count) {
2016 return;
2017 }
2018
2019 memory_region_transaction_begin();
2020 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2021 memory_region_update_pending |= mr->enabled;
2022 memory_region_transaction_commit();
2023 }
2024
2025 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
2026 hwaddr size, unsigned client)
2027 {
2028 assert(mr->ram_block);
2029 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
2030 size, client);
2031 }
2032
2033 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2034 hwaddr size)
2035 {
2036 assert(mr->ram_block);
2037 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2038 size,
2039 memory_region_get_dirty_log_mask(mr));
2040 }
2041
2042 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2043 {
2044 MemoryListener *listener;
2045 AddressSpace *as;
2046 FlatView *view;
2047 FlatRange *fr;
2048
2049 /* If the same address space has multiple log_sync listeners, we
2050 * visit that address space's FlatView multiple times. But because
2051 * log_sync listeners are rare, it's still cheaper than walking each
2052 * address space once.
2053 */
2054 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2055 if (!listener->log_sync) {
2056 continue;
2057 }
2058 as = listener->address_space;
2059 view = address_space_get_flatview(as);
2060 FOR_EACH_FLAT_RANGE(fr, view) {
2061 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2062 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2063 listener->log_sync(listener, &mrs);
2064 }
2065 }
2066 flatview_unref(view);
2067 }
2068 }
2069
2070 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2071 hwaddr addr,
2072 hwaddr size,
2073 unsigned client)
2074 {
2075 assert(mr->ram_block);
2076 memory_region_sync_dirty_bitmap(mr);
2077 return cpu_physical_memory_snapshot_and_clear_dirty(
2078 memory_region_get_ram_addr(mr) + addr, size, client);
2079 }
2080
2081 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2082 hwaddr addr, hwaddr size)
2083 {
2084 assert(mr->ram_block);
2085 return cpu_physical_memory_snapshot_get_dirty(snap,
2086 memory_region_get_ram_addr(mr) + addr, size);
2087 }
2088
2089 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2090 {
2091 if (mr->readonly != readonly) {
2092 memory_region_transaction_begin();
2093 mr->readonly = readonly;
2094 memory_region_update_pending |= mr->enabled;
2095 memory_region_transaction_commit();
2096 }
2097 }
2098
2099 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2100 {
2101 if (mr->nonvolatile != nonvolatile) {
2102 memory_region_transaction_begin();
2103 mr->nonvolatile = nonvolatile;
2104 memory_region_update_pending |= mr->enabled;
2105 memory_region_transaction_commit();
2106 }
2107 }
2108
2109 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2110 {
2111 if (mr->romd_mode != romd_mode) {
2112 memory_region_transaction_begin();
2113 mr->romd_mode = romd_mode;
2114 memory_region_update_pending |= mr->enabled;
2115 memory_region_transaction_commit();
2116 }
2117 }
2118
2119 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2120 hwaddr size, unsigned client)
2121 {
2122 assert(mr->ram_block);
2123 cpu_physical_memory_test_and_clear_dirty(
2124 memory_region_get_ram_addr(mr) + addr, size, client);
2125 }
2126
2127 int memory_region_get_fd(MemoryRegion *mr)
2128 {
2129 int fd;
2130
2131 rcu_read_lock();
2132 while (mr->alias) {
2133 mr = mr->alias;
2134 }
2135 fd = mr->ram_block->fd;
2136 rcu_read_unlock();
2137
2138 return fd;
2139 }
2140
2141 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2142 {
2143 void *ptr;
2144 uint64_t offset = 0;
2145
2146 rcu_read_lock();
2147 while (mr->alias) {
2148 offset += mr->alias_offset;
2149 mr = mr->alias;
2150 }
2151 assert(mr->ram_block);
2152 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2153 rcu_read_unlock();
2154
2155 return ptr;
2156 }
2157
2158 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2159 {
2160 RAMBlock *block;
2161
2162 block = qemu_ram_block_from_host(ptr, false, offset);
2163 if (!block) {
2164 return NULL;
2165 }
2166
2167 return block->mr;
2168 }
2169
2170 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2171 {
2172 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2173 }
2174
2175 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2176 {
2177 assert(mr->ram_block);
2178
2179 qemu_ram_resize(mr->ram_block, newsize, errp);
2180 }
2181
2182 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2183 {
2184 FlatView *view;
2185 FlatRange *fr;
2186
2187 view = address_space_get_flatview(as);
2188 FOR_EACH_FLAT_RANGE(fr, view) {
2189 if (fr->mr == mr) {
2190 flat_range_coalesced_io_del(fr, as);
2191 flat_range_coalesced_io_add(fr, as);
2192 }
2193 }
2194 flatview_unref(view);
2195 }
2196
2197 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2198 {
2199 AddressSpace *as;
2200
2201 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2202 memory_region_update_coalesced_range_as(mr, as);
2203 }
2204 }
2205
2206 void memory_region_set_coalescing(MemoryRegion *mr)
2207 {
2208 memory_region_clear_coalescing(mr);
2209 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2210 }
2211
2212 void memory_region_add_coalescing(MemoryRegion *mr,
2213 hwaddr offset,
2214 uint64_t size)
2215 {
2216 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2217
2218 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2219 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2220 memory_region_update_coalesced_range(mr);
2221 memory_region_set_flush_coalesced(mr);
2222 }
2223
2224 void memory_region_clear_coalescing(MemoryRegion *mr)
2225 {
2226 CoalescedMemoryRange *cmr;
2227 bool updated = false;
2228
2229 qemu_flush_coalesced_mmio_buffer();
2230 mr->flush_coalesced_mmio = false;
2231
2232 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2233 cmr = QTAILQ_FIRST(&mr->coalesced);
2234 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2235 g_free(cmr);
2236 updated = true;
2237 }
2238
2239 if (updated) {
2240 memory_region_update_coalesced_range(mr);
2241 }
2242 }
2243
2244 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2245 {
2246 mr->flush_coalesced_mmio = true;
2247 }
2248
2249 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2250 {
2251 qemu_flush_coalesced_mmio_buffer();
2252 if (QTAILQ_EMPTY(&mr->coalesced)) {
2253 mr->flush_coalesced_mmio = false;
2254 }
2255 }
2256
2257 void memory_region_clear_global_locking(MemoryRegion *mr)
2258 {
2259 mr->global_locking = false;
2260 }
2261
2262 static bool userspace_eventfd_warning;
2263
2264 void memory_region_add_eventfd(MemoryRegion *mr,
2265 hwaddr addr,
2266 unsigned size,
2267 bool match_data,
2268 uint64_t data,
2269 EventNotifier *e)
2270 {
2271 MemoryRegionIoeventfd mrfd = {
2272 .addr.start = int128_make64(addr),
2273 .addr.size = int128_make64(size),
2274 .match_data = match_data,
2275 .data = data,
2276 .e = e,
2277 };
2278 unsigned i;
2279
2280 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2281 userspace_eventfd_warning))) {
2282 userspace_eventfd_warning = true;
2283 error_report("Using eventfd without MMIO binding in KVM. "
2284 "Suboptimal performance expected");
2285 }
2286
2287 if (size) {
2288 adjust_endianness(mr, &mrfd.data, size);
2289 }
2290 memory_region_transaction_begin();
2291 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2292 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2293 break;
2294 }
2295 }
2296 ++mr->ioeventfd_nb;
2297 mr->ioeventfds = g_realloc(mr->ioeventfds,
2298 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2299 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2300 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2301 mr->ioeventfds[i] = mrfd;
2302 ioeventfd_update_pending |= mr->enabled;
2303 memory_region_transaction_commit();
2304 }
2305
2306 void memory_region_del_eventfd(MemoryRegion *mr,
2307 hwaddr addr,
2308 unsigned size,
2309 bool match_data,
2310 uint64_t data,
2311 EventNotifier *e)
2312 {
2313 MemoryRegionIoeventfd mrfd = {
2314 .addr.start = int128_make64(addr),
2315 .addr.size = int128_make64(size),
2316 .match_data = match_data,
2317 .data = data,
2318 .e = e,
2319 };
2320 unsigned i;
2321
2322 if (size) {
2323 adjust_endianness(mr, &mrfd.data, size);
2324 }
2325 memory_region_transaction_begin();
2326 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2327 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2328 break;
2329 }
2330 }
2331 assert(i != mr->ioeventfd_nb);
2332 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2333 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2334 --mr->ioeventfd_nb;
2335 mr->ioeventfds = g_realloc(mr->ioeventfds,
2336 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2337 ioeventfd_update_pending |= mr->enabled;
2338 memory_region_transaction_commit();
2339 }
2340
2341 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2342 {
2343 MemoryRegion *mr = subregion->container;
2344 MemoryRegion *other;
2345
2346 memory_region_transaction_begin();
2347
2348 memory_region_ref(subregion);
2349 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2350 if (subregion->priority >= other->priority) {
2351 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2352 goto done;
2353 }
2354 }
2355 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2356 done:
2357 memory_region_update_pending |= mr->enabled && subregion->enabled;
2358 memory_region_transaction_commit();
2359 }
2360
2361 static void memory_region_add_subregion_common(MemoryRegion *mr,
2362 hwaddr offset,
2363 MemoryRegion *subregion)
2364 {
2365 assert(!subregion->container);
2366 subregion->container = mr;
2367 subregion->addr = offset;
2368 memory_region_update_container_subregions(subregion);
2369 }
2370
2371 void memory_region_add_subregion(MemoryRegion *mr,
2372 hwaddr offset,
2373 MemoryRegion *subregion)
2374 {
2375 subregion->priority = 0;
2376 memory_region_add_subregion_common(mr, offset, subregion);
2377 }
2378
2379 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2380 hwaddr offset,
2381 MemoryRegion *subregion,
2382 int priority)
2383 {
2384 subregion->priority = priority;
2385 memory_region_add_subregion_common(mr, offset, subregion);
2386 }
2387
2388 void memory_region_del_subregion(MemoryRegion *mr,
2389 MemoryRegion *subregion)
2390 {
2391 memory_region_transaction_begin();
2392 assert(subregion->container == mr);
2393 subregion->container = NULL;
2394 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2395 memory_region_unref(subregion);
2396 memory_region_update_pending |= mr->enabled && subregion->enabled;
2397 memory_region_transaction_commit();
2398 }
2399
2400 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2401 {
2402 if (enabled == mr->enabled) {
2403 return;
2404 }
2405 memory_region_transaction_begin();
2406 mr->enabled = enabled;
2407 memory_region_update_pending = true;
2408 memory_region_transaction_commit();
2409 }
2410
2411 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2412 {
2413 Int128 s = int128_make64(size);
2414
2415 if (size == UINT64_MAX) {
2416 s = int128_2_64();
2417 }
2418 if (int128_eq(s, mr->size)) {
2419 return;
2420 }
2421 memory_region_transaction_begin();
2422 mr->size = s;
2423 memory_region_update_pending = true;
2424 memory_region_transaction_commit();
2425 }
2426
2427 static void memory_region_readd_subregion(MemoryRegion *mr)
2428 {
2429 MemoryRegion *container = mr->container;
2430
2431 if (container) {
2432 memory_region_transaction_begin();
2433 memory_region_ref(mr);
2434 memory_region_del_subregion(container, mr);
2435 mr->container = container;
2436 memory_region_update_container_subregions(mr);
2437 memory_region_unref(mr);
2438 memory_region_transaction_commit();
2439 }
2440 }
2441
2442 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2443 {
2444 if (addr != mr->addr) {
2445 mr->addr = addr;
2446 memory_region_readd_subregion(mr);
2447 }
2448 }
2449
2450 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2451 {
2452 assert(mr->alias);
2453
2454 if (offset == mr->alias_offset) {
2455 return;
2456 }
2457
2458 memory_region_transaction_begin();
2459 mr->alias_offset = offset;
2460 memory_region_update_pending |= mr->enabled;
2461 memory_region_transaction_commit();
2462 }
2463
2464 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2465 {
2466 return mr->align;
2467 }
2468
2469 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2470 {
2471 const AddrRange *addr = addr_;
2472 const FlatRange *fr = fr_;
2473
2474 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2475 return -1;
2476 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2477 return 1;
2478 }
2479 return 0;
2480 }
2481
2482 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2483 {
2484 return bsearch(&addr, view->ranges, view->nr,
2485 sizeof(FlatRange), cmp_flatrange_addr);
2486 }
2487
2488 bool memory_region_is_mapped(MemoryRegion *mr)
2489 {
2490 return mr->container ? true : false;
2491 }
2492
2493 /* Same as memory_region_find, but it does not add a reference to the
2494 * returned region. It must be called from an RCU critical section.
2495 */
2496 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2497 hwaddr addr, uint64_t size)
2498 {
2499 MemoryRegionSection ret = { .mr = NULL };
2500 MemoryRegion *root;
2501 AddressSpace *as;
2502 AddrRange range;
2503 FlatView *view;
2504 FlatRange *fr;
2505
2506 addr += mr->addr;
2507 for (root = mr; root->container; ) {
2508 root = root->container;
2509 addr += root->addr;
2510 }
2511
2512 as = memory_region_to_address_space(root);
2513 if (!as) {
2514 return ret;
2515 }
2516 range = addrrange_make(int128_make64(addr), int128_make64(size));
2517
2518 view = address_space_to_flatview(as);
2519 fr = flatview_lookup(view, range);
2520 if (!fr) {
2521 return ret;
2522 }
2523
2524 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2525 --fr;
2526 }
2527
2528 ret.mr = fr->mr;
2529 ret.fv = view;
2530 range = addrrange_intersection(range, fr->addr);
2531 ret.offset_within_region = fr->offset_in_region;
2532 ret.offset_within_region += int128_get64(int128_sub(range.start,
2533 fr->addr.start));
2534 ret.size = range.size;
2535 ret.offset_within_address_space = int128_get64(range.start);
2536 ret.readonly = fr->readonly;
2537 ret.nonvolatile = fr->nonvolatile;
2538 return ret;
2539 }
2540
2541 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2542 hwaddr addr, uint64_t size)
2543 {
2544 MemoryRegionSection ret;
2545 rcu_read_lock();
2546 ret = memory_region_find_rcu(mr, addr, size);
2547 if (ret.mr) {
2548 memory_region_ref(ret.mr);
2549 }
2550 rcu_read_unlock();
2551 return ret;
2552 }
2553
2554 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2555 {
2556 MemoryRegion *mr;
2557
2558 rcu_read_lock();
2559 mr = memory_region_find_rcu(container, addr, 1).mr;
2560 rcu_read_unlock();
2561 return mr && mr != container;
2562 }
2563
2564 void memory_global_dirty_log_sync(void)
2565 {
2566 memory_region_sync_dirty_bitmap(NULL);
2567 }
2568
2569 static VMChangeStateEntry *vmstate_change;
2570
2571 void memory_global_dirty_log_start(void)
2572 {
2573 if (vmstate_change) {
2574 qemu_del_vm_change_state_handler(vmstate_change);
2575 vmstate_change = NULL;
2576 }
2577
2578 global_dirty_log = true;
2579
2580 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2581
2582 /* Refresh DIRTY_LOG_MIGRATION bit. */
2583 memory_region_transaction_begin();
2584 memory_region_update_pending = true;
2585 memory_region_transaction_commit();
2586 }
2587
2588 static void memory_global_dirty_log_do_stop(void)
2589 {
2590 global_dirty_log = false;
2591
2592 /* Refresh DIRTY_LOG_MIGRATION bit. */
2593 memory_region_transaction_begin();
2594 memory_region_update_pending = true;
2595 memory_region_transaction_commit();
2596
2597 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2598 }
2599
2600 static void memory_vm_change_state_handler(void *opaque, int running,
2601 RunState state)
2602 {
2603 if (running) {
2604 memory_global_dirty_log_do_stop();
2605
2606 if (vmstate_change) {
2607 qemu_del_vm_change_state_handler(vmstate_change);
2608 vmstate_change = NULL;
2609 }
2610 }
2611 }
2612
2613 void memory_global_dirty_log_stop(void)
2614 {
2615 if (!runstate_is_running()) {
2616 if (vmstate_change) {
2617 return;
2618 }
2619 vmstate_change = qemu_add_vm_change_state_handler(
2620 memory_vm_change_state_handler, NULL);
2621 return;
2622 }
2623
2624 memory_global_dirty_log_do_stop();
2625 }
2626
2627 static void listener_add_address_space(MemoryListener *listener,
2628 AddressSpace *as)
2629 {
2630 FlatView *view;
2631 FlatRange *fr;
2632
2633 if (listener->begin) {
2634 listener->begin(listener);
2635 }
2636 if (global_dirty_log) {
2637 if (listener->log_global_start) {
2638 listener->log_global_start(listener);
2639 }
2640 }
2641
2642 view = address_space_get_flatview(as);
2643 FOR_EACH_FLAT_RANGE(fr, view) {
2644 MemoryRegionSection section = section_from_flat_range(fr, view);
2645
2646 if (listener->region_add) {
2647 listener->region_add(listener, &section);
2648 }
2649 if (fr->dirty_log_mask && listener->log_start) {
2650 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2651 }
2652 }
2653 if (listener->commit) {
2654 listener->commit(listener);
2655 }
2656 flatview_unref(view);
2657 }
2658
2659 static void listener_del_address_space(MemoryListener *listener,
2660 AddressSpace *as)
2661 {
2662 FlatView *view;
2663 FlatRange *fr;
2664
2665 if (listener->begin) {
2666 listener->begin(listener);
2667 }
2668 view = address_space_get_flatview(as);
2669 FOR_EACH_FLAT_RANGE(fr, view) {
2670 MemoryRegionSection section = section_from_flat_range(fr, view);
2671
2672 if (fr->dirty_log_mask && listener->log_stop) {
2673 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2674 }
2675 if (listener->region_del) {
2676 listener->region_del(listener, &section);
2677 }
2678 }
2679 if (listener->commit) {
2680 listener->commit(listener);
2681 }
2682 flatview_unref(view);
2683 }
2684
2685 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2686 {
2687 MemoryListener *other = NULL;
2688
2689 listener->address_space = as;
2690 if (QTAILQ_EMPTY(&memory_listeners)
2691 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2692 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2693 } else {
2694 QTAILQ_FOREACH(other, &memory_listeners, link) {
2695 if (listener->priority < other->priority) {
2696 break;
2697 }
2698 }
2699 QTAILQ_INSERT_BEFORE(other, listener, link);
2700 }
2701
2702 if (QTAILQ_EMPTY(&as->listeners)
2703 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2704 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2705 } else {
2706 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2707 if (listener->priority < other->priority) {
2708 break;
2709 }
2710 }
2711 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2712 }
2713
2714 listener_add_address_space(listener, as);
2715 }
2716
2717 void memory_listener_unregister(MemoryListener *listener)
2718 {
2719 if (!listener->address_space) {
2720 return;
2721 }
2722
2723 listener_del_address_space(listener, listener->address_space);
2724 QTAILQ_REMOVE(&memory_listeners, listener, link);
2725 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2726 listener->address_space = NULL;
2727 }
2728
2729 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2730 {
2731 memory_region_ref(root);
2732 as->root = root;
2733 as->current_map = NULL;
2734 as->ioeventfd_nb = 0;
2735 as->ioeventfds = NULL;
2736 QTAILQ_INIT(&as->listeners);
2737 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2738 as->name = g_strdup(name ? name : "anonymous");
2739 address_space_update_topology(as);
2740 address_space_update_ioeventfds(as);
2741 }
2742
2743 static void do_address_space_destroy(AddressSpace *as)
2744 {
2745 assert(QTAILQ_EMPTY(&as->listeners));
2746
2747 flatview_unref(as->current_map);
2748 g_free(as->name);
2749 g_free(as->ioeventfds);
2750 memory_region_unref(as->root);
2751 }
2752
2753 void address_space_destroy(AddressSpace *as)
2754 {
2755 MemoryRegion *root = as->root;
2756
2757 /* Flush out anything from MemoryListeners listening in on this */
2758 memory_region_transaction_begin();
2759 as->root = NULL;
2760 memory_region_transaction_commit();
2761 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2762
2763 /* At this point, as->dispatch and as->current_map are dummy
2764 * entries that the guest should never use. Wait for the old
2765 * values to expire before freeing the data.
2766 */
2767 as->root = root;
2768 call_rcu(as, do_address_space_destroy, rcu);
2769 }
2770
2771 static const char *memory_region_type(MemoryRegion *mr)
2772 {
2773 if (memory_region_is_ram_device(mr)) {
2774 return "ramd";
2775 } else if (memory_region_is_romd(mr)) {
2776 return "romd";
2777 } else if (memory_region_is_rom(mr)) {
2778 return "rom";
2779 } else if (memory_region_is_ram(mr)) {
2780 return "ram";
2781 } else {
2782 return "i/o";
2783 }
2784 }
2785
2786 typedef struct MemoryRegionList MemoryRegionList;
2787
2788 struct MemoryRegionList {
2789 const MemoryRegion *mr;
2790 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2791 };
2792
2793 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2794
2795 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2796 int128_sub((size), int128_one())) : 0)
2797 #define MTREE_INDENT " "
2798
2799 static void mtree_expand_owner(fprintf_function mon_printf, void *f,
2800 const char *label, Object *obj)
2801 {
2802 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2803
2804 mon_printf(f, " %s:{%s", label, dev ? "dev" : "obj");
2805 if (dev && dev->id) {
2806 mon_printf(f, " id=%s", dev->id);
2807 } else {
2808 gchar *canonical_path = object_get_canonical_path(obj);
2809 if (canonical_path) {
2810 mon_printf(f, " path=%s", canonical_path);
2811 g_free(canonical_path);
2812 } else {
2813 mon_printf(f, " type=%s", object_get_typename(obj));
2814 }
2815 }
2816 mon_printf(f, "}");
2817 }
2818
2819 static void mtree_print_mr_owner(fprintf_function mon_printf, void *f,
2820 const MemoryRegion *mr)
2821 {
2822 Object *owner = mr->owner;
2823 Object *parent = memory_region_owner((MemoryRegion *)mr);
2824
2825 if (!owner && !parent) {
2826 mon_printf(f, " orphan");
2827 return;
2828 }
2829 if (owner) {
2830 mtree_expand_owner(mon_printf, f, "owner", owner);
2831 }
2832 if (parent && parent != owner) {
2833 mtree_expand_owner(mon_printf, f, "parent", parent);
2834 }
2835 }
2836
2837 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2838 const MemoryRegion *mr, unsigned int level,
2839 hwaddr base,
2840 MemoryRegionListHead *alias_print_queue,
2841 bool owner)
2842 {
2843 MemoryRegionList *new_ml, *ml, *next_ml;
2844 MemoryRegionListHead submr_print_queue;
2845 const MemoryRegion *submr;
2846 unsigned int i;
2847 hwaddr cur_start, cur_end;
2848
2849 if (!mr) {
2850 return;
2851 }
2852
2853 for (i = 0; i < level; i++) {
2854 mon_printf(f, MTREE_INDENT);
2855 }
2856
2857 cur_start = base + mr->addr;
2858 cur_end = cur_start + MR_SIZE(mr->size);
2859
2860 /*
2861 * Try to detect overflow of memory region. This should never
2862 * happen normally. When it happens, we dump something to warn the
2863 * user who is observing this.
2864 */
2865 if (cur_start < base || cur_end < cur_start) {
2866 mon_printf(f, "[DETECTED OVERFLOW!] ");
2867 }
2868
2869 if (mr->alias) {
2870 MemoryRegionList *ml;
2871 bool found = false;
2872
2873 /* check if the alias is already in the queue */
2874 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2875 if (ml->mr == mr->alias) {
2876 found = true;
2877 }
2878 }
2879
2880 if (!found) {
2881 ml = g_new(MemoryRegionList, 1);
2882 ml->mr = mr->alias;
2883 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2884 }
2885 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2886 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2887 "-" TARGET_FMT_plx "%s",
2888 cur_start, cur_end,
2889 mr->priority,
2890 mr->nonvolatile ? "nv-" : "",
2891 memory_region_type((MemoryRegion *)mr),
2892 memory_region_name(mr),
2893 memory_region_name(mr->alias),
2894 mr->alias_offset,
2895 mr->alias_offset + MR_SIZE(mr->size),
2896 mr->enabled ? "" : " [disabled]");
2897 if (owner) {
2898 mtree_print_mr_owner(mon_printf, f, mr);
2899 }
2900 } else {
2901 mon_printf(f,
2902 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s%s): %s%s",
2903 cur_start, cur_end,
2904 mr->priority,
2905 mr->nonvolatile ? "nv-" : "",
2906 memory_region_type((MemoryRegion *)mr),
2907 memory_region_name(mr),
2908 mr->enabled ? "" : " [disabled]");
2909 if (owner) {
2910 mtree_print_mr_owner(mon_printf, f, mr);
2911 }
2912 }
2913 mon_printf(f, "\n");
2914
2915 QTAILQ_INIT(&submr_print_queue);
2916
2917 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2918 new_ml = g_new(MemoryRegionList, 1);
2919 new_ml->mr = submr;
2920 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2921 if (new_ml->mr->addr < ml->mr->addr ||
2922 (new_ml->mr->addr == ml->mr->addr &&
2923 new_ml->mr->priority > ml->mr->priority)) {
2924 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2925 new_ml = NULL;
2926 break;
2927 }
2928 }
2929 if (new_ml) {
2930 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2931 }
2932 }
2933
2934 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2935 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2936 alias_print_queue, owner);
2937 }
2938
2939 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2940 g_free(ml);
2941 }
2942 }
2943
2944 struct FlatViewInfo {
2945 fprintf_function mon_printf;
2946 void *f;
2947 int counter;
2948 bool dispatch_tree;
2949 bool owner;
2950 };
2951
2952 static void mtree_print_flatview(gpointer key, gpointer value,
2953 gpointer user_data)
2954 {
2955 FlatView *view = key;
2956 GArray *fv_address_spaces = value;
2957 struct FlatViewInfo *fvi = user_data;
2958 fprintf_function p = fvi->mon_printf;
2959 void *f = fvi->f;
2960 FlatRange *range = &view->ranges[0];
2961 MemoryRegion *mr;
2962 int n = view->nr;
2963 int i;
2964 AddressSpace *as;
2965
2966 p(f, "FlatView #%d\n", fvi->counter);
2967 ++fvi->counter;
2968
2969 for (i = 0; i < fv_address_spaces->len; ++i) {
2970 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2971 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2972 if (as->root->alias) {
2973 p(f, ", alias %s", memory_region_name(as->root->alias));
2974 }
2975 p(f, "\n");
2976 }
2977
2978 p(f, " Root memory region: %s\n",
2979 view->root ? memory_region_name(view->root) : "(none)");
2980
2981 if (n <= 0) {
2982 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2983 return;
2984 }
2985
2986 while (n--) {
2987 mr = range->mr;
2988 if (range->offset_in_region) {
2989 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2990 TARGET_FMT_plx " (prio %d, %s%s): %s @" TARGET_FMT_plx,
2991 int128_get64(range->addr.start),
2992 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2993 mr->priority,
2994 range->nonvolatile ? "nv-" : "",
2995 range->readonly ? "rom" : memory_region_type(mr),
2996 memory_region_name(mr),
2997 range->offset_in_region);
2998 } else {
2999 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3000 TARGET_FMT_plx " (prio %d, %s%s): %s",
3001 int128_get64(range->addr.start),
3002 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3003 mr->priority,
3004 range->nonvolatile ? "nv-" : "",
3005 range->readonly ? "rom" : memory_region_type(mr),
3006 memory_region_name(mr));
3007 }
3008 if (fvi->owner) {
3009 mtree_print_mr_owner(p, f, mr);
3010 }
3011 p(f, "\n");
3012 range++;
3013 }
3014
3015 #if !defined(CONFIG_USER_ONLY)
3016 if (fvi->dispatch_tree && view->root) {
3017 mtree_print_dispatch(p, f, view->dispatch, view->root);
3018 }
3019 #endif
3020
3021 p(f, "\n");
3022 }
3023
3024 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3025 gpointer user_data)
3026 {
3027 FlatView *view = key;
3028 GArray *fv_address_spaces = value;
3029
3030 g_array_unref(fv_address_spaces);
3031 flatview_unref(view);
3032
3033 return true;
3034 }
3035
3036 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3037 bool dispatch_tree, bool owner)
3038 {
3039 MemoryRegionListHead ml_head;
3040 MemoryRegionList *ml, *ml2;
3041 AddressSpace *as;
3042
3043 if (flatview) {
3044 FlatView *view;
3045 struct FlatViewInfo fvi = {
3046 .mon_printf = mon_printf,
3047 .f = f,
3048 .counter = 0,
3049 .dispatch_tree = dispatch_tree,
3050 .owner = owner,
3051 };
3052 GArray *fv_address_spaces;
3053 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3054
3055 /* Gather all FVs in one table */
3056 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3057 view = address_space_get_flatview(as);
3058
3059 fv_address_spaces = g_hash_table_lookup(views, view);
3060 if (!fv_address_spaces) {
3061 fv_address_spaces = g_array_new(false, false, sizeof(as));
3062 g_hash_table_insert(views, view, fv_address_spaces);
3063 }
3064
3065 g_array_append_val(fv_address_spaces, as);
3066 }
3067
3068 /* Print */
3069 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3070
3071 /* Free */
3072 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3073 g_hash_table_unref(views);
3074
3075 return;
3076 }
3077
3078 QTAILQ_INIT(&ml_head);
3079
3080 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3081 mon_printf(f, "address-space: %s\n", as->name);
3082 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head, owner);
3083 mon_printf(f, "\n");
3084 }
3085
3086 /* print aliased regions */
3087 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3088 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3089 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head, owner);
3090 mon_printf(f, "\n");
3091 }
3092
3093 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3094 g_free(ml);
3095 }
3096 }
3097
3098 void memory_region_init_ram(MemoryRegion *mr,
3099 struct Object *owner,
3100 const char *name,
3101 uint64_t size,
3102 Error **errp)
3103 {
3104 DeviceState *owner_dev;
3105 Error *err = NULL;
3106
3107 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3108 if (err) {
3109 error_propagate(errp, err);
3110 return;
3111 }
3112 /* This will assert if owner is neither NULL nor a DeviceState.
3113 * We only want the owner here for the purposes of defining a
3114 * unique name for migration. TODO: Ideally we should implement
3115 * a naming scheme for Objects which are not DeviceStates, in
3116 * which case we can relax this restriction.
3117 */
3118 owner_dev = DEVICE(owner);
3119 vmstate_register_ram(mr, owner_dev);
3120 }
3121
3122 void memory_region_init_rom(MemoryRegion *mr,
3123 struct Object *owner,
3124 const char *name,
3125 uint64_t size,
3126 Error **errp)
3127 {
3128 DeviceState *owner_dev;
3129 Error *err = NULL;
3130
3131 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3132 if (err) {
3133 error_propagate(errp, err);
3134 return;
3135 }
3136 /* This will assert if owner is neither NULL nor a DeviceState.
3137 * We only want the owner here for the purposes of defining a
3138 * unique name for migration. TODO: Ideally we should implement
3139 * a naming scheme for Objects which are not DeviceStates, in
3140 * which case we can relax this restriction.
3141 */
3142 owner_dev = DEVICE(owner);
3143 vmstate_register_ram(mr, owner_dev);
3144 }
3145
3146 void memory_region_init_rom_device(MemoryRegion *mr,
3147 struct Object *owner,
3148 const MemoryRegionOps *ops,
3149 void *opaque,
3150 const char *name,
3151 uint64_t size,
3152 Error **errp)
3153 {
3154 DeviceState *owner_dev;
3155 Error *err = NULL;
3156
3157 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3158 name, size, &err);
3159 if (err) {
3160 error_propagate(errp, err);
3161 return;
3162 }
3163 /* This will assert if owner is neither NULL nor a DeviceState.
3164 * We only want the owner here for the purposes of defining a
3165 * unique name for migration. TODO: Ideally we should implement
3166 * a naming scheme for Objects which are not DeviceStates, in
3167 * which case we can relax this restriction.
3168 */
3169 owner_dev = DEVICE(owner);
3170 vmstate_register_ram(mr, owner_dev);
3171 }
3172
3173 static const TypeInfo memory_region_info = {
3174 .parent = TYPE_OBJECT,
3175 .name = TYPE_MEMORY_REGION,
3176 .instance_size = sizeof(MemoryRegion),
3177 .instance_init = memory_region_initfn,
3178 .instance_finalize = memory_region_finalize,
3179 };
3180
3181 static const TypeInfo iommu_memory_region_info = {
3182 .parent = TYPE_MEMORY_REGION,
3183 .name = TYPE_IOMMU_MEMORY_REGION,
3184 .class_size = sizeof(IOMMUMemoryRegionClass),
3185 .instance_size = sizeof(IOMMUMemoryRegion),
3186 .instance_init = iommu_memory_region_initfn,
3187 .abstract = true,
3188 };
3189
3190 static void memory_register_types(void)
3191 {
3192 type_register_static(&memory_region_info);
3193 type_register_static(&iommu_memory_region_info);
3194 }
3195
3196 type_init(memory_register_types)
AR7 emulation for QEMU