hw/dma/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Modifications:
   7  *  2010-Feb-14 Artyom Tarasenko : reworked irq generation
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/hw.h"
  30 #include "hw/sparc/sparc32_dma.h"
  31 #include "hw/sparc/sun4m.h"
  32 #include "hw/sysbus.h"
  33 #include "qapi/error.h"
  34 #include "trace.h"
  35
  36 /*
  37  * This is the DMA controller part of chip STP2000 (Master I/O), also
  38  * produced as NCR89C100. See
  39  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  40  * and
  41  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  42  */
  43
  44 #define DMA_SIZE (4 * sizeof(uint32_t))
  45 /* We need the mask, because one instance of the device is not page
  46    aligned (ledma, start address 0x0010) */
  47 #define DMA_MASK (DMA_SIZE - 1)
  48 /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
  49 #define DMA_ETH_SIZE (8 * sizeof(uint32_t))
  50 #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
  51
  52 #define DMA_VER 0xa0000000
  53 #define DMA_INTR 1
  54 #define DMA_INTREN 0x10
  55 #define DMA_WRITE_MEM 0x100
  56 #define DMA_EN 0x200
  57 #define DMA_LOADED 0x04000000
  58 #define DMA_DRAIN_FIFO 0x40
  59 #define DMA_RESET 0x80
  60
  61 /* XXX SCSI and ethernet should have different read-only bit masks */
  62 #define DMA_CSR_RO_MASK 0xfe000007
  63
  64 enum {
  65     GPIO_RESET = 0,
  66     GPIO_DMA,
  67 };
  68
  69 /* Note: on sparc, the lance 16 bit bus is swapped */
  70 void ledma_memory_read(void *opaque, hwaddr addr,
  71                        uint8_t *buf, int len, int do_bswap)
  72 {
  73     DMADeviceState *s = opaque;
  74     int i;
  75
  76     addr |= s->dmaregs[3];
  77     trace_ledma_memory_read(addr);
  78     if (do_bswap) {
  79         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  80     } else {
  81         addr &= ~1;
  82         len &= ~1;
  83         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  84         for(i = 0; i < len; i += 2) {
  85             bswap16s((uint16_t *)(buf + i));
  86         }
  87     }
  88 }
  89
  90 void ledma_memory_write(void *opaque, hwaddr addr,
  91                         uint8_t *buf, int len, int do_bswap)
  92 {
  93     DMADeviceState *s = opaque;
  94     int l, i;
  95     uint16_t tmp_buf[32];
  96
  97     addr |= s->dmaregs[3];
  98     trace_ledma_memory_write(addr);
  99     if (do_bswap) {
 100         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 101     } else {
 102         addr &= ~1;
 103         len &= ~1;
 104         while (len > 0) {
 105             l = len;
 106             if (l > sizeof(tmp_buf))
 107                 l = sizeof(tmp_buf);
 108             for(i = 0; i < l; i += 2) {
 109                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 110             }
 111             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 112             len -= l;
 113             buf += l;
 114             addr += l;
 115         }
 116     }
 117 }
 118
 119 static void dma_set_irq(void *opaque, int irq, int level)
 120 {
 121     DMADeviceState *s = opaque;
 122     if (level) {
 123         s->dmaregs[0] |= DMA_INTR;
 124         if (s->dmaregs[0] & DMA_INTREN) {
 125             trace_sparc32_dma_set_irq_raise();
 126             qemu_irq_raise(s->irq);
 127         }
 128     } else {
 129         if (s->dmaregs[0] & DMA_INTR) {
 130             s->dmaregs[0] &= ~DMA_INTR;
 131             if (s->dmaregs[0] & DMA_INTREN) {
 132                 trace_sparc32_dma_set_irq_lower();
 133                 qemu_irq_lower(s->irq);
 134             }
 135         }
 136     }
 137 }
 138
 139 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 140 {
 141     DMADeviceState *s = opaque;
 142
 143     trace_espdma_memory_read(s->dmaregs[1]);
 144     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 145     s->dmaregs[1] += len;
 146 }
 147
 148 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 149 {
 150     DMADeviceState *s = opaque;
 151
 152     trace_espdma_memory_write(s->dmaregs[1]);
 153     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 154     s->dmaregs[1] += len;
 155 }
 156
 157 static uint64_t dma_mem_read(void *opaque, hwaddr addr,
 158                              unsigned size)
 159 {
 160     DMADeviceState *s = opaque;
 161     uint32_t saddr;
 162
 163     if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
 164         /* aliased to espdma, but we can't get there from here */
 165         /* buggy driver if using undocumented behavior, just return 0 */
 166         trace_sparc32_dma_mem_readl(addr, 0);
 167         return 0;
 168     }
 169     saddr = (addr & DMA_MASK) >> 2;
 170     trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
 171     return s->dmaregs[saddr];
 172 }
 173
 174 static void dma_mem_write(void *opaque, hwaddr addr,
 175                           uint64_t val, unsigned size)
 176 {
 177     DMADeviceState *s = opaque;
 178     uint32_t saddr;
 179
 180     if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
 181         /* aliased to espdma, but we can't get there from here */
 182         trace_sparc32_dma_mem_writel(addr, 0, val);
 183         return;
 184     }
 185     saddr = (addr & DMA_MASK) >> 2;
 186     trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
 187     switch (saddr) {
 188     case 0:
 189         if (val & DMA_INTREN) {
 190             if (s->dmaregs[0] & DMA_INTR) {
 191                 trace_sparc32_dma_set_irq_raise();
 192                 qemu_irq_raise(s->irq);
 193             }
 194         } else {
 195             if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
 196                 trace_sparc32_dma_set_irq_lower();
 197                 qemu_irq_lower(s->irq);
 198             }
 199         }
 200         if (val & DMA_RESET) {
 201             qemu_irq_raise(s->gpio[GPIO_RESET]);
 202             qemu_irq_lower(s->gpio[GPIO_RESET]);
 203         } else if (val & DMA_DRAIN_FIFO) {
 204             val &= ~DMA_DRAIN_FIFO;
 205         } else if (val == 0)
 206             val = DMA_DRAIN_FIFO;
 207
 208         if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
 209             trace_sparc32_dma_enable_raise();
 210             qemu_irq_raise(s->gpio[GPIO_DMA]);
 211         } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
 212             trace_sparc32_dma_enable_lower();
 213             qemu_irq_lower(s->gpio[GPIO_DMA]);
 214         }
 215
 216         val &= ~DMA_CSR_RO_MASK;
 217         val |= DMA_VER;
 218         s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
 219         break;
 220     case 1:
 221         s->dmaregs[0] |= DMA_LOADED;
 222         /* fall through */
 223     default:
 224         s->dmaregs[saddr] = val;
 225         break;
 226     }
 227 }
 228
 229 static const MemoryRegionOps dma_mem_ops = {
 230     .read = dma_mem_read,
 231     .write = dma_mem_write,
 232     .endianness = DEVICE_NATIVE_ENDIAN,
 233     .valid = {
 234         .min_access_size = 4,
 235         .max_access_size = 4,
 236     },
 237 };
 238
 239 static void sparc32_dma_device_reset(DeviceState *d)
 240 {
 241     DMADeviceState *s = SPARC32_DMA_DEVICE(d);
 242
 243     memset(s->dmaregs, 0, DMA_SIZE);
 244     s->dmaregs[0] = DMA_VER;
 245 }
 246
 247 static const VMStateDescription vmstate_sparc32_dma_device = {
 248     .name ="sparc32_dma",
 249     .version_id = 2,
 250     .minimum_version_id = 2,
 251     .fields = (VMStateField[]) {
 252         VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
 253         VMSTATE_END_OF_LIST()
 254     }
 255 };
 256
 257 static void sparc32_dma_device_init(Object *obj)
 258 {
 259     DeviceState *dev = DEVICE(obj);
 260     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 261     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 262
 263     sysbus_init_irq(sbd, &s->irq);
 264
 265     sysbus_init_mmio(sbd, &s->iomem);
 266
 267     object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
 268                              (Object **) &s->iommu,
 269                              qdev_prop_allow_set_link_before_realize,
 270                              0, NULL);
 271
 272     qdev_init_gpio_in(dev, dma_set_irq, 1);
 273     qdev_init_gpio_out(dev, s->gpio, 2);
 274 }
 275
 276 static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
 277 {
 278     DeviceClass *dc = DEVICE_CLASS(klass);
 279
 280     dc->reset = sparc32_dma_device_reset;
 281     dc->vmsd = &vmstate_sparc32_dma_device;
 282 }
 283
 284 static const TypeInfo sparc32_dma_device_info = {
 285     .name          = TYPE_SPARC32_DMA_DEVICE,
 286     .parent        = TYPE_SYS_BUS_DEVICE,
 287     .abstract      = true,
 288     .instance_size = sizeof(DMADeviceState),
 289     .instance_init = sparc32_dma_device_init,
 290     .class_init    = sparc32_dma_device_class_init,
 291 };
 292
 293 static void sparc32_espdma_device_init(Object *obj)
 294 {
 295     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 296
 297     memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
 298                           "espdma-mmio", DMA_SIZE);
 299     s->is_ledma = 0;
 300 }
 301
 302 static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
 303 {
 304     DeviceState *d;
 305     SysBusESPState *sysbus;
 306     ESPState *esp;
 307
 308     d = qdev_create(NULL, TYPE_ESP);
 309     object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp);
 310     sysbus = ESP_STATE(d);
 311     esp = &sysbus->esp;
 312     esp->dma_memory_read = espdma_memory_read;
 313     esp->dma_memory_write = espdma_memory_write;
 314     esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
 315     sysbus->it_shift = 2;
 316     esp->dma_enabled = 1;
 317     qdev_init_nofail(d);
 318 }
 319
 320 static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
 321 {
 322     DeviceClass *dc = DEVICE_CLASS(klass);
 323
 324     dc->realize = sparc32_espdma_device_realize;
 325 }
 326
 327 static const TypeInfo sparc32_espdma_device_info = {
 328     .name          = TYPE_SPARC32_ESPDMA_DEVICE,
 329     .parent        = TYPE_SPARC32_DMA_DEVICE,
 330     .instance_size = sizeof(ESPDMADeviceState),
 331     .instance_init = sparc32_espdma_device_init,
 332     .class_init    = sparc32_espdma_device_class_init,
 333 };
 334
 335 static void sparc32_ledma_device_init(Object *obj)
 336 {
 337     DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
 338
 339     memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
 340                           "ledma-mmio", DMA_ETH_SIZE);
 341     s->is_ledma = 1;
 342 }
 343
 344 static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
 345 {
 346     DeviceState *d;
 347     NICInfo *nd = &nd_table[0];
 348
 349     qemu_check_nic_model(nd, TYPE_LANCE);
 350
 351     d = qdev_create(NULL, TYPE_LANCE);
 352     object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);
 353     qdev_set_nic_properties(d, nd);
 354     qdev_prop_set_ptr(d, "dma", dev);
 355     qdev_init_nofail(d);
 356 }
 357
 358 static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
 359 {
 360     DeviceClass *dc = DEVICE_CLASS(klass);
 361
 362     dc->realize = sparc32_ledma_device_realize;
 363 }
 364
 365 static const TypeInfo sparc32_ledma_device_info = {
 366     .name          = TYPE_SPARC32_LEDMA_DEVICE,
 367     .parent        = TYPE_SPARC32_DMA_DEVICE,
 368     .instance_size = sizeof(LEDMADeviceState),
 369     .instance_init = sparc32_ledma_device_init,
 370     .class_init    = sparc32_ledma_device_class_init,
 371 };
 372
 373 static void sparc32_dma_realize(DeviceState *dev, Error **errp)
 374 {
 375     SPARC32DMAState *s = SPARC32_DMA(dev);
 376     DeviceState *espdma, *esp, *ledma, *lance;
 377     SysBusDevice *sbd;
 378     Object *iommu;
 379
 380     iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
 381     if (!iommu) {
 382         error_setg(errp, "unable to locate sun4m IOMMU device");
 383         return;
 384     }
 385
 386     espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);
 387     object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
 388     object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma), errp);
 389     qdev_init_nofail(espdma);
 390
 391     esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
 392     sbd = SYS_BUS_DEVICE(esp);
 393     sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
 394     qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
 395     qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
 396
 397     sbd = SYS_BUS_DEVICE(espdma);
 398     memory_region_add_subregion(&s->dmamem, 0x0,
 399                                 sysbus_mmio_get_region(sbd, 0));
 400
 401     ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);
 402     object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
 403     object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma), errp);
 404     qdev_init_nofail(ledma);
 405
 406     lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
 407     sbd = SYS_BUS_DEVICE(lance);
 408     sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
 409     qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
 410
 411     sbd = SYS_BUS_DEVICE(ledma);
 412     memory_region_add_subregion(&s->dmamem, 0x10,
 413                                 sysbus_mmio_get_region(sbd, 0));
 414 }
 415
 416 static void sparc32_dma_init(Object *obj)
 417 {
 418     SPARC32DMAState *s = SPARC32_DMA(obj);
 419     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 420
 421     memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
 422     sysbus_init_mmio(sbd, &s->dmamem);
 423 }
 424
 425 static void sparc32_dma_class_init(ObjectClass *klass, void *data)
 426 {
 427     DeviceClass *dc = DEVICE_CLASS(klass);
 428
 429     dc->realize = sparc32_dma_realize;
 430 }
 431
 432 static const TypeInfo sparc32_dma_info = {
 433     .name          = TYPE_SPARC32_DMA,
 434     .parent        = TYPE_SYS_BUS_DEVICE,
 435     .instance_size = sizeof(SPARC32DMAState),
 436     .instance_init = sparc32_dma_init,
 437     .class_init    = sparc32_dma_class_init,
 438 };
 439
 440
 441 static void sparc32_dma_register_types(void)
 442 {
 443     type_register_static(&sparc32_dma_device_info);
 444     type_register_static(&sparc32_espdma_device_info);
 445     type_register_static(&sparc32_ledma_device_info);
 446     type_register_static(&sparc32_dma_info);
 447 }
 448
 449 type_init(sparc32_dma_register_types)