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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target-sparc / translate.c
blobca03a8064c11efe4d1c004dd183142a6f66a5622
1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/helper-proto.h"
25 #include "tcg-op.h"
26 #include "exec/cpu_ldst.h"
27
28 #include "exec/helper-gen.h"
29
30 #include "trace-tcg.h"
31
32
33 #define DEBUG_DISAS
34
35 #define DYNAMIC_PC 1 /* dynamic pc value */
36 #define JUMP_PC 2 /* dynamic pc value which takes only two values
37 according to jump_pc[T2] */
38
39 /* global register indexes */
40 static TCGv_ptr cpu_env, cpu_regwptr;
41 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
42 static TCGv_i32 cpu_cc_op;
43 static TCGv_i32 cpu_psr;
44 static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
45 static TCGv cpu_y;
46 #ifndef CONFIG_USER_ONLY
47 static TCGv cpu_tbr;
48 #endif
49 static TCGv cpu_cond;
50 #ifdef TARGET_SPARC64
51 static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
52 static TCGv cpu_gsr;
53 static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
54 static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
55 static TCGv_i32 cpu_softint;
56 #else
57 static TCGv cpu_wim;
58 #endif
59 /* Floating point registers */
60 static TCGv_i64 cpu_fpr[TARGET_DPREGS];
61
62 static target_ulong gen_opc_npc[OPC_BUF_SIZE];
63 static target_ulong gen_opc_jump_pc[2];
64
65 #include "exec/gen-icount.h"
66
67 typedef struct DisasContext {
68 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
69 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
70 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
71 int is_br;
72 int mem_idx;
73 int fpu_enabled;
74 int address_mask_32bit;
75 int singlestep;
76 uint32_t cc_op; /* current CC operation */
77 struct TranslationBlock *tb;
78 sparc_def_t *def;
79 TCGv_i32 t32[3];
80 TCGv ttl[5];
81 int n_t32;
82 int n_ttl;
83 } DisasContext;
84
85 typedef struct {
86 TCGCond cond;
87 bool is_bool;
88 bool g1, g2;
89 TCGv c1, c2;
90 } DisasCompare;
91
92 // This function uses non-native bit order
93 #define GET_FIELD(X, FROM, TO) \
94 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
95
96 // This function uses the order in the manuals, i.e. bit 0 is 2^0
97 #define GET_FIELD_SP(X, FROM, TO) \
98 GET_FIELD(X, 31 - (TO), 31 - (FROM))
99
100 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
101 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
102
103 #ifdef TARGET_SPARC64
104 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
105 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
106 #else
107 #define DFPREG(r) (r & 0x1e)
108 #define QFPREG(r) (r & 0x1c)
109 #endif
110
111 #define UA2005_HTRAP_MASK 0xff
112 #define V8_TRAP_MASK 0x7f
113
114 static int sign_extend(int x, int len)
115 {
116 len = 32 - len;
117 return (x << len) >> len;
118 }
119
120 #define IS_IMM (insn & (1<<13))
121
122 static inline TCGv_i32 get_temp_i32(DisasContext *dc)
123 {
124 TCGv_i32 t;
125 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
126 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
127 return t;
128 }
129
130 static inline TCGv get_temp_tl(DisasContext *dc)
131 {
132 TCGv t;
133 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
134 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
135 return t;
136 }
137
138 static inline void gen_update_fprs_dirty(int rd)
139 {
140 #if defined(TARGET_SPARC64)
141 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
142 #endif
143 }
144
145 /* floating point registers moves */
146 static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
147 {
148 #if TCG_TARGET_REG_BITS == 32
149 if (src & 1) {
150 return TCGV_LOW(cpu_fpr[src / 2]);
151 } else {
152 return TCGV_HIGH(cpu_fpr[src / 2]);
153 }
154 #else
155 if (src & 1) {
156 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
157 } else {
158 TCGv_i32 ret = get_temp_i32(dc);
159 TCGv_i64 t = tcg_temp_new_i64();
160
161 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
162 tcg_gen_extrl_i64_i32(ret, t);
163 tcg_temp_free_i64(t);
164
165 return ret;
166 }
167 #endif
168 }
169
170 static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
171 {
172 #if TCG_TARGET_REG_BITS == 32
173 if (dst & 1) {
174 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
175 } else {
176 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
177 }
178 #else
179 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
180 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
181 (dst & 1 ? 0 : 32), 32);
182 #endif
183 gen_update_fprs_dirty(dst);
184 }
185
186 static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
187 {
188 return get_temp_i32(dc);
189 }
190
191 static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
192 {
193 src = DFPREG(src);
194 return cpu_fpr[src / 2];
195 }
196
197 static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
198 {
199 dst = DFPREG(dst);
200 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
201 gen_update_fprs_dirty(dst);
202 }
203
204 static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
205 {
206 return cpu_fpr[DFPREG(dst) / 2];
207 }
208
209 static void gen_op_load_fpr_QT0(unsigned int src)
210 {
211 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
212 offsetof(CPU_QuadU, ll.upper));
213 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
214 offsetof(CPU_QuadU, ll.lower));
215 }
216
217 static void gen_op_load_fpr_QT1(unsigned int src)
218 {
219 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
220 offsetof(CPU_QuadU, ll.upper));
221 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
222 offsetof(CPU_QuadU, ll.lower));
223 }
224
225 static void gen_op_store_QT0_fpr(unsigned int dst)
226 {
227 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
228 offsetof(CPU_QuadU, ll.upper));
229 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
230 offsetof(CPU_QuadU, ll.lower));
231 }
232
233 #ifdef TARGET_SPARC64
234 static void gen_move_Q(unsigned int rd, unsigned int rs)
235 {
236 rd = QFPREG(rd);
237 rs = QFPREG(rs);
238
239 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
240 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
241 gen_update_fprs_dirty(rd);
242 }
243 #endif
244
245 /* moves */
246 #ifdef CONFIG_USER_ONLY
247 #define supervisor(dc) 0
248 #ifdef TARGET_SPARC64
249 #define hypervisor(dc) 0
250 #endif
251 #else
252 #define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
253 #ifdef TARGET_SPARC64
254 #define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
255 #else
256 #endif
257 #endif
258
259 #ifdef TARGET_SPARC64
260 #ifndef TARGET_ABI32
261 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
262 #else
263 #define AM_CHECK(dc) (1)
264 #endif
265 #endif
266
267 static inline void gen_address_mask(DisasContext *dc, TCGv addr)
268 {
269 #ifdef TARGET_SPARC64
270 if (AM_CHECK(dc))
271 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
272 #endif
273 }
274
275 static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
276 {
277 if (reg == 0 || reg >= 8) {
278 TCGv t = get_temp_tl(dc);
279 if (reg == 0) {
280 tcg_gen_movi_tl(t, 0);
281 } else {
282 tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
283 }
284 return t;
285 } else {
286 return cpu_gregs[reg];
287 }
288 }
289
290 static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
291 {
292 if (reg > 0) {
293 if (reg < 8) {
294 tcg_gen_mov_tl(cpu_gregs[reg], v);
295 } else {
296 tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
297 }
298 }
299 }
300
301 static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
302 {
303 if (reg == 0 || reg >= 8) {
304 return get_temp_tl(dc);
305 } else {
306 return cpu_gregs[reg];
307 }
308 }
309
310 static inline void gen_goto_tb(DisasContext *s, int tb_num,
311 target_ulong pc, target_ulong npc)
312 {
313 TranslationBlock *tb;
314
315 tb = s->tb;
316 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
317 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
318 !s->singlestep) {
319 /* jump to same page: we can use a direct jump */
320 tcg_gen_goto_tb(tb_num);
321 tcg_gen_movi_tl(cpu_pc, pc);
322 tcg_gen_movi_tl(cpu_npc, npc);
323 tcg_gen_exit_tb((uintptr_t)tb + tb_num);
324 } else {
325 /* jump to another page: currently not optimized */
326 tcg_gen_movi_tl(cpu_pc, pc);
327 tcg_gen_movi_tl(cpu_npc, npc);
328 tcg_gen_exit_tb(0);
329 }
330 }
331
332 // XXX suboptimal
333 static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
334 {
335 tcg_gen_extu_i32_tl(reg, src);
336 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
337 tcg_gen_andi_tl(reg, reg, 0x1);
338 }
339
340 static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
341 {
342 tcg_gen_extu_i32_tl(reg, src);
343 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
344 tcg_gen_andi_tl(reg, reg, 0x1);
345 }
346
347 static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
348 {
349 tcg_gen_extu_i32_tl(reg, src);
350 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
351 tcg_gen_andi_tl(reg, reg, 0x1);
352 }
353
354 static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
355 {
356 tcg_gen_extu_i32_tl(reg, src);
357 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
358 tcg_gen_andi_tl(reg, reg, 0x1);
359 }
360
361 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
362 {
363 tcg_gen_mov_tl(cpu_cc_src, src1);
364 tcg_gen_mov_tl(cpu_cc_src2, src2);
365 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
366 tcg_gen_mov_tl(dst, cpu_cc_dst);
367 }
368
369 static TCGv_i32 gen_add32_carry32(void)
370 {
371 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
372
373 /* Carry is computed from a previous add: (dst < src) */
374 #if TARGET_LONG_BITS == 64
375 cc_src1_32 = tcg_temp_new_i32();
376 cc_src2_32 = tcg_temp_new_i32();
377 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
378 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
379 #else
380 cc_src1_32 = cpu_cc_dst;
381 cc_src2_32 = cpu_cc_src;
382 #endif
383
384 carry_32 = tcg_temp_new_i32();
385 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
386
387 #if TARGET_LONG_BITS == 64
388 tcg_temp_free_i32(cc_src1_32);
389 tcg_temp_free_i32(cc_src2_32);
390 #endif
391
392 return carry_32;
393 }
394
395 static TCGv_i32 gen_sub32_carry32(void)
396 {
397 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
398
399 /* Carry is computed from a previous borrow: (src1 < src2) */
400 #if TARGET_LONG_BITS == 64
401 cc_src1_32 = tcg_temp_new_i32();
402 cc_src2_32 = tcg_temp_new_i32();
403 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
404 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
405 #else
406 cc_src1_32 = cpu_cc_src;
407 cc_src2_32 = cpu_cc_src2;
408 #endif
409
410 carry_32 = tcg_temp_new_i32();
411 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
412
413 #if TARGET_LONG_BITS == 64
414 tcg_temp_free_i32(cc_src1_32);
415 tcg_temp_free_i32(cc_src2_32);
416 #endif
417
418 return carry_32;
419 }
420
421 static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
422 TCGv src2, int update_cc)
423 {
424 TCGv_i32 carry_32;
425 TCGv carry;
426
427 switch (dc->cc_op) {
428 case CC_OP_DIV:
429 case CC_OP_LOGIC:
430 /* Carry is known to be zero. Fall back to plain ADD. */
431 if (update_cc) {
432 gen_op_add_cc(dst, src1, src2);
433 } else {
434 tcg_gen_add_tl(dst, src1, src2);
435 }
436 return;
437
438 case CC_OP_ADD:
439 case CC_OP_TADD:
440 case CC_OP_TADDTV:
441 if (TARGET_LONG_BITS == 32) {
442 /* We can re-use the host's hardware carry generation by using
443 an ADD2 opcode. We discard the low part of the output.
444 Ideally we'd combine this operation with the add that
445 generated the carry in the first place. */
446 carry = tcg_temp_new();
447 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
448 tcg_temp_free(carry);
449 goto add_done;
450 }
451 carry_32 = gen_add32_carry32();
452 break;
453
454 case CC_OP_SUB:
455 case CC_OP_TSUB:
456 case CC_OP_TSUBTV:
457 carry_32 = gen_sub32_carry32();
458 break;
459
460 default:
461 /* We need external help to produce the carry. */
462 carry_32 = tcg_temp_new_i32();
463 gen_helper_compute_C_icc(carry_32, cpu_env);
464 break;
465 }
466
467 #if TARGET_LONG_BITS == 64
468 carry = tcg_temp_new();
469 tcg_gen_extu_i32_i64(carry, carry_32);
470 #else
471 carry = carry_32;
472 #endif
473
474 tcg_gen_add_tl(dst, src1, src2);
475 tcg_gen_add_tl(dst, dst, carry);
476
477 tcg_temp_free_i32(carry_32);
478 #if TARGET_LONG_BITS == 64
479 tcg_temp_free(carry);
480 #endif
481
482 add_done:
483 if (update_cc) {
484 tcg_gen_mov_tl(cpu_cc_src, src1);
485 tcg_gen_mov_tl(cpu_cc_src2, src2);
486 tcg_gen_mov_tl(cpu_cc_dst, dst);
487 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
488 dc->cc_op = CC_OP_ADDX;
489 }
490 }
491
492 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
493 {
494 tcg_gen_mov_tl(cpu_cc_src, src1);
495 tcg_gen_mov_tl(cpu_cc_src2, src2);
496 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
497 tcg_gen_mov_tl(dst, cpu_cc_dst);
498 }
499
500 static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
501 TCGv src2, int update_cc)
502 {
503 TCGv_i32 carry_32;
504 TCGv carry;
505
506 switch (dc->cc_op) {
507 case CC_OP_DIV:
508 case CC_OP_LOGIC:
509 /* Carry is known to be zero. Fall back to plain SUB. */
510 if (update_cc) {
511 gen_op_sub_cc(dst, src1, src2);
512 } else {
513 tcg_gen_sub_tl(dst, src1, src2);
514 }
515 return;
516
517 case CC_OP_ADD:
518 case CC_OP_TADD:
519 case CC_OP_TADDTV:
520 carry_32 = gen_add32_carry32();
521 break;
522
523 case CC_OP_SUB:
524 case CC_OP_TSUB:
525 case CC_OP_TSUBTV:
526 if (TARGET_LONG_BITS == 32) {
527 /* We can re-use the host's hardware carry generation by using
528 a SUB2 opcode. We discard the low part of the output.
529 Ideally we'd combine this operation with the add that
530 generated the carry in the first place. */
531 carry = tcg_temp_new();
532 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
533 tcg_temp_free(carry);
534 goto sub_done;
535 }
536 carry_32 = gen_sub32_carry32();
537 break;
538
539 default:
540 /* We need external help to produce the carry. */
541 carry_32 = tcg_temp_new_i32();
542 gen_helper_compute_C_icc(carry_32, cpu_env);
543 break;
544 }
545
546 #if TARGET_LONG_BITS == 64
547 carry = tcg_temp_new();
548 tcg_gen_extu_i32_i64(carry, carry_32);
549 #else
550 carry = carry_32;
551 #endif
552
553 tcg_gen_sub_tl(dst, src1, src2);
554 tcg_gen_sub_tl(dst, dst, carry);
555
556 tcg_temp_free_i32(carry_32);
557 #if TARGET_LONG_BITS == 64
558 tcg_temp_free(carry);
559 #endif
560
561 sub_done:
562 if (update_cc) {
563 tcg_gen_mov_tl(cpu_cc_src, src1);
564 tcg_gen_mov_tl(cpu_cc_src2, src2);
565 tcg_gen_mov_tl(cpu_cc_dst, dst);
566 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
567 dc->cc_op = CC_OP_SUBX;
568 }
569 }
570
571 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
572 {
573 TCGv r_temp, zero, t0;
574
575 r_temp = tcg_temp_new();
576 t0 = tcg_temp_new();
577
578 /* old op:
579 if (!(env->y & 1))
580 T1 = 0;
581 */
582 zero = tcg_const_tl(0);
583 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
584 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
585 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
586 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
587 zero, cpu_cc_src2);
588 tcg_temp_free(zero);
589
590 // b2 = T0 & 1;
591 // env->y = (b2 << 31) | (env->y >> 1);
592 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
593 tcg_gen_shli_tl(r_temp, r_temp, 31);
594 tcg_gen_shri_tl(t0, cpu_y, 1);
595 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
596 tcg_gen_or_tl(t0, t0, r_temp);
597 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
598
599 // b1 = N ^ V;
600 gen_mov_reg_N(t0, cpu_psr);
601 gen_mov_reg_V(r_temp, cpu_psr);
602 tcg_gen_xor_tl(t0, t0, r_temp);
603 tcg_temp_free(r_temp);
604
605 // T0 = (b1 << 31) | (T0 >> 1);
606 // src1 = T0;
607 tcg_gen_shli_tl(t0, t0, 31);
608 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
609 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
610 tcg_temp_free(t0);
611
612 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
613
614 tcg_gen_mov_tl(dst, cpu_cc_dst);
615 }
616
617 static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
618 {
619 #if TARGET_LONG_BITS == 32
620 if (sign_ext) {
621 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
622 } else {
623 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
624 }
625 #else
626 TCGv t0 = tcg_temp_new_i64();
627 TCGv t1 = tcg_temp_new_i64();
628
629 if (sign_ext) {
630 tcg_gen_ext32s_i64(t0, src1);
631 tcg_gen_ext32s_i64(t1, src2);
632 } else {
633 tcg_gen_ext32u_i64(t0, src1);
634 tcg_gen_ext32u_i64(t1, src2);
635 }
636
637 tcg_gen_mul_i64(dst, t0, t1);
638 tcg_temp_free(t0);
639 tcg_temp_free(t1);
640
641 tcg_gen_shri_i64(cpu_y, dst, 32);
642 #endif
643 }
644
645 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
646 {
647 /* zero-extend truncated operands before multiplication */
648 gen_op_multiply(dst, src1, src2, 0);
649 }
650
651 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
652 {
653 /* sign-extend truncated operands before multiplication */
654 gen_op_multiply(dst, src1, src2, 1);
655 }
656
657 // 1
658 static inline void gen_op_eval_ba(TCGv dst)
659 {
660 tcg_gen_movi_tl(dst, 1);
661 }
662
663 // Z
664 static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
665 {
666 gen_mov_reg_Z(dst, src);
667 }
668
669 // Z | (N ^ V)
670 static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
671 {
672 TCGv t0 = tcg_temp_new();
673 gen_mov_reg_N(t0, src);
674 gen_mov_reg_V(dst, src);
675 tcg_gen_xor_tl(dst, dst, t0);
676 gen_mov_reg_Z(t0, src);
677 tcg_gen_or_tl(dst, dst, t0);
678 tcg_temp_free(t0);
679 }
680
681 // N ^ V
682 static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
683 {
684 TCGv t0 = tcg_temp_new();
685 gen_mov_reg_V(t0, src);
686 gen_mov_reg_N(dst, src);
687 tcg_gen_xor_tl(dst, dst, t0);
688 tcg_temp_free(t0);
689 }
690
691 // C | Z
692 static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
693 {
694 TCGv t0 = tcg_temp_new();
695 gen_mov_reg_Z(t0, src);
696 gen_mov_reg_C(dst, src);
697 tcg_gen_or_tl(dst, dst, t0);
698 tcg_temp_free(t0);
699 }
700
701 // C
702 static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
703 {
704 gen_mov_reg_C(dst, src);
705 }
706
707 // V
708 static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
709 {
710 gen_mov_reg_V(dst, src);
711 }
712
713 // 0
714 static inline void gen_op_eval_bn(TCGv dst)
715 {
716 tcg_gen_movi_tl(dst, 0);
717 }
718
719 // N
720 static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
721 {
722 gen_mov_reg_N(dst, src);
723 }
724
725 // !Z
726 static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
727 {
728 gen_mov_reg_Z(dst, src);
729 tcg_gen_xori_tl(dst, dst, 0x1);
730 }
731
732 // !(Z | (N ^ V))
733 static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
734 {
735 gen_op_eval_ble(dst, src);
736 tcg_gen_xori_tl(dst, dst, 0x1);
737 }
738
739 // !(N ^ V)
740 static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
741 {
742 gen_op_eval_bl(dst, src);
743 tcg_gen_xori_tl(dst, dst, 0x1);
744 }
745
746 // !(C | Z)
747 static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
748 {
749 gen_op_eval_bleu(dst, src);
750 tcg_gen_xori_tl(dst, dst, 0x1);
751 }
752
753 // !C
754 static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
755 {
756 gen_mov_reg_C(dst, src);
757 tcg_gen_xori_tl(dst, dst, 0x1);
758 }
759
760 // !N
761 static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
762 {
763 gen_mov_reg_N(dst, src);
764 tcg_gen_xori_tl(dst, dst, 0x1);
765 }
766
767 // !V
768 static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
769 {
770 gen_mov_reg_V(dst, src);
771 tcg_gen_xori_tl(dst, dst, 0x1);
772 }
773
774 /*
775 FPSR bit field FCC1 | FCC0:
776 0 =
777 1 <
778 2 >
779 3 unordered
780 */
781 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
782 unsigned int fcc_offset)
783 {
784 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
785 tcg_gen_andi_tl(reg, reg, 0x1);
786 }
787
788 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
789 unsigned int fcc_offset)
790 {
791 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
792 tcg_gen_andi_tl(reg, reg, 0x1);
793 }
794
795 // !0: FCC0 | FCC1
796 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
797 unsigned int fcc_offset)
798 {
799 TCGv t0 = tcg_temp_new();
800 gen_mov_reg_FCC0(dst, src, fcc_offset);
801 gen_mov_reg_FCC1(t0, src, fcc_offset);
802 tcg_gen_or_tl(dst, dst, t0);
803 tcg_temp_free(t0);
804 }
805
806 // 1 or 2: FCC0 ^ FCC1
807 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
808 unsigned int fcc_offset)
809 {
810 TCGv t0 = tcg_temp_new();
811 gen_mov_reg_FCC0(dst, src, fcc_offset);
812 gen_mov_reg_FCC1(t0, src, fcc_offset);
813 tcg_gen_xor_tl(dst, dst, t0);
814 tcg_temp_free(t0);
815 }
816
817 // 1 or 3: FCC0
818 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
819 unsigned int fcc_offset)
820 {
821 gen_mov_reg_FCC0(dst, src, fcc_offset);
822 }
823
824 // 1: FCC0 & !FCC1
825 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
826 unsigned int fcc_offset)
827 {
828 TCGv t0 = tcg_temp_new();
829 gen_mov_reg_FCC0(dst, src, fcc_offset);
830 gen_mov_reg_FCC1(t0, src, fcc_offset);
831 tcg_gen_andc_tl(dst, dst, t0);
832 tcg_temp_free(t0);
833 }
834
835 // 2 or 3: FCC1
836 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
837 unsigned int fcc_offset)
838 {
839 gen_mov_reg_FCC1(dst, src, fcc_offset);
840 }
841
842 // 2: !FCC0 & FCC1
843 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
844 unsigned int fcc_offset)
845 {
846 TCGv t0 = tcg_temp_new();
847 gen_mov_reg_FCC0(dst, src, fcc_offset);
848 gen_mov_reg_FCC1(t0, src, fcc_offset);
849 tcg_gen_andc_tl(dst, t0, dst);
850 tcg_temp_free(t0);
851 }
852
853 // 3: FCC0 & FCC1
854 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
855 unsigned int fcc_offset)
856 {
857 TCGv t0 = tcg_temp_new();
858 gen_mov_reg_FCC0(dst, src, fcc_offset);
859 gen_mov_reg_FCC1(t0, src, fcc_offset);
860 tcg_gen_and_tl(dst, dst, t0);
861 tcg_temp_free(t0);
862 }
863
864 // 0: !(FCC0 | FCC1)
865 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
866 unsigned int fcc_offset)
867 {
868 TCGv t0 = tcg_temp_new();
869 gen_mov_reg_FCC0(dst, src, fcc_offset);
870 gen_mov_reg_FCC1(t0, src, fcc_offset);
871 tcg_gen_or_tl(dst, dst, t0);
872 tcg_gen_xori_tl(dst, dst, 0x1);
873 tcg_temp_free(t0);
874 }
875
876 // 0 or 3: !(FCC0 ^ FCC1)
877 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
878 unsigned int fcc_offset)
879 {
880 TCGv t0 = tcg_temp_new();
881 gen_mov_reg_FCC0(dst, src, fcc_offset);
882 gen_mov_reg_FCC1(t0, src, fcc_offset);
883 tcg_gen_xor_tl(dst, dst, t0);
884 tcg_gen_xori_tl(dst, dst, 0x1);
885 tcg_temp_free(t0);
886 }
887
888 // 0 or 2: !FCC0
889 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
890 unsigned int fcc_offset)
891 {
892 gen_mov_reg_FCC0(dst, src, fcc_offset);
893 tcg_gen_xori_tl(dst, dst, 0x1);
894 }
895
896 // !1: !(FCC0 & !FCC1)
897 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
898 unsigned int fcc_offset)
899 {
900 TCGv t0 = tcg_temp_new();
901 gen_mov_reg_FCC0(dst, src, fcc_offset);
902 gen_mov_reg_FCC1(t0, src, fcc_offset);
903 tcg_gen_andc_tl(dst, dst, t0);
904 tcg_gen_xori_tl(dst, dst, 0x1);
905 tcg_temp_free(t0);
906 }
907
908 // 0 or 1: !FCC1
909 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
910 unsigned int fcc_offset)
911 {
912 gen_mov_reg_FCC1(dst, src, fcc_offset);
913 tcg_gen_xori_tl(dst, dst, 0x1);
914 }
915
916 // !2: !(!FCC0 & FCC1)
917 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
918 unsigned int fcc_offset)
919 {
920 TCGv t0 = tcg_temp_new();
921 gen_mov_reg_FCC0(dst, src, fcc_offset);
922 gen_mov_reg_FCC1(t0, src, fcc_offset);
923 tcg_gen_andc_tl(dst, t0, dst);
924 tcg_gen_xori_tl(dst, dst, 0x1);
925 tcg_temp_free(t0);
926 }
927
928 // !3: !(FCC0 & FCC1)
929 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
930 unsigned int fcc_offset)
931 {
932 TCGv t0 = tcg_temp_new();
933 gen_mov_reg_FCC0(dst, src, fcc_offset);
934 gen_mov_reg_FCC1(t0, src, fcc_offset);
935 tcg_gen_and_tl(dst, dst, t0);
936 tcg_gen_xori_tl(dst, dst, 0x1);
937 tcg_temp_free(t0);
938 }
939
940 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
941 target_ulong pc2, TCGv r_cond)
942 {
943 TCGLabel *l1 = gen_new_label();
944
945 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
946
947 gen_goto_tb(dc, 0, pc1, pc1 + 4);
948
949 gen_set_label(l1);
950 gen_goto_tb(dc, 1, pc2, pc2 + 4);
951 }
952
953 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
954 target_ulong pc2, TCGv r_cond)
955 {
956 TCGLabel *l1 = gen_new_label();
957
958 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
959
960 gen_goto_tb(dc, 0, pc2, pc1);
961
962 gen_set_label(l1);
963 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
964 }
965
966 static inline void gen_generic_branch(DisasContext *dc)
967 {
968 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
969 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
970 TCGv zero = tcg_const_tl(0);
971
972 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
973
974 tcg_temp_free(npc0);
975 tcg_temp_free(npc1);
976 tcg_temp_free(zero);
977 }
978
979 /* call this function before using the condition register as it may
980 have been set for a jump */
981 static inline void flush_cond(DisasContext *dc)
982 {
983 if (dc->npc == JUMP_PC) {
984 gen_generic_branch(dc);
985 dc->npc = DYNAMIC_PC;
986 }
987 }
988
989 static inline void save_npc(DisasContext *dc)
990 {
991 if (dc->npc == JUMP_PC) {
992 gen_generic_branch(dc);
993 dc->npc = DYNAMIC_PC;
994 } else if (dc->npc != DYNAMIC_PC) {
995 tcg_gen_movi_tl(cpu_npc, dc->npc);
996 }
997 }
998
999 static inline void update_psr(DisasContext *dc)
1000 {
1001 if (dc->cc_op != CC_OP_FLAGS) {
1002 dc->cc_op = CC_OP_FLAGS;
1003 gen_helper_compute_psr(cpu_env);
1004 }
1005 }
1006
1007 static inline void save_state(DisasContext *dc)
1008 {
1009 tcg_gen_movi_tl(cpu_pc, dc->pc);
1010 save_npc(dc);
1011 }
1012
1013 static inline void gen_mov_pc_npc(DisasContext *dc)
1014 {
1015 if (dc->npc == JUMP_PC) {
1016 gen_generic_branch(dc);
1017 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1018 dc->pc = DYNAMIC_PC;
1019 } else if (dc->npc == DYNAMIC_PC) {
1020 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1021 dc->pc = DYNAMIC_PC;
1022 } else {
1023 dc->pc = dc->npc;
1024 }
1025 }
1026
1027 static inline void gen_op_next_insn(void)
1028 {
1029 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1030 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1031 }
1032
1033 static void free_compare(DisasCompare *cmp)
1034 {
1035 if (!cmp->g1) {
1036 tcg_temp_free(cmp->c1);
1037 }
1038 if (!cmp->g2) {
1039 tcg_temp_free(cmp->c2);
1040 }
1041 }
1042
1043 static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
1044 DisasContext *dc)
1045 {
1046 static int subcc_cond[16] = {
1047 TCG_COND_NEVER,
1048 TCG_COND_EQ,
1049 TCG_COND_LE,
1050 TCG_COND_LT,
1051 TCG_COND_LEU,
1052 TCG_COND_LTU,
1053 -1, /* neg */
1054 -1, /* overflow */
1055 TCG_COND_ALWAYS,
1056 TCG_COND_NE,
1057 TCG_COND_GT,
1058 TCG_COND_GE,
1059 TCG_COND_GTU,
1060 TCG_COND_GEU,
1061 -1, /* pos */
1062 -1, /* no overflow */
1063 };
1064
1065 static int logic_cond[16] = {
1066 TCG_COND_NEVER,
1067 TCG_COND_EQ, /* eq: Z */
1068 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1069 TCG_COND_LT, /* lt: N ^ V -> N */
1070 TCG_COND_EQ, /* leu: C | Z -> Z */
1071 TCG_COND_NEVER, /* ltu: C -> 0 */
1072 TCG_COND_LT, /* neg: N */
1073 TCG_COND_NEVER, /* vs: V -> 0 */
1074 TCG_COND_ALWAYS,
1075 TCG_COND_NE, /* ne: !Z */
1076 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1077 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1078 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1079 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1080 TCG_COND_GE, /* pos: !N */
1081 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1082 };
1083
1084 TCGv_i32 r_src;
1085 TCGv r_dst;
1086
1087 #ifdef TARGET_SPARC64
1088 if (xcc) {
1089 r_src = cpu_xcc;
1090 } else {
1091 r_src = cpu_psr;
1092 }
1093 #else
1094 r_src = cpu_psr;
1095 #endif
1096
1097 switch (dc->cc_op) {
1098 case CC_OP_LOGIC:
1099 cmp->cond = logic_cond[cond];
1100 do_compare_dst_0:
1101 cmp->is_bool = false;
1102 cmp->g2 = false;
1103 cmp->c2 = tcg_const_tl(0);
1104 #ifdef TARGET_SPARC64
1105 if (!xcc) {
1106 cmp->g1 = false;
1107 cmp->c1 = tcg_temp_new();
1108 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1109 break;
1110 }
1111 #endif
1112 cmp->g1 = true;
1113 cmp->c1 = cpu_cc_dst;
1114 break;
1115
1116 case CC_OP_SUB:
1117 switch (cond) {
1118 case 6: /* neg */
1119 case 14: /* pos */
1120 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
1121 goto do_compare_dst_0;
1122
1123 case 7: /* overflow */
1124 case 15: /* !overflow */
1125 goto do_dynamic;
1126
1127 default:
1128 cmp->cond = subcc_cond[cond];
1129 cmp->is_bool = false;
1130 #ifdef TARGET_SPARC64
1131 if (!xcc) {
1132 /* Note that sign-extension works for unsigned compares as
1133 long as both operands are sign-extended. */
1134 cmp->g1 = cmp->g2 = false;
1135 cmp->c1 = tcg_temp_new();
1136 cmp->c2 = tcg_temp_new();
1137 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1138 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
1139 break;
1140 }
1141 #endif
1142 cmp->g1 = cmp->g2 = true;
1143 cmp->c1 = cpu_cc_src;
1144 cmp->c2 = cpu_cc_src2;
1145 break;
1146 }
1147 break;
1148
1149 default:
1150 do_dynamic:
1151 gen_helper_compute_psr(cpu_env);
1152 dc->cc_op = CC_OP_FLAGS;
1153 /* FALLTHRU */
1154
1155 case CC_OP_FLAGS:
1156 /* We're going to generate a boolean result. */
1157 cmp->cond = TCG_COND_NE;
1158 cmp->is_bool = true;
1159 cmp->g1 = cmp->g2 = false;
1160 cmp->c1 = r_dst = tcg_temp_new();
1161 cmp->c2 = tcg_const_tl(0);
1162
1163 switch (cond) {
1164 case 0x0:
1165 gen_op_eval_bn(r_dst);
1166 break;
1167 case 0x1:
1168 gen_op_eval_be(r_dst, r_src);
1169 break;
1170 case 0x2:
1171 gen_op_eval_ble(r_dst, r_src);
1172 break;
1173 case 0x3:
1174 gen_op_eval_bl(r_dst, r_src);
1175 break;
1176 case 0x4:
1177 gen_op_eval_bleu(r_dst, r_src);
1178 break;
1179 case 0x5:
1180 gen_op_eval_bcs(r_dst, r_src);
1181 break;
1182 case 0x6:
1183 gen_op_eval_bneg(r_dst, r_src);
1184 break;
1185 case 0x7:
1186 gen_op_eval_bvs(r_dst, r_src);
1187 break;
1188 case 0x8:
1189 gen_op_eval_ba(r_dst);
1190 break;
1191 case 0x9:
1192 gen_op_eval_bne(r_dst, r_src);
1193 break;
1194 case 0xa:
1195 gen_op_eval_bg(r_dst, r_src);
1196 break;
1197 case 0xb:
1198 gen_op_eval_bge(r_dst, r_src);
1199 break;
1200 case 0xc:
1201 gen_op_eval_bgu(r_dst, r_src);
1202 break;
1203 case 0xd:
1204 gen_op_eval_bcc(r_dst, r_src);
1205 break;
1206 case 0xe:
1207 gen_op_eval_bpos(r_dst, r_src);
1208 break;
1209 case 0xf:
1210 gen_op_eval_bvc(r_dst, r_src);
1211 break;
1212 }
1213 break;
1214 }
1215 }
1216
1217 static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
1218 {
1219 unsigned int offset;
1220 TCGv r_dst;
1221
1222 /* For now we still generate a straight boolean result. */
1223 cmp->cond = TCG_COND_NE;
1224 cmp->is_bool = true;
1225 cmp->g1 = cmp->g2 = false;
1226 cmp->c1 = r_dst = tcg_temp_new();
1227 cmp->c2 = tcg_const_tl(0);
1228
1229 switch (cc) {
1230 default:
1231 case 0x0:
1232 offset = 0;
1233 break;
1234 case 0x1:
1235 offset = 32 - 10;
1236 break;
1237 case 0x2:
1238 offset = 34 - 10;
1239 break;
1240 case 0x3:
1241 offset = 36 - 10;
1242 break;
1243 }
1244
1245 switch (cond) {
1246 case 0x0:
1247 gen_op_eval_bn(r_dst);
1248 break;
1249 case 0x1:
1250 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1251 break;
1252 case 0x2:
1253 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1254 break;
1255 case 0x3:
1256 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1257 break;
1258 case 0x4:
1259 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1260 break;
1261 case 0x5:
1262 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1263 break;
1264 case 0x6:
1265 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1266 break;
1267 case 0x7:
1268 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1269 break;
1270 case 0x8:
1271 gen_op_eval_ba(r_dst);
1272 break;
1273 case 0x9:
1274 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1275 break;
1276 case 0xa:
1277 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1278 break;
1279 case 0xb:
1280 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1281 break;
1282 case 0xc:
1283 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1284 break;
1285 case 0xd:
1286 gen_op_eval_fble(r_dst, cpu_fsr, offset);
1287 break;
1288 case 0xe:
1289 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1290 break;
1291 case 0xf:
1292 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1293 break;
1294 }
1295 }
1296
1297 static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1298 DisasContext *dc)
1299 {
1300 DisasCompare cmp;
1301 gen_compare(&cmp, cc, cond, dc);
1302
1303 /* The interface is to return a boolean in r_dst. */
1304 if (cmp.is_bool) {
1305 tcg_gen_mov_tl(r_dst, cmp.c1);
1306 } else {
1307 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1308 }
1309
1310 free_compare(&cmp);
1311 }
1312
1313 static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1314 {
1315 DisasCompare cmp;
1316 gen_fcompare(&cmp, cc, cond);
1317
1318 /* The interface is to return a boolean in r_dst. */
1319 if (cmp.is_bool) {
1320 tcg_gen_mov_tl(r_dst, cmp.c1);
1321 } else {
1322 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1323 }
1324
1325 free_compare(&cmp);
1326 }
1327
1328 #ifdef TARGET_SPARC64
1329 // Inverted logic
1330 static const int gen_tcg_cond_reg[8] = {
1331 -1,
1332 TCG_COND_NE,
1333 TCG_COND_GT,
1334 TCG_COND_GE,
1335 -1,
1336 TCG_COND_EQ,
1337 TCG_COND_LE,
1338 TCG_COND_LT,
1339 };
1340
1341 static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1342 {
1343 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1344 cmp->is_bool = false;
1345 cmp->g1 = true;
1346 cmp->g2 = false;
1347 cmp->c1 = r_src;
1348 cmp->c2 = tcg_const_tl(0);
1349 }
1350
1351 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1352 {
1353 DisasCompare cmp;
1354 gen_compare_reg(&cmp, cond, r_src);
1355
1356 /* The interface is to return a boolean in r_dst. */
1357 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1358
1359 free_compare(&cmp);
1360 }
1361 #endif
1362
1363 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
1364 {
1365 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1366 target_ulong target = dc->pc + offset;
1367
1368 #ifdef TARGET_SPARC64
1369 if (unlikely(AM_CHECK(dc))) {
1370 target &= 0xffffffffULL;
1371 }
1372 #endif
1373 if (cond == 0x0) {
1374 /* unconditional not taken */
1375 if (a) {
1376 dc->pc = dc->npc + 4;
1377 dc->npc = dc->pc + 4;
1378 } else {
1379 dc->pc = dc->npc;
1380 dc->npc = dc->pc + 4;
1381 }
1382 } else if (cond == 0x8) {
1383 /* unconditional taken */
1384 if (a) {
1385 dc->pc = target;
1386 dc->npc = dc->pc + 4;
1387 } else {
1388 dc->pc = dc->npc;
1389 dc->npc = target;
1390 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1391 }
1392 } else {
1393 flush_cond(dc);
1394 gen_cond(cpu_cond, cc, cond, dc);
1395 if (a) {
1396 gen_branch_a(dc, target, dc->npc, cpu_cond);
1397 dc->is_br = 1;
1398 } else {
1399 dc->pc = dc->npc;
1400 dc->jump_pc[0] = target;
1401 if (unlikely(dc->npc == DYNAMIC_PC)) {
1402 dc->jump_pc[1] = DYNAMIC_PC;
1403 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1404 } else {
1405 dc->jump_pc[1] = dc->npc + 4;
1406 dc->npc = JUMP_PC;
1407 }
1408 }
1409 }
1410 }
1411
1412 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
1413 {
1414 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1415 target_ulong target = dc->pc + offset;
1416
1417 #ifdef TARGET_SPARC64
1418 if (unlikely(AM_CHECK(dc))) {
1419 target &= 0xffffffffULL;
1420 }
1421 #endif
1422 if (cond == 0x0) {
1423 /* unconditional not taken */
1424 if (a) {
1425 dc->pc = dc->npc + 4;
1426 dc->npc = dc->pc + 4;
1427 } else {
1428 dc->pc = dc->npc;
1429 dc->npc = dc->pc + 4;
1430 }
1431 } else if (cond == 0x8) {
1432 /* unconditional taken */
1433 if (a) {
1434 dc->pc = target;
1435 dc->npc = dc->pc + 4;
1436 } else {
1437 dc->pc = dc->npc;
1438 dc->npc = target;
1439 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1440 }
1441 } else {
1442 flush_cond(dc);
1443 gen_fcond(cpu_cond, cc, cond);
1444 if (a) {
1445 gen_branch_a(dc, target, dc->npc, cpu_cond);
1446 dc->is_br = 1;
1447 } else {
1448 dc->pc = dc->npc;
1449 dc->jump_pc[0] = target;
1450 if (unlikely(dc->npc == DYNAMIC_PC)) {
1451 dc->jump_pc[1] = DYNAMIC_PC;
1452 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1453 } else {
1454 dc->jump_pc[1] = dc->npc + 4;
1455 dc->npc = JUMP_PC;
1456 }
1457 }
1458 }
1459 }
1460
1461 #ifdef TARGET_SPARC64
1462 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1463 TCGv r_reg)
1464 {
1465 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1466 target_ulong target = dc->pc + offset;
1467
1468 if (unlikely(AM_CHECK(dc))) {
1469 target &= 0xffffffffULL;
1470 }
1471 flush_cond(dc);
1472 gen_cond_reg(cpu_cond, cond, r_reg);
1473 if (a) {
1474 gen_branch_a(dc, target, dc->npc, cpu_cond);
1475 dc->is_br = 1;
1476 } else {
1477 dc->pc = dc->npc;
1478 dc->jump_pc[0] = target;
1479 if (unlikely(dc->npc == DYNAMIC_PC)) {
1480 dc->jump_pc[1] = DYNAMIC_PC;
1481 tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
1482 } else {
1483 dc->jump_pc[1] = dc->npc + 4;
1484 dc->npc = JUMP_PC;
1485 }
1486 }
1487 }
1488
1489 static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1490 {
1491 switch (fccno) {
1492 case 0:
1493 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
1494 break;
1495 case 1:
1496 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
1497 break;
1498 case 2:
1499 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
1500 break;
1501 case 3:
1502 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
1503 break;
1504 }
1505 }
1506
1507 static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1508 {
1509 switch (fccno) {
1510 case 0:
1511 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
1512 break;
1513 case 1:
1514 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
1515 break;
1516 case 2:
1517 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
1518 break;
1519 case 3:
1520 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
1521 break;
1522 }
1523 }
1524
1525 static inline void gen_op_fcmpq(int fccno)
1526 {
1527 switch (fccno) {
1528 case 0:
1529 gen_helper_fcmpq(cpu_env);
1530 break;
1531 case 1:
1532 gen_helper_fcmpq_fcc1(cpu_env);
1533 break;
1534 case 2:
1535 gen_helper_fcmpq_fcc2(cpu_env);
1536 break;
1537 case 3:
1538 gen_helper_fcmpq_fcc3(cpu_env);
1539 break;
1540 }
1541 }
1542
1543 static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1544 {
1545 switch (fccno) {
1546 case 0:
1547 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
1548 break;
1549 case 1:
1550 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
1551 break;
1552 case 2:
1553 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
1554 break;
1555 case 3:
1556 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
1557 break;
1558 }
1559 }
1560
1561 static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1562 {
1563 switch (fccno) {
1564 case 0:
1565 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
1566 break;
1567 case 1:
1568 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
1569 break;
1570 case 2:
1571 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
1572 break;
1573 case 3:
1574 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
1575 break;
1576 }
1577 }
1578
1579 static inline void gen_op_fcmpeq(int fccno)
1580 {
1581 switch (fccno) {
1582 case 0:
1583 gen_helper_fcmpeq(cpu_env);
1584 break;
1585 case 1:
1586 gen_helper_fcmpeq_fcc1(cpu_env);
1587 break;
1588 case 2:
1589 gen_helper_fcmpeq_fcc2(cpu_env);
1590 break;
1591 case 3:
1592 gen_helper_fcmpeq_fcc3(cpu_env);
1593 break;
1594 }
1595 }
1596
1597 #else
1598
1599 static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
1600 {
1601 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
1602 }
1603
1604 static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1605 {
1606 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
1607 }
1608
1609 static inline void gen_op_fcmpq(int fccno)
1610 {
1611 gen_helper_fcmpq(cpu_env);
1612 }
1613
1614 static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
1615 {
1616 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
1617 }
1618
1619 static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
1620 {
1621 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
1622 }
1623
1624 static inline void gen_op_fcmpeq(int fccno)
1625 {
1626 gen_helper_fcmpeq(cpu_env);
1627 }
1628 #endif
1629
1630 static inline void gen_op_fpexception_im(int fsr_flags)
1631 {
1632 TCGv_i32 r_const;
1633
1634 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
1635 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1636 r_const = tcg_const_i32(TT_FP_EXCP);
1637 gen_helper_raise_exception(cpu_env, r_const);
1638 tcg_temp_free_i32(r_const);
1639 }
1640
1641 static int gen_trap_ifnofpu(DisasContext *dc)
1642 {
1643 #if !defined(CONFIG_USER_ONLY)
1644 if (!dc->fpu_enabled) {
1645 TCGv_i32 r_const;
1646
1647 save_state(dc);
1648 r_const = tcg_const_i32(TT_NFPU_INSN);
1649 gen_helper_raise_exception(cpu_env, r_const);
1650 tcg_temp_free_i32(r_const);
1651 dc->is_br = 1;
1652 return 1;
1653 }
1654 #endif
1655 return 0;
1656 }
1657
1658 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1659 {
1660 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
1661 }
1662
1663 static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1664 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1665 {
1666 TCGv_i32 dst, src;
1667
1668 src = gen_load_fpr_F(dc, rs);
1669 dst = gen_dest_fpr_F(dc);
1670
1671 gen(dst, cpu_env, src);
1672
1673 gen_store_fpr_F(dc, rd, dst);
1674 }
1675
1676 static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1677 void (*gen)(TCGv_i32, TCGv_i32))
1678 {
1679 TCGv_i32 dst, src;
1680
1681 src = gen_load_fpr_F(dc, rs);
1682 dst = gen_dest_fpr_F(dc);
1683
1684 gen(dst, src);
1685
1686 gen_store_fpr_F(dc, rd, dst);
1687 }
1688
1689 static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1690 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1691 {
1692 TCGv_i32 dst, src1, src2;
1693
1694 src1 = gen_load_fpr_F(dc, rs1);
1695 src2 = gen_load_fpr_F(dc, rs2);
1696 dst = gen_dest_fpr_F(dc);
1697
1698 gen(dst, cpu_env, src1, src2);
1699
1700 gen_store_fpr_F(dc, rd, dst);
1701 }
1702
1703 #ifdef TARGET_SPARC64
1704 static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1705 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1706 {
1707 TCGv_i32 dst, src1, src2;
1708
1709 src1 = gen_load_fpr_F(dc, rs1);
1710 src2 = gen_load_fpr_F(dc, rs2);
1711 dst = gen_dest_fpr_F(dc);
1712
1713 gen(dst, src1, src2);
1714
1715 gen_store_fpr_F(dc, rd, dst);
1716 }
1717 #endif
1718
1719 static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1720 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1721 {
1722 TCGv_i64 dst, src;
1723
1724 src = gen_load_fpr_D(dc, rs);
1725 dst = gen_dest_fpr_D(dc, rd);
1726
1727 gen(dst, cpu_env, src);
1728
1729 gen_store_fpr_D(dc, rd, dst);
1730 }
1731
1732 #ifdef TARGET_SPARC64
1733 static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1734 void (*gen)(TCGv_i64, TCGv_i64))
1735 {
1736 TCGv_i64 dst, src;
1737
1738 src = gen_load_fpr_D(dc, rs);
1739 dst = gen_dest_fpr_D(dc, rd);
1740
1741 gen(dst, src);
1742
1743 gen_store_fpr_D(dc, rd, dst);
1744 }
1745 #endif
1746
1747 static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1748 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1749 {
1750 TCGv_i64 dst, src1, src2;
1751
1752 src1 = gen_load_fpr_D(dc, rs1);
1753 src2 = gen_load_fpr_D(dc, rs2);
1754 dst = gen_dest_fpr_D(dc, rd);
1755
1756 gen(dst, cpu_env, src1, src2);
1757
1758 gen_store_fpr_D(dc, rd, dst);
1759 }
1760
1761 #ifdef TARGET_SPARC64
1762 static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1763 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1764 {
1765 TCGv_i64 dst, src1, src2;
1766
1767 src1 = gen_load_fpr_D(dc, rs1);
1768 src2 = gen_load_fpr_D(dc, rs2);
1769 dst = gen_dest_fpr_D(dc, rd);
1770
1771 gen(dst, src1, src2);
1772
1773 gen_store_fpr_D(dc, rd, dst);
1774 }
1775
1776 static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1777 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1778 {
1779 TCGv_i64 dst, src1, src2;
1780
1781 src1 = gen_load_fpr_D(dc, rs1);
1782 src2 = gen_load_fpr_D(dc, rs2);
1783 dst = gen_dest_fpr_D(dc, rd);
1784
1785 gen(dst, cpu_gsr, src1, src2);
1786
1787 gen_store_fpr_D(dc, rd, dst);
1788 }
1789
1790 static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1791 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1792 {
1793 TCGv_i64 dst, src0, src1, src2;
1794
1795 src1 = gen_load_fpr_D(dc, rs1);
1796 src2 = gen_load_fpr_D(dc, rs2);
1797 src0 = gen_load_fpr_D(dc, rd);
1798 dst = gen_dest_fpr_D(dc, rd);
1799
1800 gen(dst, src0, src1, src2);
1801
1802 gen_store_fpr_D(dc, rd, dst);
1803 }
1804 #endif
1805
1806 static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1807 void (*gen)(TCGv_ptr))
1808 {
1809 gen_op_load_fpr_QT1(QFPREG(rs));
1810
1811 gen(cpu_env);
1812
1813 gen_op_store_QT0_fpr(QFPREG(rd));
1814 gen_update_fprs_dirty(QFPREG(rd));
1815 }
1816
1817 #ifdef TARGET_SPARC64
1818 static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1819 void (*gen)(TCGv_ptr))
1820 {
1821 gen_op_load_fpr_QT1(QFPREG(rs));
1822
1823 gen(cpu_env);
1824
1825 gen_op_store_QT0_fpr(QFPREG(rd));
1826 gen_update_fprs_dirty(QFPREG(rd));
1827 }
1828 #endif
1829
1830 static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1831 void (*gen)(TCGv_ptr))
1832 {
1833 gen_op_load_fpr_QT0(QFPREG(rs1));
1834 gen_op_load_fpr_QT1(QFPREG(rs2));
1835
1836 gen(cpu_env);
1837
1838 gen_op_store_QT0_fpr(QFPREG(rd));
1839 gen_update_fprs_dirty(QFPREG(rd));
1840 }
1841
1842 static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1843 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1844 {
1845 TCGv_i64 dst;
1846 TCGv_i32 src1, src2;
1847
1848 src1 = gen_load_fpr_F(dc, rs1);
1849 src2 = gen_load_fpr_F(dc, rs2);
1850 dst = gen_dest_fpr_D(dc, rd);
1851
1852 gen(dst, cpu_env, src1, src2);
1853
1854 gen_store_fpr_D(dc, rd, dst);
1855 }
1856
1857 static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1858 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1859 {
1860 TCGv_i64 src1, src2;
1861
1862 src1 = gen_load_fpr_D(dc, rs1);
1863 src2 = gen_load_fpr_D(dc, rs2);
1864
1865 gen(cpu_env, src1, src2);
1866
1867 gen_op_store_QT0_fpr(QFPREG(rd));
1868 gen_update_fprs_dirty(QFPREG(rd));
1869 }
1870
1871 #ifdef TARGET_SPARC64
1872 static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1873 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1874 {
1875 TCGv_i64 dst;
1876 TCGv_i32 src;
1877
1878 src = gen_load_fpr_F(dc, rs);
1879 dst = gen_dest_fpr_D(dc, rd);
1880
1881 gen(dst, cpu_env, src);
1882
1883 gen_store_fpr_D(dc, rd, dst);
1884 }
1885 #endif
1886
1887 static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1888 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1889 {
1890 TCGv_i64 dst;
1891 TCGv_i32 src;
1892
1893 src = gen_load_fpr_F(dc, rs);
1894 dst = gen_dest_fpr_D(dc, rd);
1895
1896 gen(dst, cpu_env, src);
1897
1898 gen_store_fpr_D(dc, rd, dst);
1899 }
1900
1901 static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1902 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1903 {
1904 TCGv_i32 dst;
1905 TCGv_i64 src;
1906
1907 src = gen_load_fpr_D(dc, rs);
1908 dst = gen_dest_fpr_F(dc);
1909
1910 gen(dst, cpu_env, src);
1911
1912 gen_store_fpr_F(dc, rd, dst);
1913 }
1914
1915 static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1916 void (*gen)(TCGv_i32, TCGv_ptr))
1917 {
1918 TCGv_i32 dst;
1919
1920 gen_op_load_fpr_QT1(QFPREG(rs));
1921 dst = gen_dest_fpr_F(dc);
1922
1923 gen(dst, cpu_env);
1924
1925 gen_store_fpr_F(dc, rd, dst);
1926 }
1927
1928 static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1929 void (*gen)(TCGv_i64, TCGv_ptr))
1930 {
1931 TCGv_i64 dst;
1932
1933 gen_op_load_fpr_QT1(QFPREG(rs));
1934 dst = gen_dest_fpr_D(dc, rd);
1935
1936 gen(dst, cpu_env);
1937
1938 gen_store_fpr_D(dc, rd, dst);
1939 }
1940
1941 static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1942 void (*gen)(TCGv_ptr, TCGv_i32))
1943 {
1944 TCGv_i32 src;
1945
1946 src = gen_load_fpr_F(dc, rs);
1947
1948 gen(cpu_env, src);
1949
1950 gen_op_store_QT0_fpr(QFPREG(rd));
1951 gen_update_fprs_dirty(QFPREG(rd));
1952 }
1953
1954 static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1955 void (*gen)(TCGv_ptr, TCGv_i64))
1956 {
1957 TCGv_i64 src;
1958
1959 src = gen_load_fpr_D(dc, rs);
1960
1961 gen(cpu_env, src);
1962
1963 gen_op_store_QT0_fpr(QFPREG(rd));
1964 gen_update_fprs_dirty(QFPREG(rd));
1965 }
1966
1967 /* asi moves */
1968 #ifdef TARGET_SPARC64
1969 static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1970 {
1971 int asi;
1972 TCGv_i32 r_asi;
1973
1974 if (IS_IMM) {
1975 r_asi = tcg_temp_new_i32();
1976 tcg_gen_mov_i32(r_asi, cpu_asi);
1977 } else {
1978 asi = GET_FIELD(insn, 19, 26);
1979 r_asi = tcg_const_i32(asi);
1980 }
1981 return r_asi;
1982 }
1983
1984 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1985 int sign)
1986 {
1987 TCGv_i32 r_asi, r_size, r_sign;
1988
1989 r_asi = gen_get_asi(insn, addr);
1990 r_size = tcg_const_i32(size);
1991 r_sign = tcg_const_i32(sign);
1992 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
1993 tcg_temp_free_i32(r_sign);
1994 tcg_temp_free_i32(r_size);
1995 tcg_temp_free_i32(r_asi);
1996 }
1997
1998 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1999 {
2000 TCGv_i32 r_asi, r_size;
2001
2002 r_asi = gen_get_asi(insn, addr);
2003 r_size = tcg_const_i32(size);
2004 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
2005 tcg_temp_free_i32(r_size);
2006 tcg_temp_free_i32(r_asi);
2007 }
2008
2009 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
2010 {
2011 TCGv_i32 r_asi, r_size, r_rd;
2012
2013 r_asi = gen_get_asi(insn, addr);
2014 r_size = tcg_const_i32(size);
2015 r_rd = tcg_const_i32(rd);
2016 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
2017 tcg_temp_free_i32(r_rd);
2018 tcg_temp_free_i32(r_size);
2019 tcg_temp_free_i32(r_asi);
2020 }
2021
2022 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
2023 {
2024 TCGv_i32 r_asi, r_size, r_rd;
2025
2026 r_asi = gen_get_asi(insn, addr);
2027 r_size = tcg_const_i32(size);
2028 r_rd = tcg_const_i32(rd);
2029 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
2030 tcg_temp_free_i32(r_rd);
2031 tcg_temp_free_i32(r_size);
2032 tcg_temp_free_i32(r_asi);
2033 }
2034
2035 static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
2036 {
2037 TCGv_i32 r_asi, r_size, r_sign;
2038 TCGv_i64 t64 = tcg_temp_new_i64();
2039
2040 r_asi = gen_get_asi(insn, addr);
2041 r_size = tcg_const_i32(4);
2042 r_sign = tcg_const_i32(0);
2043 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2044 tcg_temp_free_i32(r_sign);
2045 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
2046 tcg_temp_free_i32(r_size);
2047 tcg_temp_free_i32(r_asi);
2048 tcg_gen_trunc_i64_tl(dst, t64);
2049 tcg_temp_free_i64(t64);
2050 }
2051
2052 static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2053 int insn, int rd)
2054 {
2055 TCGv_i32 r_asi, r_rd;
2056
2057 r_asi = gen_get_asi(insn, addr);
2058 r_rd = tcg_const_i32(rd);
2059 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
2060 tcg_temp_free_i32(r_rd);
2061 tcg_temp_free_i32(r_asi);
2062 }
2063
2064 static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2065 int insn, int rd)
2066 {
2067 TCGv_i32 r_asi, r_size;
2068 TCGv lo = gen_load_gpr(dc, rd + 1);
2069 TCGv_i64 t64 = tcg_temp_new_i64();
2070
2071 tcg_gen_concat_tl_i64(t64, lo, hi);
2072 r_asi = gen_get_asi(insn, addr);
2073 r_size = tcg_const_i32(8);
2074 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2075 tcg_temp_free_i32(r_size);
2076 tcg_temp_free_i32(r_asi);
2077 tcg_temp_free_i64(t64);
2078 }
2079
2080 static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
2081 TCGv val2, int insn, int rd)
2082 {
2083 TCGv val1 = gen_load_gpr(dc, rd);
2084 TCGv dst = gen_dest_gpr(dc, rd);
2085 TCGv_i32 r_asi = gen_get_asi(insn, addr);
2086
2087 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
2088 tcg_temp_free_i32(r_asi);
2089 gen_store_gpr(dc, rd, dst);
2090 }
2091
2092 #elif !defined(CONFIG_USER_ONLY)
2093
2094 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
2095 int sign)
2096 {
2097 TCGv_i32 r_asi, r_size, r_sign;
2098 TCGv_i64 t64 = tcg_temp_new_i64();
2099
2100 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2101 r_size = tcg_const_i32(size);
2102 r_sign = tcg_const_i32(sign);
2103 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2104 tcg_temp_free_i32(r_sign);
2105 tcg_temp_free_i32(r_size);
2106 tcg_temp_free_i32(r_asi);
2107 tcg_gen_trunc_i64_tl(dst, t64);
2108 tcg_temp_free_i64(t64);
2109 }
2110
2111 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
2112 {
2113 TCGv_i32 r_asi, r_size;
2114 TCGv_i64 t64 = tcg_temp_new_i64();
2115
2116 tcg_gen_extu_tl_i64(t64, src);
2117 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2118 r_size = tcg_const_i32(size);
2119 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2120 tcg_temp_free_i32(r_size);
2121 tcg_temp_free_i32(r_asi);
2122 tcg_temp_free_i64(t64);
2123 }
2124
2125 static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
2126 {
2127 TCGv_i32 r_asi, r_size, r_sign;
2128 TCGv_i64 r_val, t64;
2129
2130 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2131 r_size = tcg_const_i32(4);
2132 r_sign = tcg_const_i32(0);
2133 t64 = tcg_temp_new_i64();
2134 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2135 tcg_temp_free(r_sign);
2136 r_val = tcg_temp_new_i64();
2137 tcg_gen_extu_tl_i64(r_val, src);
2138 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
2139 tcg_temp_free_i64(r_val);
2140 tcg_temp_free_i32(r_size);
2141 tcg_temp_free_i32(r_asi);
2142 tcg_gen_trunc_i64_tl(dst, t64);
2143 tcg_temp_free_i64(t64);
2144 }
2145
2146 static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2147 int insn, int rd)
2148 {
2149 TCGv_i32 r_asi, r_size, r_sign;
2150 TCGv t;
2151 TCGv_i64 t64;
2152
2153 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2154 r_size = tcg_const_i32(8);
2155 r_sign = tcg_const_i32(0);
2156 t64 = tcg_temp_new_i64();
2157 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2158 tcg_temp_free_i32(r_sign);
2159 tcg_temp_free_i32(r_size);
2160 tcg_temp_free_i32(r_asi);
2161
2162 t = gen_dest_gpr(dc, rd + 1);
2163 tcg_gen_trunc_i64_tl(t, t64);
2164 gen_store_gpr(dc, rd + 1, t);
2165
2166 tcg_gen_shri_i64(t64, t64, 32);
2167 tcg_gen_trunc_i64_tl(hi, t64);
2168 tcg_temp_free_i64(t64);
2169 gen_store_gpr(dc, rd, hi);
2170 }
2171
2172 static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2173 int insn, int rd)
2174 {
2175 TCGv_i32 r_asi, r_size;
2176 TCGv lo = gen_load_gpr(dc, rd + 1);
2177 TCGv_i64 t64 = tcg_temp_new_i64();
2178
2179 tcg_gen_concat_tl_i64(t64, lo, hi);
2180 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2181 r_size = tcg_const_i32(8);
2182 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2183 tcg_temp_free_i32(r_size);
2184 tcg_temp_free_i32(r_asi);
2185 tcg_temp_free_i64(t64);
2186 }
2187 #endif
2188
2189 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2190 static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
2191 TCGv val2, int insn, int rd)
2192 {
2193 TCGv val1 = gen_load_gpr(dc, rd);
2194 TCGv dst = gen_dest_gpr(dc, rd);
2195 #ifdef TARGET_SPARC64
2196 TCGv_i32 r_asi = gen_get_asi(insn, addr);
2197 #else
2198 TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2199 #endif
2200
2201 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2202 tcg_temp_free_i32(r_asi);
2203 gen_store_gpr(dc, rd, dst);
2204 }
2205
2206 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
2207 {
2208 TCGv_i64 r_val;
2209 TCGv_i32 r_asi, r_size;
2210
2211 gen_ld_asi(dst, addr, insn, 1, 0);
2212
2213 r_val = tcg_const_i64(0xffULL);
2214 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2215 r_size = tcg_const_i32(1);
2216 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
2217 tcg_temp_free_i32(r_size);
2218 tcg_temp_free_i32(r_asi);
2219 tcg_temp_free_i64(r_val);
2220 }
2221 #endif
2222
2223 static TCGv get_src1(DisasContext *dc, unsigned int insn)
2224 {
2225 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2226 return gen_load_gpr(dc, rs1);
2227 }
2228
2229 static TCGv get_src2(DisasContext *dc, unsigned int insn)
2230 {
2231 if (IS_IMM) { /* immediate */
2232 target_long simm = GET_FIELDs(insn, 19, 31);
2233 TCGv t = get_temp_tl(dc);
2234 tcg_gen_movi_tl(t, simm);
2235 return t;
2236 } else { /* register */
2237 unsigned int rs2 = GET_FIELD(insn, 27, 31);
2238 return gen_load_gpr(dc, rs2);
2239 }
2240 }
2241
2242 #ifdef TARGET_SPARC64
2243 static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2244 {
2245 TCGv_i32 c32, zero, dst, s1, s2;
2246
2247 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2248 or fold the comparison down to 32 bits and use movcond_i32. Choose
2249 the later. */
2250 c32 = tcg_temp_new_i32();
2251 if (cmp->is_bool) {
2252 tcg_gen_extrl_i64_i32(c32, cmp->c1);
2253 } else {
2254 TCGv_i64 c64 = tcg_temp_new_i64();
2255 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
2256 tcg_gen_extrl_i64_i32(c32, c64);
2257 tcg_temp_free_i64(c64);
2258 }
2259
2260 s1 = gen_load_fpr_F(dc, rs);
2261 s2 = gen_load_fpr_F(dc, rd);
2262 dst = gen_dest_fpr_F(dc);
2263 zero = tcg_const_i32(0);
2264
2265 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2266
2267 tcg_temp_free_i32(c32);
2268 tcg_temp_free_i32(zero);
2269 gen_store_fpr_F(dc, rd, dst);
2270 }
2271
2272 static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2273 {
2274 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
2275 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2276 gen_load_fpr_D(dc, rs),
2277 gen_load_fpr_D(dc, rd));
2278 gen_store_fpr_D(dc, rd, dst);
2279 }
2280
2281 static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2282 {
2283 int qd = QFPREG(rd);
2284 int qs = QFPREG(rs);
2285
2286 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2287 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2288 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2289 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2290
2291 gen_update_fprs_dirty(qd);
2292 }
2293
2294 #ifndef CONFIG_USER_ONLY
2295 static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
2296 {
2297 TCGv_i32 r_tl = tcg_temp_new_i32();
2298
2299 /* load env->tl into r_tl */
2300 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
2301
2302 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
2303 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
2304
2305 /* calculate offset to current trap state from env->ts, reuse r_tl */
2306 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
2307 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
2308
2309 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
2310 {
2311 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2312 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2313 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
2314 tcg_temp_free_ptr(r_tl_tmp);
2315 }
2316
2317 tcg_temp_free_i32(r_tl);
2318 }
2319 #endif
2320
2321 static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2322 int width, bool cc, bool left)
2323 {
2324 TCGv lo1, lo2, t1, t2;
2325 uint64_t amask, tabl, tabr;
2326 int shift, imask, omask;
2327
2328 if (cc) {
2329 tcg_gen_mov_tl(cpu_cc_src, s1);
2330 tcg_gen_mov_tl(cpu_cc_src2, s2);
2331 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2332 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2333 dc->cc_op = CC_OP_SUB;
2334 }
2335
2336 /* Theory of operation: there are two tables, left and right (not to
2337 be confused with the left and right versions of the opcode). These
2338 are indexed by the low 3 bits of the inputs. To make things "easy",
2339 these tables are loaded into two constants, TABL and TABR below.
2340 The operation index = (input & imask) << shift calculates the index
2341 into the constant, while val = (table >> index) & omask calculates
2342 the value we're looking for. */
2343 switch (width) {
2344 case 8:
2345 imask = 0x7;
2346 shift = 3;
2347 omask = 0xff;
2348 if (left) {
2349 tabl = 0x80c0e0f0f8fcfeffULL;
2350 tabr = 0xff7f3f1f0f070301ULL;
2351 } else {
2352 tabl = 0x0103070f1f3f7fffULL;
2353 tabr = 0xfffefcf8f0e0c080ULL;
2354 }
2355 break;
2356 case 16:
2357 imask = 0x6;
2358 shift = 1;
2359 omask = 0xf;
2360 if (left) {
2361 tabl = 0x8cef;
2362 tabr = 0xf731;
2363 } else {
2364 tabl = 0x137f;
2365 tabr = 0xfec8;
2366 }
2367 break;
2368 case 32:
2369 imask = 0x4;
2370 shift = 0;
2371 omask = 0x3;
2372 if (left) {
2373 tabl = (2 << 2) | 3;
2374 tabr = (3 << 2) | 1;
2375 } else {
2376 tabl = (1 << 2) | 3;
2377 tabr = (3 << 2) | 2;
2378 }
2379 break;
2380 default:
2381 abort();
2382 }
2383
2384 lo1 = tcg_temp_new();
2385 lo2 = tcg_temp_new();
2386 tcg_gen_andi_tl(lo1, s1, imask);
2387 tcg_gen_andi_tl(lo2, s2, imask);
2388 tcg_gen_shli_tl(lo1, lo1, shift);
2389 tcg_gen_shli_tl(lo2, lo2, shift);
2390
2391 t1 = tcg_const_tl(tabl);
2392 t2 = tcg_const_tl(tabr);
2393 tcg_gen_shr_tl(lo1, t1, lo1);
2394 tcg_gen_shr_tl(lo2, t2, lo2);
2395 tcg_gen_andi_tl(dst, lo1, omask);
2396 tcg_gen_andi_tl(lo2, lo2, omask);
2397
2398 amask = -8;
2399 if (AM_CHECK(dc)) {
2400 amask &= 0xffffffffULL;
2401 }
2402 tcg_gen_andi_tl(s1, s1, amask);
2403 tcg_gen_andi_tl(s2, s2, amask);
2404
2405 /* We want to compute
2406 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2407 We've already done dst = lo1, so this reduces to
2408 dst &= (s1 == s2 ? -1 : lo2)
2409 Which we perform by
2410 lo2 |= -(s1 == s2)
2411 dst &= lo2
2412 */
2413 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2414 tcg_gen_neg_tl(t1, t1);
2415 tcg_gen_or_tl(lo2, lo2, t1);
2416 tcg_gen_and_tl(dst, dst, lo2);
2417
2418 tcg_temp_free(lo1);
2419 tcg_temp_free(lo2);
2420 tcg_temp_free(t1);
2421 tcg_temp_free(t2);
2422 }
2423
2424 static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2425 {
2426 TCGv tmp = tcg_temp_new();
2427
2428 tcg_gen_add_tl(tmp, s1, s2);
2429 tcg_gen_andi_tl(dst, tmp, -8);
2430 if (left) {
2431 tcg_gen_neg_tl(tmp, tmp);
2432 }
2433 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2434
2435 tcg_temp_free(tmp);
2436 }
2437
2438 static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2439 {
2440 TCGv t1, t2, shift;
2441
2442 t1 = tcg_temp_new();
2443 t2 = tcg_temp_new();
2444 shift = tcg_temp_new();
2445
2446 tcg_gen_andi_tl(shift, gsr, 7);
2447 tcg_gen_shli_tl(shift, shift, 3);
2448 tcg_gen_shl_tl(t1, s1, shift);
2449
2450 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2451 shift of (up to 63) followed by a constant shift of 1. */
2452 tcg_gen_xori_tl(shift, shift, 63);
2453 tcg_gen_shr_tl(t2, s2, shift);
2454 tcg_gen_shri_tl(t2, t2, 1);
2455
2456 tcg_gen_or_tl(dst, t1, t2);
2457
2458 tcg_temp_free(t1);
2459 tcg_temp_free(t2);
2460 tcg_temp_free(shift);
2461 }
2462 #endif
2463
2464 #define CHECK_IU_FEATURE(dc, FEATURE) \
2465 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2466 goto illegal_insn;
2467 #define CHECK_FPU_FEATURE(dc, FEATURE) \
2468 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
2469 goto nfpu_insn;
2470
2471 /* before an instruction, dc->pc must be static */
2472 static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
2473 {
2474 unsigned int opc, rs1, rs2, rd;
2475 TCGv cpu_src1, cpu_src2;
2476 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
2477 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
2478 target_long simm;
2479
2480 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
2481 tcg_gen_debug_insn_start(dc->pc);
2482 }
2483
2484 opc = GET_FIELD(insn, 0, 1);
2485 rd = GET_FIELD(insn, 2, 6);
2486
2487 switch (opc) {
2488 case 0: /* branches/sethi */
2489 {
2490 unsigned int xop = GET_FIELD(insn, 7, 9);
2491 int32_t target;
2492 switch (xop) {
2493 #ifdef TARGET_SPARC64
2494 case 0x1: /* V9 BPcc */
2495 {
2496 int cc;
2497
2498 target = GET_FIELD_SP(insn, 0, 18);
2499 target = sign_extend(target, 19);
2500 target <<= 2;
2501 cc = GET_FIELD_SP(insn, 20, 21);
2502 if (cc == 0)
2503 do_branch(dc, target, insn, 0);
2504 else if (cc == 2)
2505 do_branch(dc, target, insn, 1);
2506 else
2507 goto illegal_insn;
2508 goto jmp_insn;
2509 }
2510 case 0x3: /* V9 BPr */
2511 {
2512 target = GET_FIELD_SP(insn, 0, 13) |
2513 (GET_FIELD_SP(insn, 20, 21) << 14);
2514 target = sign_extend(target, 16);
2515 target <<= 2;
2516 cpu_src1 = get_src1(dc, insn);
2517 do_branch_reg(dc, target, insn, cpu_src1);
2518 goto jmp_insn;
2519 }
2520 case 0x5: /* V9 FBPcc */
2521 {
2522 int cc = GET_FIELD_SP(insn, 20, 21);
2523 if (gen_trap_ifnofpu(dc)) {
2524 goto jmp_insn;
2525 }
2526 target = GET_FIELD_SP(insn, 0, 18);
2527 target = sign_extend(target, 19);
2528 target <<= 2;
2529 do_fbranch(dc, target, insn, cc);
2530 goto jmp_insn;
2531 }
2532 #else
2533 case 0x7: /* CBN+x */
2534 {
2535 goto ncp_insn;
2536 }
2537 #endif
2538 case 0x2: /* BN+x */
2539 {
2540 target = GET_FIELD(insn, 10, 31);
2541 target = sign_extend(target, 22);
2542 target <<= 2;
2543 do_branch(dc, target, insn, 0);
2544 goto jmp_insn;
2545 }
2546 case 0x6: /* FBN+x */
2547 {
2548 if (gen_trap_ifnofpu(dc)) {
2549 goto jmp_insn;
2550 }
2551 target = GET_FIELD(insn, 10, 31);
2552 target = sign_extend(target, 22);
2553 target <<= 2;
2554 do_fbranch(dc, target, insn, 0);
2555 goto jmp_insn;
2556 }
2557 case 0x4: /* SETHI */
2558 /* Special-case %g0 because that's the canonical nop. */
2559 if (rd) {
2560 uint32_t value = GET_FIELD(insn, 10, 31);
2561 TCGv t = gen_dest_gpr(dc, rd);
2562 tcg_gen_movi_tl(t, value << 10);
2563 gen_store_gpr(dc, rd, t);
2564 }
2565 break;
2566 case 0x0: /* UNIMPL */
2567 default:
2568 goto illegal_insn;
2569 }
2570 break;
2571 }
2572 break;
2573 case 1: /*CALL*/
2574 {
2575 target_long target = GET_FIELDs(insn, 2, 31) << 2;
2576 TCGv o7 = gen_dest_gpr(dc, 15);
2577
2578 tcg_gen_movi_tl(o7, dc->pc);
2579 gen_store_gpr(dc, 15, o7);
2580 target += dc->pc;
2581 gen_mov_pc_npc(dc);
2582 #ifdef TARGET_SPARC64
2583 if (unlikely(AM_CHECK(dc))) {
2584 target &= 0xffffffffULL;
2585 }
2586 #endif
2587 dc->npc = target;
2588 }
2589 goto jmp_insn;
2590 case 2: /* FPU & Logical Operations */
2591 {
2592 unsigned int xop = GET_FIELD(insn, 7, 12);
2593 TCGv cpu_dst = get_temp_tl(dc);
2594 TCGv cpu_tmp0;
2595
2596 if (xop == 0x3a) { /* generate trap */
2597 int cond = GET_FIELD(insn, 3, 6);
2598 TCGv_i32 trap;
2599 TCGLabel *l1 = NULL;
2600 int mask;
2601
2602 if (cond == 0) {
2603 /* Trap never. */
2604 break;
2605 }
2606
2607 save_state(dc);
2608
2609 if (cond != 8) {
2610 /* Conditional trap. */
2611 DisasCompare cmp;
2612 #ifdef TARGET_SPARC64
2613 /* V9 icc/xcc */
2614 int cc = GET_FIELD_SP(insn, 11, 12);
2615 if (cc == 0) {
2616 gen_compare(&cmp, 0, cond, dc);
2617 } else if (cc == 2) {
2618 gen_compare(&cmp, 1, cond, dc);
2619 } else {
2620 goto illegal_insn;
2621 }
2622 #else
2623 gen_compare(&cmp, 0, cond, dc);
2624 #endif
2625 l1 = gen_new_label();
2626 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2627 cmp.c1, cmp.c2, l1);
2628 free_compare(&cmp);
2629 }
2630
2631 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2632 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2633
2634 /* Don't use the normal temporaries, as they may well have
2635 gone out of scope with the branch above. While we're
2636 doing that we might as well pre-truncate to 32-bit. */
2637 trap = tcg_temp_new_i32();
2638
2639 rs1 = GET_FIELD_SP(insn, 14, 18);
2640 if (IS_IMM) {
2641 rs2 = GET_FIELD_SP(insn, 0, 6);
2642 if (rs1 == 0) {
2643 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2644 /* Signal that the trap value is fully constant. */
2645 mask = 0;
2646 } else {
2647 TCGv t1 = gen_load_gpr(dc, rs1);
2648 tcg_gen_trunc_tl_i32(trap, t1);
2649 tcg_gen_addi_i32(trap, trap, rs2);
2650 }
2651 } else {
2652 TCGv t1, t2;
2653 rs2 = GET_FIELD_SP(insn, 0, 4);
2654 t1 = gen_load_gpr(dc, rs1);
2655 t2 = gen_load_gpr(dc, rs2);
2656 tcg_gen_add_tl(t1, t1, t2);
2657 tcg_gen_trunc_tl_i32(trap, t1);
2658 }
2659 if (mask != 0) {
2660 tcg_gen_andi_i32(trap, trap, mask);
2661 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2662 }
2663
2664 gen_helper_raise_exception(cpu_env, trap);
2665 tcg_temp_free_i32(trap);
2666
2667 if (cond == 8) {
2668 /* An unconditional trap ends the TB. */
2669 dc->is_br = 1;
2670 goto jmp_insn;
2671 } else {
2672 /* A conditional trap falls through to the next insn. */
2673 gen_set_label(l1);
2674 break;
2675 }
2676 } else if (xop == 0x28) {
2677 rs1 = GET_FIELD(insn, 13, 17);
2678 switch(rs1) {
2679 case 0: /* rdy */
2680 #ifndef TARGET_SPARC64
2681 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2682 manual, rdy on the microSPARC
2683 II */
2684 case 0x0f: /* stbar in the SPARCv8 manual,
2685 rdy on the microSPARC II */
2686 case 0x10 ... 0x1f: /* implementation-dependent in the
2687 SPARCv8 manual, rdy on the
2688 microSPARC II */
2689 /* Read Asr17 */
2690 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
2691 TCGv t = gen_dest_gpr(dc, rd);
2692 /* Read Asr17 for a Leon3 monoprocessor */
2693 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2694 gen_store_gpr(dc, rd, t);
2695 break;
2696 }
2697 #endif
2698 gen_store_gpr(dc, rd, cpu_y);
2699 break;
2700 #ifdef TARGET_SPARC64
2701 case 0x2: /* V9 rdccr */
2702 update_psr(dc);
2703 gen_helper_rdccr(cpu_dst, cpu_env);
2704 gen_store_gpr(dc, rd, cpu_dst);
2705 break;
2706 case 0x3: /* V9 rdasi */
2707 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
2708 gen_store_gpr(dc, rd, cpu_dst);
2709 break;
2710 case 0x4: /* V9 rdtick */
2711 {
2712 TCGv_ptr r_tickptr;
2713
2714 r_tickptr = tcg_temp_new_ptr();
2715 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2716 offsetof(CPUSPARCState, tick));
2717 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2718 tcg_temp_free_ptr(r_tickptr);
2719 gen_store_gpr(dc, rd, cpu_dst);
2720 }
2721 break;
2722 case 0x5: /* V9 rdpc */
2723 {
2724 TCGv t = gen_dest_gpr(dc, rd);
2725 if (unlikely(AM_CHECK(dc))) {
2726 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
2727 } else {
2728 tcg_gen_movi_tl(t, dc->pc);
2729 }
2730 gen_store_gpr(dc, rd, t);
2731 }
2732 break;
2733 case 0x6: /* V9 rdfprs */
2734 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
2735 gen_store_gpr(dc, rd, cpu_dst);
2736 break;
2737 case 0xf: /* V9 membar */
2738 break; /* no effect */
2739 case 0x13: /* Graphics Status */
2740 if (gen_trap_ifnofpu(dc)) {
2741 goto jmp_insn;
2742 }
2743 gen_store_gpr(dc, rd, cpu_gsr);
2744 break;
2745 case 0x16: /* Softint */
2746 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
2747 gen_store_gpr(dc, rd, cpu_dst);
2748 break;
2749 case 0x17: /* Tick compare */
2750 gen_store_gpr(dc, rd, cpu_tick_cmpr);
2751 break;
2752 case 0x18: /* System tick */
2753 {
2754 TCGv_ptr r_tickptr;
2755
2756 r_tickptr = tcg_temp_new_ptr();
2757 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2758 offsetof(CPUSPARCState, stick));
2759 gen_helper_tick_get_count(cpu_dst, r_tickptr);
2760 tcg_temp_free_ptr(r_tickptr);
2761 gen_store_gpr(dc, rd, cpu_dst);
2762 }
2763 break;
2764 case 0x19: /* System tick compare */
2765 gen_store_gpr(dc, rd, cpu_stick_cmpr);
2766 break;
2767 case 0x10: /* Performance Control */
2768 case 0x11: /* Performance Instrumentation Counter */
2769 case 0x12: /* Dispatch Control */
2770 case 0x14: /* Softint set, WO */
2771 case 0x15: /* Softint clear, WO */
2772 #endif
2773 default:
2774 goto illegal_insn;
2775 }
2776 #if !defined(CONFIG_USER_ONLY)
2777 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2778 #ifndef TARGET_SPARC64
2779 if (!supervisor(dc)) {
2780 goto priv_insn;
2781 }
2782 update_psr(dc);
2783 gen_helper_rdpsr(cpu_dst, cpu_env);
2784 #else
2785 CHECK_IU_FEATURE(dc, HYPV);
2786 if (!hypervisor(dc))
2787 goto priv_insn;
2788 rs1 = GET_FIELD(insn, 13, 17);
2789 switch (rs1) {
2790 case 0: // hpstate
2791 // gen_op_rdhpstate();
2792 break;
2793 case 1: // htstate
2794 // gen_op_rdhtstate();
2795 break;
2796 case 3: // hintp
2797 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
2798 break;
2799 case 5: // htba
2800 tcg_gen_mov_tl(cpu_dst, cpu_htba);
2801 break;
2802 case 6: // hver
2803 tcg_gen_mov_tl(cpu_dst, cpu_hver);
2804 break;
2805 case 31: // hstick_cmpr
2806 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
2807 break;
2808 default:
2809 goto illegal_insn;
2810 }
2811 #endif
2812 gen_store_gpr(dc, rd, cpu_dst);
2813 break;
2814 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2815 if (!supervisor(dc)) {
2816 goto priv_insn;
2817 }
2818 cpu_tmp0 = get_temp_tl(dc);
2819 #ifdef TARGET_SPARC64
2820 rs1 = GET_FIELD(insn, 13, 17);
2821 switch (rs1) {
2822 case 0: // tpc
2823 {
2824 TCGv_ptr r_tsptr;
2825
2826 r_tsptr = tcg_temp_new_ptr();
2827 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2828 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2829 offsetof(trap_state, tpc));
2830 tcg_temp_free_ptr(r_tsptr);
2831 }
2832 break;
2833 case 1: // tnpc
2834 {
2835 TCGv_ptr r_tsptr;
2836
2837 r_tsptr = tcg_temp_new_ptr();
2838 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2839 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2840 offsetof(trap_state, tnpc));
2841 tcg_temp_free_ptr(r_tsptr);
2842 }
2843 break;
2844 case 2: // tstate
2845 {
2846 TCGv_ptr r_tsptr;
2847
2848 r_tsptr = tcg_temp_new_ptr();
2849 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2850 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2851 offsetof(trap_state, tstate));
2852 tcg_temp_free_ptr(r_tsptr);
2853 }
2854 break;
2855 case 3: // tt
2856 {
2857 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
2858
2859 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2860 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2861 offsetof(trap_state, tt));
2862 tcg_temp_free_ptr(r_tsptr);
2863 }
2864 break;
2865 case 4: // tick
2866 {
2867 TCGv_ptr r_tickptr;
2868
2869 r_tickptr = tcg_temp_new_ptr();
2870 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2871 offsetof(CPUSPARCState, tick));
2872 gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
2873 tcg_temp_free_ptr(r_tickptr);
2874 }
2875 break;
2876 case 5: // tba
2877 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
2878 break;
2879 case 6: // pstate
2880 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2881 offsetof(CPUSPARCState, pstate));
2882 break;
2883 case 7: // tl
2884 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2885 offsetof(CPUSPARCState, tl));
2886 break;
2887 case 8: // pil
2888 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2889 offsetof(CPUSPARCState, psrpil));
2890 break;
2891 case 9: // cwp
2892 gen_helper_rdcwp(cpu_tmp0, cpu_env);
2893 break;
2894 case 10: // cansave
2895 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2896 offsetof(CPUSPARCState, cansave));
2897 break;
2898 case 11: // canrestore
2899 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2900 offsetof(CPUSPARCState, canrestore));
2901 break;
2902 case 12: // cleanwin
2903 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2904 offsetof(CPUSPARCState, cleanwin));
2905 break;
2906 case 13: // otherwin
2907 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2908 offsetof(CPUSPARCState, otherwin));
2909 break;
2910 case 14: // wstate
2911 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2912 offsetof(CPUSPARCState, wstate));
2913 break;
2914 case 16: // UA2005 gl
2915 CHECK_IU_FEATURE(dc, GL);
2916 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2917 offsetof(CPUSPARCState, gl));
2918 break;
2919 case 26: // UA2005 strand status
2920 CHECK_IU_FEATURE(dc, HYPV);
2921 if (!hypervisor(dc))
2922 goto priv_insn;
2923 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
2924 break;
2925 case 31: // ver
2926 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
2927 break;
2928 case 15: // fq
2929 default:
2930 goto illegal_insn;
2931 }
2932 #else
2933 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
2934 #endif
2935 gen_store_gpr(dc, rd, cpu_tmp0);
2936 break;
2937 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2938 #ifdef TARGET_SPARC64
2939 save_state(dc);
2940 gen_helper_flushw(cpu_env);
2941 #else
2942 if (!supervisor(dc))
2943 goto priv_insn;
2944 gen_store_gpr(dc, rd, cpu_tbr);
2945 #endif
2946 break;
2947 #endif
2948 } else if (xop == 0x34) { /* FPU Operations */
2949 if (gen_trap_ifnofpu(dc)) {
2950 goto jmp_insn;
2951 }
2952 gen_op_clear_ieee_excp_and_FTT();
2953 rs1 = GET_FIELD(insn, 13, 17);
2954 rs2 = GET_FIELD(insn, 27, 31);
2955 xop = GET_FIELD(insn, 18, 26);
2956 save_state(dc);
2957 switch (xop) {
2958 case 0x1: /* fmovs */
2959 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2960 gen_store_fpr_F(dc, rd, cpu_src1_32);
2961 break;
2962 case 0x5: /* fnegs */
2963 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
2964 break;
2965 case 0x9: /* fabss */
2966 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
2967 break;
2968 case 0x29: /* fsqrts */
2969 CHECK_FPU_FEATURE(dc, FSQRT);
2970 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
2971 break;
2972 case 0x2a: /* fsqrtd */
2973 CHECK_FPU_FEATURE(dc, FSQRT);
2974 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
2975 break;
2976 case 0x2b: /* fsqrtq */
2977 CHECK_FPU_FEATURE(dc, FLOAT128);
2978 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
2979 break;
2980 case 0x41: /* fadds */
2981 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
2982 break;
2983 case 0x42: /* faddd */
2984 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
2985 break;
2986 case 0x43: /* faddq */
2987 CHECK_FPU_FEATURE(dc, FLOAT128);
2988 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
2989 break;
2990 case 0x45: /* fsubs */
2991 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
2992 break;
2993 case 0x46: /* fsubd */
2994 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
2995 break;
2996 case 0x47: /* fsubq */
2997 CHECK_FPU_FEATURE(dc, FLOAT128);
2998 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
2999 break;
3000 case 0x49: /* fmuls */
3001 CHECK_FPU_FEATURE(dc, FMUL);
3002 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
3003 break;
3004 case 0x4a: /* fmuld */
3005 CHECK_FPU_FEATURE(dc, FMUL);
3006 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
3007 break;
3008 case 0x4b: /* fmulq */
3009 CHECK_FPU_FEATURE(dc, FLOAT128);
3010 CHECK_FPU_FEATURE(dc, FMUL);
3011 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
3012 break;
3013 case 0x4d: /* fdivs */
3014 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
3015 break;
3016 case 0x4e: /* fdivd */
3017 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
3018 break;
3019 case 0x4f: /* fdivq */
3020 CHECK_FPU_FEATURE(dc, FLOAT128);
3021 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
3022 break;
3023 case 0x69: /* fsmuld */
3024 CHECK_FPU_FEATURE(dc, FSMULD);
3025 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
3026 break;
3027 case 0x6e: /* fdmulq */
3028 CHECK_FPU_FEATURE(dc, FLOAT128);
3029 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
3030 break;
3031 case 0xc4: /* fitos */
3032 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
3033 break;
3034 case 0xc6: /* fdtos */
3035 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
3036 break;
3037 case 0xc7: /* fqtos */
3038 CHECK_FPU_FEATURE(dc, FLOAT128);
3039 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
3040 break;
3041 case 0xc8: /* fitod */
3042 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
3043 break;
3044 case 0xc9: /* fstod */
3045 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
3046 break;
3047 case 0xcb: /* fqtod */
3048 CHECK_FPU_FEATURE(dc, FLOAT128);
3049 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
3050 break;
3051 case 0xcc: /* fitoq */
3052 CHECK_FPU_FEATURE(dc, FLOAT128);
3053 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
3054 break;
3055 case 0xcd: /* fstoq */
3056 CHECK_FPU_FEATURE(dc, FLOAT128);
3057 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
3058 break;
3059 case 0xce: /* fdtoq */
3060 CHECK_FPU_FEATURE(dc, FLOAT128);
3061 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
3062 break;
3063 case 0xd1: /* fstoi */
3064 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
3065 break;
3066 case 0xd2: /* fdtoi */
3067 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
3068 break;
3069 case 0xd3: /* fqtoi */
3070 CHECK_FPU_FEATURE(dc, FLOAT128);
3071 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
3072 break;
3073 #ifdef TARGET_SPARC64
3074 case 0x2: /* V9 fmovd */
3075 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3076 gen_store_fpr_D(dc, rd, cpu_src1_64);
3077 break;
3078 case 0x3: /* V9 fmovq */
3079 CHECK_FPU_FEATURE(dc, FLOAT128);
3080 gen_move_Q(rd, rs2);
3081 break;
3082 case 0x6: /* V9 fnegd */
3083 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
3084 break;
3085 case 0x7: /* V9 fnegq */
3086 CHECK_FPU_FEATURE(dc, FLOAT128);
3087 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
3088 break;
3089 case 0xa: /* V9 fabsd */
3090 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
3091 break;
3092 case 0xb: /* V9 fabsq */
3093 CHECK_FPU_FEATURE(dc, FLOAT128);
3094 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
3095 break;
3096 case 0x81: /* V9 fstox */
3097 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
3098 break;
3099 case 0x82: /* V9 fdtox */
3100 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
3101 break;
3102 case 0x83: /* V9 fqtox */
3103 CHECK_FPU_FEATURE(dc, FLOAT128);
3104 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
3105 break;
3106 case 0x84: /* V9 fxtos */
3107 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
3108 break;
3109 case 0x88: /* V9 fxtod */
3110 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
3111 break;
3112 case 0x8c: /* V9 fxtoq */
3113 CHECK_FPU_FEATURE(dc, FLOAT128);
3114 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
3115 break;
3116 #endif
3117 default:
3118 goto illegal_insn;
3119 }
3120 } else if (xop == 0x35) { /* FPU Operations */
3121 #ifdef TARGET_SPARC64
3122 int cond;
3123 #endif
3124 if (gen_trap_ifnofpu(dc)) {
3125 goto jmp_insn;
3126 }
3127 gen_op_clear_ieee_excp_and_FTT();
3128 rs1 = GET_FIELD(insn, 13, 17);
3129 rs2 = GET_FIELD(insn, 27, 31);
3130 xop = GET_FIELD(insn, 18, 26);
3131 save_state(dc);
3132
3133 #ifdef TARGET_SPARC64
3134 #define FMOVR(sz) \
3135 do { \
3136 DisasCompare cmp; \
3137 cond = GET_FIELD_SP(insn, 10, 12); \
3138 cpu_src1 = get_src1(dc, insn); \
3139 gen_compare_reg(&cmp, cond, cpu_src1); \
3140 gen_fmov##sz(dc, &cmp, rd, rs2); \
3141 free_compare(&cmp); \
3142 } while (0)
3143
3144 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3145 FMOVR(s);
3146 break;
3147 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
3148 FMOVR(d);
3149 break;
3150 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
3151 CHECK_FPU_FEATURE(dc, FLOAT128);
3152 FMOVR(q);
3153 break;
3154 }
3155 #undef FMOVR
3156 #endif
3157 switch (xop) {
3158 #ifdef TARGET_SPARC64
3159 #define FMOVCC(fcc, sz) \
3160 do { \
3161 DisasCompare cmp; \
3162 cond = GET_FIELD_SP(insn, 14, 17); \
3163 gen_fcompare(&cmp, fcc, cond); \
3164 gen_fmov##sz(dc, &cmp, rd, rs2); \
3165 free_compare(&cmp); \
3166 } while (0)
3167
3168 case 0x001: /* V9 fmovscc %fcc0 */
3169 FMOVCC(0, s);
3170 break;
3171 case 0x002: /* V9 fmovdcc %fcc0 */
3172 FMOVCC(0, d);
3173 break;
3174 case 0x003: /* V9 fmovqcc %fcc0 */
3175 CHECK_FPU_FEATURE(dc, FLOAT128);
3176 FMOVCC(0, q);
3177 break;
3178 case 0x041: /* V9 fmovscc %fcc1 */
3179 FMOVCC(1, s);
3180 break;
3181 case 0x042: /* V9 fmovdcc %fcc1 */
3182 FMOVCC(1, d);
3183 break;
3184 case 0x043: /* V9 fmovqcc %fcc1 */
3185 CHECK_FPU_FEATURE(dc, FLOAT128);
3186 FMOVCC(1, q);
3187 break;
3188 case 0x081: /* V9 fmovscc %fcc2 */
3189 FMOVCC(2, s);
3190 break;
3191 case 0x082: /* V9 fmovdcc %fcc2 */
3192 FMOVCC(2, d);
3193 break;
3194 case 0x083: /* V9 fmovqcc %fcc2 */
3195 CHECK_FPU_FEATURE(dc, FLOAT128);
3196 FMOVCC(2, q);
3197 break;
3198 case 0x0c1: /* V9 fmovscc %fcc3 */
3199 FMOVCC(3, s);
3200 break;
3201 case 0x0c2: /* V9 fmovdcc %fcc3 */
3202 FMOVCC(3, d);
3203 break;
3204 case 0x0c3: /* V9 fmovqcc %fcc3 */
3205 CHECK_FPU_FEATURE(dc, FLOAT128);
3206 FMOVCC(3, q);
3207 break;
3208 #undef FMOVCC
3209 #define FMOVCC(xcc, sz) \
3210 do { \
3211 DisasCompare cmp; \
3212 cond = GET_FIELD_SP(insn, 14, 17); \
3213 gen_compare(&cmp, xcc, cond, dc); \
3214 gen_fmov##sz(dc, &cmp, rd, rs2); \
3215 free_compare(&cmp); \
3216 } while (0)
3217
3218 case 0x101: /* V9 fmovscc %icc */
3219 FMOVCC(0, s);
3220 break;
3221 case 0x102: /* V9 fmovdcc %icc */
3222 FMOVCC(0, d);
3223 break;
3224 case 0x103: /* V9 fmovqcc %icc */
3225 CHECK_FPU_FEATURE(dc, FLOAT128);
3226 FMOVCC(0, q);
3227 break;
3228 case 0x181: /* V9 fmovscc %xcc */
3229 FMOVCC(1, s);
3230 break;
3231 case 0x182: /* V9 fmovdcc %xcc */
3232 FMOVCC(1, d);
3233 break;
3234 case 0x183: /* V9 fmovqcc %xcc */
3235 CHECK_FPU_FEATURE(dc, FLOAT128);
3236 FMOVCC(1, q);
3237 break;
3238 #undef FMOVCC
3239 #endif
3240 case 0x51: /* fcmps, V9 %fcc */
3241 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3242 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3243 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
3244 break;
3245 case 0x52: /* fcmpd, V9 %fcc */
3246 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3247 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3248 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
3249 break;
3250 case 0x53: /* fcmpq, V9 %fcc */
3251 CHECK_FPU_FEATURE(dc, FLOAT128);
3252 gen_op_load_fpr_QT0(QFPREG(rs1));
3253 gen_op_load_fpr_QT1(QFPREG(rs2));
3254 gen_op_fcmpq(rd & 3);
3255 break;
3256 case 0x55: /* fcmpes, V9 %fcc */
3257 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3258 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3259 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
3260 break;
3261 case 0x56: /* fcmped, V9 %fcc */
3262 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3263 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3264 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
3265 break;
3266 case 0x57: /* fcmpeq, V9 %fcc */
3267 CHECK_FPU_FEATURE(dc, FLOAT128);
3268 gen_op_load_fpr_QT0(QFPREG(rs1));
3269 gen_op_load_fpr_QT1(QFPREG(rs2));
3270 gen_op_fcmpeq(rd & 3);
3271 break;
3272 default:
3273 goto illegal_insn;
3274 }
3275 } else if (xop == 0x2) {
3276 TCGv dst = gen_dest_gpr(dc, rd);
3277 rs1 = GET_FIELD(insn, 13, 17);
3278 if (rs1 == 0) {
3279 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
3280 if (IS_IMM) { /* immediate */
3281 simm = GET_FIELDs(insn, 19, 31);
3282 tcg_gen_movi_tl(dst, simm);
3283 gen_store_gpr(dc, rd, dst);
3284 } else { /* register */
3285 rs2 = GET_FIELD(insn, 27, 31);
3286 if (rs2 == 0) {
3287 tcg_gen_movi_tl(dst, 0);
3288 gen_store_gpr(dc, rd, dst);
3289 } else {
3290 cpu_src2 = gen_load_gpr(dc, rs2);
3291 gen_store_gpr(dc, rd, cpu_src2);
3292 }
3293 }
3294 } else {
3295 cpu_src1 = get_src1(dc, insn);
3296 if (IS_IMM) { /* immediate */
3297 simm = GET_FIELDs(insn, 19, 31);
3298 tcg_gen_ori_tl(dst, cpu_src1, simm);
3299 gen_store_gpr(dc, rd, dst);
3300 } else { /* register */
3301 rs2 = GET_FIELD(insn, 27, 31);
3302 if (rs2 == 0) {
3303 /* mov shortcut: or x, %g0, y -> mov x, y */
3304 gen_store_gpr(dc, rd, cpu_src1);
3305 } else {
3306 cpu_src2 = gen_load_gpr(dc, rs2);
3307 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3308 gen_store_gpr(dc, rd, dst);
3309 }
3310 }
3311 }
3312 #ifdef TARGET_SPARC64
3313 } else if (xop == 0x25) { /* sll, V9 sllx */
3314 cpu_src1 = get_src1(dc, insn);
3315 if (IS_IMM) { /* immediate */
3316 simm = GET_FIELDs(insn, 20, 31);
3317 if (insn & (1 << 12)) {
3318 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
3319 } else {
3320 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
3321 }
3322 } else { /* register */
3323 rs2 = GET_FIELD(insn, 27, 31);
3324 cpu_src2 = gen_load_gpr(dc, rs2);
3325 cpu_tmp0 = get_temp_tl(dc);
3326 if (insn & (1 << 12)) {
3327 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3328 } else {
3329 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3330 }
3331 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
3332 }
3333 gen_store_gpr(dc, rd, cpu_dst);
3334 } else if (xop == 0x26) { /* srl, V9 srlx */
3335 cpu_src1 = get_src1(dc, insn);
3336 if (IS_IMM) { /* immediate */
3337 simm = GET_FIELDs(insn, 20, 31);
3338 if (insn & (1 << 12)) {
3339 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
3340 } else {
3341 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3342 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
3343 }
3344 } else { /* register */
3345 rs2 = GET_FIELD(insn, 27, 31);
3346 cpu_src2 = gen_load_gpr(dc, rs2);
3347 cpu_tmp0 = get_temp_tl(dc);
3348 if (insn & (1 << 12)) {
3349 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3350 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
3351 } else {
3352 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3353 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3354 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
3355 }
3356 }
3357 gen_store_gpr(dc, rd, cpu_dst);
3358 } else if (xop == 0x27) { /* sra, V9 srax */
3359 cpu_src1 = get_src1(dc, insn);
3360 if (IS_IMM) { /* immediate */
3361 simm = GET_FIELDs(insn, 20, 31);
3362 if (insn & (1 << 12)) {
3363 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
3364 } else {
3365 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
3366 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
3367 }
3368 } else { /* register */
3369 rs2 = GET_FIELD(insn, 27, 31);
3370 cpu_src2 = gen_load_gpr(dc, rs2);
3371 cpu_tmp0 = get_temp_tl(dc);
3372 if (insn & (1 << 12)) {
3373 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3374 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
3375 } else {
3376 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3377 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
3378 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
3379 }
3380 }
3381 gen_store_gpr(dc, rd, cpu_dst);
3382 #endif
3383 } else if (xop < 0x36) {
3384 if (xop < 0x20) {
3385 cpu_src1 = get_src1(dc, insn);
3386 cpu_src2 = get_src2(dc, insn);
3387 switch (xop & ~0x10) {
3388 case 0x0: /* add */
3389 if (xop & 0x10) {
3390 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3391 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3392 dc->cc_op = CC_OP_ADD;
3393 } else {
3394 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3395 }
3396 break;
3397 case 0x1: /* and */
3398 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3399 if (xop & 0x10) {
3400 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3401 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3402 dc->cc_op = CC_OP_LOGIC;
3403 }
3404 break;
3405 case 0x2: /* or */
3406 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3407 if (xop & 0x10) {
3408 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3409 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3410 dc->cc_op = CC_OP_LOGIC;
3411 }
3412 break;
3413 case 0x3: /* xor */
3414 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3415 if (xop & 0x10) {
3416 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3417 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3418 dc->cc_op = CC_OP_LOGIC;
3419 }
3420 break;
3421 case 0x4: /* sub */
3422 if (xop & 0x10) {
3423 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3424 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3425 dc->cc_op = CC_OP_SUB;
3426 } else {
3427 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3428 }
3429 break;
3430 case 0x5: /* andn */
3431 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
3432 if (xop & 0x10) {
3433 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3434 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3435 dc->cc_op = CC_OP_LOGIC;
3436 }
3437 break;
3438 case 0x6: /* orn */
3439 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
3440 if (xop & 0x10) {
3441 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3442 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3443 dc->cc_op = CC_OP_LOGIC;
3444 }
3445 break;
3446 case 0x7: /* xorn */
3447 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
3448 if (xop & 0x10) {
3449 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3450 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3451 dc->cc_op = CC_OP_LOGIC;
3452 }
3453 break;
3454 case 0x8: /* addx, V9 addc */
3455 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3456 (xop & 0x10));
3457 break;
3458 #ifdef TARGET_SPARC64
3459 case 0x9: /* V9 mulx */
3460 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3461 break;
3462 #endif
3463 case 0xa: /* umul */
3464 CHECK_IU_FEATURE(dc, MUL);
3465 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3466 if (xop & 0x10) {
3467 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3468 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3469 dc->cc_op = CC_OP_LOGIC;
3470 }
3471 break;
3472 case 0xb: /* smul */
3473 CHECK_IU_FEATURE(dc, MUL);
3474 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3475 if (xop & 0x10) {
3476 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3477 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3478 dc->cc_op = CC_OP_LOGIC;
3479 }
3480 break;
3481 case 0xc: /* subx, V9 subc */
3482 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3483 (xop & 0x10));
3484 break;
3485 #ifdef TARGET_SPARC64
3486 case 0xd: /* V9 udivx */
3487 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
3488 break;
3489 #endif
3490 case 0xe: /* udiv */
3491 CHECK_IU_FEATURE(dc, DIV);
3492 if (xop & 0x10) {
3493 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3494 cpu_src2);
3495 dc->cc_op = CC_OP_DIV;
3496 } else {
3497 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3498 cpu_src2);
3499 }
3500 break;
3501 case 0xf: /* sdiv */
3502 CHECK_IU_FEATURE(dc, DIV);
3503 if (xop & 0x10) {
3504 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3505 cpu_src2);
3506 dc->cc_op = CC_OP_DIV;
3507 } else {
3508 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3509 cpu_src2);
3510 }
3511 break;
3512 default:
3513 goto illegal_insn;
3514 }
3515 gen_store_gpr(dc, rd, cpu_dst);
3516 } else {
3517 cpu_src1 = get_src1(dc, insn);
3518 cpu_src2 = get_src2(dc, insn);
3519 switch (xop) {
3520 case 0x20: /* taddcc */
3521 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3522 gen_store_gpr(dc, rd, cpu_dst);
3523 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3524 dc->cc_op = CC_OP_TADD;
3525 break;
3526 case 0x21: /* tsubcc */
3527 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3528 gen_store_gpr(dc, rd, cpu_dst);
3529 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3530 dc->cc_op = CC_OP_TSUB;
3531 break;
3532 case 0x22: /* taddcctv */
3533 gen_helper_taddcctv(cpu_dst, cpu_env,
3534 cpu_src1, cpu_src2);
3535 gen_store_gpr(dc, rd, cpu_dst);
3536 dc->cc_op = CC_OP_TADDTV;
3537 break;
3538 case 0x23: /* tsubcctv */
3539 gen_helper_tsubcctv(cpu_dst, cpu_env,
3540 cpu_src1, cpu_src2);
3541 gen_store_gpr(dc, rd, cpu_dst);
3542 dc->cc_op = CC_OP_TSUBTV;
3543 break;
3544 case 0x24: /* mulscc */
3545 update_psr(dc);
3546 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3547 gen_store_gpr(dc, rd, cpu_dst);
3548 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3549 dc->cc_op = CC_OP_ADD;
3550 break;
3551 #ifndef TARGET_SPARC64
3552 case 0x25: /* sll */
3553 if (IS_IMM) { /* immediate */
3554 simm = GET_FIELDs(insn, 20, 31);
3555 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
3556 } else { /* register */
3557 cpu_tmp0 = get_temp_tl(dc);
3558 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3559 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3560 }
3561 gen_store_gpr(dc, rd, cpu_dst);
3562 break;
3563 case 0x26: /* srl */
3564 if (IS_IMM) { /* immediate */
3565 simm = GET_FIELDs(insn, 20, 31);
3566 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
3567 } else { /* register */
3568 cpu_tmp0 = get_temp_tl(dc);
3569 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3570 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3571 }
3572 gen_store_gpr(dc, rd, cpu_dst);
3573 break;
3574 case 0x27: /* sra */
3575 if (IS_IMM) { /* immediate */
3576 simm = GET_FIELDs(insn, 20, 31);
3577 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
3578 } else { /* register */
3579 cpu_tmp0 = get_temp_tl(dc);
3580 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3581 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3582 }
3583 gen_store_gpr(dc, rd, cpu_dst);
3584 break;
3585 #endif
3586 case 0x30:
3587 {
3588 cpu_tmp0 = get_temp_tl(dc);
3589 switch(rd) {
3590 case 0: /* wry */
3591 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3592 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
3593 break;
3594 #ifndef TARGET_SPARC64
3595 case 0x01 ... 0x0f: /* undefined in the
3596 SPARCv8 manual, nop
3597 on the microSPARC
3598 II */
3599 case 0x10 ... 0x1f: /* implementation-dependent
3600 in the SPARCv8
3601 manual, nop on the
3602 microSPARC II */
3603 if ((rd == 0x13) && (dc->def->features &
3604 CPU_FEATURE_POWERDOWN)) {
3605 /* LEON3 power-down */
3606 save_state(dc);
3607 gen_helper_power_down(cpu_env);
3608 }
3609 break;
3610 #else
3611 case 0x2: /* V9 wrccr */
3612 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3613 gen_helper_wrccr(cpu_env, cpu_tmp0);
3614 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3615 dc->cc_op = CC_OP_FLAGS;
3616 break;
3617 case 0x3: /* V9 wrasi */
3618 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3619 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
3620 tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
3621 break;
3622 case 0x6: /* V9 wrfprs */
3623 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3624 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
3625 save_state(dc);
3626 gen_op_next_insn();
3627 tcg_gen_exit_tb(0);
3628 dc->is_br = 1;
3629 break;
3630 case 0xf: /* V9 sir, nop if user */
3631 #if !defined(CONFIG_USER_ONLY)
3632 if (supervisor(dc)) {
3633 ; // XXX
3634 }
3635 #endif
3636 break;
3637 case 0x13: /* Graphics Status */
3638 if (gen_trap_ifnofpu(dc)) {
3639 goto jmp_insn;
3640 }
3641 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
3642 break;
3643 case 0x14: /* Softint set */
3644 if (!supervisor(dc))
3645 goto illegal_insn;
3646 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3647 gen_helper_set_softint(cpu_env, cpu_tmp0);
3648 break;
3649 case 0x15: /* Softint clear */
3650 if (!supervisor(dc))
3651 goto illegal_insn;
3652 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3653 gen_helper_clear_softint(cpu_env, cpu_tmp0);
3654 break;
3655 case 0x16: /* Softint write */
3656 if (!supervisor(dc))
3657 goto illegal_insn;
3658 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3659 gen_helper_write_softint(cpu_env, cpu_tmp0);
3660 break;
3661 case 0x17: /* Tick compare */
3662 #if !defined(CONFIG_USER_ONLY)
3663 if (!supervisor(dc))
3664 goto illegal_insn;
3665 #endif
3666 {
3667 TCGv_ptr r_tickptr;
3668
3669 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
3670 cpu_src2);
3671 r_tickptr = tcg_temp_new_ptr();
3672 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3673 offsetof(CPUSPARCState, tick));
3674 gen_helper_tick_set_limit(r_tickptr,
3675 cpu_tick_cmpr);
3676 tcg_temp_free_ptr(r_tickptr);
3677 }
3678 break;
3679 case 0x18: /* System tick */
3680 #if !defined(CONFIG_USER_ONLY)
3681 if (!supervisor(dc))
3682 goto illegal_insn;
3683 #endif
3684 {
3685 TCGv_ptr r_tickptr;
3686
3687 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3688 cpu_src2);
3689 r_tickptr = tcg_temp_new_ptr();
3690 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3691 offsetof(CPUSPARCState, stick));
3692 gen_helper_tick_set_count(r_tickptr,
3693 cpu_tmp0);
3694 tcg_temp_free_ptr(r_tickptr);
3695 }
3696 break;
3697 case 0x19: /* System tick compare */
3698 #if !defined(CONFIG_USER_ONLY)
3699 if (!supervisor(dc))
3700 goto illegal_insn;
3701 #endif
3702 {
3703 TCGv_ptr r_tickptr;
3704
3705 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
3706 cpu_src2);
3707 r_tickptr = tcg_temp_new_ptr();
3708 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3709 offsetof(CPUSPARCState, stick));
3710 gen_helper_tick_set_limit(r_tickptr,
3711 cpu_stick_cmpr);
3712 tcg_temp_free_ptr(r_tickptr);
3713 }
3714 break;
3715
3716 case 0x10: /* Performance Control */
3717 case 0x11: /* Performance Instrumentation
3718 Counter */
3719 case 0x12: /* Dispatch Control */
3720 #endif
3721 default:
3722 goto illegal_insn;
3723 }
3724 }
3725 break;
3726 #if !defined(CONFIG_USER_ONLY)
3727 case 0x31: /* wrpsr, V9 saved, restored */
3728 {
3729 if (!supervisor(dc))
3730 goto priv_insn;
3731 #ifdef TARGET_SPARC64
3732 switch (rd) {
3733 case 0:
3734 gen_helper_saved(cpu_env);
3735 break;
3736 case 1:
3737 gen_helper_restored(cpu_env);
3738 break;
3739 case 2: /* UA2005 allclean */
3740 case 3: /* UA2005 otherw */
3741 case 4: /* UA2005 normalw */
3742 case 5: /* UA2005 invalw */
3743 // XXX
3744 default:
3745 goto illegal_insn;
3746 }
3747 #else
3748 cpu_tmp0 = get_temp_tl(dc);
3749 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3750 gen_helper_wrpsr(cpu_env, cpu_tmp0);
3751 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3752 dc->cc_op = CC_OP_FLAGS;
3753 save_state(dc);
3754 gen_op_next_insn();
3755 tcg_gen_exit_tb(0);
3756 dc->is_br = 1;
3757 #endif
3758 }
3759 break;
3760 case 0x32: /* wrwim, V9 wrpr */
3761 {
3762 if (!supervisor(dc))
3763 goto priv_insn;
3764 cpu_tmp0 = get_temp_tl(dc);
3765 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3766 #ifdef TARGET_SPARC64
3767 switch (rd) {
3768 case 0: // tpc
3769 {
3770 TCGv_ptr r_tsptr;
3771
3772 r_tsptr = tcg_temp_new_ptr();
3773 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3774 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3775 offsetof(trap_state, tpc));
3776 tcg_temp_free_ptr(r_tsptr);
3777 }
3778 break;
3779 case 1: // tnpc
3780 {
3781 TCGv_ptr r_tsptr;
3782
3783 r_tsptr = tcg_temp_new_ptr();
3784 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3785 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3786 offsetof(trap_state, tnpc));
3787 tcg_temp_free_ptr(r_tsptr);
3788 }
3789 break;
3790 case 2: // tstate
3791 {
3792 TCGv_ptr r_tsptr;
3793
3794 r_tsptr = tcg_temp_new_ptr();
3795 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3796 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3797 offsetof(trap_state,
3798 tstate));
3799 tcg_temp_free_ptr(r_tsptr);
3800 }
3801 break;
3802 case 3: // tt
3803 {
3804 TCGv_ptr r_tsptr;
3805
3806 r_tsptr = tcg_temp_new_ptr();
3807 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3808 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3809 offsetof(trap_state, tt));
3810 tcg_temp_free_ptr(r_tsptr);
3811 }
3812 break;
3813 case 4: // tick
3814 {
3815 TCGv_ptr r_tickptr;
3816
3817 r_tickptr = tcg_temp_new_ptr();
3818 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3819 offsetof(CPUSPARCState, tick));
3820 gen_helper_tick_set_count(r_tickptr,
3821 cpu_tmp0);
3822 tcg_temp_free_ptr(r_tickptr);
3823 }
3824 break;
3825 case 5: // tba
3826 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
3827 break;
3828 case 6: // pstate
3829 save_state(dc);
3830 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3831 dc->npc = DYNAMIC_PC;
3832 break;
3833 case 7: // tl
3834 save_state(dc);
3835 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3836 offsetof(CPUSPARCState, tl));
3837 dc->npc = DYNAMIC_PC;
3838 break;
3839 case 8: // pil
3840 gen_helper_wrpil(cpu_env, cpu_tmp0);
3841 break;
3842 case 9: // cwp
3843 gen_helper_wrcwp(cpu_env, cpu_tmp0);
3844 break;
3845 case 10: // cansave
3846 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3847 offsetof(CPUSPARCState,
3848 cansave));
3849 break;
3850 case 11: // canrestore
3851 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3852 offsetof(CPUSPARCState,
3853 canrestore));
3854 break;
3855 case 12: // cleanwin
3856 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3857 offsetof(CPUSPARCState,
3858 cleanwin));
3859 break;
3860 case 13: // otherwin
3861 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3862 offsetof(CPUSPARCState,
3863 otherwin));
3864 break;
3865 case 14: // wstate
3866 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3867 offsetof(CPUSPARCState,
3868 wstate));
3869 break;
3870 case 16: // UA2005 gl
3871 CHECK_IU_FEATURE(dc, GL);
3872 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3873 offsetof(CPUSPARCState, gl));
3874 break;
3875 case 26: // UA2005 strand status
3876 CHECK_IU_FEATURE(dc, HYPV);
3877 if (!hypervisor(dc))
3878 goto priv_insn;
3879 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
3880 break;
3881 default:
3882 goto illegal_insn;
3883 }
3884 #else
3885 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
3886 if (dc->def->nwindows != 32) {
3887 tcg_gen_andi_tl(cpu_wim, cpu_wim,
3888 (1 << dc->def->nwindows) - 1);
3889 }
3890 #endif
3891 }
3892 break;
3893 case 0x33: /* wrtbr, UA2005 wrhpr */
3894 {
3895 #ifndef TARGET_SPARC64
3896 if (!supervisor(dc))
3897 goto priv_insn;
3898 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
3899 #else
3900 CHECK_IU_FEATURE(dc, HYPV);
3901 if (!hypervisor(dc))
3902 goto priv_insn;
3903 cpu_tmp0 = get_temp_tl(dc);
3904 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3905 switch (rd) {
3906 case 0: // hpstate
3907 // XXX gen_op_wrhpstate();
3908 save_state(dc);
3909 gen_op_next_insn();
3910 tcg_gen_exit_tb(0);
3911 dc->is_br = 1;
3912 break;
3913 case 1: // htstate
3914 // XXX gen_op_wrhtstate();
3915 break;
3916 case 3: // hintp
3917 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
3918 break;
3919 case 5: // htba
3920 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
3921 break;
3922 case 31: // hstick_cmpr
3923 {
3924 TCGv_ptr r_tickptr;
3925
3926 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
3927 r_tickptr = tcg_temp_new_ptr();
3928 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3929 offsetof(CPUSPARCState, hstick));
3930 gen_helper_tick_set_limit(r_tickptr,
3931 cpu_hstick_cmpr);
3932 tcg_temp_free_ptr(r_tickptr);
3933 }
3934 break;
3935 case 6: // hver readonly
3936 default:
3937 goto illegal_insn;
3938 }
3939 #endif
3940 }
3941 break;
3942 #endif
3943 #ifdef TARGET_SPARC64
3944 case 0x2c: /* V9 movcc */
3945 {
3946 int cc = GET_FIELD_SP(insn, 11, 12);
3947 int cond = GET_FIELD_SP(insn, 14, 17);
3948 DisasCompare cmp;
3949 TCGv dst;
3950
3951 if (insn & (1 << 18)) {
3952 if (cc == 0) {
3953 gen_compare(&cmp, 0, cond, dc);
3954 } else if (cc == 2) {
3955 gen_compare(&cmp, 1, cond, dc);
3956 } else {
3957 goto illegal_insn;
3958 }
3959 } else {
3960 gen_fcompare(&cmp, cc, cond);
3961 }
3962
3963 /* The get_src2 above loaded the normal 13-bit
3964 immediate field, not the 11-bit field we have
3965 in movcc. But it did handle the reg case. */
3966 if (IS_IMM) {
3967 simm = GET_FIELD_SPs(insn, 0, 10);
3968 tcg_gen_movi_tl(cpu_src2, simm);
3969 }
3970
3971 dst = gen_load_gpr(dc, rd);
3972 tcg_gen_movcond_tl(cmp.cond, dst,
3973 cmp.c1, cmp.c2,
3974 cpu_src2, dst);
3975 free_compare(&cmp);
3976 gen_store_gpr(dc, rd, dst);
3977 break;
3978 }
3979 case 0x2d: /* V9 sdivx */
3980 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
3981 gen_store_gpr(dc, rd, cpu_dst);
3982 break;
3983 case 0x2e: /* V9 popc */
3984 gen_helper_popc(cpu_dst, cpu_src2);
3985 gen_store_gpr(dc, rd, cpu_dst);
3986 break;
3987 case 0x2f: /* V9 movr */
3988 {
3989 int cond = GET_FIELD_SP(insn, 10, 12);
3990 DisasCompare cmp;
3991 TCGv dst;
3992
3993 gen_compare_reg(&cmp, cond, cpu_src1);
3994
3995 /* The get_src2 above loaded the normal 13-bit
3996 immediate field, not the 10-bit field we have
3997 in movr. But it did handle the reg case. */
3998 if (IS_IMM) {
3999 simm = GET_FIELD_SPs(insn, 0, 9);
4000 tcg_gen_movi_tl(cpu_src2, simm);
4001 }
4002
4003 dst = gen_load_gpr(dc, rd);
4004 tcg_gen_movcond_tl(cmp.cond, dst,
4005 cmp.c1, cmp.c2,
4006 cpu_src2, dst);
4007 free_compare(&cmp);
4008 gen_store_gpr(dc, rd, dst);
4009 break;
4010 }
4011 #endif
4012 default:
4013 goto illegal_insn;
4014 }
4015 }
4016 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4017 #ifdef TARGET_SPARC64
4018 int opf = GET_FIELD_SP(insn, 5, 13);
4019 rs1 = GET_FIELD(insn, 13, 17);
4020 rs2 = GET_FIELD(insn, 27, 31);
4021 if (gen_trap_ifnofpu(dc)) {
4022 goto jmp_insn;
4023 }
4024
4025 switch (opf) {
4026 case 0x000: /* VIS I edge8cc */
4027 CHECK_FPU_FEATURE(dc, VIS1);
4028 cpu_src1 = gen_load_gpr(dc, rs1);
4029 cpu_src2 = gen_load_gpr(dc, rs2);
4030 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
4031 gen_store_gpr(dc, rd, cpu_dst);
4032 break;
4033 case 0x001: /* VIS II edge8n */
4034 CHECK_FPU_FEATURE(dc, VIS2);
4035 cpu_src1 = gen_load_gpr(dc, rs1);
4036 cpu_src2 = gen_load_gpr(dc, rs2);
4037 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
4038 gen_store_gpr(dc, rd, cpu_dst);
4039 break;
4040 case 0x002: /* VIS I edge8lcc */
4041 CHECK_FPU_FEATURE(dc, VIS1);
4042 cpu_src1 = gen_load_gpr(dc, rs1);
4043 cpu_src2 = gen_load_gpr(dc, rs2);
4044 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
4045 gen_store_gpr(dc, rd, cpu_dst);
4046 break;
4047 case 0x003: /* VIS II edge8ln */
4048 CHECK_FPU_FEATURE(dc, VIS2);
4049 cpu_src1 = gen_load_gpr(dc, rs1);
4050 cpu_src2 = gen_load_gpr(dc, rs2);
4051 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
4052 gen_store_gpr(dc, rd, cpu_dst);
4053 break;
4054 case 0x004: /* VIS I edge16cc */
4055 CHECK_FPU_FEATURE(dc, VIS1);
4056 cpu_src1 = gen_load_gpr(dc, rs1);
4057 cpu_src2 = gen_load_gpr(dc, rs2);
4058 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
4059 gen_store_gpr(dc, rd, cpu_dst);
4060 break;
4061 case 0x005: /* VIS II edge16n */
4062 CHECK_FPU_FEATURE(dc, VIS2);
4063 cpu_src1 = gen_load_gpr(dc, rs1);
4064 cpu_src2 = gen_load_gpr(dc, rs2);
4065 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
4066 gen_store_gpr(dc, rd, cpu_dst);
4067 break;
4068 case 0x006: /* VIS I edge16lcc */
4069 CHECK_FPU_FEATURE(dc, VIS1);
4070 cpu_src1 = gen_load_gpr(dc, rs1);
4071 cpu_src2 = gen_load_gpr(dc, rs2);
4072 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
4073 gen_store_gpr(dc, rd, cpu_dst);
4074 break;
4075 case 0x007: /* VIS II edge16ln */
4076 CHECK_FPU_FEATURE(dc, VIS2);
4077 cpu_src1 = gen_load_gpr(dc, rs1);
4078 cpu_src2 = gen_load_gpr(dc, rs2);
4079 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
4080 gen_store_gpr(dc, rd, cpu_dst);
4081 break;
4082 case 0x008: /* VIS I edge32cc */
4083 CHECK_FPU_FEATURE(dc, VIS1);
4084 cpu_src1 = gen_load_gpr(dc, rs1);
4085 cpu_src2 = gen_load_gpr(dc, rs2);
4086 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
4087 gen_store_gpr(dc, rd, cpu_dst);
4088 break;
4089 case 0x009: /* VIS II edge32n */
4090 CHECK_FPU_FEATURE(dc, VIS2);
4091 cpu_src1 = gen_load_gpr(dc, rs1);
4092 cpu_src2 = gen_load_gpr(dc, rs2);
4093 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
4094 gen_store_gpr(dc, rd, cpu_dst);
4095 break;
4096 case 0x00a: /* VIS I edge32lcc */
4097 CHECK_FPU_FEATURE(dc, VIS1);
4098 cpu_src1 = gen_load_gpr(dc, rs1);
4099 cpu_src2 = gen_load_gpr(dc, rs2);
4100 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
4101 gen_store_gpr(dc, rd, cpu_dst);
4102 break;
4103 case 0x00b: /* VIS II edge32ln */
4104 CHECK_FPU_FEATURE(dc, VIS2);
4105 cpu_src1 = gen_load_gpr(dc, rs1);
4106 cpu_src2 = gen_load_gpr(dc, rs2);
4107 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
4108 gen_store_gpr(dc, rd, cpu_dst);
4109 break;
4110 case 0x010: /* VIS I array8 */
4111 CHECK_FPU_FEATURE(dc, VIS1);
4112 cpu_src1 = gen_load_gpr(dc, rs1);
4113 cpu_src2 = gen_load_gpr(dc, rs2);
4114 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
4115 gen_store_gpr(dc, rd, cpu_dst);
4116 break;
4117 case 0x012: /* VIS I array16 */
4118 CHECK_FPU_FEATURE(dc, VIS1);
4119 cpu_src1 = gen_load_gpr(dc, rs1);
4120 cpu_src2 = gen_load_gpr(dc, rs2);
4121 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
4122 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
4123 gen_store_gpr(dc, rd, cpu_dst);
4124 break;
4125 case 0x014: /* VIS I array32 */
4126 CHECK_FPU_FEATURE(dc, VIS1);
4127 cpu_src1 = gen_load_gpr(dc, rs1);
4128 cpu_src2 = gen_load_gpr(dc, rs2);
4129 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
4130 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
4131 gen_store_gpr(dc, rd, cpu_dst);
4132 break;
4133 case 0x018: /* VIS I alignaddr */
4134 CHECK_FPU_FEATURE(dc, VIS1);
4135 cpu_src1 = gen_load_gpr(dc, rs1);
4136 cpu_src2 = gen_load_gpr(dc, rs2);
4137 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
4138 gen_store_gpr(dc, rd, cpu_dst);
4139 break;
4140 case 0x01a: /* VIS I alignaddrl */
4141 CHECK_FPU_FEATURE(dc, VIS1);
4142 cpu_src1 = gen_load_gpr(dc, rs1);
4143 cpu_src2 = gen_load_gpr(dc, rs2);
4144 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
4145 gen_store_gpr(dc, rd, cpu_dst);
4146 break;
4147 case 0x019: /* VIS II bmask */
4148 CHECK_FPU_FEATURE(dc, VIS2);
4149 cpu_src1 = gen_load_gpr(dc, rs1);
4150 cpu_src2 = gen_load_gpr(dc, rs2);
4151 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4152 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
4153 gen_store_gpr(dc, rd, cpu_dst);
4154 break;
4155 case 0x020: /* VIS I fcmple16 */
4156 CHECK_FPU_FEATURE(dc, VIS1);
4157 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4158 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4159 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
4160 gen_store_gpr(dc, rd, cpu_dst);
4161 break;
4162 case 0x022: /* VIS I fcmpne16 */
4163 CHECK_FPU_FEATURE(dc, VIS1);
4164 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4165 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4166 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
4167 gen_store_gpr(dc, rd, cpu_dst);
4168 break;
4169 case 0x024: /* VIS I fcmple32 */
4170 CHECK_FPU_FEATURE(dc, VIS1);
4171 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4172 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4173 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
4174 gen_store_gpr(dc, rd, cpu_dst);
4175 break;
4176 case 0x026: /* VIS I fcmpne32 */
4177 CHECK_FPU_FEATURE(dc, VIS1);
4178 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4179 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4180 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
4181 gen_store_gpr(dc, rd, cpu_dst);
4182 break;
4183 case 0x028: /* VIS I fcmpgt16 */
4184 CHECK_FPU_FEATURE(dc, VIS1);
4185 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4186 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4187 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
4188 gen_store_gpr(dc, rd, cpu_dst);
4189 break;
4190 case 0x02a: /* VIS I fcmpeq16 */
4191 CHECK_FPU_FEATURE(dc, VIS1);
4192 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4193 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4194 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
4195 gen_store_gpr(dc, rd, cpu_dst);
4196 break;
4197 case 0x02c: /* VIS I fcmpgt32 */
4198 CHECK_FPU_FEATURE(dc, VIS1);
4199 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4200 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4201 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
4202 gen_store_gpr(dc, rd, cpu_dst);
4203 break;
4204 case 0x02e: /* VIS I fcmpeq32 */
4205 CHECK_FPU_FEATURE(dc, VIS1);
4206 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4207 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
4208 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
4209 gen_store_gpr(dc, rd, cpu_dst);
4210 break;
4211 case 0x031: /* VIS I fmul8x16 */
4212 CHECK_FPU_FEATURE(dc, VIS1);
4213 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
4214 break;
4215 case 0x033: /* VIS I fmul8x16au */
4216 CHECK_FPU_FEATURE(dc, VIS1);
4217 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
4218 break;
4219 case 0x035: /* VIS I fmul8x16al */
4220 CHECK_FPU_FEATURE(dc, VIS1);
4221 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
4222 break;
4223 case 0x036: /* VIS I fmul8sux16 */
4224 CHECK_FPU_FEATURE(dc, VIS1);
4225 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
4226 break;
4227 case 0x037: /* VIS I fmul8ulx16 */
4228 CHECK_FPU_FEATURE(dc, VIS1);
4229 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
4230 break;
4231 case 0x038: /* VIS I fmuld8sux16 */
4232 CHECK_FPU_FEATURE(dc, VIS1);
4233 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
4234 break;
4235 case 0x039: /* VIS I fmuld8ulx16 */
4236 CHECK_FPU_FEATURE(dc, VIS1);
4237 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
4238 break;
4239 case 0x03a: /* VIS I fpack32 */
4240 CHECK_FPU_FEATURE(dc, VIS1);
4241 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4242 break;
4243 case 0x03b: /* VIS I fpack16 */
4244 CHECK_FPU_FEATURE(dc, VIS1);
4245 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4246 cpu_dst_32 = gen_dest_fpr_F(dc);
4247 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4248 gen_store_fpr_F(dc, rd, cpu_dst_32);
4249 break;
4250 case 0x03d: /* VIS I fpackfix */
4251 CHECK_FPU_FEATURE(dc, VIS1);
4252 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4253 cpu_dst_32 = gen_dest_fpr_F(dc);
4254 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4255 gen_store_fpr_F(dc, rd, cpu_dst_32);
4256 break;
4257 case 0x03e: /* VIS I pdist */
4258 CHECK_FPU_FEATURE(dc, VIS1);
4259 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4260 break;
4261 case 0x048: /* VIS I faligndata */
4262 CHECK_FPU_FEATURE(dc, VIS1);
4263 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
4264 break;
4265 case 0x04b: /* VIS I fpmerge */
4266 CHECK_FPU_FEATURE(dc, VIS1);
4267 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
4268 break;
4269 case 0x04c: /* VIS II bshuffle */
4270 CHECK_FPU_FEATURE(dc, VIS2);
4271 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4272 break;
4273 case 0x04d: /* VIS I fexpand */
4274 CHECK_FPU_FEATURE(dc, VIS1);
4275 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
4276 break;
4277 case 0x050: /* VIS I fpadd16 */
4278 CHECK_FPU_FEATURE(dc, VIS1);
4279 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
4280 break;
4281 case 0x051: /* VIS I fpadd16s */
4282 CHECK_FPU_FEATURE(dc, VIS1);
4283 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
4284 break;
4285 case 0x052: /* VIS I fpadd32 */
4286 CHECK_FPU_FEATURE(dc, VIS1);
4287 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
4288 break;
4289 case 0x053: /* VIS I fpadd32s */
4290 CHECK_FPU_FEATURE(dc, VIS1);
4291 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
4292 break;
4293 case 0x054: /* VIS I fpsub16 */
4294 CHECK_FPU_FEATURE(dc, VIS1);
4295 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
4296 break;
4297 case 0x055: /* VIS I fpsub16s */
4298 CHECK_FPU_FEATURE(dc, VIS1);
4299 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
4300 break;
4301 case 0x056: /* VIS I fpsub32 */
4302 CHECK_FPU_FEATURE(dc, VIS1);
4303 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
4304 break;
4305 case 0x057: /* VIS I fpsub32s */
4306 CHECK_FPU_FEATURE(dc, VIS1);
4307 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
4308 break;
4309 case 0x060: /* VIS I fzero */
4310 CHECK_FPU_FEATURE(dc, VIS1);
4311 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
4312 tcg_gen_movi_i64(cpu_dst_64, 0);
4313 gen_store_fpr_D(dc, rd, cpu_dst_64);
4314 break;
4315 case 0x061: /* VIS I fzeros */
4316 CHECK_FPU_FEATURE(dc, VIS1);
4317 cpu_dst_32 = gen_dest_fpr_F(dc);
4318 tcg_gen_movi_i32(cpu_dst_32, 0);
4319 gen_store_fpr_F(dc, rd, cpu_dst_32);
4320 break;
4321 case 0x062: /* VIS I fnor */
4322 CHECK_FPU_FEATURE(dc, VIS1);
4323 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
4324 break;
4325 case 0x063: /* VIS I fnors */
4326 CHECK_FPU_FEATURE(dc, VIS1);
4327 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
4328 break;
4329 case 0x064: /* VIS I fandnot2 */
4330 CHECK_FPU_FEATURE(dc, VIS1);
4331 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
4332 break;
4333 case 0x065: /* VIS I fandnot2s */
4334 CHECK_FPU_FEATURE(dc, VIS1);
4335 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
4336 break;
4337 case 0x066: /* VIS I fnot2 */
4338 CHECK_FPU_FEATURE(dc, VIS1);
4339 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
4340 break;
4341 case 0x067: /* VIS I fnot2s */
4342 CHECK_FPU_FEATURE(dc, VIS1);
4343 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
4344 break;
4345 case 0x068: /* VIS I fandnot1 */
4346 CHECK_FPU_FEATURE(dc, VIS1);
4347 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
4348 break;
4349 case 0x069: /* VIS I fandnot1s */
4350 CHECK_FPU_FEATURE(dc, VIS1);
4351 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
4352 break;
4353 case 0x06a: /* VIS I fnot1 */
4354 CHECK_FPU_FEATURE(dc, VIS1);
4355 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
4356 break;
4357 case 0x06b: /* VIS I fnot1s */
4358 CHECK_FPU_FEATURE(dc, VIS1);
4359 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
4360 break;
4361 case 0x06c: /* VIS I fxor */
4362 CHECK_FPU_FEATURE(dc, VIS1);
4363 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
4364 break;
4365 case 0x06d: /* VIS I fxors */
4366 CHECK_FPU_FEATURE(dc, VIS1);
4367 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
4368 break;
4369 case 0x06e: /* VIS I fnand */
4370 CHECK_FPU_FEATURE(dc, VIS1);
4371 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
4372 break;
4373 case 0x06f: /* VIS I fnands */
4374 CHECK_FPU_FEATURE(dc, VIS1);
4375 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
4376 break;
4377 case 0x070: /* VIS I fand */
4378 CHECK_FPU_FEATURE(dc, VIS1);
4379 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
4380 break;
4381 case 0x071: /* VIS I fands */
4382 CHECK_FPU_FEATURE(dc, VIS1);
4383 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
4384 break;
4385 case 0x072: /* VIS I fxnor */
4386 CHECK_FPU_FEATURE(dc, VIS1);
4387 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
4388 break;
4389 case 0x073: /* VIS I fxnors */
4390 CHECK_FPU_FEATURE(dc, VIS1);
4391 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
4392 break;
4393 case 0x074: /* VIS I fsrc1 */
4394 CHECK_FPU_FEATURE(dc, VIS1);
4395 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4396 gen_store_fpr_D(dc, rd, cpu_src1_64);
4397 break;
4398 case 0x075: /* VIS I fsrc1s */
4399 CHECK_FPU_FEATURE(dc, VIS1);
4400 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4401 gen_store_fpr_F(dc, rd, cpu_src1_32);
4402 break;
4403 case 0x076: /* VIS I fornot2 */
4404 CHECK_FPU_FEATURE(dc, VIS1);
4405 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
4406 break;
4407 case 0x077: /* VIS I fornot2s */
4408 CHECK_FPU_FEATURE(dc, VIS1);
4409 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
4410 break;
4411 case 0x078: /* VIS I fsrc2 */
4412 CHECK_FPU_FEATURE(dc, VIS1);
4413 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4414 gen_store_fpr_D(dc, rd, cpu_src1_64);
4415 break;
4416 case 0x079: /* VIS I fsrc2s */
4417 CHECK_FPU_FEATURE(dc, VIS1);
4418 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4419 gen_store_fpr_F(dc, rd, cpu_src1_32);
4420 break;
4421 case 0x07a: /* VIS I fornot1 */
4422 CHECK_FPU_FEATURE(dc, VIS1);
4423 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
4424 break;
4425 case 0x07b: /* VIS I fornot1s */
4426 CHECK_FPU_FEATURE(dc, VIS1);
4427 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
4428 break;
4429 case 0x07c: /* VIS I for */
4430 CHECK_FPU_FEATURE(dc, VIS1);
4431 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
4432 break;
4433 case 0x07d: /* VIS I fors */
4434 CHECK_FPU_FEATURE(dc, VIS1);
4435 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
4436 break;
4437 case 0x07e: /* VIS I fone */
4438 CHECK_FPU_FEATURE(dc, VIS1);
4439 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
4440 tcg_gen_movi_i64(cpu_dst_64, -1);
4441 gen_store_fpr_D(dc, rd, cpu_dst_64);
4442 break;
4443 case 0x07f: /* VIS I fones */
4444 CHECK_FPU_FEATURE(dc, VIS1);
4445 cpu_dst_32 = gen_dest_fpr_F(dc);
4446 tcg_gen_movi_i32(cpu_dst_32, -1);
4447 gen_store_fpr_F(dc, rd, cpu_dst_32);
4448 break;
4449 case 0x080: /* VIS I shutdown */
4450 case 0x081: /* VIS II siam */
4451 // XXX
4452 goto illegal_insn;
4453 default:
4454 goto illegal_insn;
4455 }
4456 #else
4457 goto ncp_insn;
4458 #endif
4459 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4460 #ifdef TARGET_SPARC64
4461 goto illegal_insn;
4462 #else
4463 goto ncp_insn;
4464 #endif
4465 #ifdef TARGET_SPARC64
4466 } else if (xop == 0x39) { /* V9 return */
4467 TCGv_i32 r_const;
4468
4469 save_state(dc);
4470 cpu_src1 = get_src1(dc, insn);
4471 cpu_tmp0 = get_temp_tl(dc);
4472 if (IS_IMM) { /* immediate */
4473 simm = GET_FIELDs(insn, 19, 31);
4474 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
4475 } else { /* register */
4476 rs2 = GET_FIELD(insn, 27, 31);
4477 if (rs2) {
4478 cpu_src2 = gen_load_gpr(dc, rs2);
4479 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
4480 } else {
4481 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
4482 }
4483 }
4484 gen_helper_restore(cpu_env);
4485 gen_mov_pc_npc(dc);
4486 r_const = tcg_const_i32(3);
4487 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
4488 tcg_temp_free_i32(r_const);
4489 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
4490 dc->npc = DYNAMIC_PC;
4491 goto jmp_insn;
4492 #endif
4493 } else {
4494 cpu_src1 = get_src1(dc, insn);
4495 cpu_tmp0 = get_temp_tl(dc);
4496 if (IS_IMM) { /* immediate */
4497 simm = GET_FIELDs(insn, 19, 31);
4498 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
4499 } else { /* register */
4500 rs2 = GET_FIELD(insn, 27, 31);
4501 if (rs2) {
4502 cpu_src2 = gen_load_gpr(dc, rs2);
4503 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
4504 } else {
4505 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
4506 }
4507 }
4508 switch (xop) {
4509 case 0x38: /* jmpl */
4510 {
4511 TCGv t;
4512 TCGv_i32 r_const;
4513
4514 t = gen_dest_gpr(dc, rd);
4515 tcg_gen_movi_tl(t, dc->pc);
4516 gen_store_gpr(dc, rd, t);
4517 gen_mov_pc_npc(dc);
4518 r_const = tcg_const_i32(3);
4519 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
4520 tcg_temp_free_i32(r_const);
4521 gen_address_mask(dc, cpu_tmp0);
4522 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
4523 dc->npc = DYNAMIC_PC;
4524 }
4525 goto jmp_insn;
4526 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4527 case 0x39: /* rett, V9 return */
4528 {
4529 TCGv_i32 r_const;
4530
4531 if (!supervisor(dc))
4532 goto priv_insn;
4533 gen_mov_pc_npc(dc);
4534 r_const = tcg_const_i32(3);
4535 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
4536 tcg_temp_free_i32(r_const);
4537 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
4538 dc->npc = DYNAMIC_PC;
4539 gen_helper_rett(cpu_env);
4540 }
4541 goto jmp_insn;
4542 #endif
4543 case 0x3b: /* flush */
4544 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4545 goto unimp_flush;
4546 /* nop */
4547 break;
4548 case 0x3c: /* save */
4549 save_state(dc);
4550 gen_helper_save(cpu_env);
4551 gen_store_gpr(dc, rd, cpu_tmp0);
4552 break;
4553 case 0x3d: /* restore */
4554 save_state(dc);
4555 gen_helper_restore(cpu_env);
4556 gen_store_gpr(dc, rd, cpu_tmp0);
4557 break;
4558 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4559 case 0x3e: /* V9 done/retry */
4560 {
4561 switch (rd) {
4562 case 0:
4563 if (!supervisor(dc))
4564 goto priv_insn;
4565 dc->npc = DYNAMIC_PC;
4566 dc->pc = DYNAMIC_PC;
4567 gen_helper_done(cpu_env);
4568 goto jmp_insn;
4569 case 1:
4570 if (!supervisor(dc))
4571 goto priv_insn;
4572 dc->npc = DYNAMIC_PC;
4573 dc->pc = DYNAMIC_PC;
4574 gen_helper_retry(cpu_env);
4575 goto jmp_insn;
4576 default:
4577 goto illegal_insn;
4578 }
4579 }
4580 break;
4581 #endif
4582 default:
4583 goto illegal_insn;
4584 }
4585 }
4586 break;
4587 }
4588 break;
4589 case 3: /* load/store instructions */
4590 {
4591 unsigned int xop = GET_FIELD(insn, 7, 12);
4592 /* ??? gen_address_mask prevents us from using a source
4593 register directly. Always generate a temporary. */
4594 TCGv cpu_addr = get_temp_tl(dc);
4595
4596 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4597 if (xop == 0x3c || xop == 0x3e) {
4598 /* V9 casa/casxa : no offset */
4599 } else if (IS_IMM) { /* immediate */
4600 simm = GET_FIELDs(insn, 19, 31);
4601 if (simm != 0) {
4602 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4603 }
4604 } else { /* register */
4605 rs2 = GET_FIELD(insn, 27, 31);
4606 if (rs2 != 0) {
4607 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
4608 }
4609 }
4610 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4611 (xop > 0x17 && xop <= 0x1d ) ||
4612 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4613 TCGv cpu_val = gen_dest_gpr(dc, rd);
4614
4615 switch (xop) {
4616 case 0x0: /* ld, V9 lduw, load unsigned word */
4617 gen_address_mask(dc, cpu_addr);
4618 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4619 break;
4620 case 0x1: /* ldub, load unsigned byte */
4621 gen_address_mask(dc, cpu_addr);
4622 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4623 break;
4624 case 0x2: /* lduh, load unsigned halfword */
4625 gen_address_mask(dc, cpu_addr);
4626 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4627 break;
4628 case 0x3: /* ldd, load double word */
4629 if (rd & 1)
4630 goto illegal_insn;
4631 else {
4632 TCGv_i32 r_const;
4633 TCGv_i64 t64;
4634
4635 save_state(dc);
4636 r_const = tcg_const_i32(7);
4637 /* XXX remove alignment check */
4638 gen_helper_check_align(cpu_env, cpu_addr, r_const);
4639 tcg_temp_free_i32(r_const);
4640 gen_address_mask(dc, cpu_addr);
4641 t64 = tcg_temp_new_i64();
4642 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4643 tcg_gen_trunc_i64_tl(cpu_val, t64);
4644 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4645 gen_store_gpr(dc, rd + 1, cpu_val);
4646 tcg_gen_shri_i64(t64, t64, 32);
4647 tcg_gen_trunc_i64_tl(cpu_val, t64);
4648 tcg_temp_free_i64(t64);
4649 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4650 }
4651 break;
4652 case 0x9: /* ldsb, load signed byte */
4653 gen_address_mask(dc, cpu_addr);
4654 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4655 break;
4656 case 0xa: /* ldsh, load signed halfword */
4657 gen_address_mask(dc, cpu_addr);
4658 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4659 break;
4660 case 0xd: /* ldstub -- XXX: should be atomically */
4661 {
4662 TCGv r_const;
4663
4664 gen_address_mask(dc, cpu_addr);
4665 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4666 r_const = tcg_const_tl(0xff);
4667 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4668 tcg_temp_free(r_const);
4669 }
4670 break;
4671 case 0x0f:
4672 /* swap, swap register with memory. Also atomically */
4673 {
4674 TCGv t0 = get_temp_tl(dc);
4675 CHECK_IU_FEATURE(dc, SWAP);
4676 cpu_src1 = gen_load_gpr(dc, rd);
4677 gen_address_mask(dc, cpu_addr);
4678 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4679 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4680 tcg_gen_mov_tl(cpu_val, t0);
4681 }
4682 break;
4683 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4684 case 0x10: /* lda, V9 lduwa, load word alternate */
4685 #ifndef TARGET_SPARC64
4686 if (IS_IMM)
4687 goto illegal_insn;
4688 if (!supervisor(dc))
4689 goto priv_insn;
4690 #endif
4691 save_state(dc);
4692 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4693 break;
4694 case 0x11: /* lduba, load unsigned byte alternate */
4695 #ifndef TARGET_SPARC64
4696 if (IS_IMM)
4697 goto illegal_insn;
4698 if (!supervisor(dc))
4699 goto priv_insn;
4700 #endif
4701 save_state(dc);
4702 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4703 break;
4704 case 0x12: /* lduha, load unsigned halfword alternate */
4705 #ifndef TARGET_SPARC64
4706 if (IS_IMM)
4707 goto illegal_insn;
4708 if (!supervisor(dc))
4709 goto priv_insn;
4710 #endif
4711 save_state(dc);
4712 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4713 break;
4714 case 0x13: /* ldda, load double word alternate */
4715 #ifndef TARGET_SPARC64
4716 if (IS_IMM)
4717 goto illegal_insn;
4718 if (!supervisor(dc))
4719 goto priv_insn;
4720 #endif
4721 if (rd & 1)
4722 goto illegal_insn;
4723 save_state(dc);
4724 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
4725 goto skip_move;
4726 case 0x19: /* ldsba, load signed byte alternate */
4727 #ifndef TARGET_SPARC64
4728 if (IS_IMM)
4729 goto illegal_insn;
4730 if (!supervisor(dc))
4731 goto priv_insn;
4732 #endif
4733 save_state(dc);
4734 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4735 break;
4736 case 0x1a: /* ldsha, load signed halfword alternate */
4737 #ifndef TARGET_SPARC64
4738 if (IS_IMM)
4739 goto illegal_insn;
4740 if (!supervisor(dc))
4741 goto priv_insn;
4742 #endif
4743 save_state(dc);
4744 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4745 break;
4746 case 0x1d: /* ldstuba -- XXX: should be atomically */
4747 #ifndef TARGET_SPARC64
4748 if (IS_IMM)
4749 goto illegal_insn;
4750 if (!supervisor(dc))
4751 goto priv_insn;
4752 #endif
4753 save_state(dc);
4754 gen_ldstub_asi(cpu_val, cpu_addr, insn);
4755 break;
4756 case 0x1f: /* swapa, swap reg with alt. memory. Also
4757 atomically */
4758 CHECK_IU_FEATURE(dc, SWAP);
4759 #ifndef TARGET_SPARC64
4760 if (IS_IMM)
4761 goto illegal_insn;
4762 if (!supervisor(dc))
4763 goto priv_insn;
4764 #endif
4765 save_state(dc);
4766 cpu_src1 = gen_load_gpr(dc, rd);
4767 gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
4768 break;
4769
4770 #ifndef TARGET_SPARC64
4771 case 0x30: /* ldc */
4772 case 0x31: /* ldcsr */
4773 case 0x33: /* lddc */
4774 goto ncp_insn;
4775 #endif
4776 #endif
4777 #ifdef TARGET_SPARC64
4778 case 0x08: /* V9 ldsw */
4779 gen_address_mask(dc, cpu_addr);
4780 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4781 break;
4782 case 0x0b: /* V9 ldx */
4783 gen_address_mask(dc, cpu_addr);
4784 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4785 break;
4786 case 0x18: /* V9 ldswa */
4787 save_state(dc);
4788 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4789 break;
4790 case 0x1b: /* V9 ldxa */
4791 save_state(dc);
4792 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4793 break;
4794 case 0x2d: /* V9 prefetch, no effect */
4795 goto skip_move;
4796 case 0x30: /* V9 ldfa */
4797 if (gen_trap_ifnofpu(dc)) {
4798 goto jmp_insn;
4799 }
4800 save_state(dc);
4801 gen_ldf_asi(cpu_addr, insn, 4, rd);
4802 gen_update_fprs_dirty(rd);
4803 goto skip_move;
4804 case 0x33: /* V9 lddfa */
4805 if (gen_trap_ifnofpu(dc)) {
4806 goto jmp_insn;
4807 }
4808 save_state(dc);
4809 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4810 gen_update_fprs_dirty(DFPREG(rd));
4811 goto skip_move;
4812 case 0x3d: /* V9 prefetcha, no effect */
4813 goto skip_move;
4814 case 0x32: /* V9 ldqfa */
4815 CHECK_FPU_FEATURE(dc, FLOAT128);
4816 if (gen_trap_ifnofpu(dc)) {
4817 goto jmp_insn;
4818 }
4819 save_state(dc);
4820 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4821 gen_update_fprs_dirty(QFPREG(rd));
4822 goto skip_move;
4823 #endif
4824 default:
4825 goto illegal_insn;
4826 }
4827 gen_store_gpr(dc, rd, cpu_val);
4828 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4829 skip_move: ;
4830 #endif
4831 } else if (xop >= 0x20 && xop < 0x24) {
4832 TCGv t0;
4833
4834 if (gen_trap_ifnofpu(dc)) {
4835 goto jmp_insn;
4836 }
4837 save_state(dc);
4838 switch (xop) {
4839 case 0x20: /* ldf, load fpreg */
4840 gen_address_mask(dc, cpu_addr);
4841 t0 = get_temp_tl(dc);
4842 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4843 cpu_dst_32 = gen_dest_fpr_F(dc);
4844 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4845 gen_store_fpr_F(dc, rd, cpu_dst_32);
4846 break;
4847 case 0x21: /* ldfsr, V9 ldxfsr */
4848 #ifdef TARGET_SPARC64
4849 gen_address_mask(dc, cpu_addr);
4850 if (rd == 1) {
4851 TCGv_i64 t64 = tcg_temp_new_i64();
4852 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4853 gen_helper_ldxfsr(cpu_env, t64);
4854 tcg_temp_free_i64(t64);
4855 break;
4856 }
4857 #endif
4858 cpu_dst_32 = get_temp_i32(dc);
4859 t0 = get_temp_tl(dc);
4860 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4861 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4862 gen_helper_ldfsr(cpu_env, cpu_dst_32);
4863 break;
4864 case 0x22: /* ldqf, load quad fpreg */
4865 {
4866 TCGv_i32 r_const;
4867
4868 CHECK_FPU_FEATURE(dc, FLOAT128);
4869 r_const = tcg_const_i32(dc->mem_idx);
4870 gen_address_mask(dc, cpu_addr);
4871 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
4872 tcg_temp_free_i32(r_const);
4873 gen_op_store_QT0_fpr(QFPREG(rd));
4874 gen_update_fprs_dirty(QFPREG(rd));
4875 }
4876 break;
4877 case 0x23: /* lddf, load double fpreg */
4878 gen_address_mask(dc, cpu_addr);
4879 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
4880 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4881 gen_store_fpr_D(dc, rd, cpu_dst_64);
4882 break;
4883 default:
4884 goto illegal_insn;
4885 }
4886 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
4887 xop == 0xe || xop == 0x1e) {
4888 TCGv cpu_val = gen_load_gpr(dc, rd);
4889
4890 switch (xop) {
4891 case 0x4: /* st, store word */
4892 gen_address_mask(dc, cpu_addr);
4893 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4894 break;
4895 case 0x5: /* stb, store byte */
4896 gen_address_mask(dc, cpu_addr);
4897 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4898 break;
4899 case 0x6: /* sth, store halfword */
4900 gen_address_mask(dc, cpu_addr);
4901 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4902 break;
4903 case 0x7: /* std, store double word */
4904 if (rd & 1)
4905 goto illegal_insn;
4906 else {
4907 TCGv_i32 r_const;
4908 TCGv_i64 t64;
4909 TCGv lo;
4910
4911 save_state(dc);
4912 gen_address_mask(dc, cpu_addr);
4913 r_const = tcg_const_i32(7);
4914 /* XXX remove alignment check */
4915 gen_helper_check_align(cpu_env, cpu_addr, r_const);
4916 tcg_temp_free_i32(r_const);
4917 lo = gen_load_gpr(dc, rd + 1);
4918
4919 t64 = tcg_temp_new_i64();
4920 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
4921 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
4922 tcg_temp_free_i64(t64);
4923 }
4924 break;
4925 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4926 case 0x14: /* sta, V9 stwa, store word alternate */
4927 #ifndef TARGET_SPARC64
4928 if (IS_IMM)
4929 goto illegal_insn;
4930 if (!supervisor(dc))
4931 goto priv_insn;
4932 #endif
4933 save_state(dc);
4934 gen_st_asi(cpu_val, cpu_addr, insn, 4);
4935 dc->npc = DYNAMIC_PC;
4936 break;
4937 case 0x15: /* stba, store byte alternate */
4938 #ifndef TARGET_SPARC64
4939 if (IS_IMM)
4940 goto illegal_insn;
4941 if (!supervisor(dc))
4942 goto priv_insn;
4943 #endif
4944 save_state(dc);
4945 gen_st_asi(cpu_val, cpu_addr, insn, 1);
4946 dc->npc = DYNAMIC_PC;
4947 break;
4948 case 0x16: /* stha, store halfword alternate */
4949 #ifndef TARGET_SPARC64
4950 if (IS_IMM)
4951 goto illegal_insn;
4952 if (!supervisor(dc))
4953 goto priv_insn;
4954 #endif
4955 save_state(dc);
4956 gen_st_asi(cpu_val, cpu_addr, insn, 2);
4957 dc->npc = DYNAMIC_PC;
4958 break;
4959 case 0x17: /* stda, store double word alternate */
4960 #ifndef TARGET_SPARC64
4961 if (IS_IMM)
4962 goto illegal_insn;
4963 if (!supervisor(dc))
4964 goto priv_insn;
4965 #endif
4966 if (rd & 1)
4967 goto illegal_insn;
4968 else {
4969 save_state(dc);
4970 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
4971 }
4972 break;
4973 #endif
4974 #ifdef TARGET_SPARC64
4975 case 0x0e: /* V9 stx */
4976 gen_address_mask(dc, cpu_addr);
4977 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4978 break;
4979 case 0x1e: /* V9 stxa */
4980 save_state(dc);
4981 gen_st_asi(cpu_val, cpu_addr, insn, 8);
4982 dc->npc = DYNAMIC_PC;
4983 break;
4984 #endif
4985 default:
4986 goto illegal_insn;
4987 }
4988 } else if (xop > 0x23 && xop < 0x28) {
4989 if (gen_trap_ifnofpu(dc)) {
4990 goto jmp_insn;
4991 }
4992 save_state(dc);
4993 switch (xop) {
4994 case 0x24: /* stf, store fpreg */
4995 {
4996 TCGv t = get_temp_tl(dc);
4997 gen_address_mask(dc, cpu_addr);
4998 cpu_src1_32 = gen_load_fpr_F(dc, rd);
4999 tcg_gen_ext_i32_tl(t, cpu_src1_32);
5000 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5001 }
5002 break;
5003 case 0x25: /* stfsr, V9 stxfsr */
5004 {
5005 TCGv t = get_temp_tl(dc);
5006
5007 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
5008 #ifdef TARGET_SPARC64
5009 gen_address_mask(dc, cpu_addr);
5010 if (rd == 1) {
5011 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5012 break;
5013 }
5014 #endif
5015 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5016 }
5017 break;
5018 case 0x26:
5019 #ifdef TARGET_SPARC64
5020 /* V9 stqf, store quad fpreg */
5021 {
5022 TCGv_i32 r_const;
5023
5024 CHECK_FPU_FEATURE(dc, FLOAT128);
5025 gen_op_load_fpr_QT0(QFPREG(rd));
5026 r_const = tcg_const_i32(dc->mem_idx);
5027 gen_address_mask(dc, cpu_addr);
5028 gen_helper_stqf(cpu_env, cpu_addr, r_const);
5029 tcg_temp_free_i32(r_const);
5030 }
5031 break;
5032 #else /* !TARGET_SPARC64 */
5033 /* stdfq, store floating point queue */
5034 #if defined(CONFIG_USER_ONLY)
5035 goto illegal_insn;
5036 #else
5037 if (!supervisor(dc))
5038 goto priv_insn;
5039 if (gen_trap_ifnofpu(dc)) {
5040 goto jmp_insn;
5041 }
5042 goto nfq_insn;
5043 #endif
5044 #endif
5045 case 0x27: /* stdf, store double fpreg */
5046 gen_address_mask(dc, cpu_addr);
5047 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5048 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
5049 break;
5050 default:
5051 goto illegal_insn;
5052 }
5053 } else if (xop > 0x33 && xop < 0x3f) {
5054 save_state(dc);
5055 switch (xop) {
5056 #ifdef TARGET_SPARC64
5057 case 0x34: /* V9 stfa */
5058 if (gen_trap_ifnofpu(dc)) {
5059 goto jmp_insn;
5060 }
5061 gen_stf_asi(cpu_addr, insn, 4, rd);
5062 break;
5063 case 0x36: /* V9 stqfa */
5064 {
5065 TCGv_i32 r_const;
5066
5067 CHECK_FPU_FEATURE(dc, FLOAT128);
5068 if (gen_trap_ifnofpu(dc)) {
5069 goto jmp_insn;
5070 }
5071 r_const = tcg_const_i32(7);
5072 gen_helper_check_align(cpu_env, cpu_addr, r_const);
5073 tcg_temp_free_i32(r_const);
5074 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
5075 }
5076 break;
5077 case 0x37: /* V9 stdfa */
5078 if (gen_trap_ifnofpu(dc)) {
5079 goto jmp_insn;
5080 }
5081 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
5082 break;
5083 case 0x3e: /* V9 casxa */
5084 rs2 = GET_FIELD(insn, 27, 31);
5085 cpu_src2 = gen_load_gpr(dc, rs2);
5086 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
5087 break;
5088 #else
5089 case 0x34: /* stc */
5090 case 0x35: /* stcsr */
5091 case 0x36: /* stdcq */
5092 case 0x37: /* stdc */
5093 goto ncp_insn;
5094 #endif
5095 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5096 case 0x3c: /* V9 or LEON3 casa */
5097 #ifndef TARGET_SPARC64
5098 CHECK_IU_FEATURE(dc, CASA);
5099 if (IS_IMM) {
5100 goto illegal_insn;
5101 }
5102 if (!supervisor(dc)) {
5103 goto priv_insn;
5104 }
5105 #endif
5106 rs2 = GET_FIELD(insn, 27, 31);
5107 cpu_src2 = gen_load_gpr(dc, rs2);
5108 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5109 break;
5110 #endif
5111 default:
5112 goto illegal_insn;
5113 }
5114 } else {
5115 goto illegal_insn;
5116 }
5117 }
5118 break;
5119 }
5120 /* default case for non jump instructions */
5121 if (dc->npc == DYNAMIC_PC) {
5122 dc->pc = DYNAMIC_PC;
5123 gen_op_next_insn();
5124 } else if (dc->npc == JUMP_PC) {
5125 /* we can do a static jump */
5126 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
5127 dc->is_br = 1;
5128 } else {
5129 dc->pc = dc->npc;
5130 dc->npc = dc->npc + 4;
5131 }
5132 jmp_insn:
5133 goto egress;
5134 illegal_insn:
5135 {
5136 TCGv_i32 r_const;
5137
5138 save_state(dc);
5139 r_const = tcg_const_i32(TT_ILL_INSN);
5140 gen_helper_raise_exception(cpu_env, r_const);
5141 tcg_temp_free_i32(r_const);
5142 dc->is_br = 1;
5143 }
5144 goto egress;
5145 unimp_flush:
5146 {
5147 TCGv_i32 r_const;
5148
5149 save_state(dc);
5150 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
5151 gen_helper_raise_exception(cpu_env, r_const);
5152 tcg_temp_free_i32(r_const);
5153 dc->is_br = 1;
5154 }
5155 goto egress;
5156 #if !defined(CONFIG_USER_ONLY)
5157 priv_insn:
5158 {
5159 TCGv_i32 r_const;
5160
5161 save_state(dc);
5162 r_const = tcg_const_i32(TT_PRIV_INSN);
5163 gen_helper_raise_exception(cpu_env, r_const);
5164 tcg_temp_free_i32(r_const);
5165 dc->is_br = 1;
5166 }
5167 goto egress;
5168 #endif
5169 nfpu_insn:
5170 save_state(dc);
5171 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
5172 dc->is_br = 1;
5173 goto egress;
5174 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
5175 nfq_insn:
5176 save_state(dc);
5177 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
5178 dc->is_br = 1;
5179 goto egress;
5180 #endif
5181 #ifndef TARGET_SPARC64
5182 ncp_insn:
5183 {
5184 TCGv r_const;
5185
5186 save_state(dc);
5187 r_const = tcg_const_i32(TT_NCP_INSN);
5188 gen_helper_raise_exception(cpu_env, r_const);
5189 tcg_temp_free(r_const);
5190 dc->is_br = 1;
5191 }
5192 goto egress;
5193 #endif
5194 egress:
5195 if (dc->n_t32 != 0) {
5196 int i;
5197 for (i = dc->n_t32 - 1; i >= 0; --i) {
5198 tcg_temp_free_i32(dc->t32[i]);
5199 }
5200 dc->n_t32 = 0;
5201 }
5202 if (dc->n_ttl != 0) {
5203 int i;
5204 for (i = dc->n_ttl - 1; i >= 0; --i) {
5205 tcg_temp_free(dc->ttl[i]);
5206 }
5207 dc->n_ttl = 0;
5208 }
5209 }
5210
5211 static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
5212 TranslationBlock *tb,
5213 bool spc)
5214 {
5215 CPUState *cs = CPU(cpu);
5216 CPUSPARCState *env = &cpu->env;
5217 target_ulong pc_start, last_pc;
5218 DisasContext dc1, *dc = &dc1;
5219 CPUBreakpoint *bp;
5220 int j, lj = -1;
5221 int num_insns;
5222 int max_insns;
5223 unsigned int insn;
5224
5225 memset(dc, 0, sizeof(DisasContext));
5226 dc->tb = tb;
5227 pc_start = tb->pc;
5228 dc->pc = pc_start;
5229 last_pc = dc->pc;
5230 dc->npc = (target_ulong) tb->cs_base;
5231 dc->cc_op = CC_OP_DYNAMIC;
5232 dc->mem_idx = cpu_mmu_index(env, false);
5233 dc->def = env->def;
5234 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5235 dc->address_mask_32bit = tb_am_enabled(tb->flags);
5236 dc->singlestep = (cs->singlestep_enabled || singlestep);
5237
5238 num_insns = 0;
5239 max_insns = tb->cflags & CF_COUNT_MASK;
5240 if (max_insns == 0)
5241 max_insns = CF_COUNT_MASK;
5242 gen_tb_start(tb);
5243 do {
5244 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
5245 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
5246 if (bp->pc == dc->pc) {
5247 if (dc->pc != pc_start)
5248 save_state(dc);
5249 gen_helper_debug(cpu_env);
5250 tcg_gen_exit_tb(0);
5251 dc->is_br = 1;
5252 goto exit_gen_loop;
5253 }
5254 }
5255 }
5256 if (spc) {
5257 qemu_log("Search PC...\n");
5258 j = tcg_op_buf_count();
5259 if (lj < j) {
5260 lj++;
5261 while (lj < j)
5262 tcg_ctx.gen_opc_instr_start[lj++] = 0;
5263 tcg_ctx.gen_opc_pc[lj] = dc->pc;
5264 gen_opc_npc[lj] = dc->npc;
5265 tcg_ctx.gen_opc_instr_start[lj] = 1;
5266 tcg_ctx.gen_opc_icount[lj] = num_insns;
5267 }
5268 }
5269 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
5270 gen_io_start();
5271 last_pc = dc->pc;
5272 insn = cpu_ldl_code(env, dc->pc);
5273
5274 disas_sparc_insn(dc, insn);
5275 num_insns++;
5276
5277 if (dc->is_br)
5278 break;
5279 /* if the next PC is different, we abort now */
5280 if (dc->pc != (last_pc + 4))
5281 break;
5282 /* if we reach a page boundary, we stop generation so that the
5283 PC of a TT_TFAULT exception is always in the right page */
5284 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5285 break;
5286 /* if single step mode, we generate only one instruction and
5287 generate an exception */
5288 if (dc->singlestep) {
5289 break;
5290 }
5291 } while (!tcg_op_buf_full() &&
5292 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5293 num_insns < max_insns);
5294
5295 exit_gen_loop:
5296 if (tb->cflags & CF_LAST_IO) {
5297 gen_io_end();
5298 }
5299 if (!dc->is_br) {
5300 if (dc->pc != DYNAMIC_PC &&
5301 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5302 /* static PC and NPC: we can use direct chaining */
5303 gen_goto_tb(dc, 0, dc->pc, dc->npc);
5304 } else {
5305 if (dc->pc != DYNAMIC_PC) {
5306 tcg_gen_movi_tl(cpu_pc, dc->pc);
5307 }
5308 save_npc(dc);
5309 tcg_gen_exit_tb(0);
5310 }
5311 }
5312 gen_tb_end(tb, num_insns);
5313
5314 if (spc) {
5315 j = tcg_op_buf_count();
5316 lj++;
5317 while (lj <= j)
5318 tcg_ctx.gen_opc_instr_start[lj++] = 0;
5319 #if 0
5320 log_page_dump();
5321 #endif
5322 gen_opc_jump_pc[0] = dc->jump_pc[0];
5323 gen_opc_jump_pc[1] = dc->jump_pc[1];
5324 } else {
5325 tb->size = last_pc + 4 - pc_start;
5326 tb->icount = num_insns;
5327 }
5328 #ifdef DEBUG_DISAS
5329 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
5330 qemu_log("--------------\n");
5331 qemu_log("IN: %s\n", lookup_symbol(pc_start));
5332 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
5333 qemu_log("\n");
5334 }
5335 #endif
5336 }
5337
5338 void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
5339 {
5340 gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, false);
5341 }
5342
5343 void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
5344 {
5345 gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, true);
5346 }
5347
5348 void gen_intermediate_code_init(CPUSPARCState *env)
5349 {
5350 unsigned int i;
5351 static int inited;
5352 static const char * const gregnames[8] = {
5353 NULL, // g0 not used
5354 "g1",
5355 "g2",
5356 "g3",
5357 "g4",
5358 "g5",
5359 "g6",
5360 "g7",
5361 };
5362 static const char * const fregnames[32] = {
5363 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5364 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5365 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5366 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5367 };
5368
5369 /* init various static tables */
5370 if (!inited) {
5371 inited = 1;
5372
5373 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
5374 cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
5375 offsetof(CPUSPARCState, regwptr),
5376 "regwptr");
5377 #ifdef TARGET_SPARC64
5378 cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, xcc),
5379 "xcc");
5380 cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, asi),
5381 "asi");
5382 cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, fprs),
5383 "fprs");
5384 cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, gsr),
5385 "gsr");
5386 cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
5387 offsetof(CPUSPARCState, tick_cmpr),
5388 "tick_cmpr");
5389 cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
5390 offsetof(CPUSPARCState, stick_cmpr),
5391 "stick_cmpr");
5392 cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
5393 offsetof(CPUSPARCState, hstick_cmpr),
5394 "hstick_cmpr");
5395 cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hintp),
5396 "hintp");
5397 cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, htba),
5398 "htba");
5399 cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hver),
5400 "hver");
5401 cpu_ssr = tcg_global_mem_new(TCG_AREG0,
5402 offsetof(CPUSPARCState, ssr), "ssr");
5403 cpu_ver = tcg_global_mem_new(TCG_AREG0,
5404 offsetof(CPUSPARCState, version), "ver");
5405 cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
5406 offsetof(CPUSPARCState, softint),
5407 "softint");
5408 #else
5409 cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, wim),
5410 "wim");
5411 #endif
5412 cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cond),
5413 "cond");
5414 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_src),
5415 "cc_src");
5416 cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
5417 offsetof(CPUSPARCState, cc_src2),
5418 "cc_src2");
5419 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_dst),
5420 "cc_dst");
5421 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, cc_op),
5422 "cc_op");
5423 cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, psr),
5424 "psr");
5425 cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, fsr),
5426 "fsr");
5427 cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, pc),
5428 "pc");
5429 cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, npc),
5430 "npc");
5431 cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, y), "y");
5432 #ifndef CONFIG_USER_ONLY
5433 cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, tbr),
5434 "tbr");
5435 #endif
5436 for (i = 1; i < 8; i++) {
5437 cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
5438 offsetof(CPUSPARCState, gregs[i]),
5439 gregnames[i]);
5440 }
5441 for (i = 0; i < TARGET_DPREGS; i++) {
5442 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
5443 offsetof(CPUSPARCState, fpr[i]),
5444 fregnames[i]);
5445 }
5446 }
5447 }
5448
5449 void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos)
5450 {
5451 target_ulong npc;
5452 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
5453 npc = gen_opc_npc[pc_pos];
5454 if (npc == 1) {
5455 /* dynamic NPC: already stored */
5456 } else if (npc == 2) {
5457 /* jump PC: use 'cond' and the jump targets of the translation */
5458 if (env->cond) {
5459 env->npc = gen_opc_jump_pc[0];
5460 } else {
5461 env->npc = gen_opc_jump_pc[1];
5462 }
5463 } else {
5464 env->npc = npc;
5465 }
5466 }
AR7 emulation for QEMU