target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 QEMU_NORETURN
  34 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  35                                 int error_code)
  36 {
  37     do_raise_exception_err(env, exception, error_code, 0);
  38 }
  39
  40 QEMU_NORETURN
  41 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  42 {
  43     do_raise_exception(env, exception, GETPC());
  44 }
  45
  46 QEMU_NORETURN void helper_raise_exception_debug(CPUMIPSState *env)
  47 {
  48     do_raise_exception(env, EXCP_DEBUG, 0);
  49 }
  50
  51 static QEMU_NORETURN
  52 void raise_exception(CPUMIPSState *env, uint32_t exception)
  53 {
  54     do_raise_exception(env, exception, 0);
  55 }
  56
  57 #if defined(CONFIG_USER_ONLY)
  58 #define HELPER_LD(name, insn, type)                                     \
  59 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  60                              int mem_idx, uintptr_t retaddr)            \
  61 {                                                                       \
  62     return (type) cpu_##insn##_data_ra(env, addr, retaddr);             \
  63 }
  64 #else
  65 #define HELPER_LD(name, insn, type)                                     \
  66 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  67                              int mem_idx, uintptr_t retaddr)            \
  68 {                                                                       \
  69     switch (mem_idx)                                                    \
  70     {                                                                   \
  71     case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr);   \
  72     case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr);    \
  73     default:                                                            \
  74     case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr);     \
  75     }                                                                   \
  76 }
  77 #endif
  78 HELPER_LD(lw, ldl, int32_t)
  79 #if defined(TARGET_MIPS64)
  80 HELPER_LD(ld, ldq, int64_t)
  81 #endif
  82 #undef HELPER_LD
  83
  84 #if defined(CONFIG_USER_ONLY)
  85 #define HELPER_ST(name, insn, type)                                     \
  86 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  87                              type val, int mem_idx, uintptr_t retaddr)  \
  88 {                                                                       \
  89     cpu_##insn##_data_ra(env, addr, val, retaddr);                      \
  90 }
  91 #else
  92 #define HELPER_ST(name, insn, type)                                     \
  93 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  94                              type val, int mem_idx, uintptr_t retaddr)  \
  95 {                                                                       \
  96     switch (mem_idx)                                                    \
  97     {                                                                   \
  98     case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break;     \
  99     case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break;      \
 100     default:                                                            \
 101     case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break;       \
 102     }                                                                   \
 103 }
 104 #endif
 105 HELPER_ST(sb, stb, uint8_t)
 106 HELPER_ST(sw, stl, uint32_t)
 107 #if defined(TARGET_MIPS64)
 108 HELPER_ST(sd, stq, uint64_t)
 109 #endif
 110 #undef HELPER_ST
 111
 112 target_ulong helper_clo (target_ulong arg1)
 113 {
 114     return clo32(arg1);
 115 }
 116
 117 target_ulong helper_clz (target_ulong arg1)
 118 {
 119     return clz32(arg1);
 120 }
 121
 122 #if defined(TARGET_MIPS64)
 123 target_ulong helper_dclo (target_ulong arg1)
 124 {
 125     return clo64(arg1);
 126 }
 127
 128 target_ulong helper_dclz (target_ulong arg1)
 129 {
 130     return clz64(arg1);
 131 }
 132 #endif /* TARGET_MIPS64 */
 133
 134 /* 64 bits arithmetic for 32 bits hosts */
 135 static inline uint64_t get_HILO(CPUMIPSState *env)
 136 {
 137     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 138 }
 139
 140 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 141 {
 142     target_ulong tmp;
 143     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 144     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 145     return tmp;
 146 }
 147
 148 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 149 {
 150     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 151     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 152     return tmp;
 153 }
 154
 155 /* Multiplication variants of the vr54xx. */
 156 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 157                          target_ulong arg2)
 158 {
 159     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 160                                  (int64_t)(int32_t)arg2));
 161 }
 162
 163 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 164                           target_ulong arg2)
 165 {
 166     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 167                        (uint64_t)(uint32_t)arg2);
 168 }
 169
 170 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 171                          target_ulong arg2)
 172 {
 173     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 174                        (int64_t)(int32_t)arg2);
 175 }
 176
 177 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 178                            target_ulong arg2)
 179 {
 180     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 181                        (int64_t)(int32_t)arg2);
 182 }
 183
 184 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 185                           target_ulong arg2)
 186 {
 187     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 188                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 189 }
 190
 191 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 192                             target_ulong arg2)
 193 {
 194     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 195                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 196 }
 197
 198 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 199                          target_ulong arg2)
 200 {
 201     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 202                        (int64_t)(int32_t)arg2);
 203 }
 204
 205 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 206                            target_ulong arg2)
 207 {
 208     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 209                        (int64_t)(int32_t)arg2);
 210 }
 211
 212 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 213                           target_ulong arg2)
 214 {
 215     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 216                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 217 }
 218
 219 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 220                             target_ulong arg2)
 221 {
 222     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 223                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 224 }
 225
 226 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 227                           target_ulong arg2)
 228 {
 229     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 230 }
 231
 232 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 233                            target_ulong arg2)
 234 {
 235     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 236                        (uint64_t)(uint32_t)arg2);
 237 }
 238
 239 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 240                            target_ulong arg2)
 241 {
 242     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 243                        (int64_t)(int32_t)arg2);
 244 }
 245
 246 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 247                             target_ulong arg2)
 248 {
 249     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 250                        (uint64_t)(uint32_t)arg2);
 251 }
 252
 253 static inline target_ulong bitswap(target_ulong v)
 254 {
 255     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 256               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 257     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 258               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 259     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 260               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 261     return v;
 262 }
 263
 264 #ifdef TARGET_MIPS64
 265 target_ulong helper_dbitswap(target_ulong rt)
 266 {
 267     return bitswap(rt);
 268 }
 269 #endif
 270
 271 target_ulong helper_bitswap(target_ulong rt)
 272 {
 273     return (int32_t)bitswap(rt);
 274 }
 275
 276 #ifndef CONFIG_USER_ONLY
 277
 278 static inline hwaddr do_translate_address(CPUMIPSState *env,
 279                                                       target_ulong address,
 280                                                       int rw, uintptr_t retaddr)
 281 {
 282     hwaddr lladdr;
 283     CPUState *cs = CPU(mips_env_get_cpu(env));
 284
 285     lladdr = cpu_mips_translate_address(env, address, rw);
 286
 287     if (lladdr == -1LL) {
 288         cpu_loop_exit_restore(cs, retaddr);
 289     } else {
 290         return lladdr;
 291     }
 292 }
 293
 294 #define HELPER_LD_ATOMIC(name, insn, almask)                                  \
 295 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 296 {                                                                             \
 297     if (arg & almask) {                                                       \
 298         env->CP0_BadVAddr = arg;                                              \
 299         do_raise_exception(env, EXCP_AdEL, GETPC());                          \
 300     }                                                                         \
 301     env->lladdr = do_translate_address(env, arg, 0, GETPC());                 \
 302     env->llval = do_##insn(env, arg, mem_idx, GETPC());                       \
 303     return env->llval;                                                        \
 304 }
 305 HELPER_LD_ATOMIC(ll, lw, 0x3)
 306 #ifdef TARGET_MIPS64
 307 HELPER_LD_ATOMIC(lld, ld, 0x7)
 308 #endif
 309 #undef HELPER_LD_ATOMIC
 310
 311 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 312 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 313                            target_ulong arg2, int mem_idx)                    \
 314 {                                                                             \
 315     target_long tmp;                                                          \
 316                                                                               \
 317     if (arg2 & almask) {                                                      \
 318         env->CP0_BadVAddr = arg2;                                             \
 319         do_raise_exception(env, EXCP_AdES, GETPC());                          \
 320     }                                                                         \
 321     if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) {         \
 322         tmp = do_##ld_insn(env, arg2, mem_idx, GETPC());                      \
 323         if (tmp == env->llval) {                                              \
 324             do_##st_insn(env, arg2, arg1, mem_idx, GETPC());                  \
 325             return 1;                                                         \
 326         }                                                                     \
 327     }                                                                         \
 328     return 0;                                                                 \
 329 }
 330 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 331 #ifdef TARGET_MIPS64
 332 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 333 #endif
 334 #undef HELPER_ST_ATOMIC
 335 #endif
 336
 337 #ifdef TARGET_WORDS_BIGENDIAN
 338 #define GET_LMASK(v) ((v) & 3)
 339 #define GET_OFFSET(addr, offset) (addr + (offset))
 340 #else
 341 #define GET_LMASK(v) (((v) & 3) ^ 3)
 342 #define GET_OFFSET(addr, offset) (addr - (offset))
 343 #endif
 344
 345 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 346                 int mem_idx)
 347 {
 348     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
 349
 350     if (GET_LMASK(arg2) <= 2) {
 351         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
 352               GETPC());
 353     }
 354
 355     if (GET_LMASK(arg2) <= 1) {
 356         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
 357               GETPC());
 358     }
 359
 360     if (GET_LMASK(arg2) == 0) {
 361         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
 362               GETPC());
 363     }
 364 }
 365
 366 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 367                 int mem_idx)
 368 {
 369     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 370
 371     if (GET_LMASK(arg2) >= 1) {
 372         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 373               GETPC());
 374     }
 375
 376     if (GET_LMASK(arg2) >= 2) {
 377         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 378               GETPC());
 379     }
 380
 381     if (GET_LMASK(arg2) == 3) {
 382         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 383               GETPC());
 384     }
 385 }
 386
 387 #if defined(TARGET_MIPS64)
 388 /* "half" load and stores.  We must do the memory access inline,
 389    or fault handling won't work.  */
 390
 391 #ifdef TARGET_WORDS_BIGENDIAN
 392 #define GET_LMASK64(v) ((v) & 7)
 393 #else
 394 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 395 #endif
 396
 397 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 398                 int mem_idx)
 399 {
 400     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
 401
 402     if (GET_LMASK64(arg2) <= 6) {
 403         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
 404               GETPC());
 405     }
 406
 407     if (GET_LMASK64(arg2) <= 5) {
 408         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
 409               GETPC());
 410     }
 411
 412     if (GET_LMASK64(arg2) <= 4) {
 413         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
 414               GETPC());
 415     }
 416
 417     if (GET_LMASK64(arg2) <= 3) {
 418         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
 419               GETPC());
 420     }
 421
 422     if (GET_LMASK64(arg2) <= 2) {
 423         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
 424               GETPC());
 425     }
 426
 427     if (GET_LMASK64(arg2) <= 1) {
 428         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
 429               GETPC());
 430     }
 431
 432     if (GET_LMASK64(arg2) <= 0) {
 433         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
 434               GETPC());
 435     }
 436 }
 437
 438 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 439                 int mem_idx)
 440 {
 441     do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 442
 443     if (GET_LMASK64(arg2) >= 1) {
 444         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
 445               GETPC());
 446     }
 447
 448     if (GET_LMASK64(arg2) >= 2) {
 449         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
 450               GETPC());
 451     }
 452
 453     if (GET_LMASK64(arg2) >= 3) {
 454         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
 455               GETPC());
 456     }
 457
 458     if (GET_LMASK64(arg2) >= 4) {
 459         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
 460               GETPC());
 461     }
 462
 463     if (GET_LMASK64(arg2) >= 5) {
 464         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
 465               GETPC());
 466     }
 467
 468     if (GET_LMASK64(arg2) >= 6) {
 469         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
 470               GETPC());
 471     }
 472
 473     if (GET_LMASK64(arg2) == 7) {
 474         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
 475               GETPC());
 476     }
 477 }
 478 #endif /* TARGET_MIPS64 */
 479
 480 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 481
 482 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 483                 uint32_t mem_idx)
 484 {
 485     target_ulong base_reglist = reglist & 0xf;
 486     target_ulong do_r31 = reglist & 0x10;
 487
 488     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 489         target_ulong i;
 490
 491         for (i = 0; i < base_reglist; i++) {
 492             env->active_tc.gpr[multiple_regs[i]] =
 493                 (target_long)do_lw(env, addr, mem_idx, GETPC());
 494             addr += 4;
 495         }
 496     }
 497
 498     if (do_r31) {
 499         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
 500                                                     GETPC());
 501     }
 502 }
 503
 504 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 505                 uint32_t mem_idx)
 506 {
 507     target_ulong base_reglist = reglist & 0xf;
 508     target_ulong do_r31 = reglist & 0x10;
 509
 510     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 511         target_ulong i;
 512
 513         for (i = 0; i < base_reglist; i++) {
 514             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 515                   GETPC());
 516             addr += 4;
 517         }
 518     }
 519
 520     if (do_r31) {
 521         do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 522     }
 523 }
 524
 525 #if defined(TARGET_MIPS64)
 526 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 527                 uint32_t mem_idx)
 528 {
 529     target_ulong base_reglist = reglist & 0xf;
 530     target_ulong do_r31 = reglist & 0x10;
 531
 532     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 533         target_ulong i;
 534
 535         for (i = 0; i < base_reglist; i++) {
 536             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
 537                                                          GETPC());
 538             addr += 8;
 539         }
 540     }
 541
 542     if (do_r31) {
 543         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
 544     }
 545 }
 546
 547 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 548                 uint32_t mem_idx)
 549 {
 550     target_ulong base_reglist = reglist & 0xf;
 551     target_ulong do_r31 = reglist & 0x10;
 552
 553     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 554         target_ulong i;
 555
 556         for (i = 0; i < base_reglist; i++) {
 557             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
 558                   GETPC());
 559             addr += 8;
 560         }
 561     }
 562
 563     if (do_r31) {
 564         do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
 565     }
 566 }
 567 #endif
 568
 569 #ifndef CONFIG_USER_ONLY
 570 /* SMP helpers.  */
 571 static bool mips_vpe_is_wfi(MIPSCPU *c)
 572 {
 573     CPUState *cpu = CPU(c);
 574     CPUMIPSState *env = &c->env;
 575
 576     /* If the VPE is halted but otherwise active, it means it's waiting for
 577        an interrupt.  */
 578     return cpu->halted && mips_vpe_active(env);
 579 }
 580
 581 static inline void mips_vpe_wake(MIPSCPU *c)
 582 {
 583     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 584        because there might be other conditions that state that c should
 585        be sleeping.  */
 586     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 587 }
 588
 589 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 590 {
 591     CPUState *cs = CPU(cpu);
 592
 593     /* The VPE was shut off, really go to bed.
 594        Reset any old _WAKE requests.  */
 595     cs->halted = 1;
 596     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 597 }
 598
 599 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 600 {
 601     CPUMIPSState *c = &cpu->env;
 602
 603     /* FIXME: TC reschedule.  */
 604     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 605         mips_vpe_wake(cpu);
 606     }
 607 }
 608
 609 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 610 {
 611     CPUMIPSState *c = &cpu->env;
 612
 613     /* FIXME: TC reschedule.  */
 614     if (!mips_vpe_active(c)) {
 615         mips_vpe_sleep(cpu);
 616     }
 617 }
 618
 619 /**
 620  * mips_cpu_map_tc:
 621  * @env: CPU from which mapping is performed.
 622  * @tc: Should point to an int with the value of the global TC index.
 623  *
 624  * This function will transform @tc into a local index within the
 625  * returned #CPUMIPSState.
 626  */
 627 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 628           which depends on runtime setup. Can probably be fixed by
 629           walking the list of CPUMIPSStates.  */
 630 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 631 {
 632     MIPSCPU *cpu;
 633     CPUState *cs;
 634     CPUState *other_cs;
 635     int vpe_idx;
 636     int tc_idx = *tc;
 637
 638     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 639         /* Not allowed to address other CPUs.  */
 640         *tc = env->current_tc;
 641         return env;
 642     }
 643
 644     cs = CPU(mips_env_get_cpu(env));
 645     vpe_idx = tc_idx / cs->nr_threads;
 646     *tc = tc_idx % cs->nr_threads;
 647     other_cs = qemu_get_cpu(vpe_idx);
 648     if (other_cs == NULL) {
 649         return env;
 650     }
 651     cpu = MIPS_CPU(other_cs);
 652     return &cpu->env;
 653 }
 654
 655 /* The per VPE CP0_Status register shares some fields with the per TC
 656    CP0_TCStatus registers. These fields are wired to the same registers,
 657    so changes to either of them should be reflected on both registers.
 658
 659    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 660
 661    These helper call synchronizes the regs for a given cpu.  */
 662
 663 /* Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.  */
 664 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 665                                      int tc);  */
 666
 667 /* Called for updates to CP0_TCStatus.  */
 668 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 669                              target_ulong v)
 670 {
 671     uint32_t status;
 672     uint32_t tcu, tmx, tasid, tksu;
 673     uint32_t mask = ((1U << CP0St_CU3)
 674                        | (1 << CP0St_CU2)
 675                        | (1 << CP0St_CU1)
 676                        | (1 << CP0St_CU0)
 677                        | (1 << CP0St_MX)
 678                        | (3 << CP0St_KSU));
 679
 680     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 681     tmx = (v >> CP0TCSt_TMX) & 0x1;
 682     tasid = v & 0xff;
 683     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 684
 685     status = tcu << CP0St_CU0;
 686     status |= tmx << CP0St_MX;
 687     status |= tksu << CP0St_KSU;
 688
 689     cpu->CP0_Status &= ~mask;
 690     cpu->CP0_Status |= status;
 691
 692     /* Sync the TASID with EntryHi.  */
 693     cpu->CP0_EntryHi &= ~0xff;
 694     cpu->CP0_EntryHi |= tasid;
 695
 696     compute_hflags(cpu);
 697 }
 698
 699 /* Called for updates to CP0_EntryHi.  */
 700 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 701 {
 702     int32_t *tcst;
 703     uint32_t asid, v = cpu->CP0_EntryHi;
 704
 705     asid = v & 0xff;
 706
 707     if (tc == cpu->current_tc) {
 708         tcst = &cpu->active_tc.CP0_TCStatus;
 709     } else {
 710         tcst = &cpu->tcs[tc].CP0_TCStatus;
 711     }
 712
 713     *tcst &= ~0xff;
 714     *tcst |= asid;
 715 }
 716
 717 /* CP0 helpers */
 718 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 719 {
 720     return env->mvp->CP0_MVPControl;
 721 }
 722
 723 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 724 {
 725     return env->mvp->CP0_MVPConf0;
 726 }
 727
 728 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 729 {
 730     return env->mvp->CP0_MVPConf1;
 731 }
 732
 733 target_ulong helper_mfc0_random(CPUMIPSState *env)
 734 {
 735     return (int32_t)cpu_mips_get_random(env);
 736 }
 737
 738 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 739 {
 740     return env->active_tc.CP0_TCStatus;
 741 }
 742
 743 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 744 {
 745     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 746     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 747
 748     if (other_tc == other->current_tc)
 749         return other->active_tc.CP0_TCStatus;
 750     else
 751         return other->tcs[other_tc].CP0_TCStatus;
 752 }
 753
 754 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 755 {
 756     return env->active_tc.CP0_TCBind;
 757 }
 758
 759 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 760 {
 761     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 762     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 763
 764     if (other_tc == other->current_tc)
 765         return other->active_tc.CP0_TCBind;
 766     else
 767         return other->tcs[other_tc].CP0_TCBind;
 768 }
 769
 770 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 771 {
 772     return env->active_tc.PC;
 773 }
 774
 775 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 776 {
 777     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 778     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 779
 780     if (other_tc == other->current_tc)
 781         return other->active_tc.PC;
 782     else
 783         return other->tcs[other_tc].PC;
 784 }
 785
 786 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 787 {
 788     return env->active_tc.CP0_TCHalt;
 789 }
 790
 791 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 792 {
 793     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 794     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 795
 796     if (other_tc == other->current_tc)
 797         return other->active_tc.CP0_TCHalt;
 798     else
 799         return other->tcs[other_tc].CP0_TCHalt;
 800 }
 801
 802 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 803 {
 804     return env->active_tc.CP0_TCContext;
 805 }
 806
 807 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 808 {
 809     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 810     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 811
 812     if (other_tc == other->current_tc)
 813         return other->active_tc.CP0_TCContext;
 814     else
 815         return other->tcs[other_tc].CP0_TCContext;
 816 }
 817
 818 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 819 {
 820     return env->active_tc.CP0_TCSchedule;
 821 }
 822
 823 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 824 {
 825     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 826     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 827
 828     if (other_tc == other->current_tc)
 829         return other->active_tc.CP0_TCSchedule;
 830     else
 831         return other->tcs[other_tc].CP0_TCSchedule;
 832 }
 833
 834 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 835 {
 836     return env->active_tc.CP0_TCScheFBack;
 837 }
 838
 839 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 840 {
 841     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 842     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 843
 844     if (other_tc == other->current_tc)
 845         return other->active_tc.CP0_TCScheFBack;
 846     else
 847         return other->tcs[other_tc].CP0_TCScheFBack;
 848 }
 849
 850 target_ulong helper_mfc0_count(CPUMIPSState *env)
 851 {
 852     return (int32_t)cpu_mips_get_count(env);
 853 }
 854
 855 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 856 {
 857     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 858     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 859
 860     return other->CP0_EntryHi;
 861 }
 862
 863 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 864 {
 865     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 866     int32_t tccause;
 867     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 868
 869     if (other_tc == other->current_tc) {
 870         tccause = other->CP0_Cause;
 871     } else {
 872         tccause = other->CP0_Cause;
 873     }
 874
 875     return tccause;
 876 }
 877
 878 target_ulong helper_mftc0_status(CPUMIPSState *env)
 879 {
 880     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 881     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 882
 883     return other->CP0_Status;
 884 }
 885
 886 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 887 {
 888     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 889 }
 890
 891 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 892 {
 893     return (int32_t)env->CP0_WatchLo[sel];
 894 }
 895
 896 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 897 {
 898     return env->CP0_WatchHi[sel];
 899 }
 900
 901 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 902 {
 903     target_ulong t0 = env->CP0_Debug;
 904     if (env->hflags & MIPS_HFLAG_DM)
 905         t0 |= 1 << CP0DB_DM;
 906
 907     return t0;
 908 }
 909
 910 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 911 {
 912     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 913     int32_t tcstatus;
 914     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 915
 916     if (other_tc == other->current_tc)
 917         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 918     else
 919         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 920
 921     /* XXX: Might be wrong, check with EJTAG spec. */
 922     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 923             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 924 }
 925
 926 #if defined(TARGET_MIPS64)
 927 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 928 {
 929     return env->active_tc.PC;
 930 }
 931
 932 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 933 {
 934     return env->active_tc.CP0_TCHalt;
 935 }
 936
 937 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 938 {
 939     return env->active_tc.CP0_TCContext;
 940 }
 941
 942 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 943 {
 944     return env->active_tc.CP0_TCSchedule;
 945 }
 946
 947 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 948 {
 949     return env->active_tc.CP0_TCScheFBack;
 950 }
 951
 952 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 953 {
 954     return env->lladdr >> env->CP0_LLAddr_shift;
 955 }
 956
 957 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 958 {
 959     return env->CP0_WatchLo[sel];
 960 }
 961 #endif /* TARGET_MIPS64 */
 962
 963 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 964 {
 965     uint32_t index_p = env->CP0_Index & 0x80000000;
 966     uint32_t tlb_index = arg1 & 0x7fffffff;
 967     if (tlb_index < env->tlb->nb_tlb) {
 968         if (env->insn_flags & ISA_MIPS32R6) {
 969             index_p |= arg1 & 0x80000000;
 970         }
 971         env->CP0_Index = index_p | tlb_index;
 972     }
 973 }
 974
 975 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 976 {
 977     uint32_t mask = 0;
 978     uint32_t newval;
 979
 980     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 981         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 982                 (1 << CP0MVPCo_EVP);
 983     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 984         mask |= (1 << CP0MVPCo_STLB);
 985     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 986
 987     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 988
 989     env->mvp->CP0_MVPControl = newval;
 990 }
 991
 992 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 993 {
 994     uint32_t mask;
 995     uint32_t newval;
 996
 997     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 998            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 999     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1000
1001     /* Yield scheduler intercept not implemented. */
1002     /* Gating storage scheduler intercept not implemented. */
1003
1004     // TODO: Enable/disable TCs.
1005
1006     env->CP0_VPEControl = newval;
1007 }
1008
1009 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1010 {
1011     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1012     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1013     uint32_t mask;
1014     uint32_t newval;
1015
1016     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1017            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1018     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1019
1020     /* TODO: Enable/disable TCs.  */
1021
1022     other->CP0_VPEControl = newval;
1023 }
1024
1025 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1026 {
1027     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1028     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1029     /* FIXME: Mask away return zero on read bits.  */
1030     return other->CP0_VPEControl;
1031 }
1032
1033 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1034 {
1035     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1036     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1037
1038     return other->CP0_VPEConf0;
1039 }
1040
1041 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1042 {
1043     uint32_t mask = 0;
1044     uint32_t newval;
1045
1046     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1047         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1048             mask |= (0xff << CP0VPEC0_XTC);
1049         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1050     }
1051     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1052
1053     // TODO: TC exclusive handling due to ERL/EXL.
1054
1055     env->CP0_VPEConf0 = newval;
1056 }
1057
1058 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1059 {
1060     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1061     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1062     uint32_t mask = 0;
1063     uint32_t newval;
1064
1065     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1066     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1067
1068     /* TODO: TC exclusive handling due to ERL/EXL.  */
1069     other->CP0_VPEConf0 = newval;
1070 }
1071
1072 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1073 {
1074     uint32_t mask = 0;
1075     uint32_t newval;
1076
1077     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1078         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1079                 (0xff << CP0VPEC1_NCP1);
1080     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1081
1082     /* UDI not implemented. */
1083     /* CP2 not implemented. */
1084
1085     // TODO: Handle FPU (CP1) binding.
1086
1087     env->CP0_VPEConf1 = newval;
1088 }
1089
1090 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1091 {
1092     /* Yield qualifier inputs not implemented. */
1093     env->CP0_YQMask = 0x00000000;
1094 }
1095
1096 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1097 {
1098     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1099 }
1100
1101 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1102
1103 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1104 {
1105     /* 1k pages not implemented */
1106     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1107     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1108                         | (rxi << (CP0EnLo_XI - 30));
1109 }
1110
1111 #if defined(TARGET_MIPS64)
1112 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1113
1114 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1115 {
1116     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1117     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1118 }
1119 #endif
1120
1121 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1122 {
1123     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1124     uint32_t newval;
1125
1126     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1127
1128     env->active_tc.CP0_TCStatus = newval;
1129     sync_c0_tcstatus(env, env->current_tc, newval);
1130 }
1131
1132 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1133 {
1134     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1135     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1136
1137     if (other_tc == other->current_tc)
1138         other->active_tc.CP0_TCStatus = arg1;
1139     else
1140         other->tcs[other_tc].CP0_TCStatus = arg1;
1141     sync_c0_tcstatus(other, other_tc, arg1);
1142 }
1143
1144 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1145 {
1146     uint32_t mask = (1 << CP0TCBd_TBE);
1147     uint32_t newval;
1148
1149     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1150         mask |= (1 << CP0TCBd_CurVPE);
1151     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1152     env->active_tc.CP0_TCBind = newval;
1153 }
1154
1155 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1156 {
1157     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1158     uint32_t mask = (1 << CP0TCBd_TBE);
1159     uint32_t newval;
1160     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1161
1162     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1163         mask |= (1 << CP0TCBd_CurVPE);
1164     if (other_tc == other->current_tc) {
1165         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1166         other->active_tc.CP0_TCBind = newval;
1167     } else {
1168         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1169         other->tcs[other_tc].CP0_TCBind = newval;
1170     }
1171 }
1172
1173 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1174 {
1175     env->active_tc.PC = arg1;
1176     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1177     env->lladdr = 0ULL;
1178     /* MIPS16 not implemented. */
1179 }
1180
1181 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1182 {
1183     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1184     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1185
1186     if (other_tc == other->current_tc) {
1187         other->active_tc.PC = arg1;
1188         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1189         other->lladdr = 0ULL;
1190         /* MIPS16 not implemented. */
1191     } else {
1192         other->tcs[other_tc].PC = arg1;
1193         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1194         other->lladdr = 0ULL;
1195         /* MIPS16 not implemented. */
1196     }
1197 }
1198
1199 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1200 {
1201     MIPSCPU *cpu = mips_env_get_cpu(env);
1202
1203     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1204
1205     // TODO: Halt TC / Restart (if allocated+active) TC.
1206     if (env->active_tc.CP0_TCHalt & 1) {
1207         mips_tc_sleep(cpu, env->current_tc);
1208     } else {
1209         mips_tc_wake(cpu, env->current_tc);
1210     }
1211 }
1212
1213 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1214 {
1215     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1216     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1217     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1218
1219     // TODO: Halt TC / Restart (if allocated+active) TC.
1220
1221     if (other_tc == other->current_tc)
1222         other->active_tc.CP0_TCHalt = arg1;
1223     else
1224         other->tcs[other_tc].CP0_TCHalt = arg1;
1225
1226     if (arg1 & 1) {
1227         mips_tc_sleep(other_cpu, other_tc);
1228     } else {
1229         mips_tc_wake(other_cpu, other_tc);
1230     }
1231 }
1232
1233 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1234 {
1235     env->active_tc.CP0_TCContext = arg1;
1236 }
1237
1238 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1239 {
1240     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1241     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1242
1243     if (other_tc == other->current_tc)
1244         other->active_tc.CP0_TCContext = arg1;
1245     else
1246         other->tcs[other_tc].CP0_TCContext = arg1;
1247 }
1248
1249 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1250 {
1251     env->active_tc.CP0_TCSchedule = arg1;
1252 }
1253
1254 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1255 {
1256     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1257     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1258
1259     if (other_tc == other->current_tc)
1260         other->active_tc.CP0_TCSchedule = arg1;
1261     else
1262         other->tcs[other_tc].CP0_TCSchedule = arg1;
1263 }
1264
1265 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1266 {
1267     env->active_tc.CP0_TCScheFBack = arg1;
1268 }
1269
1270 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1271 {
1272     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1273     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1274
1275     if (other_tc == other->current_tc)
1276         other->active_tc.CP0_TCScheFBack = arg1;
1277     else
1278         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1279 }
1280
1281 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1282 {
1283     /* 1k pages not implemented */
1284     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1285     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1286                         | (rxi << (CP0EnLo_XI - 30));
1287 }
1288
1289 #if defined(TARGET_MIPS64)
1290 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1291 {
1292     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1293     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1294 }
1295 #endif
1296
1297 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1298 {
1299     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1300 }
1301
1302 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1303 {
1304     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1305     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1306         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1307          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1308          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1309         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1310     }
1311 }
1312
1313 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1314 {
1315     /* SmartMIPS not implemented */
1316     /* 1k pages not implemented */
1317     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1318                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1319     compute_hflags(env);
1320     restore_pamask(env);
1321 }
1322
1323 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1324 {
1325     if (env->insn_flags & ISA_MIPS32R6) {
1326         if (arg1 < env->tlb->nb_tlb) {
1327             env->CP0_Wired = arg1;
1328         }
1329     } else {
1330         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1331     }
1332 }
1333
1334 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1335 {
1336     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1337 }
1338
1339 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1340 {
1341     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1342 }
1343
1344 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1345 {
1346     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1347 }
1348
1349 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1350 {
1351     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1352 }
1353
1354 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1355 {
1356     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1357 }
1358
1359 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1360 {
1361     uint32_t mask = 0x0000000F;
1362
1363     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1364         mask |= (1 << 29);
1365
1366         if (arg1 & (1 << 29)) {
1367             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1368         } else {
1369             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1370         }
1371     }
1372
1373     env->CP0_HWREna = arg1 & mask;
1374 }
1375
1376 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1377 {
1378     cpu_mips_store_count(env, arg1);
1379 }
1380
1381 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1382 {
1383     target_ulong old, val, mask;
1384     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1385     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1386         mask |= 1 << CP0EnHi_EHINV;
1387     }
1388
1389     /* 1k pages not implemented */
1390 #if defined(TARGET_MIPS64)
1391     if (env->insn_flags & ISA_MIPS32R6) {
1392         int entryhi_r = extract64(arg1, 62, 2);
1393         int config0_at = extract32(env->CP0_Config0, 13, 2);
1394         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1395         if ((entryhi_r == 2) ||
1396             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1397             /* skip EntryHi.R field if new value is reserved */
1398             mask &= ~(0x3ull << 62);
1399         }
1400     }
1401     mask &= env->SEGMask;
1402 #endif
1403     old = env->CP0_EntryHi;
1404     val = (arg1 & mask) | (old & ~mask);
1405     env->CP0_EntryHi = val;
1406     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1407         sync_c0_entryhi(env, env->current_tc);
1408     }
1409     /* If the ASID changes, flush qemu's TLB.  */
1410     if ((old & 0xFF) != (val & 0xFF))
1411         cpu_mips_tlb_flush(env, 1);
1412 }
1413
1414 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1415 {
1416     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1417     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1418
1419     other->CP0_EntryHi = arg1;
1420     sync_c0_entryhi(other, other_tc);
1421 }
1422
1423 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1424 {
1425     cpu_mips_store_compare(env, arg1);
1426 }
1427
1428 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1429 {
1430     MIPSCPU *cpu = mips_env_get_cpu(env);
1431     uint32_t val, old;
1432
1433     old = env->CP0_Status;
1434     cpu_mips_store_status(env, arg1);
1435     val = env->CP0_Status;
1436
1437     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1438         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1439                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1440                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1441                 env->CP0_Cause);
1442         switch (env->hflags & MIPS_HFLAG_KSU) {
1443         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1444         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1445         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1446         default:
1447             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1448             break;
1449         }
1450     }
1451 }
1452
1453 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1454 {
1455     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1456     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1457     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1458
1459     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1460     sync_c0_status(env, other, other_tc);
1461 }
1462
1463 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1464 {
1465     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1466 }
1467
1468 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1469 {
1470     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1471     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1472 }
1473
1474 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1475 {
1476     cpu_mips_store_cause(env, arg1);
1477 }
1478
1479 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1480 {
1481     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1482     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1483
1484     cpu_mips_store_cause(other, arg1);
1485 }
1486
1487 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1488 {
1489     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1490     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1491
1492     return other->CP0_EPC;
1493 }
1494
1495 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1496 {
1497     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1498     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1499
1500     return other->CP0_EBase;
1501 }
1502
1503 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1504 {
1505     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1506 }
1507
1508 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1509 {
1510     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1511     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1512     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1513 }
1514
1515 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1516 {
1517     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1518     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1519
1520     switch (idx) {
1521     case 0: return other->CP0_Config0;
1522     case 1: return other->CP0_Config1;
1523     case 2: return other->CP0_Config2;
1524     case 3: return other->CP0_Config3;
1525     /* 4 and 5 are reserved.  */
1526     case 6: return other->CP0_Config6;
1527     case 7: return other->CP0_Config7;
1528     default:
1529         break;
1530     }
1531     return 0;
1532 }
1533
1534 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1535 {
1536     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1537 }
1538
1539 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1540 {
1541     /* tertiary/secondary caches not implemented */
1542     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1543 }
1544
1545 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1546 {
1547     if (env->insn_flags & ASE_MICROMIPS) {
1548         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1549                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1550     }
1551 }
1552
1553 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1554 {
1555     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1556                        (arg1 & env->CP0_Config4_rw_bitmask);
1557 }
1558
1559 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1560 {
1561     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1562                        (arg1 & env->CP0_Config5_rw_bitmask);
1563     compute_hflags(env);
1564 }
1565
1566 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1567 {
1568     target_long mask = env->CP0_LLAddr_rw_bitmask;
1569     arg1 = arg1 << env->CP0_LLAddr_shift;
1570     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1571 }
1572
1573 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1574 {
1575     /* Watch exceptions for instructions, data loads, data stores
1576        not implemented. */
1577     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1578 }
1579
1580 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1581 {
1582     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1583     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1584 }
1585
1586 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1587 {
1588     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1589     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1590 }
1591
1592 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1593 {
1594     env->CP0_Framemask = arg1; /* XXX */
1595 }
1596
1597 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1598 {
1599     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1600     if (arg1 & (1 << CP0DB_DM))
1601         env->hflags |= MIPS_HFLAG_DM;
1602     else
1603         env->hflags &= ~MIPS_HFLAG_DM;
1604 }
1605
1606 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1607 {
1608     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1609     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1610     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1611
1612     /* XXX: Might be wrong, check with EJTAG spec. */
1613     if (other_tc == other->current_tc)
1614         other->active_tc.CP0_Debug_tcstatus = val;
1615     else
1616         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1617     other->CP0_Debug = (other->CP0_Debug &
1618                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1619                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1620 }
1621
1622 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1623 {
1624     env->CP0_Performance0 = arg1 & 0x000007ff;
1625 }
1626
1627 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1628 {
1629     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1630 }
1631
1632 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1633 {
1634     env->CP0_DataLo = arg1; /* XXX */
1635 }
1636
1637 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1638 {
1639     env->CP0_TagHi = arg1; /* XXX */
1640 }
1641
1642 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1643 {
1644     env->CP0_DataHi = arg1; /* XXX */
1645 }
1646
1647 /* MIPS MT functions */
1648 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1649 {
1650     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1651     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1652
1653     if (other_tc == other->current_tc)
1654         return other->active_tc.gpr[sel];
1655     else
1656         return other->tcs[other_tc].gpr[sel];
1657 }
1658
1659 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1660 {
1661     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1662     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1663
1664     if (other_tc == other->current_tc)
1665         return other->active_tc.LO[sel];
1666     else
1667         return other->tcs[other_tc].LO[sel];
1668 }
1669
1670 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1671 {
1672     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1673     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1674
1675     if (other_tc == other->current_tc)
1676         return other->active_tc.HI[sel];
1677     else
1678         return other->tcs[other_tc].HI[sel];
1679 }
1680
1681 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1682 {
1683     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1684     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1685
1686     if (other_tc == other->current_tc)
1687         return other->active_tc.ACX[sel];
1688     else
1689         return other->tcs[other_tc].ACX[sel];
1690 }
1691
1692 target_ulong helper_mftdsp(CPUMIPSState *env)
1693 {
1694     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1695     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1696
1697     if (other_tc == other->current_tc)
1698         return other->active_tc.DSPControl;
1699     else
1700         return other->tcs[other_tc].DSPControl;
1701 }
1702
1703 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1704 {
1705     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1706     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1707
1708     if (other_tc == other->current_tc)
1709         other->active_tc.gpr[sel] = arg1;
1710     else
1711         other->tcs[other_tc].gpr[sel] = arg1;
1712 }
1713
1714 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1715 {
1716     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1717     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1718
1719     if (other_tc == other->current_tc)
1720         other->active_tc.LO[sel] = arg1;
1721     else
1722         other->tcs[other_tc].LO[sel] = arg1;
1723 }
1724
1725 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1726 {
1727     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1728     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1729
1730     if (other_tc == other->current_tc)
1731         other->active_tc.HI[sel] = arg1;
1732     else
1733         other->tcs[other_tc].HI[sel] = arg1;
1734 }
1735
1736 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1737 {
1738     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1739     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1740
1741     if (other_tc == other->current_tc)
1742         other->active_tc.ACX[sel] = arg1;
1743     else
1744         other->tcs[other_tc].ACX[sel] = arg1;
1745 }
1746
1747 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1748 {
1749     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1750     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1751
1752     if (other_tc == other->current_tc)
1753         other->active_tc.DSPControl = arg1;
1754     else
1755         other->tcs[other_tc].DSPControl = arg1;
1756 }
1757
1758 /* MIPS MT functions */
1759 target_ulong helper_dmt(void)
1760 {
1761     // TODO
1762      return 0;
1763 }
1764
1765 target_ulong helper_emt(void)
1766 {
1767     // TODO
1768     return 0;
1769 }
1770
1771 target_ulong helper_dvpe(CPUMIPSState *env)
1772 {
1773     CPUState *other_cs = first_cpu;
1774     target_ulong prev = env->mvp->CP0_MVPControl;
1775
1776     CPU_FOREACH(other_cs) {
1777         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1778         /* Turn off all VPEs except the one executing the dvpe.  */
1779         if (&other_cpu->env != env) {
1780             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1781             mips_vpe_sleep(other_cpu);
1782         }
1783     }
1784     return prev;
1785 }
1786
1787 target_ulong helper_evpe(CPUMIPSState *env)
1788 {
1789     CPUState *other_cs = first_cpu;
1790     target_ulong prev = env->mvp->CP0_MVPControl;
1791
1792     CPU_FOREACH(other_cs) {
1793         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1794
1795         if (&other_cpu->env != env
1796             /* If the VPE is WFI, don't disturb its sleep.  */
1797             && !mips_vpe_is_wfi(other_cpu)) {
1798             /* Enable the VPE.  */
1799             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1800             mips_vpe_wake(other_cpu); /* And wake it up.  */
1801         }
1802     }
1803     return prev;
1804 }
1805 #endif /* !CONFIG_USER_ONLY */
1806
1807 void helper_fork(target_ulong arg1, target_ulong arg2)
1808 {
1809     fprintf(stderr, "%s:%u - %s\n", __FILE__, __LINE__, __func__);
1810     // arg1 = rt, arg2 = rs
1811     // TODO: store to TC register, assert to detect test cases.
1812     g_assert_not_reached();
1813 }
1814
1815 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1816 {
1817     target_long arg1 = arg;
1818
1819     if (arg1 < 0) {
1820         /* No scheduling policy implemented. */
1821         if (arg1 != -2) {
1822             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1823                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1824                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1825                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1826                 do_raise_exception(env, EXCP_THREAD, GETPC());
1827             }
1828         }
1829     } else if (arg1 == 0) {
1830         if (0 /* TODO: TC underflow */) {
1831             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1832             do_raise_exception(env, EXCP_THREAD, GETPC());
1833         } else {
1834             // TODO: Deallocate TC
1835         }
1836     } else if (arg1 > 0) {
1837         /* Yield qualifier inputs not implemented. */
1838         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1839         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1840         do_raise_exception(env, EXCP_THREAD, GETPC());
1841     }
1842     return env->CP0_YQMask;
1843 }
1844
1845 #ifndef CONFIG_USER_ONLY
1846 /* TLB management */
1847 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1848 {
1849     MIPSCPU *cpu = mips_env_get_cpu(env);
1850
1851     /* Flush qemu's TLB and discard all shadowed entries.  */
1852     tlb_flush(CPU(cpu), flush_global);
1853     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1854 }
1855
1856 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1857 {
1858     /* Discard entries from env->tlb[first] onwards.  */
1859     while (env->tlb->tlb_in_use > first) {
1860         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1861     }
1862 }
1863
1864 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1865 {
1866 #if defined(TARGET_MIPS64)
1867     return extract64(entrylo, 6, 54);
1868 #else
1869     return extract64(entrylo, 6, 24) | /* PFN */
1870            (extract64(entrylo, 32, 32) << 24); /* PFNX */
1871 #endif
1872 }
1873
1874 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1875 {
1876     r4k_tlb_t *tlb;
1877
1878     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1879     tlb = &env->tlb->mmu.r4k.tlb[idx];
1880     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1881         tlb->EHINV = 1;
1882         return;
1883     }
1884     tlb->EHINV = 0;
1885     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1886 #if defined(TARGET_MIPS64)
1887     tlb->VPN &= env->SEGMask;
1888 #endif
1889     tlb->ASID = env->CP0_EntryHi & 0xFF;
1890     tlb->PageMask = env->CP0_PageMask;
1891     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1892     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1893     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1894     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1895     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1896     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1897     tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
1898     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1899     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1900     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1901     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1902     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1903     tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
1904 }
1905
1906 void r4k_helper_tlbinv(CPUMIPSState *env)
1907 {
1908     int idx;
1909     r4k_tlb_t *tlb;
1910     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1911
1912     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1913         tlb = &env->tlb->mmu.r4k.tlb[idx];
1914         if (!tlb->G && tlb->ASID == ASID) {
1915             tlb->EHINV = 1;
1916         }
1917     }
1918     cpu_mips_tlb_flush(env, 1);
1919 }
1920
1921 void r4k_helper_tlbinvf(CPUMIPSState *env)
1922 {
1923     int idx;
1924
1925     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1926         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1927     }
1928     cpu_mips_tlb_flush(env, 1);
1929 }
1930
1931 void r4k_helper_tlbwi(CPUMIPSState *env)
1932 {
1933     r4k_tlb_t *tlb;
1934     int idx;
1935     target_ulong VPN;
1936     uint8_t ASID;
1937     bool G, V0, D0, V1, D1;
1938
1939     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1940     tlb = &env->tlb->mmu.r4k.tlb[idx];
1941     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1942 #if defined(TARGET_MIPS64)
1943     VPN &= env->SEGMask;
1944 #endif
1945     ASID = env->CP0_EntryHi & 0xff;
1946     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1947     V0 = (env->CP0_EntryLo0 & 2) != 0;
1948     D0 = (env->CP0_EntryLo0 & 4) != 0;
1949     V1 = (env->CP0_EntryLo1 & 2) != 0;
1950     D1 = (env->CP0_EntryLo1 & 4) != 0;
1951
1952     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1953        permissions on the current entry. */
1954     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1955         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1956         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1957         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1958     }
1959
1960     r4k_invalidate_tlb(env, idx, 0);
1961     r4k_fill_tlb(env, idx);
1962 }
1963
1964 void r4k_helper_tlbwr(CPUMIPSState *env)
1965 {
1966     int r = cpu_mips_get_random(env);
1967
1968     r4k_invalidate_tlb(env, r, 1);
1969     r4k_fill_tlb(env, r);
1970 }
1971
1972 void r4k_helper_tlbp(CPUMIPSState *env)
1973 {
1974     r4k_tlb_t *tlb;
1975     target_ulong mask;
1976     target_ulong tag;
1977     target_ulong VPN;
1978     uint8_t ASID;
1979     int i;
1980
1981     ASID = env->CP0_EntryHi & 0xFF;
1982     for (i = 0; i < env->tlb->nb_tlb; i++) {
1983         tlb = &env->tlb->mmu.r4k.tlb[i];
1984         /* 1k pages are not supported. */
1985         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1986         tag = env->CP0_EntryHi & ~mask;
1987         VPN = tlb->VPN & ~mask;
1988 #if defined(TARGET_MIPS64)
1989         tag &= env->SEGMask;
1990 #endif
1991         /* Check ASID, virtual page number & size */
1992         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1993             /* TLB match */
1994             env->CP0_Index = i;
1995             break;
1996         }
1997     }
1998     if (i == env->tlb->nb_tlb) {
1999         /* No match.  Discard any shadow entries, if any of them match.  */
2000         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2001             tlb = &env->tlb->mmu.r4k.tlb[i];
2002             /* 1k pages are not supported. */
2003             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2004             tag = env->CP0_EntryHi & ~mask;
2005             VPN = tlb->VPN & ~mask;
2006 #if defined(TARGET_MIPS64)
2007             tag &= env->SEGMask;
2008 #endif
2009             /* Check ASID, virtual page number & size */
2010             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2011                 r4k_mips_tlb_flush_extra (env, i);
2012                 break;
2013             }
2014         }
2015
2016         env->CP0_Index |= 0x80000000;
2017     }
2018 }
2019
2020 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2021 {
2022 #if defined(TARGET_MIPS64)
2023     return tlb_pfn << 6;
2024 #else
2025     return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2026            (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2027 #endif
2028 }
2029
2030 void r4k_helper_tlbr(CPUMIPSState *env)
2031 {
2032     r4k_tlb_t *tlb;
2033     uint8_t ASID;
2034     int idx;
2035
2036     ASID = env->CP0_EntryHi & 0xFF;
2037     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2038     tlb = &env->tlb->mmu.r4k.tlb[idx];
2039
2040     /* If this will change the current ASID, flush qemu's TLB.  */
2041     if (ASID != tlb->ASID)
2042         cpu_mips_tlb_flush (env, 1);
2043
2044     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2045
2046     if (tlb->EHINV) {
2047         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2048         env->CP0_PageMask = 0;
2049         env->CP0_EntryLo0 = 0;
2050         env->CP0_EntryLo1 = 0;
2051     } else {
2052         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2053         env->CP0_PageMask = tlb->PageMask;
2054         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2055                         ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2056                         ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2057                         get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2058         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2059                         ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2060                         ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2061                         get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2062     }
2063 }
2064
2065 void helper_tlbwi(CPUMIPSState *env)
2066 {
2067     env->tlb->helper_tlbwi(env);
2068 }
2069
2070 void helper_tlbwr(CPUMIPSState *env)
2071 {
2072     env->tlb->helper_tlbwr(env);
2073 }
2074
2075 void helper_tlbp(CPUMIPSState *env)
2076 {
2077     env->tlb->helper_tlbp(env);
2078 }
2079
2080 void helper_tlbr(CPUMIPSState *env)
2081 {
2082     env->tlb->helper_tlbr(env);
2083 }
2084
2085 void helper_tlbinv(CPUMIPSState *env)
2086 {
2087     env->tlb->helper_tlbinv(env);
2088 }
2089
2090 void helper_tlbinvf(CPUMIPSState *env)
2091 {
2092     env->tlb->helper_tlbinvf(env);
2093 }
2094
2095 /* Specials */
2096 target_ulong helper_di(CPUMIPSState *env)
2097 {
2098     target_ulong t0 = env->CP0_Status;
2099
2100     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2101     return t0;
2102 }
2103
2104 target_ulong helper_ei(CPUMIPSState *env)
2105 {
2106     target_ulong t0 = env->CP0_Status;
2107
2108     env->CP0_Status = t0 | (1 << CP0St_IE);
2109     return t0;
2110 }
2111
2112 static void debug_pre_eret(CPUMIPSState *env)
2113 {
2114     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2115         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2116                 env->active_tc.PC, env->CP0_EPC);
2117         if (env->CP0_Status & (1 << CP0St_ERL))
2118             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2119         if (env->hflags & MIPS_HFLAG_DM)
2120             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2121         qemu_log("\n");
2122     }
2123 }
2124
2125 static void debug_post_eret(CPUMIPSState *env)
2126 {
2127     MIPSCPU *cpu = mips_env_get_cpu(env);
2128
2129     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2130         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2131                 env->active_tc.PC, env->CP0_EPC);
2132         if (env->CP0_Status & (1 << CP0St_ERL))
2133             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2134         if (env->hflags & MIPS_HFLAG_DM)
2135             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2136         switch (env->hflags & MIPS_HFLAG_KSU) {
2137         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2138         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2139         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2140         default:
2141             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2142             break;
2143         }
2144     }
2145 }
2146
2147 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2148 {
2149     env->active_tc.PC = error_pc & ~(target_ulong)1;
2150     if (error_pc & 1) {
2151         env->hflags |= MIPS_HFLAG_M16;
2152     } else {
2153         env->hflags &= ~(MIPS_HFLAG_M16);
2154     }
2155 }
2156
2157 static inline void exception_return(CPUMIPSState *env)
2158 {
2159     debug_pre_eret(env);
2160     if (env->CP0_Status & (1 << CP0St_ERL)) {
2161         set_pc(env, env->CP0_ErrorEPC);
2162         env->CP0_Status &= ~(1 << CP0St_ERL);
2163     } else {
2164         set_pc(env, env->CP0_EPC);
2165         env->CP0_Status &= ~(1 << CP0St_EXL);
2166     }
2167     compute_hflags(env);
2168     debug_post_eret(env);
2169 }
2170
2171 void helper_eret(CPUMIPSState *env)
2172 {
2173     exception_return(env);
2174     env->lladdr = 1;
2175 }
2176
2177 void helper_eretnc(CPUMIPSState *env)
2178 {
2179     exception_return(env);
2180 }
2181
2182 void helper_deret(CPUMIPSState *env)
2183 {
2184     debug_pre_eret(env);
2185     set_pc(env, env->CP0_DEPC);
2186
2187     env->hflags &= ~MIPS_HFLAG_DM;
2188     compute_hflags(env);
2189     debug_post_eret(env);
2190 }
2191 #endif /* !CONFIG_USER_ONLY */
2192
2193 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2194 {
2195     if ((env->hflags & MIPS_HFLAG_CP0) ||
2196         (env->CP0_HWREna & (1 << 0)))
2197         return env->CP0_EBase & 0x3ff;
2198     else
2199         do_raise_exception(env, EXCP_RI, GETPC());
2200
2201     return 0;
2202 }
2203
2204 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2205 {
2206     if ((env->hflags & MIPS_HFLAG_CP0) ||
2207         (env->CP0_HWREna & (1 << 1)))
2208         return env->SYNCI_Step;
2209     else
2210         do_raise_exception(env, EXCP_RI, GETPC());
2211
2212     return 0;
2213 }
2214
2215 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2216 {
2217     if ((env->hflags & MIPS_HFLAG_CP0) ||
2218         (env->CP0_HWREna & (1 << 2))) {
2219 #ifdef CONFIG_USER_ONLY
2220         return env->CP0_Count;
2221 #else
2222         return (int32_t)cpu_mips_get_count(env);
2223 #endif
2224     } else {
2225         do_raise_exception(env, EXCP_RI, GETPC());
2226     }
2227
2228     return 0;
2229 }
2230
2231 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2232 {
2233     if ((env->hflags & MIPS_HFLAG_CP0) ||
2234         (env->CP0_HWREna & (1 << 3)))
2235         return env->CCRes;
2236     else
2237         do_raise_exception(env, EXCP_RI, GETPC());
2238
2239     return 0;
2240 }
2241
2242 void helper_pmon(CPUMIPSState *env, int function)
2243 {
2244     function /= 2;
2245     switch (function) {
2246     case 2: /* TODO: char inbyte(int waitflag); */
2247         if (env->active_tc.gpr[4] == 0)
2248             env->active_tc.gpr[2] = -1;
2249         /* Fall through */
2250     case 11: /* TODO: char inbyte (void); */
2251         env->active_tc.gpr[2] = -1;
2252         break;
2253     case 3:
2254     case 12:
2255         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2256         break;
2257     case 17:
2258         break;
2259 #ifndef CONFIG_USER_ONLY
2260     case 158:
2261         {
2262             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2263             printf("%s", fmt);
2264         }
2265         break;
2266 #endif
2267     }
2268 }
2269
2270 void QEMU_NORETURN helper_wait(CPUMIPSState *env)
2271 {
2272     CPUState *cs = CPU(mips_env_get_cpu(env));
2273
2274     cs->halted = 1;
2275     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2276     /* Last instruction in the block, PC was updated before
2277        - no need to recover PC and icount */
2278     raise_exception(env, EXCP_HLT);
2279 }
2280
2281 #if !defined(CONFIG_USER_ONLY)
2282
2283 void QEMU_NORETURN mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2284                                   int access_type, int is_user,
2285                                   uintptr_t retaddr)
2286 {
2287     MIPSCPU *cpu = MIPS_CPU(cs);
2288     CPUMIPSState *env = &cpu->env;
2289     int error_code = 0;
2290     int excp;
2291
2292     env->CP0_BadVAddr = addr;
2293
2294     if (access_type == MMU_DATA_STORE) {
2295         excp = EXCP_AdES;
2296     } else {
2297         excp = EXCP_AdEL;
2298         if (access_type == MMU_INST_FETCH) {
2299             error_code |= EXCP_INST_NOTAVAIL;
2300         }
2301     }
2302
2303     do_raise_exception_err(env, excp, error_code, retaddr);
2304 }
2305
2306 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2307               uintptr_t retaddr)
2308 {
2309     int ret;
2310
2311     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2312     if (ret) {
2313         MIPSCPU *cpu = MIPS_CPU(cs);
2314         CPUMIPSState *env = &cpu->env;
2315
2316         do_raise_exception_err(env, cs->exception_index,
2317                                env->error_code, retaddr);
2318     }
2319 }
2320
2321 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2322                                 bool is_write, bool is_exec, int unused,
2323                                 unsigned size)
2324 {
2325     MIPSCPU *cpu = MIPS_CPU(cs);
2326     CPUMIPSState *env = &cpu->env;
2327
2328     /*
2329      * Raising an exception with KVM enabled will crash because it won't be from
2330      * the main execution loop so the longjmp won't have a matching setjmp.
2331      * Until we can trigger a bus error exception through KVM lets just ignore
2332      * the access.
2333      */
2334     if (kvm_enabled()) {
2335         /* TODO: here a return was replaced by an assertion. */
2336         g_assert_not_reached();
2337     }
2338
2339     if (is_exec) {
2340         raise_exception(env, EXCP_IBE);
2341     } else {
2342         raise_exception(env, EXCP_DBE);
2343     }
2344 }
2345 #endif /* !CONFIG_USER_ONLY */
2346
2347 /* Complex FPU operations which may need stack space. */
2348
2349 #define FLOAT_TWO32 make_float32(1 << 30)
2350 #define FLOAT_TWO64 make_float64(1ULL << 62)
2351 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2352 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2353
2354 /* convert MIPS rounding mode in FCR31 to IEEE library */
2355 unsigned int ieee_rm[] = {
2356     float_round_nearest_even,
2357     float_round_to_zero,
2358     float_round_up,
2359     float_round_down
2360 };
2361
2362 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2363 {
2364     target_ulong arg1 = 0;
2365
2366     switch (reg) {
2367     case 0:
2368         arg1 = (int32_t)env->active_fpu.fcr0;
2369         break;
2370     case 1:
2371         /* UFR Support - Read Status FR */
2372         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2373             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2374                 arg1 = (int32_t)
2375                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2376             } else {
2377                 do_raise_exception(env, EXCP_RI, GETPC());
2378             }
2379         }
2380         break;
2381     case 5:
2382         /* FRE Support - read Config5.FRE bit */
2383         if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2384             if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2385                 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2386             } else {
2387                 helper_raise_exception(env, EXCP_RI);
2388             }
2389         }
2390         break;
2391     case 25:
2392         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2393         break;
2394     case 26:
2395         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2396         break;
2397     case 28:
2398         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2399         break;
2400     default:
2401         arg1 = (int32_t)env->active_fpu.fcr31;
2402         break;
2403     }
2404
2405     return arg1;
2406 }
2407
2408 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2409 {
2410     switch (fs) {
2411     case 1:
2412         /* UFR Alias - Reset Status FR */
2413         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2414             return;
2415         }
2416         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2417             env->CP0_Status &= ~(1 << CP0St_FR);
2418             compute_hflags(env);
2419         } else {
2420             do_raise_exception(env, EXCP_RI, GETPC());
2421         }
2422         break;
2423     case 4:
2424         /* UNFR Alias - Set Status FR */
2425         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2426             return;
2427         }
2428         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2429             env->CP0_Status |= (1 << CP0St_FR);
2430             compute_hflags(env);
2431         } else {
2432             do_raise_exception(env, EXCP_RI, GETPC());
2433         }
2434         break;
2435     case 5:
2436         /* FRE Support - clear Config5.FRE bit */
2437         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2438             return;
2439         }
2440         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2441             env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2442             compute_hflags(env);
2443         } else {
2444             helper_raise_exception(env, EXCP_RI);
2445         }
2446         break;
2447     case 6:
2448         /* FRE Support - set Config5.FRE bit */
2449         if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2450             return;
2451         }
2452         if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2453             env->CP0_Config5 |= (1 << CP0C5_FRE);
2454             compute_hflags(env);
2455         } else {
2456             helper_raise_exception(env, EXCP_RI);
2457         }
2458         break;
2459     case 25:
2460         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2461             return;
2462         }
2463         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2464                      ((arg1 & 0x1) << 23);
2465         break;
2466     case 26:
2467         if (arg1 & 0x007c0000)
2468             return;
2469         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2470         break;
2471     case 28:
2472         if (arg1 & 0x007c0000)
2473             return;
2474         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2475                      ((arg1 & 0x4) << 22);
2476         break;
2477     case 31:
2478         if (env->insn_flags & ISA_MIPS32R6) {
2479             uint32_t mask = 0xfefc0000;
2480             env->active_fpu.fcr31 = (arg1 & ~mask) |
2481                 (env->active_fpu.fcr31 & mask);
2482         } else if (!(arg1 & 0x007c0000)) {
2483             env->active_fpu.fcr31 = arg1;
2484         }
2485         break;
2486     default:
2487         return;
2488     }
2489     /* set rounding mode */
2490     restore_rounding_mode(env);
2491     /* set flush-to-zero mode */
2492     restore_flush_mode(env);
2493     set_float_exception_flags(0, &env->active_fpu.fp_status);
2494     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) {
2495         do_raise_exception(env, EXCP_FPE, GETPC());
2496     }
2497 }
2498
2499 int ieee_ex_to_mips(int xcpt)
2500 {
2501     int ret = 0;
2502     if (xcpt) {
2503         if (xcpt & float_flag_invalid) {
2504             ret |= FP_INVALID;
2505         }
2506         if (xcpt & float_flag_overflow) {
2507             ret |= FP_OVERFLOW;
2508         }
2509         if (xcpt & float_flag_underflow) {
2510             ret |= FP_UNDERFLOW;
2511         }
2512         if (xcpt & float_flag_divbyzero) {
2513             ret |= FP_DIV0;
2514         }
2515         if (xcpt & float_flag_inexact) {
2516             ret |= FP_INEXACT;
2517         }
2518     }
2519     return ret;
2520 }
2521
2522 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2523 {
2524     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2525
2526     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2527
2528     if (tmp) {
2529         set_float_exception_flags(0, &env->active_fpu.fp_status);
2530
2531         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2532             do_raise_exception(env, EXCP_FPE, pc);
2533         } else {
2534             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2535         }
2536     }
2537 }
2538
2539 /* Float support.
2540    Single precition routines have a "s" suffix, double precision a
2541    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2542    paired single lower "pl", paired single upper "pu".  */
2543
2544 /* unary operations, modifying fp status  */
2545 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2546 {
2547     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2548     update_fcr31(env, GETPC());
2549     return fdt0;
2550 }
2551
2552 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2553 {
2554     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2555     update_fcr31(env, GETPC());
2556     return fst0;
2557 }
2558
2559 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2560 {
2561     uint64_t fdt2;
2562
2563     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2564     update_fcr31(env, GETPC());
2565     return fdt2;
2566 }
2567
2568 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2569 {
2570     uint64_t fdt2;
2571
2572     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2573     update_fcr31(env, GETPC());
2574     return fdt2;
2575 }
2576
2577 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2578 {
2579     uint64_t fdt2;
2580
2581     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2582     update_fcr31(env, GETPC());
2583     return fdt2;
2584 }
2585
2586 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2587 {
2588     uint64_t dt2;
2589
2590     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2591     if (get_float_exception_flags(&env->active_fpu.fp_status)
2592         & (float_flag_invalid | float_flag_overflow)) {
2593         dt2 = FP_TO_INT64_OVERFLOW;
2594     }
2595     update_fcr31(env, GETPC());
2596     return dt2;
2597 }
2598
2599 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2600 {
2601     uint64_t dt2;
2602
2603     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2604     if (get_float_exception_flags(&env->active_fpu.fp_status)
2605         & (float_flag_invalid | float_flag_overflow)) {
2606         dt2 = FP_TO_INT64_OVERFLOW;
2607     }
2608     update_fcr31(env, GETPC());
2609     return dt2;
2610 }
2611
2612 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2613 {
2614     uint32_t fst2;
2615     uint32_t fsth2;
2616
2617     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2618     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2619     update_fcr31(env, GETPC());
2620     return ((uint64_t)fsth2 << 32) | fst2;
2621 }
2622
2623 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2624 {
2625     uint32_t wt2;
2626     uint32_t wth2;
2627     int excp, excph;
2628
2629     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2630     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2631     if (excp & (float_flag_overflow | float_flag_invalid)) {
2632         wt2 = FP_TO_INT32_OVERFLOW;
2633     }
2634
2635     set_float_exception_flags(0, &env->active_fpu.fp_status);
2636     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2637     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2638     if (excph & (float_flag_overflow | float_flag_invalid)) {
2639         wth2 = FP_TO_INT32_OVERFLOW;
2640     }
2641
2642     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2643     update_fcr31(env, GETPC());
2644
2645     return ((uint64_t)wth2 << 32) | wt2;
2646 }
2647
2648 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2649 {
2650     uint32_t fst2;
2651
2652     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2653     update_fcr31(env, GETPC());
2654     return fst2;
2655 }
2656
2657 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2658 {
2659     uint32_t fst2;
2660
2661     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2662     update_fcr31(env, GETPC());
2663     return fst2;
2664 }
2665
2666 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2667 {
2668     uint32_t fst2;
2669
2670     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2671     update_fcr31(env, GETPC());
2672     return fst2;
2673 }
2674
2675 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2676 {
2677     uint32_t wt2;
2678
2679     wt2 = wt0;
2680     update_fcr31(env, GETPC());
2681     return wt2;
2682 }
2683
2684 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2685 {
2686     uint32_t wt2;
2687
2688     wt2 = wth0;
2689     update_fcr31(env, GETPC());
2690     return wt2;
2691 }
2692
2693 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2694 {
2695     uint32_t wt2;
2696
2697     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2698     if (get_float_exception_flags(&env->active_fpu.fp_status)
2699         & (float_flag_invalid | float_flag_overflow)) {
2700         wt2 = FP_TO_INT32_OVERFLOW;
2701     }
2702     update_fcr31(env, GETPC());
2703     return wt2;
2704 }
2705
2706 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2707 {
2708     uint32_t wt2;
2709
2710     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2711     if (get_float_exception_flags(&env->active_fpu.fp_status)
2712         & (float_flag_invalid | float_flag_overflow)) {
2713         wt2 = FP_TO_INT32_OVERFLOW;
2714     }
2715     update_fcr31(env, GETPC());
2716     return wt2;
2717 }
2718
2719 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2720 {
2721     uint64_t dt2;
2722
2723     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2724     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2725     restore_rounding_mode(env);
2726     if (get_float_exception_flags(&env->active_fpu.fp_status)
2727         & (float_flag_invalid | float_flag_overflow)) {
2728         dt2 = FP_TO_INT64_OVERFLOW;
2729     }
2730     update_fcr31(env, GETPC());
2731     return dt2;
2732 }
2733
2734 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2735 {
2736     uint64_t dt2;
2737
2738     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2739     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2740     restore_rounding_mode(env);
2741     if (get_float_exception_flags(&env->active_fpu.fp_status)
2742         & (float_flag_invalid | float_flag_overflow)) {
2743         dt2 = FP_TO_INT64_OVERFLOW;
2744     }
2745     update_fcr31(env, GETPC());
2746     return dt2;
2747 }
2748
2749 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2750 {
2751     uint32_t wt2;
2752
2753     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2754     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2755     restore_rounding_mode(env);
2756     if (get_float_exception_flags(&env->active_fpu.fp_status)
2757         & (float_flag_invalid | float_flag_overflow)) {
2758         wt2 = FP_TO_INT32_OVERFLOW;
2759     }
2760     update_fcr31(env, GETPC());
2761     return wt2;
2762 }
2763
2764 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2765 {
2766     uint32_t wt2;
2767
2768     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2769     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2770     restore_rounding_mode(env);
2771     if (get_float_exception_flags(&env->active_fpu.fp_status)
2772         & (float_flag_invalid | float_flag_overflow)) {
2773         wt2 = FP_TO_INT32_OVERFLOW;
2774     }
2775     update_fcr31(env, GETPC());
2776     return wt2;
2777 }
2778
2779 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2780 {
2781     uint64_t dt2;
2782
2783     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2784     if (get_float_exception_flags(&env->active_fpu.fp_status)
2785         & (float_flag_invalid | float_flag_overflow)) {
2786         dt2 = FP_TO_INT64_OVERFLOW;
2787     }
2788     update_fcr31(env, GETPC());
2789     return dt2;
2790 }
2791
2792 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2793 {
2794     uint64_t dt2;
2795
2796     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2797     if (get_float_exception_flags(&env->active_fpu.fp_status)
2798         & (float_flag_invalid | float_flag_overflow)) {
2799         dt2 = FP_TO_INT64_OVERFLOW;
2800     }
2801     update_fcr31(env, GETPC());
2802     return dt2;
2803 }
2804
2805 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2806 {
2807     uint32_t wt2;
2808
2809     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2810     if (get_float_exception_flags(&env->active_fpu.fp_status)
2811         & (float_flag_invalid | float_flag_overflow)) {
2812         wt2 = FP_TO_INT32_OVERFLOW;
2813     }
2814     update_fcr31(env, GETPC());
2815     return wt2;
2816 }
2817
2818 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2819 {
2820     uint32_t wt2;
2821
2822     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2823     if (get_float_exception_flags(&env->active_fpu.fp_status)
2824         & (float_flag_invalid | float_flag_overflow)) {
2825         wt2 = FP_TO_INT32_OVERFLOW;
2826     }
2827     update_fcr31(env, GETPC());
2828     return wt2;
2829 }
2830
2831 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2832 {
2833     uint64_t dt2;
2834
2835     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2836     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2837     restore_rounding_mode(env);
2838     if (get_float_exception_flags(&env->active_fpu.fp_status)
2839         & (float_flag_invalid | float_flag_overflow)) {
2840         dt2 = FP_TO_INT64_OVERFLOW;
2841     }
2842     update_fcr31(env, GETPC());
2843     return dt2;
2844 }
2845
2846 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2847 {
2848     uint64_t dt2;
2849
2850     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2851     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2852     restore_rounding_mode(env);
2853     if (get_float_exception_flags(&env->active_fpu.fp_status)
2854         & (float_flag_invalid | float_flag_overflow)) {
2855         dt2 = FP_TO_INT64_OVERFLOW;
2856     }
2857     update_fcr31(env, GETPC());
2858     return dt2;
2859 }
2860
2861 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2862 {
2863     uint32_t wt2;
2864
2865     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2866     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2867     restore_rounding_mode(env);
2868     if (get_float_exception_flags(&env->active_fpu.fp_status)
2869         & (float_flag_invalid | float_flag_overflow)) {
2870         wt2 = FP_TO_INT32_OVERFLOW;
2871     }
2872     update_fcr31(env, GETPC());
2873     return wt2;
2874 }
2875
2876 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2877 {
2878     uint32_t wt2;
2879
2880     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2881     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2882     restore_rounding_mode(env);
2883     if (get_float_exception_flags(&env->active_fpu.fp_status)
2884         & (float_flag_invalid | float_flag_overflow)) {
2885         wt2 = FP_TO_INT32_OVERFLOW;
2886     }
2887     update_fcr31(env, GETPC());
2888     return wt2;
2889 }
2890
2891 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2892 {
2893     uint64_t dt2;
2894
2895     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2896     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2897     restore_rounding_mode(env);
2898     if (get_float_exception_flags(&env->active_fpu.fp_status)
2899         & (float_flag_invalid | float_flag_overflow)) {
2900         dt2 = FP_TO_INT64_OVERFLOW;
2901     }
2902     update_fcr31(env, GETPC());
2903     return dt2;
2904 }
2905
2906 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2907 {
2908     uint64_t dt2;
2909
2910     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2911     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2912     restore_rounding_mode(env);
2913     if (get_float_exception_flags(&env->active_fpu.fp_status)
2914         & (float_flag_invalid | float_flag_overflow)) {
2915         dt2 = FP_TO_INT64_OVERFLOW;
2916     }
2917     update_fcr31(env, GETPC());
2918     return dt2;
2919 }
2920
2921 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2922 {
2923     uint32_t wt2;
2924
2925     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2926     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2927     restore_rounding_mode(env);
2928     if (get_float_exception_flags(&env->active_fpu.fp_status)
2929         & (float_flag_invalid | float_flag_overflow)) {
2930         wt2 = FP_TO_INT32_OVERFLOW;
2931     }
2932     update_fcr31(env, GETPC());
2933     return wt2;
2934 }
2935
2936 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2937 {
2938     uint32_t wt2;
2939
2940     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2941     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2942     restore_rounding_mode(env);
2943     if (get_float_exception_flags(&env->active_fpu.fp_status)
2944         & (float_flag_invalid | float_flag_overflow)) {
2945         wt2 = FP_TO_INT32_OVERFLOW;
2946     }
2947     update_fcr31(env, GETPC());
2948     return wt2;
2949 }
2950
2951 /* unary operations, not modifying fp status  */
2952 #define FLOAT_UNOP(name)                                       \
2953 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2954 {                                                              \
2955     return float64_ ## name(fdt0);                             \
2956 }                                                              \
2957 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2958 {                                                              \
2959     return float32_ ## name(fst0);                             \
2960 }                                                              \
2961 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2962 {                                                              \
2963     uint32_t wt0;                                              \
2964     uint32_t wth0;                                             \
2965                                                                \
2966     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2967     wth0 = float32_ ## name(fdt0 >> 32);                       \
2968     return ((uint64_t)wth0 << 32) | wt0;                       \
2969 }
2970 FLOAT_UNOP(abs)
2971 FLOAT_UNOP(chs)
2972 #undef FLOAT_UNOP
2973
2974 /* MIPS specific unary operations */
2975 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2976 {
2977     uint64_t fdt2;
2978
2979     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2980     update_fcr31(env, GETPC());
2981     return fdt2;
2982 }
2983
2984 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2985 {
2986     uint32_t fst2;
2987
2988     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2989     update_fcr31(env, GETPC());
2990     return fst2;
2991 }
2992
2993 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2994 {
2995     uint64_t fdt2;
2996
2997     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2998     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2999     update_fcr31(env, GETPC());
3000     return fdt2;
3001 }
3002
3003 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3004 {
3005     uint32_t fst2;
3006
3007     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3008     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3009     update_fcr31(env, GETPC());
3010     return fst2;
3011 }
3012
3013 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3014 {
3015     uint64_t fdt2;
3016
3017     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3018     update_fcr31(env, GETPC());
3019     return fdt2;
3020 }
3021
3022 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3023 {
3024     uint32_t fst2;
3025
3026     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3027     update_fcr31(env, GETPC());
3028     return fst2;
3029 }
3030
3031 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3032 {
3033     uint32_t fst2;
3034     uint32_t fsth2;
3035
3036     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3037     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3038     update_fcr31(env, GETPC());
3039     return ((uint64_t)fsth2 << 32) | fst2;
3040 }
3041
3042 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3043 {
3044     uint64_t fdt2;
3045
3046     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3047     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3048     update_fcr31(env, GETPC());
3049     return fdt2;
3050 }
3051
3052 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3053 {
3054     uint32_t fst2;
3055
3056     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3057     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3058     update_fcr31(env, GETPC());
3059     return fst2;
3060 }
3061
3062 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3063 {
3064     uint32_t fst2;
3065     uint32_t fsth2;
3066
3067     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3068     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3069     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3070     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3071     update_fcr31(env, GETPC());
3072     return ((uint64_t)fsth2 << 32) | fst2;
3073 }
3074
3075 #define FLOAT_RINT(name, bits)                                              \
3076 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
3077                                           uint ## bits ## _t fs)            \
3078 {                                                                           \
3079     uint ## bits ## _t fdret;                                               \
3080                                                                             \
3081     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3082     update_fcr31(env, GETPC());                                             \
3083     return fdret;                                                           \
3084 }
3085
3086 FLOAT_RINT(rint_s, 32)
3087 FLOAT_RINT(rint_d, 64)
3088 #undef FLOAT_RINT
3089
3090 #define FLOAT_CLASS_SIGNALING_NAN      0x001
3091 #define FLOAT_CLASS_QUIET_NAN          0x002
3092 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3093 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3094 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3095 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3096 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3097 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3098 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3099 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3100
3101 #define FLOAT_CLASS(name, bits)                                      \
3102 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3103 {                                                                    \
3104     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3105         return FLOAT_CLASS_SIGNALING_NAN;                            \
3106     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3107         return FLOAT_CLASS_QUIET_NAN;                                \
3108     } else if (float ## bits ## _is_neg(arg)) {                      \
3109         if (float ## bits ## _is_infinity(arg)) {                    \
3110             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3111         } else if (float ## bits ## _is_zero(arg)) {                 \
3112             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3113         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3114             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3115         } else {                                                     \
3116             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3117         }                                                            \
3118     } else {                                                         \
3119         if (float ## bits ## _is_infinity(arg)) {                    \
3120             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3121         } else if (float ## bits ## _is_zero(arg)) {                 \
3122             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3123         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3124             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3125         } else {                                                     \
3126             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3127         }                                                            \
3128     }                                                                \
3129 }
3130
3131 FLOAT_CLASS(class_s, 32)
3132 FLOAT_CLASS(class_d, 64)
3133 #undef FLOAT_CLASS
3134
3135 /* binary operations */
3136 #define FLOAT_BINOP(name)                                          \
3137 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3138                                      uint64_t fdt0, uint64_t fdt1) \
3139 {                                                                  \
3140     uint64_t dt2;                                                  \
3141                                                                    \
3142     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3143     update_fcr31(env, GETPC());                                    \
3144     return dt2;                                                    \
3145 }                                                                  \
3146                                                                    \
3147 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3148                                      uint32_t fst0, uint32_t fst1) \
3149 {                                                                  \
3150     uint32_t wt2;                                                  \
3151                                                                    \
3152     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3153     update_fcr31(env, GETPC());                                    \
3154     return wt2;                                                    \
3155 }                                                                  \
3156                                                                    \
3157 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3158                                       uint64_t fdt0,               \
3159                                       uint64_t fdt1)               \
3160 {                                                                  \
3161     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3162     uint32_t fsth0 = fdt0 >> 32;                                   \
3163     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3164     uint32_t fsth1 = fdt1 >> 32;                                   \
3165     uint32_t wt2;                                                  \
3166     uint32_t wth2;                                                 \
3167                                                                    \
3168     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3169     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3170     update_fcr31(env, GETPC());                                    \
3171     return ((uint64_t)wth2 << 32) | wt2;                           \
3172 }
3173
3174 FLOAT_BINOP(add)
3175 FLOAT_BINOP(sub)
3176 FLOAT_BINOP(mul)
3177 FLOAT_BINOP(div)
3178 #undef FLOAT_BINOP
3179
3180 /* MIPS specific binary operations */
3181 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3182 {
3183     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3184     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3185     update_fcr31(env, GETPC());
3186     return fdt2;
3187 }
3188
3189 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3190 {
3191     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3192     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3193     update_fcr31(env, GETPC());
3194     return fst2;
3195 }
3196
3197 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3198 {
3199     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3200     uint32_t fsth0 = fdt0 >> 32;
3201     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3202     uint32_t fsth2 = fdt2 >> 32;
3203
3204     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3205     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3206     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3207     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3208     update_fcr31(env, GETPC());
3209     return ((uint64_t)fsth2 << 32) | fst2;
3210 }
3211
3212 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3213 {
3214     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3215     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3216     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3217     update_fcr31(env, GETPC());
3218     return fdt2;
3219 }
3220
3221 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3222 {
3223     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3224     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3225     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3226     update_fcr31(env, GETPC());
3227     return fst2;
3228 }
3229
3230 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3231 {
3232     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3233     uint32_t fsth0 = fdt0 >> 32;
3234     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3235     uint32_t fsth2 = fdt2 >> 32;
3236
3237     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3238     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3239     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3240     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3241     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3242     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3243     update_fcr31(env, GETPC());
3244     return ((uint64_t)fsth2 << 32) | fst2;
3245 }
3246
3247 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3248 {
3249     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3250     uint32_t fsth0 = fdt0 >> 32;
3251     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3252     uint32_t fsth1 = fdt1 >> 32;
3253     uint32_t fst2;
3254     uint32_t fsth2;
3255
3256     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3257     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3258     update_fcr31(env, GETPC());
3259     return ((uint64_t)fsth2 << 32) | fst2;
3260 }
3261
3262 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3263 {
3264     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3265     uint32_t fsth0 = fdt0 >> 32;
3266     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3267     uint32_t fsth1 = fdt1 >> 32;
3268     uint32_t fst2;
3269     uint32_t fsth2;
3270
3271     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3272     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3273     update_fcr31(env, GETPC());
3274     return ((uint64_t)fsth2 << 32) | fst2;
3275 }
3276
3277 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
3278 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3279                                           uint ## bits ## _t fs,        \
3280                                           uint ## bits ## _t ft)        \
3281 {                                                                       \
3282     uint ## bits ## _t fdret;                                           \
3283                                                                         \
3284     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
3285                                            &env->active_fpu.fp_status); \
3286     update_fcr31(env, GETPC());                                         \
3287     return fdret;                                                       \
3288 }
3289
3290 FLOAT_MINMAX(max_s, 32, maxnum)
3291 FLOAT_MINMAX(max_d, 64, maxnum)
3292 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3293 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3294
3295 FLOAT_MINMAX(min_s, 32, minnum)
3296 FLOAT_MINMAX(min_d, 64, minnum)
3297 FLOAT_MINMAX(mina_s, 32, minnummag)
3298 FLOAT_MINMAX(mina_d, 64, minnummag)
3299 #undef FLOAT_MINMAX
3300
3301 /* ternary operations */
3302 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3303 {                                                                    \
3304     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3305     if ((flags) & float_muladd_negate_c) {                           \
3306         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3307     } else {                                                         \
3308         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3309     }                                                                \
3310     if ((flags) & float_muladd_negate_result) {                      \
3311         a = prefix##_chs(a);                                         \
3312     }                                                                \
3313 }
3314
3315 /* FMA based operations */
3316 #define FLOAT_FMA(name, type)                                        \
3317 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3318                                      uint64_t fdt0, uint64_t fdt1,   \
3319                                      uint64_t fdt2)                  \
3320 {                                                                    \
3321     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3322     update_fcr31(env, GETPC());                                      \
3323     return fdt0;                                                     \
3324 }                                                                    \
3325                                                                      \
3326 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3327                                      uint32_t fst0, uint32_t fst1,   \
3328                                      uint32_t fst2)                  \
3329 {                                                                    \
3330     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3331     update_fcr31(env, GETPC());                                      \
3332     return fst0;                                                     \
3333 }                                                                    \
3334                                                                      \
3335 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3336                                       uint64_t fdt0, uint64_t fdt1,  \
3337                                       uint64_t fdt2)                 \
3338 {                                                                    \
3339     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3340     uint32_t fsth0 = fdt0 >> 32;                                     \
3341     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3342     uint32_t fsth1 = fdt1 >> 32;                                     \
3343     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3344     uint32_t fsth2 = fdt2 >> 32;                                     \
3345                                                                      \
3346     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3347     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3348     update_fcr31(env, GETPC());                                      \
3349     return ((uint64_t)fsth0 << 32) | fst0;                           \
3350 }
3351 FLOAT_FMA(madd, 0)
3352 FLOAT_FMA(msub, float_muladd_negate_c)
3353 FLOAT_FMA(nmadd, float_muladd_negate_result)
3354 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3355 #undef FLOAT_FMA
3356
3357 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
3358 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
3359                                           uint ## bits ## _t fs,        \
3360                                           uint ## bits ## _t ft,        \
3361                                           uint ## bits ## _t fd)        \
3362 {                                                                       \
3363     uint ## bits ## _t fdret;                                           \
3364                                                                         \
3365     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
3366                                      &env->active_fpu.fp_status);       \
3367     update_fcr31(env, GETPC());                                         \
3368     return fdret;                                                       \
3369 }
3370
3371 FLOAT_FMADDSUB(maddf_s, 32, 0)
3372 FLOAT_FMADDSUB(maddf_d, 64, 0)
3373 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3374 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3375 #undef FLOAT_FMADDSUB
3376
3377 /* compare operations */
3378 #define FOP_COND_D(op, cond)                                   \
3379 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3380                          uint64_t fdt1, int cc)                \
3381 {                                                              \
3382     int c;                                                     \
3383     c = cond;                                                  \
3384     update_fcr31(env, GETPC());                                \
3385     if (c)                                                     \
3386         SET_FP_COND(cc, env->active_fpu);                      \
3387     else                                                       \
3388         CLEAR_FP_COND(cc, env->active_fpu);                    \
3389 }                                                              \
3390 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3391                             uint64_t fdt1, int cc)             \
3392 {                                                              \
3393     int c;                                                     \
3394     fdt0 = float64_abs(fdt0);                                  \
3395     fdt1 = float64_abs(fdt1);                                  \
3396     c = cond;                                                  \
3397     update_fcr31(env, GETPC());                                \
3398     if (c)                                                     \
3399         SET_FP_COND(cc, env->active_fpu);                      \
3400     else                                                       \
3401         CLEAR_FP_COND(cc, env->active_fpu);                    \
3402 }
3403
3404 /* NOTE: the comma operator will make "cond" to eval to false,
3405  * but float64_unordered_quiet() is still called. */
3406 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3407 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3408 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3409 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3410 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3411 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3412 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3413 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3414 /* NOTE: the comma operator will make "cond" to eval to false,
3415  * but float64_unordered() is still called. */
3416 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3417 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3418 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3419 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3420 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3421 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3422 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3423 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3424
3425 #define FOP_COND_S(op, cond)                                   \
3426 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3427                          uint32_t fst1, int cc)                \
3428 {                                                              \
3429     int c;                                                     \
3430     c = cond;                                                  \
3431     update_fcr31(env, GETPC());                                \
3432     if (c)                                                     \
3433         SET_FP_COND(cc, env->active_fpu);                      \
3434     else                                                       \
3435         CLEAR_FP_COND(cc, env->active_fpu);                    \
3436 }                                                              \
3437 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3438                             uint32_t fst1, int cc)             \
3439 {                                                              \
3440     int c;                                                     \
3441     fst0 = float32_abs(fst0);                                  \
3442     fst1 = float32_abs(fst1);                                  \
3443     c = cond;                                                  \
3444     update_fcr31(env, GETPC());                                \
3445     if (c)                                                     \
3446         SET_FP_COND(cc, env->active_fpu);                      \
3447     else                                                       \
3448         CLEAR_FP_COND(cc, env->active_fpu);                    \
3449 }
3450
3451 /* NOTE: the comma operator will make "cond" to eval to false,
3452  * but float32_unordered_quiet() is still called. */
3453 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3454 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3455 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3456 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3457 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3458 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3459 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3460 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3461 /* NOTE: the comma operator will make "cond" to eval to false,
3462  * but float32_unordered() is still called. */
3463 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3464 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3465 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3466 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3467 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3468 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3469 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3470 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3471
3472 #define FOP_COND_PS(op, condl, condh)                           \
3473 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3474                           uint64_t fdt1, int cc)                \
3475 {                                                               \
3476     uint32_t fst0, fsth0, fst1, fsth1;                          \
3477     int ch, cl;                                                 \
3478     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3479     fsth0 = fdt0 >> 32;                                         \
3480     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3481     fsth1 = fdt1 >> 32;                                         \
3482     cl = condl;                                                 \
3483     ch = condh;                                                 \
3484     update_fcr31(env, GETPC());                                 \
3485     if (cl)                                                     \
3486         SET_FP_COND(cc, env->active_fpu);                       \
3487     else                                                        \
3488         CLEAR_FP_COND(cc, env->active_fpu);                     \
3489     if (ch)                                                     \
3490         SET_FP_COND(cc + 1, env->active_fpu);                   \
3491     else                                                        \
3492         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3493 }                                                               \
3494 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3495                              uint64_t fdt1, int cc)             \
3496 {                                                               \
3497     uint32_t fst0, fsth0, fst1, fsth1;                          \
3498     int ch, cl;                                                 \
3499     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3500     fsth0 = float32_abs(fdt0 >> 32);                            \
3501     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3502     fsth1 = float32_abs(fdt1 >> 32);                            \
3503     cl = condl;                                                 \
3504     ch = condh;                                                 \
3505     update_fcr31(env, GETPC());                                 \
3506     if (cl)                                                     \
3507         SET_FP_COND(cc, env->active_fpu);                       \
3508     else                                                        \
3509         CLEAR_FP_COND(cc, env->active_fpu);                     \
3510     if (ch)                                                     \
3511         SET_FP_COND(cc + 1, env->active_fpu);                   \
3512     else                                                        \
3513         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3514 }
3515
3516 /* NOTE: the comma operator will make "cond" to eval to false,
3517  * but float32_unordered_quiet() is still called. */
3518 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3519                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3520 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3521                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3522 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3523                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3524 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3525                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3526 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3527                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3528 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3529                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3530 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3531                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3532 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3533                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3534 /* NOTE: the comma operator will make "cond" to eval to false,
3535  * but float32_unordered() is still called. */
3536 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3537                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3538 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3539                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3540 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3541                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3542 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3543                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3544 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3545                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3546 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3547                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3548 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3549                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3550 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3551                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3552
3553 /* R6 compare operations */
3554 #define FOP_CONDN_D(op, cond)                                       \
3555 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3556                          uint64_t fdt1)                             \
3557 {                                                                   \
3558     uint64_t c;                                                     \
3559     c = cond;                                                       \
3560     update_fcr31(env, GETPC());                                     \
3561     if (c) {                                                        \
3562         return -1;                                                  \
3563     } else {                                                        \
3564         return 0;                                                   \
3565     }                                                               \
3566 }
3567
3568 /* NOTE: the comma operator will make "cond" to eval to false,
3569  * but float64_unordered_quiet() is still called. */
3570 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3571 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3572 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3573 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3574                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3575 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3576 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3577                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3578 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3579 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3580                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3581 /* NOTE: the comma operator will make "cond" to eval to false,
3582  * but float64_unordered() is still called. */
3583 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3584 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3585 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3586 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3587                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3588 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3589 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3590                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3591 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3592 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3593                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3594 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3595                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3596 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3597                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3598                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3599 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3600                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3601 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3602                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3603 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3604                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3605                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3606 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3607                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3608
3609 #define FOP_CONDN_S(op, cond)                                       \
3610 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3611                          uint32_t fst1)                             \
3612 {                                                                   \
3613     uint64_t c;                                                     \
3614     c = cond;                                                       \
3615     update_fcr31(env, GETPC());                                     \
3616     if (c) {                                                        \
3617         return -1;                                                  \
3618     } else {                                                        \
3619         return 0;                                                   \
3620     }                                                               \
3621 }
3622
3623 /* NOTE: the comma operator will make "cond" to eval to false,
3624  * but float32_unordered_quiet() is still called. */
3625 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3626 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3627 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3628 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3629                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3630 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3631 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3632                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3633 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3634 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3635                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3636 /* NOTE: the comma operator will make "cond" to eval to false,
3637  * but float32_unordered() is still called. */
3638 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3639 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3640 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3641 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3642                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3643 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3644 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3645                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3646 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3647 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3648                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3649 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3650                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3651 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3652                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3653                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3654 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3655                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3656 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3657                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3658 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3659                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3660                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3661 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3662                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3663
3664 /* MSA */
3665 /* Data format min and max values */
3666 #define DF_BITS(df) (1 << ((df) + 3))
3667
3668 /* Element-by-element access macros */
3669 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3670
3671 #if !defined(CONFIG_USER_ONLY)
3672 #define MEMOP_IDX(DF)                                           \
3673         TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN,  \
3674                                         cpu_mmu_index(env, false));
3675 #else
3676 #define MEMOP_IDX(DF)
3677 #endif
3678
3679 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...)                               \
3680 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3681                             target_ulong addr)                          \
3682 {                                                                       \
3683     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3684     wr_t wx;                                                            \
3685     int i;                                                              \
3686     MEMOP_IDX(DF)                                                       \
3687     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3688         wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__);     \
3689     }                                                                   \
3690     memcpy(pwd, &wx, sizeof(wr_t));                                     \
3691 }
3692
3693 #if !defined(CONFIG_USER_ONLY)
3694 MSA_LD_DF(DF_BYTE,   b, helper_ret_ldub_mmu, oi, GETRA())
3695 MSA_LD_DF(DF_HALF,   h, helper_ret_lduw_mmu, oi, GETRA())
3696 MSA_LD_DF(DF_WORD,   w, helper_ret_ldul_mmu, oi, GETRA())
3697 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu,  oi, GETRA())
3698 #else
3699 MSA_LD_DF(DF_BYTE,   b, cpu_ldub_data)
3700 MSA_LD_DF(DF_HALF,   h, cpu_lduw_data)
3701 MSA_LD_DF(DF_WORD,   w, cpu_ldl_data)
3702 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3703 #endif
3704
3705 #define MSA_PAGESPAN(x) \
3706         ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3707
3708 static inline void ensure_writable_pages(CPUMIPSState *env,
3709                                          target_ulong addr,
3710                                          int mmu_idx,
3711                                          uintptr_t retaddr)
3712 {
3713 #if !defined(CONFIG_USER_ONLY)
3714     target_ulong page_addr;
3715     if (unlikely(MSA_PAGESPAN(addr))) {
3716         /* first page */
3717         probe_write(env, addr, mmu_idx, retaddr);
3718         /* second page */
3719         page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3720         probe_write(env, page_addr, mmu_idx, retaddr);
3721     }
3722 #endif
3723 }
3724
3725 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...)                               \
3726 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd,             \
3727                             target_ulong addr)                          \
3728 {                                                                       \
3729     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);                          \
3730     int mmu_idx = cpu_mmu_index(env, false);                            \
3731     int i;                                                              \
3732     MEMOP_IDX(DF)                                                       \
3733     ensure_writable_pages(env, addr, mmu_idx, GETRA());                 \
3734     for (i = 0; i < DF_ELEMENTS(DF); i++) {                             \
3735         ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__);    \
3736     }                                                                   \
3737 }
3738
3739 #if !defined(CONFIG_USER_ONLY)
3740 MSA_ST_DF(DF_BYTE,   b, helper_ret_stb_mmu, oi, GETRA())
3741 MSA_ST_DF(DF_HALF,   h, helper_ret_stw_mmu, oi, GETRA())
3742 MSA_ST_DF(DF_WORD,   w, helper_ret_stl_mmu, oi, GETRA())
3743 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3744 #else
3745 MSA_ST_DF(DF_BYTE,   b, cpu_stb_data)
3746 MSA_ST_DF(DF_HALF,   h, cpu_stw_data)
3747 MSA_ST_DF(DF_WORD,   w, cpu_stl_data)
3748 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3749 #endif