2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 * The condition code translation is in need of attention.
27 #include "disas/disas.h"
29 #include "exec/helper-proto.h"
31 #include "exec/cpu_ldst.h"
32 #include "crisv32-decode.h"
34 #include "exec/helper-gen.h"
36 #include "trace-tcg.h"
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 # define LOG_DIS(...) do { } while (0)
47 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
48 #define BUG_ON(x) ({if (x) BUG();})
52 /* Used by the decoder. */
53 #define EXTRACT_FIELD(src, start, end) \
54 (((src) >> start) & ((1 << (end - start + 1)) - 1))
56 #define CC_MASK_NZ 0xc
57 #define CC_MASK_NZV 0xe
58 #define CC_MASK_NZVC 0xf
59 #define CC_MASK_RNZV 0x10e
61 static TCGv_ptr cpu_env
;
62 static TCGv cpu_R
[16];
63 static TCGv cpu_PR
[16];
67 static TCGv cc_result
;
72 static TCGv env_btaken
;
73 static TCGv env_btarget
;
76 #include "exec/gen-icount.h"
78 /* This is the state at translation time. */
79 typedef struct DisasContext
{
84 unsigned int (*decoder
)(CPUCRISState
*env
, struct DisasContext
*dc
);
89 unsigned int zsize
, zzsize
;
103 int cc_size_uptodate
; /* -1 invalid or last written value. */
105 int cc_x_uptodate
; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
106 int flags_uptodate
; /* Whether or not $ccs is up-to-date. */
107 int flagx_known
; /* Whether or not flags_x has the x flag known at
111 int clear_x
; /* Clear x after this insn? */
112 int clear_prefix
; /* Clear prefix after this insn? */
113 int clear_locked_irq
; /* Clear the irq lockout. */
114 int cpustate_changed
;
115 unsigned int tb_flags
; /* tb dependent flags. */
120 #define JMP_DIRECT_CC 2
121 #define JMP_INDIRECT 3
122 int jmp
; /* 0=nojmp, 1=direct, 2=indirect. */
127 struct TranslationBlock
*tb
;
128 int singlestep_enabled
;
131 static void QEMU_NORETURN
gen_BUG(DisasContext
*dc
, const char *file
, int line
)
133 printf("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
134 qemu_log("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
135 cpu_abort(CPU(dc
->cpu
), "%s:%d\n", file
, line
);
138 static const char *regnames
[] =
140 "$r0", "$r1", "$r2", "$r3",
141 "$r4", "$r5", "$r6", "$r7",
142 "$r8", "$r9", "$r10", "$r11",
143 "$r12", "$r13", "$sp", "$acr",
145 static const char *pregnames
[] =
147 "$bz", "$vr", "$pid", "$srs",
148 "$wz", "$exs", "$eda", "$mof",
149 "$dz", "$ebp", "$erp", "$srp",
150 "$nrp", "$ccs", "$usp", "$spc",
153 /* We need this table to handle preg-moves with implicit width. */
154 static int preg_sizes
[] = {
165 #define t_gen_mov_TN_env(tn, member) \
166 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
167 #define t_gen_mov_env_TN(member, tn) \
168 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
170 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
172 assert(r
>= 0 && r
<= 15);
173 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
174 tcg_gen_mov_tl(tn
, tcg_const_tl(0));
175 } else if (r
== PR_VR
) {
176 tcg_gen_mov_tl(tn
, tcg_const_tl(32));
178 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
181 static inline void t_gen_mov_preg_TN(DisasContext
*dc
, int r
, TCGv tn
)
183 assert(r
>= 0 && r
<= 15);
184 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
186 } else if (r
== PR_SRS
) {
187 tcg_gen_andi_tl(cpu_PR
[r
], tn
, 3);
190 gen_helper_tlb_flush_pid(cpu_env
, tn
);
192 if (dc
->tb_flags
& S_FLAG
&& r
== PR_SPC
) {
193 gen_helper_spc_write(cpu_env
, tn
);
194 } else if (r
== PR_CCS
) {
195 dc
->cpustate_changed
= 1;
197 tcg_gen_mov_tl(cpu_PR
[r
], tn
);
201 /* Sign extend at translation time. */
202 static int sign_extend(unsigned int val
, unsigned int width
)
214 static int cris_fetch(CPUCRISState
*env
, DisasContext
*dc
, uint32_t addr
,
215 unsigned int size
, unsigned int sign
)
222 r
= cpu_ldl_code(env
, addr
);
228 r
= cpu_ldsw_code(env
, addr
);
230 r
= cpu_lduw_code(env
, addr
);
237 r
= cpu_ldsb_code(env
, addr
);
239 r
= cpu_ldub_code(env
, addr
);
244 cpu_abort(CPU(dc
->cpu
), "Invalid fetch size %d\n", size
);
250 static void cris_lock_irq(DisasContext
*dc
)
252 dc
->clear_locked_irq
= 0;
253 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(1));
256 static inline void t_gen_raise_exception(uint32_t index
)
258 TCGv_i32 tmp
= tcg_const_i32(index
);
259 gen_helper_raise_exception(cpu_env
, tmp
);
260 tcg_temp_free_i32(tmp
);
263 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
268 t_31
= tcg_const_tl(31);
269 tcg_gen_shl_tl(d
, a
, b
);
271 tcg_gen_sub_tl(t0
, t_31
, b
);
272 tcg_gen_sar_tl(t0
, t0
, t_31
);
273 tcg_gen_and_tl(t0
, t0
, d
);
274 tcg_gen_xor_tl(d
, d
, t0
);
279 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
284 t_31
= tcg_temp_new();
285 tcg_gen_shr_tl(d
, a
, b
);
287 tcg_gen_movi_tl(t_31
, 31);
288 tcg_gen_sub_tl(t0
, t_31
, b
);
289 tcg_gen_sar_tl(t0
, t0
, t_31
);
290 tcg_gen_and_tl(t0
, t0
, d
);
291 tcg_gen_xor_tl(d
, d
, t0
);
296 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
301 t_31
= tcg_temp_new();
302 tcg_gen_sar_tl(d
, a
, b
);
304 tcg_gen_movi_tl(t_31
, 31);
305 tcg_gen_sub_tl(t0
, t_31
, b
);
306 tcg_gen_sar_tl(t0
, t0
, t_31
);
307 tcg_gen_or_tl(d
, d
, t0
);
312 static void t_gen_cris_dstep(TCGv d
, TCGv a
, TCGv b
)
314 TCGv t
= tcg_temp_new();
321 tcg_gen_shli_tl(d
, a
, 1);
322 tcg_gen_sub_tl(t
, d
, b
);
323 tcg_gen_movcond_tl(TCG_COND_GEU
, d
, d
, b
, t
, d
);
327 static void t_gen_cris_mstep(TCGv d
, TCGv a
, TCGv b
, TCGv ccs
)
337 tcg_gen_shli_tl(d
, a
, 1);
338 tcg_gen_shli_tl(t
, ccs
, 31 - 3);
339 tcg_gen_sari_tl(t
, t
, 31);
340 tcg_gen_and_tl(t
, t
, b
);
341 tcg_gen_add_tl(d
, d
, t
);
345 /* Extended arithmetics on CRIS. */
346 static inline void t_gen_add_flag(TCGv d
, int flag
)
351 t_gen_mov_TN_preg(c
, PR_CCS
);
352 /* Propagate carry into d. */
353 tcg_gen_andi_tl(c
, c
, 1 << flag
);
355 tcg_gen_shri_tl(c
, c
, flag
);
357 tcg_gen_add_tl(d
, d
, c
);
361 static inline void t_gen_addx_carry(DisasContext
*dc
, TCGv d
)
363 if (dc
->flagx_known
) {
368 t_gen_mov_TN_preg(c
, PR_CCS
);
369 /* C flag is already at bit 0. */
370 tcg_gen_andi_tl(c
, c
, C_FLAG
);
371 tcg_gen_add_tl(d
, d
, c
);
379 t_gen_mov_TN_preg(x
, PR_CCS
);
380 tcg_gen_mov_tl(c
, x
);
382 /* Propagate carry into d if X is set. Branch free. */
383 tcg_gen_andi_tl(c
, c
, C_FLAG
);
384 tcg_gen_andi_tl(x
, x
, X_FLAG
);
385 tcg_gen_shri_tl(x
, x
, 4);
387 tcg_gen_and_tl(x
, x
, c
);
388 tcg_gen_add_tl(d
, d
, x
);
394 static inline void t_gen_subx_carry(DisasContext
*dc
, TCGv d
)
396 if (dc
->flagx_known
) {
401 t_gen_mov_TN_preg(c
, PR_CCS
);
402 /* C flag is already at bit 0. */
403 tcg_gen_andi_tl(c
, c
, C_FLAG
);
404 tcg_gen_sub_tl(d
, d
, c
);
412 t_gen_mov_TN_preg(x
, PR_CCS
);
413 tcg_gen_mov_tl(c
, x
);
415 /* Propagate carry into d if X is set. Branch free. */
416 tcg_gen_andi_tl(c
, c
, C_FLAG
);
417 tcg_gen_andi_tl(x
, x
, X_FLAG
);
418 tcg_gen_shri_tl(x
, x
, 4);
420 tcg_gen_and_tl(x
, x
, c
);
421 tcg_gen_sub_tl(d
, d
, x
);
427 /* Swap the two bytes within each half word of the s operand.
428 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
429 static inline void t_gen_swapb(TCGv d
, TCGv s
)
434 org_s
= tcg_temp_new();
436 /* d and s may refer to the same object. */
437 tcg_gen_mov_tl(org_s
, s
);
438 tcg_gen_shli_tl(t
, org_s
, 8);
439 tcg_gen_andi_tl(d
, t
, 0xff00ff00);
440 tcg_gen_shri_tl(t
, org_s
, 8);
441 tcg_gen_andi_tl(t
, t
, 0x00ff00ff);
442 tcg_gen_or_tl(d
, d
, t
);
444 tcg_temp_free(org_s
);
447 /* Swap the halfwords of the s operand. */
448 static inline void t_gen_swapw(TCGv d
, TCGv s
)
451 /* d and s refer the same object. */
453 tcg_gen_mov_tl(t
, s
);
454 tcg_gen_shli_tl(d
, t
, 16);
455 tcg_gen_shri_tl(t
, t
, 16);
456 tcg_gen_or_tl(d
, d
, t
);
460 /* Reverse the within each byte.
461 T0 = (((T0 << 7) & 0x80808080) |
462 ((T0 << 5) & 0x40404040) |
463 ((T0 << 3) & 0x20202020) |
464 ((T0 << 1) & 0x10101010) |
465 ((T0 >> 1) & 0x08080808) |
466 ((T0 >> 3) & 0x04040404) |
467 ((T0 >> 5) & 0x02020202) |
468 ((T0 >> 7) & 0x01010101));
470 static inline void t_gen_swapr(TCGv d
, TCGv s
)
473 int shift
; /* LSL when positive, LSR when negative. */
488 /* d and s refer the same object. */
490 org_s
= tcg_temp_new();
491 tcg_gen_mov_tl(org_s
, s
);
493 tcg_gen_shli_tl(t
, org_s
, bitrev
[0].shift
);
494 tcg_gen_andi_tl(d
, t
, bitrev
[0].mask
);
495 for (i
= 1; i
< ARRAY_SIZE(bitrev
); i
++) {
496 if (bitrev
[i
].shift
>= 0) {
497 tcg_gen_shli_tl(t
, org_s
, bitrev
[i
].shift
);
499 tcg_gen_shri_tl(t
, org_s
, -bitrev
[i
].shift
);
501 tcg_gen_andi_tl(t
, t
, bitrev
[i
].mask
);
502 tcg_gen_or_tl(d
, d
, t
);
505 tcg_temp_free(org_s
);
508 static void t_gen_cc_jmp(TCGv pc_true
, TCGv pc_false
)
510 TCGLabel
*l1
= gen_new_label();
512 /* Conditional jmp. */
513 tcg_gen_mov_tl(env_pc
, pc_false
);
514 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
515 tcg_gen_mov_tl(env_pc
, pc_true
);
519 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
521 TranslationBlock
*tb
;
523 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
525 tcg_gen_movi_tl(env_pc
, dest
);
526 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
528 tcg_gen_movi_tl(env_pc
, dest
);
533 static inline void cris_clear_x_flag(DisasContext
*dc
)
535 if (dc
->flagx_known
&& dc
->flags_x
) {
536 dc
->flags_uptodate
= 0;
543 static void cris_flush_cc_state(DisasContext
*dc
)
545 if (dc
->cc_size_uptodate
!= dc
->cc_size
) {
546 tcg_gen_movi_tl(cc_size
, dc
->cc_size
);
547 dc
->cc_size_uptodate
= dc
->cc_size
;
549 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
550 tcg_gen_movi_tl(cc_mask
, dc
->cc_mask
);
553 static void cris_evaluate_flags(DisasContext
*dc
)
555 if (dc
->flags_uptodate
) {
559 cris_flush_cc_state(dc
);
563 gen_helper_evaluate_flags_mcp(cpu_PR
[PR_CCS
], cpu_env
,
564 cpu_PR
[PR_CCS
], cc_src
,
568 gen_helper_evaluate_flags_muls(cpu_PR
[PR_CCS
], cpu_env
,
569 cpu_PR
[PR_CCS
], cc_result
,
573 gen_helper_evaluate_flags_mulu(cpu_PR
[PR_CCS
], cpu_env
,
574 cpu_PR
[PR_CCS
], cc_result
,
584 switch (dc
->cc_size
) {
586 gen_helper_evaluate_flags_move_4(cpu_PR
[PR_CCS
],
587 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
590 gen_helper_evaluate_flags_move_2(cpu_PR
[PR_CCS
],
591 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
594 gen_helper_evaluate_flags(cpu_env
);
603 if (dc
->cc_size
== 4) {
604 gen_helper_evaluate_flags_sub_4(cpu_PR
[PR_CCS
], cpu_env
,
605 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
607 gen_helper_evaluate_flags(cpu_env
);
612 switch (dc
->cc_size
) {
614 gen_helper_evaluate_flags_alu_4(cpu_PR
[PR_CCS
], cpu_env
,
615 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
618 gen_helper_evaluate_flags(cpu_env
);
624 if (dc
->flagx_known
) {
626 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], X_FLAG
);
627 } else if (dc
->cc_op
== CC_OP_FLAGS
) {
628 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~X_FLAG
);
631 dc
->flags_uptodate
= 1;
634 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
643 /* Check if we need to evaluate the condition codes due to
645 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
647 /* TODO: optimize this case. It trigs all the time. */
648 cris_evaluate_flags(dc
);
654 static void cris_update_cc_op(DisasContext
*dc
, int op
, int size
)
658 dc
->flags_uptodate
= 0;
661 static inline void cris_update_cc_x(DisasContext
*dc
)
663 /* Save the x flag state at the time of the cc snapshot. */
664 if (dc
->flagx_known
) {
665 if (dc
->cc_x_uptodate
== (2 | dc
->flags_x
)) {
668 tcg_gen_movi_tl(cc_x
, dc
->flags_x
);
669 dc
->cc_x_uptodate
= 2 | dc
->flags_x
;
671 tcg_gen_andi_tl(cc_x
, cpu_PR
[PR_CCS
], X_FLAG
);
672 dc
->cc_x_uptodate
= 1;
676 /* Update cc prior to executing ALU op. Needs source operands untouched. */
677 static void cris_pre_alu_update_cc(DisasContext
*dc
, int op
,
678 TCGv dst
, TCGv src
, int size
)
681 cris_update_cc_op(dc
, op
, size
);
682 tcg_gen_mov_tl(cc_src
, src
);
690 && op
!= CC_OP_LSL
) {
691 tcg_gen_mov_tl(cc_dest
, dst
);
694 cris_update_cc_x(dc
);
698 /* Update cc after executing ALU op. needs the result. */
699 static inline void cris_update_result(DisasContext
*dc
, TCGv res
)
702 tcg_gen_mov_tl(cc_result
, res
);
706 /* Returns one if the write back stage should execute. */
707 static void cris_alu_op_exec(DisasContext
*dc
, int op
,
708 TCGv dst
, TCGv a
, TCGv b
, int size
)
710 /* Emit the ALU insns. */
713 tcg_gen_add_tl(dst
, a
, b
);
714 /* Extended arithmetics. */
715 t_gen_addx_carry(dc
, dst
);
718 tcg_gen_add_tl(dst
, a
, b
);
719 t_gen_add_flag(dst
, 0); /* C_FLAG. */
722 tcg_gen_add_tl(dst
, a
, b
);
723 t_gen_add_flag(dst
, 8); /* R_FLAG. */
726 tcg_gen_sub_tl(dst
, a
, b
);
727 /* Extended arithmetics. */
728 t_gen_subx_carry(dc
, dst
);
731 tcg_gen_mov_tl(dst
, b
);
734 tcg_gen_or_tl(dst
, a
, b
);
737 tcg_gen_and_tl(dst
, a
, b
);
740 tcg_gen_xor_tl(dst
, a
, b
);
743 t_gen_lsl(dst
, a
, b
);
746 t_gen_lsr(dst
, a
, b
);
749 t_gen_asr(dst
, a
, b
);
752 tcg_gen_neg_tl(dst
, b
);
753 /* Extended arithmetics. */
754 t_gen_subx_carry(dc
, dst
);
757 gen_helper_lz(dst
, b
);
760 tcg_gen_muls2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
763 tcg_gen_mulu2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
766 t_gen_cris_dstep(dst
, a
, b
);
769 t_gen_cris_mstep(dst
, a
, b
, cpu_PR
[PR_CCS
]);
772 tcg_gen_movcond_tl(TCG_COND_LEU
, dst
, a
, b
, a
, b
);
775 tcg_gen_sub_tl(dst
, a
, b
);
776 /* Extended arithmetics. */
777 t_gen_subx_carry(dc
, dst
);
780 qemu_log("illegal ALU op.\n");
786 tcg_gen_andi_tl(dst
, dst
, 0xff);
787 } else if (size
== 2) {
788 tcg_gen_andi_tl(dst
, dst
, 0xffff);
792 static void cris_alu(DisasContext
*dc
, int op
,
793 TCGv d
, TCGv op_a
, TCGv op_b
, int size
)
800 if (op
== CC_OP_CMP
) {
801 tmp
= tcg_temp_new();
803 } else if (size
== 4) {
807 tmp
= tcg_temp_new();
811 cris_pre_alu_update_cc(dc
, op
, op_a
, op_b
, size
);
812 cris_alu_op_exec(dc
, op
, tmp
, op_a
, op_b
, size
);
813 cris_update_result(dc
, tmp
);
818 tcg_gen_andi_tl(d
, d
, ~0xff);
820 tcg_gen_andi_tl(d
, d
, ~0xffff);
822 tcg_gen_or_tl(d
, d
, tmp
);
824 if (!TCGV_EQUAL(tmp
, d
)) {
829 static int arith_cc(DisasContext
*dc
)
833 case CC_OP_ADDC
: return 1;
834 case CC_OP_ADD
: return 1;
835 case CC_OP_SUB
: return 1;
836 case CC_OP_DSTEP
: return 1;
837 case CC_OP_LSL
: return 1;
838 case CC_OP_LSR
: return 1;
839 case CC_OP_ASR
: return 1;
840 case CC_OP_CMP
: return 1;
841 case CC_OP_NEG
: return 1;
842 case CC_OP_OR
: return 1;
843 case CC_OP_AND
: return 1;
844 case CC_OP_XOR
: return 1;
845 case CC_OP_MULU
: return 1;
846 case CC_OP_MULS
: return 1;
854 static void gen_tst_cc (DisasContext
*dc
, TCGv cc
, int cond
)
856 int arith_opt
, move_opt
;
858 /* TODO: optimize more condition codes. */
861 * If the flags are live, we've gotta look into the bits of CCS.
862 * Otherwise, if we just did an arithmetic operation we try to
863 * evaluate the condition code faster.
865 * When this function is done, T0 should be non-zero if the condition
868 arith_opt
= arith_cc(dc
) && !dc
->flags_uptodate
;
869 move_opt
= (dc
->cc_op
== CC_OP_MOVE
);
872 if ((arith_opt
|| move_opt
)
873 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
874 tcg_gen_setcond_tl(TCG_COND_EQ
, cc
,
875 cc_result
, tcg_const_tl(0));
877 cris_evaluate_flags(dc
);
879 cpu_PR
[PR_CCS
], Z_FLAG
);
883 if ((arith_opt
|| move_opt
)
884 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
885 tcg_gen_mov_tl(cc
, cc_result
);
887 cris_evaluate_flags(dc
);
888 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
890 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
894 cris_evaluate_flags(dc
);
895 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
898 cris_evaluate_flags(dc
);
899 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
900 tcg_gen_andi_tl(cc
, cc
, C_FLAG
);
903 cris_evaluate_flags(dc
);
904 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], V_FLAG
);
907 cris_evaluate_flags(dc
);
908 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
910 tcg_gen_andi_tl(cc
, cc
, V_FLAG
);
913 if (arith_opt
|| move_opt
) {
916 if (dc
->cc_size
== 1) {
918 } else if (dc
->cc_size
== 2) {
922 tcg_gen_shri_tl(cc
, cc_result
, bits
);
923 tcg_gen_xori_tl(cc
, cc
, 1);
925 cris_evaluate_flags(dc
);
926 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
928 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
932 if (arith_opt
|| move_opt
) {
935 if (dc
->cc_size
== 1) {
937 } else if (dc
->cc_size
== 2) {
941 tcg_gen_shri_tl(cc
, cc_result
, bits
);
942 tcg_gen_andi_tl(cc
, cc
, 1);
944 cris_evaluate_flags(dc
);
945 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
950 cris_evaluate_flags(dc
);
951 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
955 cris_evaluate_flags(dc
);
959 tmp
= tcg_temp_new();
960 tcg_gen_xori_tl(tmp
, cpu_PR
[PR_CCS
],
962 /* Overlay the C flag on top of the Z. */
963 tcg_gen_shli_tl(cc
, tmp
, 2);
964 tcg_gen_and_tl(cc
, tmp
, cc
);
965 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
971 cris_evaluate_flags(dc
);
972 /* Overlay the V flag on top of the N. */
973 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
976 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
977 tcg_gen_xori_tl(cc
, cc
, N_FLAG
);
980 cris_evaluate_flags(dc
);
981 /* Overlay the V flag on top of the N. */
982 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
985 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
988 cris_evaluate_flags(dc
);
995 /* To avoid a shift we overlay everything on
997 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
998 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1000 tcg_gen_xori_tl(z
, z
, 2);
1002 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1003 tcg_gen_xori_tl(n
, n
, 2);
1004 tcg_gen_and_tl(cc
, z
, n
);
1005 tcg_gen_andi_tl(cc
, cc
, 2);
1012 cris_evaluate_flags(dc
);
1019 /* To avoid a shift we overlay everything on
1021 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1022 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1024 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1025 tcg_gen_or_tl(cc
, z
, n
);
1026 tcg_gen_andi_tl(cc
, cc
, 2);
1033 cris_evaluate_flags(dc
);
1034 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], P_FLAG
);
1037 tcg_gen_movi_tl(cc
, 1);
1045 static void cris_store_direct_jmp(DisasContext
*dc
)
1047 /* Store the direct jmp state into the cpu-state. */
1048 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1049 if (dc
->jmp
== JMP_DIRECT
) {
1050 tcg_gen_movi_tl(env_btaken
, 1);
1052 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1053 dc
->jmp
= JMP_INDIRECT
;
1057 static void cris_prepare_cc_branch (DisasContext
*dc
,
1058 int offset
, int cond
)
1060 /* This helps us re-schedule the micro-code to insns in delay-slots
1061 before the actual jump. */
1062 dc
->delayed_branch
= 2;
1063 dc
->jmp
= JMP_DIRECT_CC
;
1064 dc
->jmp_pc
= dc
->pc
+ offset
;
1066 gen_tst_cc(dc
, env_btaken
, cond
);
1067 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1071 /* jumps, when the dest is in a live reg for example. Direct should be set
1072 when the dest addr is constant to allow tb chaining. */
1073 static inline void cris_prepare_jmp (DisasContext
*dc
, unsigned int type
)
1075 /* This helps us re-schedule the micro-code to insns in delay-slots
1076 before the actual jump. */
1077 dc
->delayed_branch
= 2;
1079 if (type
== JMP_INDIRECT
) {
1080 tcg_gen_movi_tl(env_btaken
, 1);
1084 static void gen_load64(DisasContext
*dc
, TCGv_i64 dst
, TCGv addr
)
1086 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1088 /* If we get a fault on a delayslot we must keep the jmp state in
1089 the cpu-state to be able to re-execute the jmp. */
1090 if (dc
->delayed_branch
== 1) {
1091 cris_store_direct_jmp(dc
);
1094 tcg_gen_qemu_ld_i64(dst
, addr
, mem_index
, MO_TEQ
);
1097 static void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
1098 unsigned int size
, int sign
)
1100 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1102 /* If we get a fault on a delayslot we must keep the jmp state in
1103 the cpu-state to be able to re-execute the jmp. */
1104 if (dc
->delayed_branch
== 1) {
1105 cris_store_direct_jmp(dc
);
1108 tcg_gen_qemu_ld_tl(dst
, addr
, mem_index
,
1109 MO_TE
+ ctz32(size
) + (sign
? MO_SIGN
: 0));
1112 static void gen_store (DisasContext
*dc
, TCGv addr
, TCGv val
,
1115 int mem_index
= cpu_mmu_index(&dc
->cpu
->env
, false);
1117 /* If we get a fault on a delayslot we must keep the jmp state in
1118 the cpu-state to be able to re-execute the jmp. */
1119 if (dc
->delayed_branch
== 1) {
1120 cris_store_direct_jmp(dc
);
1124 /* Conditional writes. We only support the kind were X and P are known
1125 at translation time. */
1126 if (dc
->flagx_known
&& dc
->flags_x
&& (dc
->tb_flags
& P_FLAG
)) {
1128 cris_evaluate_flags(dc
);
1129 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], C_FLAG
);
1133 tcg_gen_qemu_st_tl(val
, addr
, mem_index
, MO_TE
+ ctz32(size
));
1135 if (dc
->flagx_known
&& dc
->flags_x
) {
1136 cris_evaluate_flags(dc
);
1137 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~C_FLAG
);
1141 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
1144 tcg_gen_ext8s_i32(d
, s
);
1145 } else if (size
== 2) {
1146 tcg_gen_ext16s_i32(d
, s
);
1147 } else if (!TCGV_EQUAL(d
, s
)) {
1148 tcg_gen_mov_tl(d
, s
);
1152 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
1155 tcg_gen_ext8u_i32(d
, s
);
1156 } else if (size
== 2) {
1157 tcg_gen_ext16u_i32(d
, s
);
1158 } else if (!TCGV_EQUAL(d
, s
)) {
1159 tcg_gen_mov_tl(d
, s
);
1164 static char memsize_char(int size
)
1167 case 1: return 'b'; break;
1168 case 2: return 'w'; break;
1169 case 4: return 'd'; break;
1177 static inline unsigned int memsize_z(DisasContext
*dc
)
1179 return dc
->zsize
+ 1;
1182 static inline unsigned int memsize_zz(DisasContext
*dc
)
1184 switch (dc
->zzsize
) {
1192 static inline void do_postinc (DisasContext
*dc
, int size
)
1195 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], size
);
1199 static inline void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
1200 int size
, int s_ext
, TCGv dst
)
1203 t_gen_sext(dst
, cpu_R
[rs
], size
);
1205 t_gen_zext(dst
, cpu_R
[rs
], size
);
1209 /* Prepare T0 and T1 for a register alu operation.
1210 s_ext decides if the operand1 should be sign-extended or zero-extended when
1212 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
1213 int size
, int s_ext
, TCGv dst
, TCGv src
)
1215 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
, src
);
1218 t_gen_sext(dst
, cpu_R
[rd
], size
);
1220 t_gen_zext(dst
, cpu_R
[rd
], size
);
1224 static int dec_prep_move_m(CPUCRISState
*env
, DisasContext
*dc
,
1225 int s_ext
, int memsize
, TCGv dst
)
1233 is_imm
= rs
== 15 && dc
->postinc
;
1235 /* Load [$rs] onto T1. */
1237 insn_len
= 2 + memsize
;
1242 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, memsize
, s_ext
);
1243 tcg_gen_movi_tl(dst
, imm
);
1246 cris_flush_cc_state(dc
);
1247 gen_load(dc
, dst
, cpu_R
[rs
], memsize
, 0);
1249 t_gen_sext(dst
, dst
, memsize
);
1251 t_gen_zext(dst
, dst
, memsize
);
1257 /* Prepare T0 and T1 for a memory + alu operation.
1258 s_ext decides if the operand1 should be sign-extended or zero-extended when
1260 static int dec_prep_alu_m(CPUCRISState
*env
, DisasContext
*dc
,
1261 int s_ext
, int memsize
, TCGv dst
, TCGv src
)
1265 insn_len
= dec_prep_move_m(env
, dc
, s_ext
, memsize
, src
);
1266 tcg_gen_mov_tl(dst
, cpu_R
[dc
->op2
]);
1271 static const char *cc_name(int cc
)
1273 static const char *cc_names
[16] = {
1274 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1275 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1278 return cc_names
[cc
];
1282 /* Start of insn decoders. */
1284 static int dec_bccq(CPUCRISState
*env
, DisasContext
*dc
)
1288 uint32_t cond
= dc
->op2
;
1290 offset
= EXTRACT_FIELD(dc
->ir
, 1, 7);
1291 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
1294 offset
|= sign
<< 8;
1295 offset
= sign_extend(offset
, 8);
1297 LOG_DIS("b%s %x\n", cc_name(cond
), dc
->pc
+ offset
);
1299 /* op2 holds the condition-code. */
1300 cris_cc_mask(dc
, 0);
1301 cris_prepare_cc_branch(dc
, offset
, cond
);
1304 static int dec_addoq(CPUCRISState
*env
, DisasContext
*dc
)
1308 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
1309 imm
= sign_extend(dc
->op1
, 7);
1311 LOG_DIS("addoq %d, $r%u\n", imm
, dc
->op2
);
1312 cris_cc_mask(dc
, 0);
1313 /* Fetch register operand, */
1314 tcg_gen_addi_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op2
], imm
);
1318 static int dec_addq(CPUCRISState
*env
, DisasContext
*dc
)
1320 LOG_DIS("addq %u, $r%u\n", dc
->op1
, dc
->op2
);
1322 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1324 cris_cc_mask(dc
, CC_MASK_NZVC
);
1326 cris_alu(dc
, CC_OP_ADD
,
1327 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1330 static int dec_moveq(CPUCRISState
*env
, DisasContext
*dc
)
1334 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1335 imm
= sign_extend(dc
->op1
, 5);
1336 LOG_DIS("moveq %d, $r%u\n", imm
, dc
->op2
);
1338 tcg_gen_movi_tl(cpu_R
[dc
->op2
], imm
);
1341 static int dec_subq(CPUCRISState
*env
, DisasContext
*dc
)
1343 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1345 LOG_DIS("subq %u, $r%u\n", dc
->op1
, dc
->op2
);
1347 cris_cc_mask(dc
, CC_MASK_NZVC
);
1348 cris_alu(dc
, CC_OP_SUB
,
1349 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1352 static int dec_cmpq(CPUCRISState
*env
, DisasContext
*dc
)
1355 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1356 imm
= sign_extend(dc
->op1
, 5);
1358 LOG_DIS("cmpq %d, $r%d\n", imm
, dc
->op2
);
1359 cris_cc_mask(dc
, CC_MASK_NZVC
);
1361 cris_alu(dc
, CC_OP_CMP
,
1362 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1365 static int dec_andq(CPUCRISState
*env
, DisasContext
*dc
)
1368 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1369 imm
= sign_extend(dc
->op1
, 5);
1371 LOG_DIS("andq %d, $r%d\n", imm
, dc
->op2
);
1372 cris_cc_mask(dc
, CC_MASK_NZ
);
1374 cris_alu(dc
, CC_OP_AND
,
1375 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1378 static int dec_orq(CPUCRISState
*env
, DisasContext
*dc
)
1381 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1382 imm
= sign_extend(dc
->op1
, 5);
1383 LOG_DIS("orq %d, $r%d\n", imm
, dc
->op2
);
1384 cris_cc_mask(dc
, CC_MASK_NZ
);
1386 cris_alu(dc
, CC_OP_OR
,
1387 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1390 static int dec_btstq(CPUCRISState
*env
, DisasContext
*dc
)
1392 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1393 LOG_DIS("btstq %u, $r%d\n", dc
->op1
, dc
->op2
);
1395 cris_cc_mask(dc
, CC_MASK_NZ
);
1396 cris_evaluate_flags(dc
);
1397 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1398 tcg_const_tl(dc
->op1
), cpu_PR
[PR_CCS
]);
1399 cris_alu(dc
, CC_OP_MOVE
,
1400 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1401 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1402 dc
->flags_uptodate
= 1;
1405 static int dec_asrq(CPUCRISState
*env
, DisasContext
*dc
)
1407 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1408 LOG_DIS("asrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1409 cris_cc_mask(dc
, CC_MASK_NZ
);
1411 tcg_gen_sari_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1412 cris_alu(dc
, CC_OP_MOVE
,
1414 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1417 static int dec_lslq(CPUCRISState
*env
, DisasContext
*dc
)
1419 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1420 LOG_DIS("lslq %u, $r%d\n", dc
->op1
, dc
->op2
);
1422 cris_cc_mask(dc
, CC_MASK_NZ
);
1424 tcg_gen_shli_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1426 cris_alu(dc
, CC_OP_MOVE
,
1428 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1431 static int dec_lsrq(CPUCRISState
*env
, DisasContext
*dc
)
1433 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1434 LOG_DIS("lsrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1436 cris_cc_mask(dc
, CC_MASK_NZ
);
1438 tcg_gen_shri_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1439 cris_alu(dc
, CC_OP_MOVE
,
1441 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1445 static int dec_move_r(CPUCRISState
*env
, DisasContext
*dc
)
1447 int size
= memsize_zz(dc
);
1449 LOG_DIS("move.%c $r%u, $r%u\n",
1450 memsize_char(size
), dc
->op1
, dc
->op2
);
1452 cris_cc_mask(dc
, CC_MASK_NZ
);
1454 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, cpu_R
[dc
->op2
]);
1455 cris_cc_mask(dc
, CC_MASK_NZ
);
1456 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
1457 cris_update_cc_x(dc
);
1458 cris_update_result(dc
, cpu_R
[dc
->op2
]);
1462 t0
= tcg_temp_new();
1463 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1464 cris_alu(dc
, CC_OP_MOVE
,
1466 cpu_R
[dc
->op2
], t0
, size
);
1472 static int dec_scc_r(CPUCRISState
*env
, DisasContext
*dc
)
1476 LOG_DIS("s%s $r%u\n",
1477 cc_name(cond
), dc
->op1
);
1479 gen_tst_cc(dc
, cpu_R
[dc
->op1
], cond
);
1480 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], 0);
1482 cris_cc_mask(dc
, 0);
1486 static inline void cris_alu_alloc_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1489 t
[0] = cpu_R
[dc
->op2
];
1490 t
[1] = cpu_R
[dc
->op1
];
1492 t
[0] = tcg_temp_new();
1493 t
[1] = tcg_temp_new();
1497 static inline void cris_alu_free_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1500 tcg_temp_free(t
[0]);
1501 tcg_temp_free(t
[1]);
1505 static int dec_and_r(CPUCRISState
*env
, DisasContext
*dc
)
1508 int size
= memsize_zz(dc
);
1510 LOG_DIS("and.%c $r%u, $r%u\n",
1511 memsize_char(size
), dc
->op1
, dc
->op2
);
1513 cris_cc_mask(dc
, CC_MASK_NZ
);
1515 cris_alu_alloc_temps(dc
, size
, t
);
1516 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1517 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1518 cris_alu_free_temps(dc
, size
, t
);
1522 static int dec_lz_r(CPUCRISState
*env
, DisasContext
*dc
)
1525 LOG_DIS("lz $r%u, $r%u\n",
1527 cris_cc_mask(dc
, CC_MASK_NZ
);
1528 t0
= tcg_temp_new();
1529 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0, cpu_R
[dc
->op2
], t0
);
1530 cris_alu(dc
, CC_OP_LZ
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1535 static int dec_lsl_r(CPUCRISState
*env
, DisasContext
*dc
)
1538 int size
= memsize_zz(dc
);
1540 LOG_DIS("lsl.%c $r%u, $r%u\n",
1541 memsize_char(size
), dc
->op1
, dc
->op2
);
1543 cris_cc_mask(dc
, CC_MASK_NZ
);
1544 cris_alu_alloc_temps(dc
, size
, t
);
1545 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1546 tcg_gen_andi_tl(t
[1], t
[1], 63);
1547 cris_alu(dc
, CC_OP_LSL
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1548 cris_alu_alloc_temps(dc
, size
, t
);
1552 static int dec_lsr_r(CPUCRISState
*env
, DisasContext
*dc
)
1555 int size
= memsize_zz(dc
);
1557 LOG_DIS("lsr.%c $r%u, $r%u\n",
1558 memsize_char(size
), dc
->op1
, dc
->op2
);
1560 cris_cc_mask(dc
, CC_MASK_NZ
);
1561 cris_alu_alloc_temps(dc
, size
, t
);
1562 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1563 tcg_gen_andi_tl(t
[1], t
[1], 63);
1564 cris_alu(dc
, CC_OP_LSR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1565 cris_alu_free_temps(dc
, size
, t
);
1569 static int dec_asr_r(CPUCRISState
*env
, DisasContext
*dc
)
1572 int size
= memsize_zz(dc
);
1574 LOG_DIS("asr.%c $r%u, $r%u\n",
1575 memsize_char(size
), dc
->op1
, dc
->op2
);
1577 cris_cc_mask(dc
, CC_MASK_NZ
);
1578 cris_alu_alloc_temps(dc
, size
, t
);
1579 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1580 tcg_gen_andi_tl(t
[1], t
[1], 63);
1581 cris_alu(dc
, CC_OP_ASR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1582 cris_alu_free_temps(dc
, size
, t
);
1586 static int dec_muls_r(CPUCRISState
*env
, DisasContext
*dc
)
1589 int size
= memsize_zz(dc
);
1591 LOG_DIS("muls.%c $r%u, $r%u\n",
1592 memsize_char(size
), dc
->op1
, dc
->op2
);
1593 cris_cc_mask(dc
, CC_MASK_NZV
);
1594 cris_alu_alloc_temps(dc
, size
, t
);
1595 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1597 cris_alu(dc
, CC_OP_MULS
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1598 cris_alu_free_temps(dc
, size
, t
);
1602 static int dec_mulu_r(CPUCRISState
*env
, DisasContext
*dc
)
1605 int size
= memsize_zz(dc
);
1607 LOG_DIS("mulu.%c $r%u, $r%u\n",
1608 memsize_char(size
), dc
->op1
, dc
->op2
);
1609 cris_cc_mask(dc
, CC_MASK_NZV
);
1610 cris_alu_alloc_temps(dc
, size
, t
);
1611 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1613 cris_alu(dc
, CC_OP_MULU
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1614 cris_alu_alloc_temps(dc
, size
, t
);
1619 static int dec_dstep_r(CPUCRISState
*env
, DisasContext
*dc
)
1621 LOG_DIS("dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
);
1622 cris_cc_mask(dc
, CC_MASK_NZ
);
1623 cris_alu(dc
, CC_OP_DSTEP
,
1624 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1628 static int dec_xor_r(CPUCRISState
*env
, DisasContext
*dc
)
1631 int size
= memsize_zz(dc
);
1632 LOG_DIS("xor.%c $r%u, $r%u\n",
1633 memsize_char(size
), dc
->op1
, dc
->op2
);
1634 BUG_ON(size
!= 4); /* xor is dword. */
1635 cris_cc_mask(dc
, CC_MASK_NZ
);
1636 cris_alu_alloc_temps(dc
, size
, t
);
1637 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1639 cris_alu(dc
, CC_OP_XOR
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1640 cris_alu_free_temps(dc
, size
, t
);
1644 static int dec_bound_r(CPUCRISState
*env
, DisasContext
*dc
)
1647 int size
= memsize_zz(dc
);
1648 LOG_DIS("bound.%c $r%u, $r%u\n",
1649 memsize_char(size
), dc
->op1
, dc
->op2
);
1650 cris_cc_mask(dc
, CC_MASK_NZ
);
1651 l0
= tcg_temp_local_new();
1652 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, l0
);
1653 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], l0
, 4);
1658 static int dec_cmp_r(CPUCRISState
*env
, DisasContext
*dc
)
1661 int size
= memsize_zz(dc
);
1662 LOG_DIS("cmp.%c $r%u, $r%u\n",
1663 memsize_char(size
), dc
->op1
, dc
->op2
);
1664 cris_cc_mask(dc
, CC_MASK_NZVC
);
1665 cris_alu_alloc_temps(dc
, size
, t
);
1666 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1668 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1669 cris_alu_free_temps(dc
, size
, t
);
1673 static int dec_abs_r(CPUCRISState
*env
, DisasContext
*dc
)
1677 LOG_DIS("abs $r%u, $r%u\n",
1679 cris_cc_mask(dc
, CC_MASK_NZ
);
1681 t0
= tcg_temp_new();
1682 tcg_gen_sari_tl(t0
, cpu_R
[dc
->op1
], 31);
1683 tcg_gen_xor_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
);
1684 tcg_gen_sub_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
);
1687 cris_alu(dc
, CC_OP_MOVE
,
1688 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1692 static int dec_add_r(CPUCRISState
*env
, DisasContext
*dc
)
1695 int size
= memsize_zz(dc
);
1696 LOG_DIS("add.%c $r%u, $r%u\n",
1697 memsize_char(size
), dc
->op1
, dc
->op2
);
1698 cris_cc_mask(dc
, CC_MASK_NZVC
);
1699 cris_alu_alloc_temps(dc
, size
, t
);
1700 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1702 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1703 cris_alu_free_temps(dc
, size
, t
);
1707 static int dec_addc_r(CPUCRISState
*env
, DisasContext
*dc
)
1709 LOG_DIS("addc $r%u, $r%u\n",
1711 cris_evaluate_flags(dc
);
1712 /* Set for this insn. */
1713 dc
->flagx_known
= 1;
1714 dc
->flags_x
= X_FLAG
;
1716 cris_cc_mask(dc
, CC_MASK_NZVC
);
1717 cris_alu(dc
, CC_OP_ADDC
,
1718 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1722 static int dec_mcp_r(CPUCRISState
*env
, DisasContext
*dc
)
1724 LOG_DIS("mcp $p%u, $r%u\n",
1726 cris_evaluate_flags(dc
);
1727 cris_cc_mask(dc
, CC_MASK_RNZV
);
1728 cris_alu(dc
, CC_OP_MCP
,
1729 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], cpu_PR
[dc
->op2
], 4);
1734 static char * swapmode_name(int mode
, char *modename
) {
1737 modename
[i
++] = 'n';
1740 modename
[i
++] = 'w';
1743 modename
[i
++] = 'b';
1746 modename
[i
++] = 'r';
1753 static int dec_swap_r(CPUCRISState
*env
, DisasContext
*dc
)
1759 LOG_DIS("swap%s $r%u\n",
1760 swapmode_name(dc
->op2
, modename
), dc
->op1
);
1762 cris_cc_mask(dc
, CC_MASK_NZ
);
1763 t0
= tcg_temp_new();
1764 tcg_gen_mov_tl(t0
, cpu_R
[dc
->op1
]);
1766 tcg_gen_not_tl(t0
, t0
);
1769 t_gen_swapw(t0
, t0
);
1772 t_gen_swapb(t0
, t0
);
1775 t_gen_swapr(t0
, t0
);
1777 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
, 4);
1782 static int dec_or_r(CPUCRISState
*env
, DisasContext
*dc
)
1785 int size
= memsize_zz(dc
);
1786 LOG_DIS("or.%c $r%u, $r%u\n",
1787 memsize_char(size
), dc
->op1
, dc
->op2
);
1788 cris_cc_mask(dc
, CC_MASK_NZ
);
1789 cris_alu_alloc_temps(dc
, size
, t
);
1790 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1791 cris_alu(dc
, CC_OP_OR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1792 cris_alu_free_temps(dc
, size
, t
);
1796 static int dec_addi_r(CPUCRISState
*env
, DisasContext
*dc
)
1799 LOG_DIS("addi.%c $r%u, $r%u\n",
1800 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1801 cris_cc_mask(dc
, 0);
1802 t0
= tcg_temp_new();
1803 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1804 tcg_gen_add_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
);
1809 static int dec_addi_acr(CPUCRISState
*env
, DisasContext
*dc
)
1812 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1813 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1814 cris_cc_mask(dc
, 0);
1815 t0
= tcg_temp_new();
1816 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1817 tcg_gen_add_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op1
], t0
);
1822 static int dec_neg_r(CPUCRISState
*env
, DisasContext
*dc
)
1825 int size
= memsize_zz(dc
);
1826 LOG_DIS("neg.%c $r%u, $r%u\n",
1827 memsize_char(size
), dc
->op1
, dc
->op2
);
1828 cris_cc_mask(dc
, CC_MASK_NZVC
);
1829 cris_alu_alloc_temps(dc
, size
, t
);
1830 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1832 cris_alu(dc
, CC_OP_NEG
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1833 cris_alu_free_temps(dc
, size
, t
);
1837 static int dec_btst_r(CPUCRISState
*env
, DisasContext
*dc
)
1839 LOG_DIS("btst $r%u, $r%u\n",
1841 cris_cc_mask(dc
, CC_MASK_NZ
);
1842 cris_evaluate_flags(dc
);
1843 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1844 cpu_R
[dc
->op1
], cpu_PR
[PR_CCS
]);
1845 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
],
1846 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1847 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1848 dc
->flags_uptodate
= 1;
1852 static int dec_sub_r(CPUCRISState
*env
, DisasContext
*dc
)
1855 int size
= memsize_zz(dc
);
1856 LOG_DIS("sub.%c $r%u, $r%u\n",
1857 memsize_char(size
), dc
->op1
, dc
->op2
);
1858 cris_cc_mask(dc
, CC_MASK_NZVC
);
1859 cris_alu_alloc_temps(dc
, size
, t
);
1860 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1861 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1862 cris_alu_free_temps(dc
, size
, t
);
1866 /* Zero extension. From size to dword. */
1867 static int dec_movu_r(CPUCRISState
*env
, DisasContext
*dc
)
1870 int size
= memsize_z(dc
);
1871 LOG_DIS("movu.%c $r%u, $r%u\n",
1875 cris_cc_mask(dc
, CC_MASK_NZ
);
1876 t0
= tcg_temp_new();
1877 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1878 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1883 /* Sign extension. From size to dword. */
1884 static int dec_movs_r(CPUCRISState
*env
, DisasContext
*dc
)
1887 int size
= memsize_z(dc
);
1888 LOG_DIS("movs.%c $r%u, $r%u\n",
1892 cris_cc_mask(dc
, CC_MASK_NZ
);
1893 t0
= tcg_temp_new();
1894 /* Size can only be qi or hi. */
1895 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1896 cris_alu(dc
, CC_OP_MOVE
,
1897 cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
, 4);
1902 /* zero extension. From size to dword. */
1903 static int dec_addu_r(CPUCRISState
*env
, DisasContext
*dc
)
1906 int size
= memsize_z(dc
);
1907 LOG_DIS("addu.%c $r%u, $r%u\n",
1911 cris_cc_mask(dc
, CC_MASK_NZVC
);
1912 t0
= tcg_temp_new();
1913 /* Size can only be qi or hi. */
1914 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1915 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1920 /* Sign extension. From size to dword. */
1921 static int dec_adds_r(CPUCRISState
*env
, DisasContext
*dc
)
1924 int size
= memsize_z(dc
);
1925 LOG_DIS("adds.%c $r%u, $r%u\n",
1929 cris_cc_mask(dc
, CC_MASK_NZVC
);
1930 t0
= tcg_temp_new();
1931 /* Size can only be qi or hi. */
1932 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1933 cris_alu(dc
, CC_OP_ADD
,
1934 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1939 /* Zero extension. From size to dword. */
1940 static int dec_subu_r(CPUCRISState
*env
, DisasContext
*dc
)
1943 int size
= memsize_z(dc
);
1944 LOG_DIS("subu.%c $r%u, $r%u\n",
1948 cris_cc_mask(dc
, CC_MASK_NZVC
);
1949 t0
= tcg_temp_new();
1950 /* Size can only be qi or hi. */
1951 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1952 cris_alu(dc
, CC_OP_SUB
,
1953 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1958 /* Sign extension. From size to dword. */
1959 static int dec_subs_r(CPUCRISState
*env
, DisasContext
*dc
)
1962 int size
= memsize_z(dc
);
1963 LOG_DIS("subs.%c $r%u, $r%u\n",
1967 cris_cc_mask(dc
, CC_MASK_NZVC
);
1968 t0
= tcg_temp_new();
1969 /* Size can only be qi or hi. */
1970 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1971 cris_alu(dc
, CC_OP_SUB
,
1972 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1977 static int dec_setclrf(CPUCRISState
*env
, DisasContext
*dc
)
1980 int set
= (~dc
->opcode
>> 2) & 1;
1983 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
1984 | EXTRACT_FIELD(dc
->ir
, 0, 3);
1985 if (set
&& flags
== 0) {
1988 } else if (!set
&& (flags
& 0x20)) {
1991 LOG_DIS("%sf %x\n", set
? "set" : "clr", flags
);
1994 /* User space is not allowed to touch these. Silently ignore. */
1995 if (dc
->tb_flags
& U_FLAG
) {
1996 flags
&= ~(S_FLAG
| I_FLAG
| U_FLAG
);
1999 if (flags
& X_FLAG
) {
2000 dc
->flagx_known
= 1;
2002 dc
->flags_x
= X_FLAG
;
2008 /* Break the TB if any of the SPI flag changes. */
2009 if (flags
& (P_FLAG
| S_FLAG
)) {
2010 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2011 dc
->is_jmp
= DISAS_UPDATE
;
2012 dc
->cpustate_changed
= 1;
2015 /* For the I flag, only act on posedge. */
2016 if ((flags
& I_FLAG
)) {
2017 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2018 dc
->is_jmp
= DISAS_UPDATE
;
2019 dc
->cpustate_changed
= 1;
2023 /* Simply decode the flags. */
2024 cris_evaluate_flags(dc
);
2025 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2026 cris_update_cc_x(dc
);
2027 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
2030 if (!(dc
->tb_flags
& U_FLAG
) && (flags
& U_FLAG
)) {
2031 /* Enter user mode. */
2032 t_gen_mov_env_TN(ksp
, cpu_R
[R_SP
]);
2033 tcg_gen_mov_tl(cpu_R
[R_SP
], cpu_PR
[PR_USP
]);
2034 dc
->cpustate_changed
= 1;
2036 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
2038 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~flags
);
2041 dc
->flags_uptodate
= 1;
2046 static int dec_move_rs(CPUCRISState
*env
, DisasContext
*dc
)
2048 LOG_DIS("move $r%u, $s%u\n", dc
->op1
, dc
->op2
);
2049 cris_cc_mask(dc
, 0);
2050 gen_helper_movl_sreg_reg(cpu_env
, tcg_const_tl(dc
->op2
),
2051 tcg_const_tl(dc
->op1
));
2054 static int dec_move_sr(CPUCRISState
*env
, DisasContext
*dc
)
2056 LOG_DIS("move $s%u, $r%u\n", dc
->op2
, dc
->op1
);
2057 cris_cc_mask(dc
, 0);
2058 gen_helper_movl_reg_sreg(cpu_env
, tcg_const_tl(dc
->op1
),
2059 tcg_const_tl(dc
->op2
));
2063 static int dec_move_rp(CPUCRISState
*env
, DisasContext
*dc
)
2066 LOG_DIS("move $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2067 cris_cc_mask(dc
, 0);
2069 t
[0] = tcg_temp_new();
2070 if (dc
->op2
== PR_CCS
) {
2071 cris_evaluate_flags(dc
);
2072 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2073 if (dc
->tb_flags
& U_FLAG
) {
2074 t
[1] = tcg_temp_new();
2075 /* User space is not allowed to touch all flags. */
2076 tcg_gen_andi_tl(t
[0], t
[0], 0x39f);
2077 tcg_gen_andi_tl(t
[1], cpu_PR
[PR_CCS
], ~0x39f);
2078 tcg_gen_or_tl(t
[0], t
[1], t
[0]);
2079 tcg_temp_free(t
[1]);
2082 tcg_gen_mov_tl(t
[0], cpu_R
[dc
->op1
]);
2085 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[0]);
2086 if (dc
->op2
== PR_CCS
) {
2087 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2088 dc
->flags_uptodate
= 1;
2090 tcg_temp_free(t
[0]);
2093 static int dec_move_pr(CPUCRISState
*env
, DisasContext
*dc
)
2096 LOG_DIS("move $p%u, $r%u\n", dc
->op2
, dc
->op1
);
2097 cris_cc_mask(dc
, 0);
2099 if (dc
->op2
== PR_CCS
) {
2100 cris_evaluate_flags(dc
);
2103 if (dc
->op2
== PR_DZ
) {
2104 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 0);
2106 t0
= tcg_temp_new();
2107 t_gen_mov_TN_preg(t0
, dc
->op2
);
2108 cris_alu(dc
, CC_OP_MOVE
,
2109 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
,
2110 preg_sizes
[dc
->op2
]);
2116 static int dec_move_mr(CPUCRISState
*env
, DisasContext
*dc
)
2118 int memsize
= memsize_zz(dc
);
2120 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2121 memsize_char(memsize
),
2122 dc
->op1
, dc
->postinc
? "+]" : "]",
2126 insn_len
= dec_prep_move_m(env
, dc
, 0, 4, cpu_R
[dc
->op2
]);
2127 cris_cc_mask(dc
, CC_MASK_NZ
);
2128 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
2129 cris_update_cc_x(dc
);
2130 cris_update_result(dc
, cpu_R
[dc
->op2
]);
2134 t0
= tcg_temp_new();
2135 insn_len
= dec_prep_move_m(env
, dc
, 0, memsize
, t0
);
2136 cris_cc_mask(dc
, CC_MASK_NZ
);
2137 cris_alu(dc
, CC_OP_MOVE
,
2138 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, memsize
);
2141 do_postinc(dc
, memsize
);
2145 static inline void cris_alu_m_alloc_temps(TCGv
*t
)
2147 t
[0] = tcg_temp_new();
2148 t
[1] = tcg_temp_new();
2151 static inline void cris_alu_m_free_temps(TCGv
*t
)
2153 tcg_temp_free(t
[0]);
2154 tcg_temp_free(t
[1]);
2157 static int dec_movs_m(CPUCRISState
*env
, DisasContext
*dc
)
2160 int memsize
= memsize_z(dc
);
2162 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2163 memsize_char(memsize
),
2164 dc
->op1
, dc
->postinc
? "+]" : "]",
2167 cris_alu_m_alloc_temps(t
);
2169 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2170 cris_cc_mask(dc
, CC_MASK_NZ
);
2171 cris_alu(dc
, CC_OP_MOVE
,
2172 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2173 do_postinc(dc
, memsize
);
2174 cris_alu_m_free_temps(t
);
2178 static int dec_addu_m(CPUCRISState
*env
, DisasContext
*dc
)
2181 int memsize
= memsize_z(dc
);
2183 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2184 memsize_char(memsize
),
2185 dc
->op1
, dc
->postinc
? "+]" : "]",
2188 cris_alu_m_alloc_temps(t
);
2190 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2191 cris_cc_mask(dc
, CC_MASK_NZVC
);
2192 cris_alu(dc
, CC_OP_ADD
,
2193 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2194 do_postinc(dc
, memsize
);
2195 cris_alu_m_free_temps(t
);
2199 static int dec_adds_m(CPUCRISState
*env
, DisasContext
*dc
)
2202 int memsize
= memsize_z(dc
);
2204 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2205 memsize_char(memsize
),
2206 dc
->op1
, dc
->postinc
? "+]" : "]",
2209 cris_alu_m_alloc_temps(t
);
2211 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2212 cris_cc_mask(dc
, CC_MASK_NZVC
);
2213 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2214 do_postinc(dc
, memsize
);
2215 cris_alu_m_free_temps(t
);
2219 static int dec_subu_m(CPUCRISState
*env
, DisasContext
*dc
)
2222 int memsize
= memsize_z(dc
);
2224 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2225 memsize_char(memsize
),
2226 dc
->op1
, dc
->postinc
? "+]" : "]",
2229 cris_alu_m_alloc_temps(t
);
2231 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2232 cris_cc_mask(dc
, CC_MASK_NZVC
);
2233 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2234 do_postinc(dc
, memsize
);
2235 cris_alu_m_free_temps(t
);
2239 static int dec_subs_m(CPUCRISState
*env
, DisasContext
*dc
)
2242 int memsize
= memsize_z(dc
);
2244 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2245 memsize_char(memsize
),
2246 dc
->op1
, dc
->postinc
? "+]" : "]",
2249 cris_alu_m_alloc_temps(t
);
2251 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2252 cris_cc_mask(dc
, CC_MASK_NZVC
);
2253 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2254 do_postinc(dc
, memsize
);
2255 cris_alu_m_free_temps(t
);
2259 static int dec_movu_m(CPUCRISState
*env
, DisasContext
*dc
)
2262 int memsize
= memsize_z(dc
);
2265 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2266 memsize_char(memsize
),
2267 dc
->op1
, dc
->postinc
? "+]" : "]",
2270 cris_alu_m_alloc_temps(t
);
2271 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2272 cris_cc_mask(dc
, CC_MASK_NZ
);
2273 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2274 do_postinc(dc
, memsize
);
2275 cris_alu_m_free_temps(t
);
2279 static int dec_cmpu_m(CPUCRISState
*env
, DisasContext
*dc
)
2282 int memsize
= memsize_z(dc
);
2284 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2285 memsize_char(memsize
),
2286 dc
->op1
, dc
->postinc
? "+]" : "]",
2289 cris_alu_m_alloc_temps(t
);
2290 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2291 cris_cc_mask(dc
, CC_MASK_NZVC
);
2292 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2293 do_postinc(dc
, memsize
);
2294 cris_alu_m_free_temps(t
);
2298 static int dec_cmps_m(CPUCRISState
*env
, DisasContext
*dc
)
2301 int memsize
= memsize_z(dc
);
2303 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2304 memsize_char(memsize
),
2305 dc
->op1
, dc
->postinc
? "+]" : "]",
2308 cris_alu_m_alloc_temps(t
);
2309 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2310 cris_cc_mask(dc
, CC_MASK_NZVC
);
2311 cris_alu(dc
, CC_OP_CMP
,
2312 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2314 do_postinc(dc
, memsize
);
2315 cris_alu_m_free_temps(t
);
2319 static int dec_cmp_m(CPUCRISState
*env
, DisasContext
*dc
)
2322 int memsize
= memsize_zz(dc
);
2324 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2325 memsize_char(memsize
),
2326 dc
->op1
, dc
->postinc
? "+]" : "]",
2329 cris_alu_m_alloc_temps(t
);
2330 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2331 cris_cc_mask(dc
, CC_MASK_NZVC
);
2332 cris_alu(dc
, CC_OP_CMP
,
2333 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2335 do_postinc(dc
, memsize
);
2336 cris_alu_m_free_temps(t
);
2340 static int dec_test_m(CPUCRISState
*env
, DisasContext
*dc
)
2343 int memsize
= memsize_zz(dc
);
2345 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2346 memsize_char(memsize
),
2347 dc
->op1
, dc
->postinc
? "+]" : "]",
2350 cris_evaluate_flags(dc
);
2352 cris_alu_m_alloc_temps(t
);
2353 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2354 cris_cc_mask(dc
, CC_MASK_NZ
);
2355 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
2357 cris_alu(dc
, CC_OP_CMP
,
2358 cpu_R
[dc
->op2
], t
[1], tcg_const_tl(0), memsize_zz(dc
));
2359 do_postinc(dc
, memsize
);
2360 cris_alu_m_free_temps(t
);
2364 static int dec_and_m(CPUCRISState
*env
, DisasContext
*dc
)
2367 int memsize
= memsize_zz(dc
);
2369 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2370 memsize_char(memsize
),
2371 dc
->op1
, dc
->postinc
? "+]" : "]",
2374 cris_alu_m_alloc_temps(t
);
2375 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2376 cris_cc_mask(dc
, CC_MASK_NZ
);
2377 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2378 do_postinc(dc
, memsize
);
2379 cris_alu_m_free_temps(t
);
2383 static int dec_add_m(CPUCRISState
*env
, DisasContext
*dc
)
2386 int memsize
= memsize_zz(dc
);
2388 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2389 memsize_char(memsize
),
2390 dc
->op1
, dc
->postinc
? "+]" : "]",
2393 cris_alu_m_alloc_temps(t
);
2394 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2395 cris_cc_mask(dc
, CC_MASK_NZVC
);
2396 cris_alu(dc
, CC_OP_ADD
,
2397 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2398 do_postinc(dc
, memsize
);
2399 cris_alu_m_free_temps(t
);
2403 static int dec_addo_m(CPUCRISState
*env
, DisasContext
*dc
)
2406 int memsize
= memsize_zz(dc
);
2408 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2409 memsize_char(memsize
),
2410 dc
->op1
, dc
->postinc
? "+]" : "]",
2413 cris_alu_m_alloc_temps(t
);
2414 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2415 cris_cc_mask(dc
, 0);
2416 cris_alu(dc
, CC_OP_ADD
, cpu_R
[R_ACR
], t
[0], t
[1], 4);
2417 do_postinc(dc
, memsize
);
2418 cris_alu_m_free_temps(t
);
2422 static int dec_bound_m(CPUCRISState
*env
, DisasContext
*dc
)
2425 int memsize
= memsize_zz(dc
);
2427 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2428 memsize_char(memsize
),
2429 dc
->op1
, dc
->postinc
? "+]" : "]",
2432 l
[0] = tcg_temp_local_new();
2433 l
[1] = tcg_temp_local_new();
2434 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, l
[0], l
[1]);
2435 cris_cc_mask(dc
, CC_MASK_NZ
);
2436 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], l
[0], l
[1], 4);
2437 do_postinc(dc
, memsize
);
2438 tcg_temp_free(l
[0]);
2439 tcg_temp_free(l
[1]);
2443 static int dec_addc_mr(CPUCRISState
*env
, DisasContext
*dc
)
2447 LOG_DIS("addc [$r%u%s, $r%u\n",
2448 dc
->op1
, dc
->postinc
? "+]" : "]",
2451 cris_evaluate_flags(dc
);
2453 /* Set for this insn. */
2454 dc
->flagx_known
= 1;
2455 dc
->flags_x
= X_FLAG
;
2457 cris_alu_m_alloc_temps(t
);
2458 insn_len
= dec_prep_alu_m(env
, dc
, 0, 4, t
[0], t
[1]);
2459 cris_cc_mask(dc
, CC_MASK_NZVC
);
2460 cris_alu(dc
, CC_OP_ADDC
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
2462 cris_alu_m_free_temps(t
);
2466 static int dec_sub_m(CPUCRISState
*env
, DisasContext
*dc
)
2469 int memsize
= memsize_zz(dc
);
2471 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2472 memsize_char(memsize
),
2473 dc
->op1
, dc
->postinc
? "+]" : "]",
2474 dc
->op2
, dc
->ir
, dc
->zzsize
);
2476 cris_alu_m_alloc_temps(t
);
2477 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2478 cris_cc_mask(dc
, CC_MASK_NZVC
);
2479 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize
);
2480 do_postinc(dc
, memsize
);
2481 cris_alu_m_free_temps(t
);
2485 static int dec_or_m(CPUCRISState
*env
, DisasContext
*dc
)
2488 int memsize
= memsize_zz(dc
);
2490 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2491 memsize_char(memsize
),
2492 dc
->op1
, dc
->postinc
? "+]" : "]",
2495 cris_alu_m_alloc_temps(t
);
2496 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2497 cris_cc_mask(dc
, CC_MASK_NZ
);
2498 cris_alu(dc
, CC_OP_OR
,
2499 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2500 do_postinc(dc
, memsize
);
2501 cris_alu_m_free_temps(t
);
2505 static int dec_move_mp(CPUCRISState
*env
, DisasContext
*dc
)
2508 int memsize
= memsize_zz(dc
);
2511 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2512 memsize_char(memsize
),
2514 dc
->postinc
? "+]" : "]",
2517 cris_alu_m_alloc_temps(t
);
2518 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2519 cris_cc_mask(dc
, 0);
2520 if (dc
->op2
== PR_CCS
) {
2521 cris_evaluate_flags(dc
);
2522 if (dc
->tb_flags
& U_FLAG
) {
2523 /* User space is not allowed to touch all flags. */
2524 tcg_gen_andi_tl(t
[1], t
[1], 0x39f);
2525 tcg_gen_andi_tl(t
[0], cpu_PR
[PR_CCS
], ~0x39f);
2526 tcg_gen_or_tl(t
[1], t
[0], t
[1]);
2530 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[1]);
2532 do_postinc(dc
, memsize
);
2533 cris_alu_m_free_temps(t
);
2537 static int dec_move_pm(CPUCRISState
*env
, DisasContext
*dc
)
2542 memsize
= preg_sizes
[dc
->op2
];
2544 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2545 memsize_char(memsize
),
2546 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]");
2548 /* prepare store. Address in T0, value in T1. */
2549 if (dc
->op2
== PR_CCS
) {
2550 cris_evaluate_flags(dc
);
2552 t0
= tcg_temp_new();
2553 t_gen_mov_TN_preg(t0
, dc
->op2
);
2554 cris_flush_cc_state(dc
);
2555 gen_store(dc
, cpu_R
[dc
->op1
], t0
, memsize
);
2558 cris_cc_mask(dc
, 0);
2560 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2565 static int dec_movem_mr(CPUCRISState
*env
, DisasContext
*dc
)
2571 int nr
= dc
->op2
+ 1;
2573 LOG_DIS("movem [$r%u%s, $r%u\n", dc
->op1
,
2574 dc
->postinc
? "+]" : "]", dc
->op2
);
2576 addr
= tcg_temp_new();
2577 /* There are probably better ways of doing this. */
2578 cris_flush_cc_state(dc
);
2579 for (i
= 0; i
< (nr
>> 1); i
++) {
2580 tmp
[i
] = tcg_temp_new_i64();
2581 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2582 gen_load64(dc
, tmp
[i
], addr
);
2585 tmp32
= tcg_temp_new_i32();
2586 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2587 gen_load(dc
, tmp32
, addr
, 4, 0);
2591 tcg_temp_free(addr
);
2593 for (i
= 0; i
< (nr
>> 1); i
++) {
2594 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2], tmp
[i
]);
2595 tcg_gen_shri_i64(tmp
[i
], tmp
[i
], 32);
2596 tcg_gen_extrl_i64_i32(cpu_R
[i
* 2 + 1], tmp
[i
]);
2597 tcg_temp_free_i64(tmp
[i
]);
2600 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tmp32
);
2601 tcg_temp_free(tmp32
);
2604 /* writeback the updated pointer value. */
2606 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], nr
* 4);
2609 /* gen_load might want to evaluate the previous insns flags. */
2610 cris_cc_mask(dc
, 0);
2614 static int dec_movem_rm(CPUCRISState
*env
, DisasContext
*dc
)
2620 LOG_DIS("movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
2621 dc
->postinc
? "+]" : "]");
2623 cris_flush_cc_state(dc
);
2625 tmp
= tcg_temp_new();
2626 addr
= tcg_temp_new();
2627 tcg_gen_movi_tl(tmp
, 4);
2628 tcg_gen_mov_tl(addr
, cpu_R
[dc
->op1
]);
2629 for (i
= 0; i
<= dc
->op2
; i
++) {
2630 /* Displace addr. */
2631 /* Perform the store. */
2632 gen_store(dc
, addr
, cpu_R
[i
], 4);
2633 tcg_gen_add_tl(addr
, addr
, tmp
);
2636 tcg_gen_mov_tl(cpu_R
[dc
->op1
], addr
);
2638 cris_cc_mask(dc
, 0);
2640 tcg_temp_free(addr
);
2644 static int dec_move_rm(CPUCRISState
*env
, DisasContext
*dc
)
2648 memsize
= memsize_zz(dc
);
2650 LOG_DIS("move.%c $r%u, [$r%u]\n",
2651 memsize_char(memsize
), dc
->op2
, dc
->op1
);
2653 /* prepare store. */
2654 cris_flush_cc_state(dc
);
2655 gen_store(dc
, cpu_R
[dc
->op1
], cpu_R
[dc
->op2
], memsize
);
2658 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2660 cris_cc_mask(dc
, 0);
2664 static int dec_lapcq(CPUCRISState
*env
, DisasContext
*dc
)
2666 LOG_DIS("lapcq %x, $r%u\n",
2667 dc
->pc
+ dc
->op1
*2, dc
->op2
);
2668 cris_cc_mask(dc
, 0);
2669 tcg_gen_movi_tl(cpu_R
[dc
->op2
], dc
->pc
+ dc
->op1
* 2);
2673 static int dec_lapc_im(CPUCRISState
*env
, DisasContext
*dc
)
2681 cris_cc_mask(dc
, 0);
2682 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2683 LOG_DIS("lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
);
2687 tcg_gen_movi_tl(cpu_R
[rd
], pc
);
2691 /* Jump to special reg. */
2692 static int dec_jump_p(CPUCRISState
*env
, DisasContext
*dc
)
2694 LOG_DIS("jump $p%u\n", dc
->op2
);
2696 if (dc
->op2
== PR_CCS
) {
2697 cris_evaluate_flags(dc
);
2699 t_gen_mov_TN_preg(env_btarget
, dc
->op2
);
2700 /* rete will often have low bit set to indicate delayslot. */
2701 tcg_gen_andi_tl(env_btarget
, env_btarget
, ~1);
2702 cris_cc_mask(dc
, 0);
2703 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2707 /* Jump and save. */
2708 static int dec_jas_r(CPUCRISState
*env
, DisasContext
*dc
)
2710 LOG_DIS("jas $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2711 cris_cc_mask(dc
, 0);
2712 /* Store the return address in Pd. */
2713 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2717 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4));
2719 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2723 static int dec_jas_im(CPUCRISState
*env
, DisasContext
*dc
)
2727 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2729 LOG_DIS("jas 0x%x\n", imm
);
2730 cris_cc_mask(dc
, 0);
2731 /* Store the return address in Pd. */
2732 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2735 cris_prepare_jmp(dc
, JMP_DIRECT
);
2739 static int dec_jasc_im(CPUCRISState
*env
, DisasContext
*dc
)
2743 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2745 LOG_DIS("jasc 0x%x\n", imm
);
2746 cris_cc_mask(dc
, 0);
2747 /* Store the return address in Pd. */
2748 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8 + 4));
2751 cris_prepare_jmp(dc
, JMP_DIRECT
);
2755 static int dec_jasc_r(CPUCRISState
*env
, DisasContext
*dc
)
2757 LOG_DIS("jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2758 cris_cc_mask(dc
, 0);
2759 /* Store the return address in Pd. */
2760 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2761 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4 + 4));
2762 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2766 static int dec_bcc_im(CPUCRISState
*env
, DisasContext
*dc
)
2769 uint32_t cond
= dc
->op2
;
2771 offset
= cris_fetch(env
, dc
, dc
->pc
+ 2, 2, 1);
2773 LOG_DIS("b%s %d pc=%x dst=%x\n",
2774 cc_name(cond
), offset
,
2775 dc
->pc
, dc
->pc
+ offset
);
2777 cris_cc_mask(dc
, 0);
2778 /* op2 holds the condition-code. */
2779 cris_prepare_cc_branch(dc
, offset
, cond
);
2783 static int dec_bas_im(CPUCRISState
*env
, DisasContext
*dc
)
2787 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2789 LOG_DIS("bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2790 cris_cc_mask(dc
, 0);
2791 /* Store the return address in Pd. */
2792 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2794 dc
->jmp_pc
= dc
->pc
+ simm
;
2795 cris_prepare_jmp(dc
, JMP_DIRECT
);
2799 static int dec_basc_im(CPUCRISState
*env
, DisasContext
*dc
)
2802 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2804 LOG_DIS("basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2805 cris_cc_mask(dc
, 0);
2806 /* Store the return address in Pd. */
2807 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 12));
2809 dc
->jmp_pc
= dc
->pc
+ simm
;
2810 cris_prepare_jmp(dc
, JMP_DIRECT
);
2814 static int dec_rfe_etc(CPUCRISState
*env
, DisasContext
*dc
)
2816 cris_cc_mask(dc
, 0);
2818 if (dc
->op2
== 15) {
2819 tcg_gen_st_i32(tcg_const_i32(1), cpu_env
,
2820 -offsetof(CRISCPU
, env
) + offsetof(CPUState
, halted
));
2821 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2822 t_gen_raise_exception(EXCP_HLT
);
2826 switch (dc
->op2
& 7) {
2830 cris_evaluate_flags(dc
);
2831 gen_helper_rfe(cpu_env
);
2832 dc
->is_jmp
= DISAS_UPDATE
;
2837 cris_evaluate_flags(dc
);
2838 gen_helper_rfn(cpu_env
);
2839 dc
->is_jmp
= DISAS_UPDATE
;
2842 LOG_DIS("break %d\n", dc
->op1
);
2843 cris_evaluate_flags(dc
);
2845 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2847 /* Breaks start at 16 in the exception vector. */
2848 t_gen_mov_env_TN(trap_vector
,
2849 tcg_const_tl(dc
->op1
+ 16));
2850 t_gen_raise_exception(EXCP_BREAK
);
2851 dc
->is_jmp
= DISAS_UPDATE
;
2854 printf("op2=%x\n", dc
->op2
);
2862 static int dec_ftag_fidx_d_m(CPUCRISState
*env
, DisasContext
*dc
)
2867 static int dec_ftag_fidx_i_m(CPUCRISState
*env
, DisasContext
*dc
)
2872 static int QEMU_NORETURN
dec_null(CPUCRISState
*env
, DisasContext
*dc
)
2874 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2875 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2880 static struct decoder_info
{
2885 int (*dec
)(CPUCRISState
*env
, DisasContext
*dc
);
2887 /* Order matters here. */
2888 {DEC_MOVEQ
, dec_moveq
},
2889 {DEC_BTSTQ
, dec_btstq
},
2890 {DEC_CMPQ
, dec_cmpq
},
2891 {DEC_ADDOQ
, dec_addoq
},
2892 {DEC_ADDQ
, dec_addq
},
2893 {DEC_SUBQ
, dec_subq
},
2894 {DEC_ANDQ
, dec_andq
},
2896 {DEC_ASRQ
, dec_asrq
},
2897 {DEC_LSLQ
, dec_lslq
},
2898 {DEC_LSRQ
, dec_lsrq
},
2899 {DEC_BCCQ
, dec_bccq
},
2901 {DEC_BCC_IM
, dec_bcc_im
},
2902 {DEC_JAS_IM
, dec_jas_im
},
2903 {DEC_JAS_R
, dec_jas_r
},
2904 {DEC_JASC_IM
, dec_jasc_im
},
2905 {DEC_JASC_R
, dec_jasc_r
},
2906 {DEC_BAS_IM
, dec_bas_im
},
2907 {DEC_BASC_IM
, dec_basc_im
},
2908 {DEC_JUMP_P
, dec_jump_p
},
2909 {DEC_LAPC_IM
, dec_lapc_im
},
2910 {DEC_LAPCQ
, dec_lapcq
},
2912 {DEC_RFE_ETC
, dec_rfe_etc
},
2913 {DEC_ADDC_MR
, dec_addc_mr
},
2915 {DEC_MOVE_MP
, dec_move_mp
},
2916 {DEC_MOVE_PM
, dec_move_pm
},
2917 {DEC_MOVEM_MR
, dec_movem_mr
},
2918 {DEC_MOVEM_RM
, dec_movem_rm
},
2919 {DEC_MOVE_PR
, dec_move_pr
},
2920 {DEC_SCC_R
, dec_scc_r
},
2921 {DEC_SETF
, dec_setclrf
},
2922 {DEC_CLEARF
, dec_setclrf
},
2924 {DEC_MOVE_SR
, dec_move_sr
},
2925 {DEC_MOVE_RP
, dec_move_rp
},
2926 {DEC_SWAP_R
, dec_swap_r
},
2927 {DEC_ABS_R
, dec_abs_r
},
2928 {DEC_LZ_R
, dec_lz_r
},
2929 {DEC_MOVE_RS
, dec_move_rs
},
2930 {DEC_BTST_R
, dec_btst_r
},
2931 {DEC_ADDC_R
, dec_addc_r
},
2933 {DEC_DSTEP_R
, dec_dstep_r
},
2934 {DEC_XOR_R
, dec_xor_r
},
2935 {DEC_MCP_R
, dec_mcp_r
},
2936 {DEC_CMP_R
, dec_cmp_r
},
2938 {DEC_ADDI_R
, dec_addi_r
},
2939 {DEC_ADDI_ACR
, dec_addi_acr
},
2941 {DEC_ADD_R
, dec_add_r
},
2942 {DEC_SUB_R
, dec_sub_r
},
2944 {DEC_ADDU_R
, dec_addu_r
},
2945 {DEC_ADDS_R
, dec_adds_r
},
2946 {DEC_SUBU_R
, dec_subu_r
},
2947 {DEC_SUBS_R
, dec_subs_r
},
2948 {DEC_LSL_R
, dec_lsl_r
},
2950 {DEC_AND_R
, dec_and_r
},
2951 {DEC_OR_R
, dec_or_r
},
2952 {DEC_BOUND_R
, dec_bound_r
},
2953 {DEC_ASR_R
, dec_asr_r
},
2954 {DEC_LSR_R
, dec_lsr_r
},
2956 {DEC_MOVU_R
, dec_movu_r
},
2957 {DEC_MOVS_R
, dec_movs_r
},
2958 {DEC_NEG_R
, dec_neg_r
},
2959 {DEC_MOVE_R
, dec_move_r
},
2961 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
2962 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
2964 {DEC_MULS_R
, dec_muls_r
},
2965 {DEC_MULU_R
, dec_mulu_r
},
2967 {DEC_ADDU_M
, dec_addu_m
},
2968 {DEC_ADDS_M
, dec_adds_m
},
2969 {DEC_SUBU_M
, dec_subu_m
},
2970 {DEC_SUBS_M
, dec_subs_m
},
2972 {DEC_CMPU_M
, dec_cmpu_m
},
2973 {DEC_CMPS_M
, dec_cmps_m
},
2974 {DEC_MOVU_M
, dec_movu_m
},
2975 {DEC_MOVS_M
, dec_movs_m
},
2977 {DEC_CMP_M
, dec_cmp_m
},
2978 {DEC_ADDO_M
, dec_addo_m
},
2979 {DEC_BOUND_M
, dec_bound_m
},
2980 {DEC_ADD_M
, dec_add_m
},
2981 {DEC_SUB_M
, dec_sub_m
},
2982 {DEC_AND_M
, dec_and_m
},
2983 {DEC_OR_M
, dec_or_m
},
2984 {DEC_MOVE_RM
, dec_move_rm
},
2985 {DEC_TEST_M
, dec_test_m
},
2986 {DEC_MOVE_MR
, dec_move_mr
},
2991 static unsigned int crisv32_decoder(CPUCRISState
*env
, DisasContext
*dc
)
2996 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
2997 tcg_gen_debug_insn_start(dc
->pc
);
3000 /* Load a halfword onto the instruction register. */
3001 dc
->ir
= cris_fetch(env
, dc
, dc
->pc
, 2, 0);
3003 /* Now decode it. */
3004 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
3005 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
3006 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
3007 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
3008 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
3009 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
3011 /* Large switch for all insns. */
3012 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
3013 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
3014 insn_len
= decinfo
[i
].dec(env
, dc
);
3019 #if !defined(CONFIG_USER_ONLY)
3020 /* Single-stepping ? */
3021 if (dc
->tb_flags
& S_FLAG
) {
3022 TCGLabel
*l1
= gen_new_label();
3023 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_PR
[PR_SPC
], dc
->pc
, l1
);
3024 /* We treat SPC as a break with an odd trap vector. */
3025 cris_evaluate_flags(dc
);
3026 t_gen_mov_env_TN(trap_vector
, tcg_const_tl(3));
3027 tcg_gen_movi_tl(env_pc
, dc
->pc
+ insn_len
);
3028 tcg_gen_movi_tl(cpu_PR
[PR_SPC
], dc
->pc
+ insn_len
);
3029 t_gen_raise_exception(EXCP_BREAK
);
3036 static void check_breakpoint(CPUCRISState
*env
, DisasContext
*dc
)
3038 CPUState
*cs
= CPU(cris_env_get_cpu(env
));
3041 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
3042 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
3043 if (bp
->pc
== dc
->pc
) {
3044 cris_evaluate_flags(dc
);
3045 tcg_gen_movi_tl(env_pc
, dc
->pc
);
3046 t_gen_raise_exception(EXCP_DEBUG
);
3047 dc
->is_jmp
= DISAS_UPDATE
;
3053 #include "translate_v10.c"
3056 * Delay slots on QEMU/CRIS.
3058 * If an exception hits on a delayslot, the core will let ERP (the Exception
3059 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3060 * to give SW a hint that the exception actually hit on the dslot.
3062 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3063 * the core and any jmp to an odd addresses will mask off that lsb. It is
3064 * simply there to let sw know there was an exception on a dslot.
3066 * When the software returns from an exception, the branch will re-execute.
3067 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3068 * and the branch and delayslot dont share pages.
3070 * The TB contaning the branch insn will set up env->btarget and evaluate
3071 * env->btaken. When the translation loop exits we will note that the branch
3072 * sequence is broken and let env->dslot be the size of the branch insn (those
3075 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3076 * set). It will also expect to have env->dslot setup with the size of the
3077 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3078 * will execute the dslot and take the branch, either to btarget or just one
3081 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3082 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3083 * branch and set lsb). Then env->dslot gets cleared so that the exception
3084 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3085 * masked off and we will reexecute the branch insn.
3089 /* generate intermediate code for basic block 'tb'. */
3091 gen_intermediate_code_internal(CRISCPU
*cpu
, TranslationBlock
*tb
,
3094 CPUState
*cs
= CPU(cpu
);
3095 CPUCRISState
*env
= &cpu
->env
;
3097 unsigned int insn_len
;
3099 struct DisasContext ctx
;
3100 struct DisasContext
*dc
= &ctx
;
3101 uint32_t next_page_start
;
3106 if (env
->pregs
[PR_VR
] == 32) {
3107 dc
->decoder
= crisv32_decoder
;
3108 dc
->clear_locked_irq
= 0;
3110 dc
->decoder
= crisv10_decoder
;
3111 dc
->clear_locked_irq
= 1;
3114 /* Odd PC indicates that branch is rexecuting due to exception in the
3115 * delayslot, like in real hw.
3117 pc_start
= tb
->pc
& ~1;
3121 dc
->is_jmp
= DISAS_NEXT
;
3124 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3125 dc
->flags_uptodate
= 1;
3126 dc
->flagx_known
= 1;
3127 dc
->flags_x
= tb
->flags
& X_FLAG
;
3128 dc
->cc_x_uptodate
= 0;
3131 dc
->clear_prefix
= 0;
3133 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
3134 dc
->cc_size_uptodate
= -1;
3136 /* Decode TB flags. */
3137 dc
->tb_flags
= tb
->flags
& (S_FLAG
| P_FLAG
| U_FLAG \
3138 | X_FLAG
| PFIX_FLAG
);
3139 dc
->delayed_branch
= !!(tb
->flags
& 7);
3140 if (dc
->delayed_branch
) {
3141 dc
->jmp
= JMP_INDIRECT
;
3143 dc
->jmp
= JMP_NOJMP
;
3146 dc
->cpustate_changed
= 0;
3148 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3150 "srch=%d pc=%x %x flg=%" PRIx64
" bt=%x ds=%u ccs=%x\n"
3156 search_pc
, dc
->pc
, dc
->ppc
,
3157 (uint64_t)tb
->flags
,
3158 env
->btarget
, (unsigned)tb
->flags
& 7,
3160 env
->pregs
[PR_PID
], env
->pregs
[PR_USP
],
3161 env
->regs
[0], env
->regs
[1], env
->regs
[2], env
->regs
[3],
3162 env
->regs
[4], env
->regs
[5], env
->regs
[6], env
->regs
[7],
3163 env
->regs
[8], env
->regs
[9],
3164 env
->regs
[10], env
->regs
[11],
3165 env
->regs
[12], env
->regs
[13],
3166 env
->regs
[14], env
->regs
[15]);
3167 qemu_log("--------------\n");
3168 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3171 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3174 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3175 if (max_insns
== 0) {
3176 max_insns
= CF_COUNT_MASK
;
3181 check_breakpoint(env
, dc
);
3184 j
= tcg_op_buf_count();
3188 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
3191 if (dc
->delayed_branch
== 1) {
3192 tcg_ctx
.gen_opc_pc
[lj
] = dc
->ppc
| 1;
3194 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
3196 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
3197 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
3201 LOG_DIS("%8.8x:\t", dc
->pc
);
3203 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3208 insn_len
= dc
->decoder(env
, dc
);
3212 cris_clear_x_flag(dc
);
3216 /* Check for delayed branches here. If we do it before
3217 actually generating any host code, the simulator will just
3218 loop doing nothing for on this program location. */
3219 if (dc
->delayed_branch
) {
3220 dc
->delayed_branch
--;
3221 if (dc
->delayed_branch
== 0) {
3222 if (tb
->flags
& 7) {
3223 t_gen_mov_env_TN(dslot
, tcg_const_tl(0));
3225 if (dc
->cpustate_changed
|| !dc
->flagx_known
3226 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
))) {
3227 cris_store_direct_jmp(dc
);
3230 if (dc
->clear_locked_irq
) {
3231 dc
->clear_locked_irq
= 0;
3232 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3235 if (dc
->jmp
== JMP_DIRECT_CC
) {
3236 TCGLabel
*l1
= gen_new_label();
3237 cris_evaluate_flags(dc
);
3239 /* Conditional jmp. */
3240 tcg_gen_brcondi_tl(TCG_COND_EQ
,
3242 gen_goto_tb(dc
, 1, dc
->jmp_pc
);
3244 gen_goto_tb(dc
, 0, dc
->pc
);
3245 dc
->is_jmp
= DISAS_TB_JUMP
;
3246 dc
->jmp
= JMP_NOJMP
;
3247 } else if (dc
->jmp
== JMP_DIRECT
) {
3248 cris_evaluate_flags(dc
);
3249 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
3250 dc
->is_jmp
= DISAS_TB_JUMP
;
3251 dc
->jmp
= JMP_NOJMP
;
3253 t_gen_cc_jmp(env_btarget
, tcg_const_tl(dc
->pc
));
3254 dc
->is_jmp
= DISAS_JUMP
;
3260 /* If we are rexecuting a branch due to exceptions on
3261 delay slots dont break. */
3262 if (!(tb
->pc
& 1) && cs
->singlestep_enabled
) {
3265 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
3266 && !tcg_op_buf_full()
3268 && (dc
->pc
< next_page_start
)
3269 && num_insns
< max_insns
);
3271 if (dc
->clear_locked_irq
) {
3272 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3277 if (tb
->cflags
& CF_LAST_IO
)
3279 /* Force an update if the per-tb cpu state has changed. */
3280 if (dc
->is_jmp
== DISAS_NEXT
3281 && (dc
->cpustate_changed
|| !dc
->flagx_known
3282 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
)))) {
3283 dc
->is_jmp
= DISAS_UPDATE
;
3284 tcg_gen_movi_tl(env_pc
, npc
);
3286 /* Broken branch+delayslot sequence. */
3287 if (dc
->delayed_branch
== 1) {
3288 /* Set env->dslot to the size of the branch insn. */
3289 t_gen_mov_env_TN(dslot
, tcg_const_tl(dc
->pc
- dc
->ppc
));
3290 cris_store_direct_jmp(dc
);
3293 cris_evaluate_flags(dc
);
3295 if (unlikely(cs
->singlestep_enabled
)) {
3296 if (dc
->is_jmp
== DISAS_NEXT
) {
3297 tcg_gen_movi_tl(env_pc
, npc
);
3299 t_gen_raise_exception(EXCP_DEBUG
);
3301 switch (dc
->is_jmp
) {
3303 gen_goto_tb(dc
, 1, npc
);
3308 /* indicate that the hash table must be used
3309 to find the next TB */
3314 /* nothing more to generate */
3318 gen_tb_end(tb
, num_insns
);
3321 j
= tcg_op_buf_count();
3324 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
3327 tb
->size
= dc
->pc
- pc_start
;
3328 tb
->icount
= num_insns
;
3333 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3334 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
3336 qemu_log("\nisize=%d osize=%d\n",
3337 dc
->pc
- pc_start
, tcg_op_buf_count());
3343 void gen_intermediate_code (CPUCRISState
*env
, struct TranslationBlock
*tb
)
3345 gen_intermediate_code_internal(cris_env_get_cpu(env
), tb
, false);
3348 void gen_intermediate_code_pc (CPUCRISState
*env
, struct TranslationBlock
*tb
)
3350 gen_intermediate_code_internal(cris_env_get_cpu(env
), tb
, true);
3353 void cris_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3356 CRISCPU
*cpu
= CRIS_CPU(cs
);
3357 CPUCRISState
*env
= &cpu
->env
;
3365 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3366 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3367 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
3369 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
);
3372 for (i
= 0; i
< 16; i
++) {
3373 cpu_fprintf(f
, "%s=%8.8x ", regnames
[i
], env
->regs
[i
]);
3374 if ((i
+ 1) % 4 == 0) {
3375 cpu_fprintf(f
, "\n");
3378 cpu_fprintf(f
, "\nspecial regs:\n");
3379 for (i
= 0; i
< 16; i
++) {
3380 cpu_fprintf(f
, "%s=%8.8x ", pregnames
[i
], env
->pregs
[i
]);
3381 if ((i
+ 1) % 4 == 0) {
3382 cpu_fprintf(f
, "\n");
3385 srs
= env
->pregs
[PR_SRS
];
3386 cpu_fprintf(f
, "\nsupport function regs bank %x:\n", srs
);
3387 if (srs
< ARRAY_SIZE(env
->sregs
)) {
3388 for (i
= 0; i
< 16; i
++) {
3389 cpu_fprintf(f
, "s%2.2d=%8.8x ",
3390 i
, env
->sregs
[srs
][i
]);
3391 if ((i
+ 1) % 4 == 0) {
3392 cpu_fprintf(f
, "\n");
3396 cpu_fprintf(f
, "\n\n");
3400 void cris_initialize_tcg(void)
3404 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
3405 cc_x
= tcg_global_mem_new(TCG_AREG0
,
3406 offsetof(CPUCRISState
, cc_x
), "cc_x");
3407 cc_src
= tcg_global_mem_new(TCG_AREG0
,
3408 offsetof(CPUCRISState
, cc_src
), "cc_src");
3409 cc_dest
= tcg_global_mem_new(TCG_AREG0
,
3410 offsetof(CPUCRISState
, cc_dest
),
3412 cc_result
= tcg_global_mem_new(TCG_AREG0
,
3413 offsetof(CPUCRISState
, cc_result
),
3415 cc_op
= tcg_global_mem_new(TCG_AREG0
,
3416 offsetof(CPUCRISState
, cc_op
), "cc_op");
3417 cc_size
= tcg_global_mem_new(TCG_AREG0
,
3418 offsetof(CPUCRISState
, cc_size
),
3420 cc_mask
= tcg_global_mem_new(TCG_AREG0
,
3421 offsetof(CPUCRISState
, cc_mask
),
3424 env_pc
= tcg_global_mem_new(TCG_AREG0
,
3425 offsetof(CPUCRISState
, pc
),
3427 env_btarget
= tcg_global_mem_new(TCG_AREG0
,
3428 offsetof(CPUCRISState
, btarget
),
3430 env_btaken
= tcg_global_mem_new(TCG_AREG0
,
3431 offsetof(CPUCRISState
, btaken
),
3433 for (i
= 0; i
< 16; i
++) {
3434 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
3435 offsetof(CPUCRISState
, regs
[i
]),
3438 for (i
= 0; i
< 16; i
++) {
3439 cpu_PR
[i
] = tcg_global_mem_new(TCG_AREG0
,
3440 offsetof(CPUCRISState
, pregs
[i
]),
3445 void restore_state_to_opc(CPUCRISState
*env
, TranslationBlock
*tb
, int pc_pos
)
3447 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];