3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
12 #include <zlib.h> /* For crc32 */
13 #include "exec/semihost.h"
15 #ifndef CONFIG_USER_ONLY
16 static inline bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
17 int access_type
, ARMMMUIdx mmu_idx
,
18 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
19 target_ulong
*page_size
, uint32_t *fsr
);
21 /* Definitions for the PMCCNTR and PMCR registers */
27 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
31 /* VFP data registers are always little-endian. */
32 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
34 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
37 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
38 /* Aliases for Q regs. */
41 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
42 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
46 switch (reg
- nregs
) {
47 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
48 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
49 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
54 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
58 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
60 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
63 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
66 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
67 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
71 switch (reg
- nregs
) {
72 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
73 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
74 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
79 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
83 /* 128 bit FP register */
84 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
85 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
89 stl_p(buf
, vfp_get_fpsr(env
));
93 stl_p(buf
, vfp_get_fpcr(env
));
100 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
104 /* 128 bit FP register */
105 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
106 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
110 vfp_set_fpsr(env
, ldl_p(buf
));
114 vfp_set_fpcr(env
, ldl_p(buf
));
121 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
123 assert(ri
->fieldoffset
);
124 if (cpreg_field_is_64bit(ri
)) {
125 return CPREG_FIELD64(env
, ri
);
127 return CPREG_FIELD32(env
, ri
);
131 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
134 assert(ri
->fieldoffset
);
135 if (cpreg_field_is_64bit(ri
)) {
136 CPREG_FIELD64(env
, ri
) = value
;
138 CPREG_FIELD32(env
, ri
) = value
;
142 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
144 return (char *)env
+ ri
->fieldoffset
;
147 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
149 /* Raw read of a coprocessor register (as needed for migration, etc). */
150 if (ri
->type
& ARM_CP_CONST
) {
151 return ri
->resetvalue
;
152 } else if (ri
->raw_readfn
) {
153 return ri
->raw_readfn(env
, ri
);
154 } else if (ri
->readfn
) {
155 return ri
->readfn(env
, ri
);
157 return raw_read(env
, ri
);
161 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
164 /* Raw write of a coprocessor register (as needed for migration, etc).
165 * Note that constant registers are treated as write-ignored; the
166 * caller should check for success by whether a readback gives the
169 if (ri
->type
& ARM_CP_CONST
) {
171 } else if (ri
->raw_writefn
) {
172 ri
->raw_writefn(env
, ri
, v
);
173 } else if (ri
->writefn
) {
174 ri
->writefn(env
, ri
, v
);
176 raw_write(env
, ri
, v
);
180 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
182 /* Return true if the regdef would cause an assertion if you called
183 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
184 * program bug for it not to have the NO_RAW flag).
185 * NB that returning false here doesn't necessarily mean that calling
186 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
187 * read/write access functions which are safe for raw use" from "has
188 * read/write access functions which have side effects but has forgotten
189 * to provide raw access functions".
190 * The tests here line up with the conditions in read/write_raw_cp_reg()
191 * and assertions in raw_read()/raw_write().
193 if ((ri
->type
& ARM_CP_CONST
) ||
195 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
201 bool write_cpustate_to_list(ARMCPU
*cpu
)
203 /* Write the coprocessor state from cpu->env to the (index,value) list. */
207 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
208 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
209 const ARMCPRegInfo
*ri
;
211 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
216 if (ri
->type
& ARM_CP_NO_RAW
) {
219 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
224 bool write_list_to_cpustate(ARMCPU
*cpu
)
229 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
230 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
231 uint64_t v
= cpu
->cpreg_values
[i
];
232 const ARMCPRegInfo
*ri
;
234 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
239 if (ri
->type
& ARM_CP_NO_RAW
) {
242 /* Write value and confirm it reads back as written
243 * (to catch read-only registers and partially read-only
244 * registers where the incoming migration value doesn't match)
246 write_raw_cp_reg(&cpu
->env
, ri
, v
);
247 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
254 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
256 ARMCPU
*cpu
= opaque
;
258 const ARMCPRegInfo
*ri
;
260 regidx
= *(uint32_t *)key
;
261 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
263 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
264 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
265 /* The value array need not be initialized at this point */
266 cpu
->cpreg_array_len
++;
270 static void count_cpreg(gpointer key
, gpointer opaque
)
272 ARMCPU
*cpu
= opaque
;
274 const ARMCPRegInfo
*ri
;
276 regidx
= *(uint32_t *)key
;
277 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
279 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
280 cpu
->cpreg_array_len
++;
284 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
286 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
287 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
298 void init_cpreg_list(ARMCPU
*cpu
)
300 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
301 * Note that we require cpreg_tuples[] to be sorted by key ID.
306 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
307 keys
= g_list_sort(keys
, cpreg_key_compare
);
309 cpu
->cpreg_array_len
= 0;
311 g_list_foreach(keys
, count_cpreg
, cpu
);
313 arraylen
= cpu
->cpreg_array_len
;
314 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
315 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
316 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
317 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
318 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
319 cpu
->cpreg_array_len
= 0;
321 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
323 assert(cpu
->cpreg_array_len
== arraylen
);
329 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
330 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
332 * access_el3_aa32ns: Used to check AArch32 register views.
333 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
335 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
336 const ARMCPRegInfo
*ri
)
338 bool secure
= arm_is_secure_below_el3(env
);
340 assert(!arm_el_is_aa64(env
, 3));
342 return CP_ACCESS_TRAP_UNCATEGORIZED
;
347 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
348 const ARMCPRegInfo
*ri
)
350 if (!arm_el_is_aa64(env
, 3)) {
351 return access_el3_aa32ns(env
, ri
);
356 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
358 ARMCPU
*cpu
= arm_env_get_cpu(env
);
360 raw_write(env
, ri
, value
);
361 tlb_flush(CPU(cpu
), 1); /* Flush TLB as domain not tracked in TLB */
364 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
366 ARMCPU
*cpu
= arm_env_get_cpu(env
);
368 if (raw_read(env
, ri
) != value
) {
369 /* Unlike real hardware the qemu TLB uses virtual addresses,
370 * not modified virtual addresses, so this causes a TLB flush.
372 tlb_flush(CPU(cpu
), 1);
373 raw_write(env
, ri
, value
);
377 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
380 ARMCPU
*cpu
= arm_env_get_cpu(env
);
382 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_MPU
)
383 && !extended_addresses_enabled(env
)) {
384 /* For VMSA (when not using the LPAE long descriptor page table
385 * format) this register includes the ASID, so do a TLB flush.
386 * For PMSA it is purely a process ID and no action is needed.
388 tlb_flush(CPU(cpu
), 1);
390 raw_write(env
, ri
, value
);
393 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
396 /* Invalidate all (TLBIALL) */
397 ARMCPU
*cpu
= arm_env_get_cpu(env
);
399 tlb_flush(CPU(cpu
), 1);
402 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
405 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
406 ARMCPU
*cpu
= arm_env_get_cpu(env
);
408 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
411 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 /* Invalidate by ASID (TLBIASID) */
415 ARMCPU
*cpu
= arm_env_get_cpu(env
);
417 tlb_flush(CPU(cpu
), value
== 0);
420 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
423 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
424 ARMCPU
*cpu
= arm_env_get_cpu(env
);
426 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
429 /* IS variants of TLB operations must affect all cores */
430 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
435 CPU_FOREACH(other_cs
) {
436 tlb_flush(other_cs
, 1);
440 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
445 CPU_FOREACH(other_cs
) {
446 tlb_flush(other_cs
, value
== 0);
450 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 CPU_FOREACH(other_cs
) {
456 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
460 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
465 CPU_FOREACH(other_cs
) {
466 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
470 static const ARMCPRegInfo cp_reginfo
[] = {
471 /* Define the secure and non-secure FCSE identifier CP registers
472 * separately because there is no secure bank in V8 (no _EL3). This allows
473 * the secure register to be properly reset and migrated. There is also no
474 * v8 EL1 version of the register so the non-secure instance stands alone.
476 { .name
= "FCSEIDR(NS)",
477 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
478 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
479 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
480 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
481 { .name
= "FCSEIDR(S)",
482 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
483 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
484 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
485 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
486 /* Define the secure and non-secure context identifier CP registers
487 * separately because there is no secure bank in V8 (no _EL3). This allows
488 * the secure register to be properly reset and migrated. In the
489 * non-secure case, the 32-bit register will have reset and migration
490 * disabled during registration as it is handled by the 64-bit instance.
492 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
493 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
494 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
495 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
496 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
497 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
498 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
499 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
500 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
501 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
505 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
506 /* NB: Some of these registers exist in v8 but with more precise
507 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
509 /* MMU Domain access control / MPU write buffer control */
511 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
512 .access
= PL1_RW
, .resetvalue
= 0,
513 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
514 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
515 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
516 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
517 * For v6 and v5, these mappings are overly broad.
519 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
520 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
521 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
522 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
523 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
524 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
525 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
526 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
527 /* Cache maintenance ops; some of this space may be overridden later. */
528 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
529 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
530 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
534 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
535 /* Not all pre-v6 cores implemented this WFI, so this is slightly
538 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
539 .access
= PL1_W
, .type
= ARM_CP_WFI
},
543 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
544 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
545 * is UNPREDICTABLE; we choose to NOP as most implementations do).
547 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
548 .access
= PL1_W
, .type
= ARM_CP_WFI
},
549 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
550 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
551 * OMAPCP will override this space.
553 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
554 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
556 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
557 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
559 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
560 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
561 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
563 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
564 * implementing it as RAZ means the "debug architecture version" bits
565 * will read as a reserved value, which should cause Linux to not try
566 * to use the debug hardware.
568 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
569 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
570 /* MMU TLB control. Note that the wildcarding means we cover not just
571 * the unified TLB ops but also the dside/iside/inner-shareable variants.
573 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
574 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
575 .type
= ARM_CP_NO_RAW
},
576 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
577 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
578 .type
= ARM_CP_NO_RAW
},
579 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
580 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
581 .type
= ARM_CP_NO_RAW
},
582 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
583 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
584 .type
= ARM_CP_NO_RAW
},
585 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
586 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
587 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
588 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
592 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
598 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
599 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
600 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
601 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
603 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
604 /* VFP coprocessor: cp10 & cp11 [23:20] */
605 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
607 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
608 /* ASEDIS [31] bit is RAO/WI */
612 /* VFPv3 and upwards with NEON implement 32 double precision
613 * registers (D0-D31).
615 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
616 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
617 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
623 env
->cp15
.cpacr_el1
= value
;
626 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
628 if (arm_feature(env
, ARM_FEATURE_V8
)) {
629 /* Check if CPACR accesses are to be trapped to EL2 */
630 if (arm_current_el(env
) == 1 &&
631 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
632 return CP_ACCESS_TRAP_EL2
;
633 /* Check if CPACR accesses are to be trapped to EL3 */
634 } else if (arm_current_el(env
) < 3 &&
635 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
636 return CP_ACCESS_TRAP_EL3
;
643 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
645 /* Check if CPTR accesses are set to trap to EL3 */
646 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
647 return CP_ACCESS_TRAP_EL3
;
653 static const ARMCPRegInfo v6_cp_reginfo
[] = {
654 /* prefetch by MVA in v6, NOP in v7 */
655 { .name
= "MVA_prefetch",
656 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
657 .access
= PL1_W
, .type
= ARM_CP_NOP
},
658 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
659 .access
= PL0_W
, .type
= ARM_CP_NOP
},
660 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
661 .access
= PL0_W
, .type
= ARM_CP_NOP
},
662 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
663 .access
= PL0_W
, .type
= ARM_CP_NOP
},
664 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
666 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
667 offsetof(CPUARMState
, cp15
.ifar_ns
) },
669 /* Watchpoint Fault Address Register : should actually only be present
670 * for 1136, 1176, 11MPCore.
672 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
673 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
674 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
675 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
676 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
677 .resetvalue
= 0, .writefn
= cpacr_write
},
681 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
683 /* Performance monitor registers user accessibility is controlled
686 if (arm_current_el(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
687 return CP_ACCESS_TRAP
;
692 #ifndef CONFIG_USER_ONLY
694 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
696 /* This does not support checking PMCCFILTR_EL0 register */
698 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
705 void pmccntr_sync(CPUARMState
*env
)
709 temp_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
710 get_ticks_per_sec(), 1000000);
712 if (env
->cp15
.c9_pmcr
& PMCRD
) {
713 /* Increment once every 64 processor clock cycles */
717 if (arm_ccnt_enabled(env
)) {
718 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
722 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
728 /* The counter has been reset */
729 env
->cp15
.c15_ccnt
= 0;
732 /* only the DP, X, D and E bits are writable */
733 env
->cp15
.c9_pmcr
&= ~0x39;
734 env
->cp15
.c9_pmcr
|= (value
& 0x39);
739 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
741 uint64_t total_ticks
;
743 if (!arm_ccnt_enabled(env
)) {
744 /* Counter is disabled, do not change value */
745 return env
->cp15
.c15_ccnt
;
748 total_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
749 get_ticks_per_sec(), 1000000);
751 if (env
->cp15
.c9_pmcr
& PMCRD
) {
752 /* Increment once every 64 processor clock cycles */
755 return total_ticks
- env
->cp15
.c15_ccnt
;
758 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
761 uint64_t total_ticks
;
763 if (!arm_ccnt_enabled(env
)) {
764 /* Counter is disabled, set the absolute value */
765 env
->cp15
.c15_ccnt
= value
;
769 total_ticks
= muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
),
770 get_ticks_per_sec(), 1000000);
772 if (env
->cp15
.c9_pmcr
& PMCRD
) {
773 /* Increment once every 64 processor clock cycles */
776 env
->cp15
.c15_ccnt
= total_ticks
- value
;
779 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
782 uint64_t cur_val
= pmccntr_read(env
, NULL
);
784 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
787 #else /* CONFIG_USER_ONLY */
789 void pmccntr_sync(CPUARMState
*env
)
795 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
799 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
803 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
807 env
->cp15
.c9_pmcnten
|= value
;
810 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
814 env
->cp15
.c9_pmcnten
&= ~value
;
817 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
820 env
->cp15
.c9_pmovsr
&= ~value
;
823 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
826 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
829 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
832 env
->cp15
.c9_pmuserenr
= value
& 1;
835 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
838 /* We have no event counters so only the C bit can be changed */
840 env
->cp15
.c9_pminten
|= value
;
843 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
847 env
->cp15
.c9_pminten
&= ~value
;
850 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
853 /* Note that even though the AArch64 view of this register has bits
854 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
855 * architectural requirements for bits which are RES0 only in some
856 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
857 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
859 raw_write(env
, ri
, value
& ~0x1FULL
);
862 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
864 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
865 * For bits that vary between AArch32/64, code needs to check the
866 * current execution mode before directly using the feature bit.
868 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
870 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
871 valid_mask
&= ~SCR_HCE
;
873 /* On ARMv7, SMD (or SCD as it is called in v7) is only
874 * supported if EL2 exists. The bit is UNK/SBZP when
875 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
876 * when EL2 is unavailable.
877 * On ARMv8, this bit is always available.
879 if (arm_feature(env
, ARM_FEATURE_V7
) &&
880 !arm_feature(env
, ARM_FEATURE_V8
)) {
881 valid_mask
&= ~SCR_SMD
;
885 /* Clear all-context RES0 bits. */
887 raw_write(env
, ri
, value
);
890 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
892 ARMCPU
*cpu
= arm_env_get_cpu(env
);
894 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
897 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
898 ri
->secure
& ARM_CP_SECSTATE_S
);
900 return cpu
->ccsidr
[index
];
903 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
906 raw_write(env
, ri
, value
& 0xf);
909 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
911 CPUState
*cs
= ENV_GET_CPU(env
);
914 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
917 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
920 /* External aborts are not possible in QEMU so A bit is always clear */
924 static const ARMCPRegInfo v7_cp_reginfo
[] = {
925 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
926 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
927 .access
= PL1_W
, .type
= ARM_CP_NOP
},
928 /* Performance monitors are implementation defined in v7,
929 * but with an ARM recommended set of registers, which we
930 * follow (although we don't actually implement any counters)
932 * Performance registers fall into three categories:
933 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
934 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
935 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
936 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
937 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
939 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
940 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
941 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
942 .writefn
= pmcntenset_write
,
943 .accessfn
= pmreg_access
,
944 .raw_writefn
= raw_write
},
945 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
946 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
947 .access
= PL0_RW
, .accessfn
= pmreg_access
,
948 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
949 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
950 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
952 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
953 .accessfn
= pmreg_access
,
954 .writefn
= pmcntenclr_write
,
955 .type
= ARM_CP_ALIAS
},
956 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
957 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
958 .access
= PL0_RW
, .accessfn
= pmreg_access
,
959 .type
= ARM_CP_ALIAS
,
960 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
961 .writefn
= pmcntenclr_write
},
962 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
963 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
964 .accessfn
= pmreg_access
,
965 .writefn
= pmovsr_write
,
966 .raw_writefn
= raw_write
},
967 /* Unimplemented so WI. */
968 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
969 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
970 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
971 * We choose to RAZ/WI.
973 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
974 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
975 .accessfn
= pmreg_access
},
976 #ifndef CONFIG_USER_ONLY
977 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
978 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
979 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
980 .accessfn
= pmreg_access
},
981 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
982 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
983 .access
= PL0_RW
, .accessfn
= pmreg_access
,
985 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
987 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
988 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
989 .writefn
= pmccfiltr_write
,
990 .access
= PL0_RW
, .accessfn
= pmreg_access
,
992 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
994 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
996 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
997 .accessfn
= pmreg_access
, .writefn
= pmxevtyper_write
,
998 .raw_writefn
= raw_write
},
999 /* Unimplemented, RAZ/WI. */
1000 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1001 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1002 .accessfn
= pmreg_access
},
1003 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1004 .access
= PL0_R
| PL1_RW
,
1005 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1007 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1008 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1010 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1012 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1013 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1014 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1015 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1016 .writefn
= pmintenclr_write
, },
1017 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
1018 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
1019 .access
= PL1_RW
, .writefn
= vbar_write
,
1020 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
1021 offsetof(CPUARMState
, cp15
.vbar_ns
) },
1023 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1024 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1025 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1026 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1027 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1028 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1029 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1030 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1031 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1032 * just RAZ for all cores:
1034 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1035 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1036 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1037 /* Auxiliary fault status registers: these also are IMPDEF, and we
1038 * choose to RAZ/WI for all cores.
1040 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1041 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1042 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1043 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1044 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1045 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1046 /* MAIR can just read-as-written because we don't implement caches
1047 * and so don't need to care about memory attributes.
1049 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1050 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1051 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1053 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1054 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1055 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1057 /* For non-long-descriptor page tables these are PRRR and NMRR;
1058 * regardless they still act as reads-as-written for QEMU.
1060 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1061 * allows them to assign the correct fieldoffset based on the endianness
1062 * handled in the field definitions.
1064 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1065 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1066 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1067 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1068 .resetfn
= arm_cp_reset_ignore
},
1069 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1070 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1071 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1072 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1073 .resetfn
= arm_cp_reset_ignore
},
1074 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1075 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1076 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1077 /* 32 bit ITLB invalidates */
1078 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1079 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1080 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1081 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1082 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1083 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1084 /* 32 bit DTLB invalidates */
1085 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1086 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1087 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1088 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1089 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1090 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1091 /* 32 bit TLB invalidates */
1092 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1093 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1094 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1095 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1096 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1097 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1098 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1099 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1103 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1104 /* 32 bit TLB invalidates, Inner Shareable */
1105 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1106 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1107 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1108 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1109 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1110 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1111 .writefn
= tlbiasid_is_write
},
1112 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1113 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1114 .writefn
= tlbimvaa_is_write
},
1118 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1125 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1127 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1128 return CP_ACCESS_TRAP
;
1130 return CP_ACCESS_OK
;
1133 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1134 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1135 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1137 .writefn
= teecr_write
},
1138 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1139 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1140 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1144 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1145 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1146 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1148 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1149 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1151 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1152 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1153 .resetfn
= arm_cp_reset_ignore
},
1154 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1155 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1156 .access
= PL0_R
|PL1_W
,
1157 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1159 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1160 .access
= PL0_R
|PL1_W
,
1161 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1162 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1163 .resetfn
= arm_cp_reset_ignore
},
1164 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1165 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1167 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1168 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1170 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1171 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1176 #ifndef CONFIG_USER_ONLY
1178 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1180 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1181 if (arm_current_el(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1182 return CP_ACCESS_TRAP
;
1184 return CP_ACCESS_OK
;
1187 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
)
1189 unsigned int cur_el
= arm_current_el(env
);
1190 bool secure
= arm_is_secure(env
);
1192 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1194 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1195 return CP_ACCESS_TRAP
;
1198 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1199 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1200 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1201 return CP_ACCESS_TRAP_EL2
;
1203 return CP_ACCESS_OK
;
1206 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
)
1208 unsigned int cur_el
= arm_current_el(env
);
1209 bool secure
= arm_is_secure(env
);
1211 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1212 * EL0[PV]TEN is zero.
1215 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1216 return CP_ACCESS_TRAP
;
1219 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1220 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1221 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1222 return CP_ACCESS_TRAP_EL2
;
1224 return CP_ACCESS_OK
;
1227 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1228 const ARMCPRegInfo
*ri
)
1230 return gt_counter_access(env
, GTIMER_PHYS
);
1233 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1234 const ARMCPRegInfo
*ri
)
1236 return gt_counter_access(env
, GTIMER_VIRT
);
1239 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1241 return gt_timer_access(env
, GTIMER_PHYS
);
1244 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1246 return gt_timer_access(env
, GTIMER_VIRT
);
1249 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1250 const ARMCPRegInfo
*ri
)
1252 /* The AArch64 register view of the secure physical timer is
1253 * always accessible from EL3, and configurably accessible from
1256 switch (arm_current_el(env
)) {
1258 if (!arm_is_secure(env
)) {
1259 return CP_ACCESS_TRAP
;
1261 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1262 return CP_ACCESS_TRAP_EL3
;
1264 return CP_ACCESS_OK
;
1267 return CP_ACCESS_TRAP
;
1269 return CP_ACCESS_OK
;
1271 g_assert_not_reached();
1275 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1277 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1280 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1282 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1285 /* Timer enabled: calculate and set current ISTATUS, irq, and
1286 * reset timer to when ISTATUS next has to change
1288 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1289 cpu
->env
.cp15
.cntvoff_el2
: 0;
1290 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1291 /* Note that this must be unsigned 64 bit arithmetic: */
1292 int istatus
= count
- offset
>= gt
->cval
;
1295 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1296 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1297 (istatus
&& !(gt
->ctl
& 2)));
1299 /* Next transition is when count rolls back over to zero */
1300 nexttick
= UINT64_MAX
;
1302 /* Next transition is when we hit cval */
1303 nexttick
= gt
->cval
+ offset
;
1305 /* Note that the desired next expiry time might be beyond the
1306 * signed-64-bit range of a QEMUTimer -- in this case we just
1307 * set the timer for as far in the future as possible. When the
1308 * timer expires we will reset the timer for any remaining period.
1310 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1311 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1313 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1315 /* Timer disabled: ISTATUS and timer output always clear */
1317 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1318 timer_del(cpu
->gt_timer
[timeridx
]);
1322 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1325 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1327 timer_del(cpu
->gt_timer
[timeridx
]);
1330 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1332 return gt_get_countervalue(env
);
1335 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1337 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1340 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1344 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1345 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1348 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1351 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1353 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1354 (gt_get_countervalue(env
) - offset
));
1357 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1361 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1363 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1364 sextract64(value
, 0, 32);
1365 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1368 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1372 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1373 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1375 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1376 if ((oldval
^ value
) & 1) {
1377 /* Enable toggled */
1378 gt_recalc_timer(cpu
, timeridx
);
1379 } else if ((oldval
^ value
) & 2) {
1380 /* IMASK toggled: don't need to recalculate,
1381 * just set the interrupt line based on ISTATUS
1383 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1384 (oldval
& 4) && !(value
& 2));
1388 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1390 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1393 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1396 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1399 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1401 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1404 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1407 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1410 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1413 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1416 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1418 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1421 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1424 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1427 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1429 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1432 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1435 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1438 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1441 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1444 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1447 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1449 raw_write(env
, ri
, value
);
1450 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1453 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1455 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1458 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1461 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1464 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1466 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1469 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1472 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1475 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1478 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1481 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1483 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1486 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1489 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1492 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1494 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1497 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1500 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1503 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1506 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1509 void arm_gt_ptimer_cb(void *opaque
)
1511 ARMCPU
*cpu
= opaque
;
1513 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1516 void arm_gt_vtimer_cb(void *opaque
)
1518 ARMCPU
*cpu
= opaque
;
1520 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1523 void arm_gt_htimer_cb(void *opaque
)
1525 ARMCPU
*cpu
= opaque
;
1527 gt_recalc_timer(cpu
, GTIMER_HYP
);
1530 void arm_gt_stimer_cb(void *opaque
)
1532 ARMCPU
*cpu
= opaque
;
1534 gt_recalc_timer(cpu
, GTIMER_SEC
);
1537 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1538 /* Note that CNTFRQ is purely reads-as-written for the benefit
1539 * of software; writing it doesn't actually change the timer frequency.
1540 * Our reset value matches the fixed frequency we implement the timer at.
1542 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1543 .type
= ARM_CP_ALIAS
,
1544 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1545 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1547 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1548 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1549 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1550 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1551 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1553 /* overall control: mostly access permissions */
1554 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1555 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1557 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1560 /* per-timer control */
1561 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1562 .secure
= ARM_CP_SECSTATE_NS
,
1563 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1564 .accessfn
= gt_ptimer_access
,
1565 .fieldoffset
= offsetoflow32(CPUARMState
,
1566 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1567 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1569 { .name
= "CNTP_CTL(S)",
1570 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1571 .secure
= ARM_CP_SECSTATE_S
,
1572 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1573 .accessfn
= gt_ptimer_access
,
1574 .fieldoffset
= offsetoflow32(CPUARMState
,
1575 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1576 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1578 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1579 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1580 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1581 .accessfn
= gt_ptimer_access
,
1582 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1584 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1586 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1587 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1588 .accessfn
= gt_vtimer_access
,
1589 .fieldoffset
= offsetoflow32(CPUARMState
,
1590 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1591 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1593 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1594 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1595 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1596 .accessfn
= gt_vtimer_access
,
1597 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1599 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1601 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1602 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1603 .secure
= ARM_CP_SECSTATE_NS
,
1604 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1605 .accessfn
= gt_ptimer_access
,
1606 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1608 { .name
= "CNTP_TVAL(S)",
1609 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1610 .secure
= ARM_CP_SECSTATE_S
,
1611 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1612 .accessfn
= gt_ptimer_access
,
1613 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
1615 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1616 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1617 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1618 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
1619 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1621 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1622 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1623 .accessfn
= gt_vtimer_access
,
1624 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
1626 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1627 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1628 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1629 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
1630 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
1632 /* The counter itself */
1633 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1634 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1635 .accessfn
= gt_pct_access
,
1636 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1638 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1639 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1640 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1641 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
1643 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1644 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1645 .accessfn
= gt_vct_access
,
1646 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1648 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1649 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1650 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1651 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
1653 /* Comparison value, indicating when the timer goes off */
1654 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1655 .secure
= ARM_CP_SECSTATE_NS
,
1656 .access
= PL1_RW
| PL0_R
,
1657 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1658 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1659 .accessfn
= gt_ptimer_access
,
1660 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
1662 { .name
= "CNTP_CVAL(S)", .cp
= 15, .crm
= 14, .opc1
= 2,
1663 .secure
= ARM_CP_SECSTATE_S
,
1664 .access
= PL1_RW
| PL0_R
,
1665 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1666 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
1667 .accessfn
= gt_ptimer_access
,
1668 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
1670 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1671 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1672 .access
= PL1_RW
| PL0_R
,
1674 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1675 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
1676 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
1678 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
1679 .access
= PL1_RW
| PL0_R
,
1680 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1681 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1682 .accessfn
= gt_vtimer_access
,
1683 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
1685 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1686 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
1687 .access
= PL1_RW
| PL0_R
,
1689 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1690 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1691 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
1693 /* Secure timer -- this is actually restricted to only EL3
1694 * and configurably Secure-EL1 via the accessfn.
1696 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
1697 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
1698 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
1699 .accessfn
= gt_stimer_access
,
1700 .readfn
= gt_sec_tval_read
,
1701 .writefn
= gt_sec_tval_write
,
1702 .resetfn
= gt_sec_timer_reset
,
1704 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
1705 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
1706 .type
= ARM_CP_IO
, .access
= PL1_RW
,
1707 .accessfn
= gt_stimer_access
,
1708 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1710 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1712 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
1713 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
1714 .type
= ARM_CP_IO
, .access
= PL1_RW
,
1715 .accessfn
= gt_stimer_access
,
1716 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
1717 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
1723 /* In user-mode none of the generic timer registers are accessible,
1724 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1725 * so instead just don't register any of them.
1727 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1733 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1735 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1736 raw_write(env
, ri
, value
);
1737 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1738 raw_write(env
, ri
, value
& 0xfffff6ff);
1740 raw_write(env
, ri
, value
& 0xfffff1ff);
1744 #ifndef CONFIG_USER_ONLY
1745 /* get_phys_addr() isn't present for user-mode-only targets */
1747 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1750 /* The ATS12NSO* operations must trap to EL3 if executed in
1751 * Secure EL1 (which can only happen if EL3 is AArch64).
1752 * They are simply UNDEF if executed from NS EL1.
1753 * They function normally from EL2 or EL3.
1755 if (arm_current_el(env
) == 1) {
1756 if (arm_is_secure_below_el3(env
)) {
1757 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
1759 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1762 return CP_ACCESS_OK
;
1765 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
1766 int access_type
, ARMMMUIdx mmu_idx
)
1769 target_ulong page_size
;
1774 MemTxAttrs attrs
= {};
1776 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
,
1777 &phys_addr
, &attrs
, &prot
, &page_size
, &fsr
);
1778 if (extended_addresses_enabled(env
)) {
1779 /* fsr is a DFSR/IFSR value for the long descriptor
1780 * translation table format, but with WnR always clear.
1781 * Convert it to a 64-bit PAR.
1783 par64
= (1 << 11); /* LPAE bit always set */
1785 par64
|= phys_addr
& ~0xfffULL
;
1786 if (!attrs
.secure
) {
1787 par64
|= (1 << 9); /* NS */
1789 /* We don't set the ATTR or SH fields in the PAR. */
1792 par64
|= (fsr
& 0x3f) << 1; /* FS */
1793 /* Note that S2WLK and FSTAGE are always zero, because we don't
1794 * implement virtualization and therefore there can't be a stage 2
1799 /* fsr is a DFSR/IFSR value for the short descriptor
1800 * translation table format (with WnR always clear).
1801 * Convert it to a 32-bit PAR.
1804 /* We do not set any attribute bits in the PAR */
1805 if (page_size
== (1 << 24)
1806 && arm_feature(env
, ARM_FEATURE_V7
)) {
1807 par64
= (phys_addr
& 0xff000000) | (1 << 1);
1809 par64
= phys_addr
& 0xfffff000;
1811 if (!attrs
.secure
) {
1812 par64
|= (1 << 9); /* NS */
1815 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
1816 ((fsr
& 0xf) << 1) | 1;
1822 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1824 int access_type
= ri
->opc2
& 1;
1827 int el
= arm_current_el(env
);
1828 bool secure
= arm_is_secure_below_el3(env
);
1830 switch (ri
->opc2
& 6) {
1832 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1835 mmu_idx
= ARMMMUIdx_S1E3
;
1838 mmu_idx
= ARMMMUIdx_S1NSE1
;
1841 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1844 g_assert_not_reached();
1848 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1851 mmu_idx
= ARMMMUIdx_S1SE0
;
1854 mmu_idx
= ARMMMUIdx_S1NSE0
;
1857 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1860 g_assert_not_reached();
1864 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1865 mmu_idx
= ARMMMUIdx_S12NSE1
;
1868 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1869 mmu_idx
= ARMMMUIdx_S12NSE0
;
1872 g_assert_not_reached();
1875 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
1877 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
1880 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1883 int access_type
= ri
->opc2
& 1;
1886 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
1888 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
1891 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1893 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
1894 return CP_ACCESS_TRAP
;
1896 return CP_ACCESS_OK
;
1899 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1902 int access_type
= ri
->opc2
& 1;
1904 int secure
= arm_is_secure_below_el3(env
);
1906 switch (ri
->opc2
& 6) {
1909 case 0: /* AT S1E1R, AT S1E1W */
1910 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1912 case 4: /* AT S1E2R, AT S1E2W */
1913 mmu_idx
= ARMMMUIdx_S1E2
;
1915 case 6: /* AT S1E3R, AT S1E3W */
1916 mmu_idx
= ARMMMUIdx_S1E3
;
1919 g_assert_not_reached();
1922 case 2: /* AT S1E0R, AT S1E0W */
1923 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1925 case 4: /* AT S12E1R, AT S12E1W */
1926 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
1928 case 6: /* AT S12E0R, AT S12E0W */
1929 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
1932 g_assert_not_reached();
1935 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
1939 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1940 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1941 .access
= PL1_RW
, .resetvalue
= 0,
1942 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
1943 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
1944 .writefn
= par_write
},
1945 #ifndef CONFIG_USER_ONLY
1946 /* This underdecoding is safe because the reginfo is NO_RAW. */
1947 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1948 .access
= PL1_W
, .accessfn
= ats_access
,
1949 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
1954 /* Return basic MPU access permission bits. */
1955 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1962 for (i
= 0; i
< 16; i
+= 2) {
1963 ret
|= (val
>> i
) & mask
;
1969 /* Pad basic MPU access permission bits to extended format. */
1970 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1977 for (i
= 0; i
< 16; i
+= 2) {
1978 ret
|= (val
& mask
) << i
;
1984 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1987 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
1990 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1992 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
1995 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1998 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2001 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2003 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2006 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2008 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2014 u32p
+= env
->cp15
.c6_rgnr
;
2018 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2021 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2022 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2028 u32p
+= env
->cp15
.c6_rgnr
;
2029 tlb_flush(CPU(cpu
), 1); /* Mappings may have changed - purge! */
2033 static void pmsav7_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2035 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2036 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2042 memset(u32p
, 0, sizeof(*u32p
) * cpu
->pmsav7_dregion
);
2045 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2048 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2049 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2051 if (value
>= nrgs
) {
2052 qemu_log_mask(LOG_GUEST_ERROR
,
2053 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2054 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2058 raw_write(env
, ri
, value
);
2061 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2062 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2063 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2064 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2065 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2066 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2067 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2068 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2069 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2070 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2071 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2072 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2073 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2074 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2076 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_rgnr
),
2077 .writefn
= pmsav7_rgnr_write
},
2081 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2082 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2083 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2084 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2085 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2086 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2087 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2088 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2089 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2090 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2092 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2094 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2096 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2098 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2100 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2101 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2103 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2104 /* Protection region base and size registers */
2105 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2106 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2107 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2108 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2109 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2110 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2111 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2112 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2113 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2114 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2115 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2116 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2117 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2118 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2119 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2120 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2121 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2122 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2123 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2124 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2125 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2126 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2127 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2128 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2132 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2135 TCR
*tcr
= raw_ptr(env
, ri
);
2136 int maskshift
= extract32(value
, 0, 3);
2138 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2139 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2140 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2141 * using Long-desciptor translation table format */
2142 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2143 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2144 /* In an implementation that includes the Security Extensions
2145 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2146 * Short-descriptor translation table format.
2148 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2154 /* Update the masks corresponding to the TCR bank being written
2155 * Note that we always calculate mask and base_mask, but
2156 * they are only used for short-descriptor tables (ie if EAE is 0);
2157 * for long-descriptor tables the TCR fields are used differently
2158 * and the mask and base_mask values are meaningless.
2160 tcr
->raw_tcr
= value
;
2161 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2162 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2165 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2168 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2170 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2171 /* With LPAE the TTBCR could result in a change of ASID
2172 * via the TTBCR.A1 bit, so do a TLB flush.
2174 tlb_flush(CPU(cpu
), 1);
2176 vmsa_ttbcr_raw_write(env
, ri
, value
);
2179 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2181 TCR
*tcr
= raw_ptr(env
, ri
);
2183 /* Reset both the TCR as well as the masks corresponding to the bank of
2184 * the TCR being reset.
2188 tcr
->base_mask
= 0xffffc000u
;
2191 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2194 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2195 TCR
*tcr
= raw_ptr(env
, ri
);
2197 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2198 tlb_flush(CPU(cpu
), 1);
2199 tcr
->raw_tcr
= value
;
2202 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2205 /* 64 bit accesses to the TTBRs can change the ASID and so we
2206 * must flush the TLB.
2208 if (cpreg_field_is_64bit(ri
)) {
2209 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2211 tlb_flush(CPU(cpu
), 1);
2213 raw_write(env
, ri
, value
);
2216 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2219 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2220 CPUState
*cs
= CPU(cpu
);
2222 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2223 if (raw_read(env
, ri
) != value
) {
2224 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
,
2225 ARMMMUIdx_S2NS
, -1);
2226 raw_write(env
, ri
, value
);
2230 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2231 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2232 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2233 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2234 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2235 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2236 .access
= PL1_RW
, .resetvalue
= 0,
2237 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2238 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2239 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2240 .access
= PL1_RW
, .resetvalue
= 0,
2241 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2242 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2243 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2244 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2245 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2250 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2251 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2252 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2254 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2255 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2256 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2257 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2258 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2259 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2260 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2261 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2262 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2263 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2264 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2265 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2266 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2267 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2268 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2269 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2270 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2271 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2272 .raw_writefn
= vmsa_ttbcr_raw_write
,
2273 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2274 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2278 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2281 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2282 /* The OS_TYPE bit in this register changes the reported CPUID! */
2283 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2284 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2287 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2290 env
->cp15
.c15_threadid
= value
& 0xffff;
2293 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2296 /* Wait-for-interrupt (deprecated) */
2297 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2300 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2303 /* On OMAP there are registers indicating the max/min index of dcache lines
2304 * containing a dirty line; cache flush operations have to reset these.
2306 env
->cp15
.c15_i_max
= 0x000;
2307 env
->cp15
.c15_i_min
= 0xff0;
2310 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2311 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2312 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2313 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2315 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2316 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2317 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2319 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2320 .writefn
= omap_ticonfig_write
},
2321 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2323 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2324 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2325 .access
= PL1_RW
, .resetvalue
= 0xff0,
2326 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2327 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2329 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2330 .writefn
= omap_threadid_write
},
2331 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2332 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2333 .type
= ARM_CP_NO_RAW
,
2334 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2335 /* TODO: Peripheral port remap register:
2336 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2337 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2340 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2341 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2342 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2343 .writefn
= omap_cachemaint_write
},
2344 { .name
= "C9", .cp
= 15, .crn
= 9,
2345 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2346 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2350 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2353 env
->cp15
.c15_cpar
= value
& 0x3fff;
2356 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2357 { .name
= "XSCALE_CPAR",
2358 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2359 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2360 .writefn
= xscale_cpar_write
, },
2361 { .name
= "XSCALE_AUXCR",
2362 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2363 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2365 /* XScale specific cache-lockdown: since we have no cache we NOP these
2366 * and hope the guest does not really rely on cache behaviour.
2368 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2369 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2370 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2371 { .name
= "XSCALE_UNLOCK_ICACHE",
2372 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2373 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2374 { .name
= "XSCALE_DCACHE_LOCK",
2375 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2376 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2377 { .name
= "XSCALE_UNLOCK_DCACHE",
2378 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2379 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2383 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2384 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2385 * implementation of this implementation-defined space.
2386 * Ideally this should eventually disappear in favour of actually
2387 * implementing the correct behaviour for all cores.
2389 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2390 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2392 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2397 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2398 /* Cache status: RAZ because we have no cache so it's always clean */
2399 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2400 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2405 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2406 /* We never have a a block transfer operation in progress */
2407 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2408 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2410 /* The cache ops themselves: these all NOP for QEMU */
2411 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2412 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2413 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2414 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2415 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2416 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2417 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2418 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2419 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2420 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2421 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2422 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2426 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2427 /* The cache test-and-clean instructions always return (1 << 30)
2428 * to indicate that there are no dirty cache lines.
2430 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2431 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2432 .resetvalue
= (1 << 30) },
2433 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2434 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2435 .resetvalue
= (1 << 30) },
2439 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2440 /* Ignore ReadBuffer accesses */
2441 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2442 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2443 .access
= PL1_RW
, .resetvalue
= 0,
2444 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2448 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2450 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2451 unsigned int cur_el
= arm_current_el(env
);
2452 bool secure
= arm_is_secure(env
);
2454 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2455 return env
->cp15
.vpidr_el2
;
2457 return raw_read(env
, ri
);
2460 static uint64_t mpidr_read_val(CPUARMState
*env
)
2462 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2463 uint64_t mpidr
= cpu
->mp_affinity
;
2465 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2466 mpidr
|= (1U << 31);
2467 /* Cores which are uniprocessor (non-coherent)
2468 * but still implement the MP extensions set
2469 * bit 30. (For instance, Cortex-R5).
2471 if (cpu
->mp_is_up
) {
2472 mpidr
|= (1u << 30);
2478 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2480 unsigned int cur_el
= arm_current_el(env
);
2481 bool secure
= arm_is_secure(env
);
2483 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2484 return env
->cp15
.vmpidr_el2
;
2486 return mpidr_read_val(env
);
2489 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2490 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2491 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2492 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2496 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2498 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2499 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2500 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2502 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2503 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2504 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2506 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2507 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2508 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2509 offsetof(CPUARMState
, cp15
.par_ns
)} },
2510 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2511 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2512 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2513 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2514 .writefn
= vmsa_ttbr_write
, },
2515 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2516 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2517 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2518 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2519 .writefn
= vmsa_ttbr_write
, },
2523 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2525 return vfp_get_fpcr(env
);
2528 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2531 vfp_set_fpcr(env
, value
);
2534 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2536 return vfp_get_fpsr(env
);
2539 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2542 vfp_set_fpsr(env
, value
);
2545 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2547 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2548 return CP_ACCESS_TRAP
;
2550 return CP_ACCESS_OK
;
2553 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2556 env
->daif
= value
& PSTATE_DAIF
;
2559 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2560 const ARMCPRegInfo
*ri
)
2562 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2563 * SCTLR_EL1.UCI is set.
2565 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2566 return CP_ACCESS_TRAP
;
2568 return CP_ACCESS_OK
;
2571 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2572 * Page D4-1736 (DDI0487A.b)
2575 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2578 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2579 CPUState
*cs
= CPU(cpu
);
2581 if (arm_is_secure_below_el3(env
)) {
2582 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2584 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
, -1);
2588 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2591 bool sec
= arm_is_secure_below_el3(env
);
2594 CPU_FOREACH(other_cs
) {
2596 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2598 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S12NSE1
,
2599 ARMMMUIdx_S12NSE0
, -1);
2604 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2607 /* Note that the 'ALL' scope must invalidate both stage 1 and
2608 * stage 2 translations, whereas most other scopes only invalidate
2609 * stage 1 translations.
2611 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2612 CPUState
*cs
= CPU(cpu
);
2614 if (arm_is_secure_below_el3(env
)) {
2615 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2617 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2618 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
,
2619 ARMMMUIdx_S2NS
, -1);
2621 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
, -1);
2626 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2629 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2630 CPUState
*cs
= CPU(cpu
);
2632 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1E2
, -1);
2635 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2638 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2639 CPUState
*cs
= CPU(cpu
);
2641 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1E3
, -1);
2644 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2647 /* Note that the 'ALL' scope must invalidate both stage 1 and
2648 * stage 2 translations, whereas most other scopes only invalidate
2649 * stage 1 translations.
2651 bool sec
= arm_is_secure_below_el3(env
);
2652 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
2655 CPU_FOREACH(other_cs
) {
2657 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2658 } else if (has_el2
) {
2659 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S12NSE1
,
2660 ARMMMUIdx_S12NSE0
, ARMMMUIdx_S2NS
, -1);
2662 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S12NSE1
,
2663 ARMMMUIdx_S12NSE0
, -1);
2668 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2673 CPU_FOREACH(other_cs
) {
2674 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1E2
, -1);
2678 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2683 CPU_FOREACH(other_cs
) {
2684 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1E3
, -1);
2688 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2691 /* Invalidate by VA, EL1&0 (AArch64 version).
2692 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2693 * since we don't support flush-for-specific-ASID-only or
2694 * flush-last-level-only.
2696 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2697 CPUState
*cs
= CPU(cpu
);
2698 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2700 if (arm_is_secure_below_el3(env
)) {
2701 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S1SE1
,
2702 ARMMMUIdx_S1SE0
, -1);
2704 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S12NSE1
,
2705 ARMMMUIdx_S12NSE0
, -1);
2709 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2712 /* Invalidate by VA, EL2
2713 * Currently handles both VAE2 and VALE2, since we don't support
2714 * flush-last-level-only.
2716 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2717 CPUState
*cs
= CPU(cpu
);
2718 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2720 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S1E2
, -1);
2723 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2726 /* Invalidate by VA, EL3
2727 * Currently handles both VAE3 and VALE3, since we don't support
2728 * flush-last-level-only.
2730 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2731 CPUState
*cs
= CPU(cpu
);
2732 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2734 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S1E3
, -1);
2737 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2740 bool sec
= arm_is_secure_below_el3(env
);
2742 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2744 CPU_FOREACH(other_cs
) {
2746 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S1SE1
,
2747 ARMMMUIdx_S1SE0
, -1);
2749 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S12NSE1
,
2750 ARMMMUIdx_S12NSE0
, -1);
2755 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2759 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2761 CPU_FOREACH(other_cs
) {
2762 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S1E2
, -1);
2766 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2770 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2772 CPU_FOREACH(other_cs
) {
2773 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S1E3
, -1);
2777 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2780 /* Invalidate by IPA. This has to invalidate any structures that
2781 * contain only stage 2 translation information, but does not need
2782 * to apply to structures that contain combined stage 1 and stage 2
2783 * translation information.
2784 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2786 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2787 CPUState
*cs
= CPU(cpu
);
2790 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
2794 pageaddr
= sextract64(value
<< 12, 0, 48);
2796 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S2NS
, -1);
2799 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2805 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
2809 pageaddr
= sextract64(value
<< 12, 0, 48);
2811 CPU_FOREACH(other_cs
) {
2812 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S2NS
, -1);
2816 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2818 /* We don't implement EL2, so the only control on DC ZVA is the
2819 * bit in the SCTLR which can prohibit access for EL0.
2821 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
2822 return CP_ACCESS_TRAP
;
2824 return CP_ACCESS_OK
;
2827 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2829 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2830 int dzp_bit
= 1 << 4;
2832 /* DZP indicates whether DC ZVA access is allowed */
2833 if (aa64_zva_access(env
, NULL
) == CP_ACCESS_OK
) {
2836 return cpu
->dcz_blocksize
| dzp_bit
;
2839 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2841 if (!(env
->pstate
& PSTATE_SP
)) {
2842 /* Access to SP_EL0 is undefined if it's being used as
2843 * the stack pointer.
2845 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2847 return CP_ACCESS_OK
;
2850 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2852 return env
->pstate
& PSTATE_SP
;
2855 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
2857 update_spsel(env
, val
);
2860 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2863 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2865 if (raw_read(env
, ri
) == value
) {
2866 /* Skip the TLB flush if nothing actually changed; Linux likes
2867 * to do a lot of pointless SCTLR writes.
2872 raw_write(env
, ri
, value
);
2873 /* ??? Lots of these bits are not implemented. */
2874 /* This may enable/disable the MMU, so do a TLB flush. */
2875 tlb_flush(CPU(cpu
), 1);
2878 static const ARMCPRegInfo v8_cp_reginfo
[] = {
2879 /* Minimal set of EL0-visible registers. This will need to be expanded
2880 * significantly for system emulation of AArch64 CPUs.
2882 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
2883 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
2884 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
2885 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
2886 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
2887 .type
= ARM_CP_NO_RAW
,
2888 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
2889 .fieldoffset
= offsetof(CPUARMState
, daif
),
2890 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
2891 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
2892 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
2893 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
2894 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
2895 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
2896 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
2897 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
2898 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
2899 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
2900 .readfn
= aa64_dczid_read
},
2901 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
2902 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
2903 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
2904 #ifndef CONFIG_USER_ONLY
2905 /* Avoid overhead of an access check that always passes in user-mode */
2906 .accessfn
= aa64_zva_access
,
2909 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
2910 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
2911 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
2912 /* Cache ops: all NOPs since we don't emulate caches */
2913 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
2914 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
2915 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2916 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
2917 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
2918 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2919 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
2920 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
2921 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2922 .accessfn
= aa64_cacheop_access
},
2923 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
2924 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
2925 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2926 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
2927 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
2928 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2929 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
2930 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
2931 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2932 .accessfn
= aa64_cacheop_access
},
2933 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
2934 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
2935 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2936 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
2937 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
2938 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2939 .accessfn
= aa64_cacheop_access
},
2940 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
2941 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
2942 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2943 .accessfn
= aa64_cacheop_access
},
2944 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
2945 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
2946 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2947 /* TLBI operations */
2948 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
2949 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2950 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2951 .writefn
= tlbi_aa64_vmalle1is_write
},
2952 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
2953 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2954 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2955 .writefn
= tlbi_aa64_vae1is_write
},
2956 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
2957 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2958 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2959 .writefn
= tlbi_aa64_vmalle1is_write
},
2960 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
2961 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2962 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2963 .writefn
= tlbi_aa64_vae1is_write
},
2964 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
2965 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
2966 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2967 .writefn
= tlbi_aa64_vae1is_write
},
2968 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
2969 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
2970 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2971 .writefn
= tlbi_aa64_vae1is_write
},
2972 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
2973 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2974 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2975 .writefn
= tlbi_aa64_vmalle1_write
},
2976 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
2977 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2978 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2979 .writefn
= tlbi_aa64_vae1_write
},
2980 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
2981 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2982 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2983 .writefn
= tlbi_aa64_vmalle1_write
},
2984 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
2985 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2986 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2987 .writefn
= tlbi_aa64_vae1_write
},
2988 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
2989 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
2990 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2991 .writefn
= tlbi_aa64_vae1_write
},
2992 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
2993 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
2994 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2995 .writefn
= tlbi_aa64_vae1_write
},
2996 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
2997 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
2998 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
2999 .writefn
= tlbi_aa64_ipas2e1is_write
},
3000 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3001 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3002 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3003 .writefn
= tlbi_aa64_ipas2e1is_write
},
3004 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3005 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3006 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3007 .writefn
= tlbi_aa64_alle1is_write
},
3008 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3009 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3010 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3011 .writefn
= tlbi_aa64_alle1is_write
},
3012 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3013 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3014 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3015 .writefn
= tlbi_aa64_ipas2e1_write
},
3016 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3017 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3018 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3019 .writefn
= tlbi_aa64_ipas2e1_write
},
3020 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3021 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3022 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3023 .writefn
= tlbi_aa64_alle1_write
},
3024 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3025 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3026 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3027 .writefn
= tlbi_aa64_alle1is_write
},
3028 #ifndef CONFIG_USER_ONLY
3029 /* 64 bit address translation operations */
3030 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3031 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3032 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3033 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3034 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3035 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3036 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3037 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3038 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3039 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3040 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3041 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3042 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3043 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3044 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3045 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3046 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3047 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3048 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3049 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3050 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3051 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3052 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3053 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3054 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3055 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3056 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3057 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3058 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3059 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3060 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3061 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3062 .type
= ARM_CP_ALIAS
,
3063 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3064 .access
= PL1_RW
, .resetvalue
= 0,
3065 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3066 .writefn
= par_write
},
3068 /* TLB invalidate last level of translation table walk */
3069 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3070 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3071 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3072 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3073 .writefn
= tlbimvaa_is_write
},
3074 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3075 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3076 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3077 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3078 /* 32 bit cache operations */
3079 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3080 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3081 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3082 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3083 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3084 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3085 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3086 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3087 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3088 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3089 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3090 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3091 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3092 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3093 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3094 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3095 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3096 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3097 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3098 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3099 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3100 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3101 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3102 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3103 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3104 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3105 /* MMU Domain access control / MPU write buffer control */
3106 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3107 .access
= PL1_RW
, .resetvalue
= 0,
3108 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3109 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3110 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3111 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3112 .type
= ARM_CP_ALIAS
,
3113 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3115 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3116 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3117 .type
= ARM_CP_ALIAS
,
3118 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3119 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[1]) },
3120 /* We rely on the access checks not allowing the guest to write to the
3121 * state field when SPSel indicates that it's being used as the stack
3124 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3125 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3126 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3127 .type
= ARM_CP_ALIAS
,
3128 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3129 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3130 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3131 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3132 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3133 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3134 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3135 .type
= ARM_CP_NO_RAW
,
3136 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3140 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3141 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3142 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3143 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3145 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3146 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3147 .type
= ARM_CP_NO_RAW
,
3148 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3150 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3151 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3152 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3153 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3154 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3155 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3156 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3158 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3159 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3160 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3161 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3162 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3163 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3165 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3166 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3167 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3169 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3170 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3171 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3173 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3174 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3175 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3177 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3178 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3179 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3180 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3181 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3182 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3183 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3184 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3185 .cp
= 15, .opc1
= 6, .crm
= 2,
3186 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3187 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3188 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3189 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3190 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3191 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3192 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3193 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3194 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3195 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3196 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3197 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3198 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3199 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3200 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3201 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3203 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3204 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3205 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3206 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3207 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3208 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3209 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3210 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3212 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3213 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3214 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3215 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3216 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3218 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3219 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3220 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3221 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3222 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3223 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3227 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3229 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3230 uint64_t valid_mask
= HCR_MASK
;
3232 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3233 valid_mask
&= ~HCR_HCD
;
3235 valid_mask
&= ~HCR_TSC
;
3238 /* Clear RES0 bits. */
3239 value
&= valid_mask
;
3241 /* These bits change the MMU setup:
3242 * HCR_VM enables stage 2 translation
3243 * HCR_PTW forbids certain page-table setups
3244 * HCR_DC Disables stage1 and enables stage2 translation
3246 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3247 tlb_flush(CPU(cpu
), 1);
3249 raw_write(env
, ri
, value
);
3252 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3253 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3254 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3255 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3256 .writefn
= hcr_write
},
3257 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3258 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3259 .access
= PL2_RW
, .resetvalue
= 0,
3260 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3261 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3262 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3263 .type
= ARM_CP_ALIAS
,
3264 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3266 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3267 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3268 .type
= ARM_CP_ALIAS
,
3269 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3270 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3271 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3272 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3273 .access
= PL2_RW
, .resetvalue
= 0,
3274 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3275 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3276 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3277 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3278 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3279 .type
= ARM_CP_ALIAS
,
3280 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3281 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[6]) },
3282 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3283 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3284 .access
= PL2_RW
, .writefn
= vbar_write
,
3285 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3287 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3288 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3289 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3290 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3291 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3292 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3293 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3294 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3295 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3296 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3297 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3299 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3300 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3301 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3302 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3303 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3304 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3305 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3307 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3308 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3309 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3310 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3312 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3313 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3314 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3316 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3317 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3318 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3320 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3321 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3322 .access
= PL2_RW
, .writefn
= vmsa_tcr_el1_write
,
3323 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3324 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3325 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3326 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3327 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3328 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3329 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3330 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3331 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3332 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3333 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3334 .cp
= 15, .opc1
= 6, .crm
= 2,
3335 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3336 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3337 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3338 .writefn
= vttbr_write
},
3339 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3340 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3341 .access
= PL2_RW
, .writefn
= vttbr_write
,
3342 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3343 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3344 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3345 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3346 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3347 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3348 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3349 .access
= PL2_RW
, .resetvalue
= 0,
3350 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3351 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3352 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3353 .access
= PL2_RW
, .resetvalue
= 0,
3354 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3355 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3356 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3357 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3358 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3359 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3360 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3361 .writefn
= tlbi_aa64_alle2_write
},
3362 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
3363 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3364 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3365 .writefn
= tlbi_aa64_vae2_write
},
3366 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
3367 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3368 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3369 .writefn
= tlbi_aa64_vae2_write
},
3370 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
3371 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3372 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3373 .writefn
= tlbi_aa64_alle2is_write
},
3374 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
3375 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3376 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3377 .writefn
= tlbi_aa64_vae2is_write
},
3378 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
3379 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3380 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3381 .writefn
= tlbi_aa64_vae2is_write
},
3382 #ifndef CONFIG_USER_ONLY
3383 /* Unlike the other EL2-related AT operations, these must
3384 * UNDEF from EL3 if EL2 is not implemented, which is why we
3385 * define them here rather than with the rest of the AT ops.
3387 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
3388 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3389 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3390 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3391 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
3392 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3393 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3394 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3395 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3396 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3397 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3398 * to behave as if SCR.NS was 1.
3400 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3402 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3403 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3405 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3406 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3407 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3408 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3409 * reset values as IMPDEF. We choose to reset to 3 to comply with
3410 * both ARMv7 and ARMv8.
3412 .access
= PL2_RW
, .resetvalue
= 3,
3413 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
3414 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3415 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3416 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
3417 .writefn
= gt_cntvoff_write
,
3418 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3419 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3420 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
3421 .writefn
= gt_cntvoff_write
,
3422 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3423 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3424 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3425 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3426 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3427 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3428 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3429 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3430 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
3431 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3432 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3433 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3434 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3435 .resetfn
= gt_hyp_timer_reset
,
3436 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
3437 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3439 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3441 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
3443 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
3448 static const ARMCPRegInfo el3_cp_reginfo
[] = {
3449 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
3450 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
3451 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
3452 .resetvalue
= 0, .writefn
= scr_write
},
3453 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
3454 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
3455 .access
= PL3_RW
, .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
3456 .writefn
= scr_write
},
3457 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
3458 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
3459 .access
= PL3_RW
, .resetvalue
= 0,
3460 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
3462 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
3463 .access
= PL3_RW
, .resetvalue
= 0,
3464 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
3465 /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3466 { .name
= "NSACR", .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
3467 .access
= PL3_W
| PL1_R
, .resetvalue
= 0,
3468 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
) },
3469 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
3470 .access
= PL3_RW
, .writefn
= vbar_write
, .resetvalue
= 0,
3471 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
3472 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
3473 .type
= ARM_CP_ALIAS
, /* reset handled by AArch32 view */
3474 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
3475 .access
= PL3_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3476 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]) },
3477 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
3478 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
3479 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3480 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
3481 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
3482 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
3483 .access
= PL3_RW
, .writefn
= vmsa_tcr_el1_write
,
3484 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3485 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
3486 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
3487 .type
= ARM_CP_ALIAS
,
3488 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
3490 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
3491 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
3492 .type
= ARM_CP_ALIAS
,
3493 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
3494 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
3495 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
3496 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
3497 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
3498 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
3499 .type
= ARM_CP_ALIAS
,
3500 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
3501 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[7]) },
3502 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
3503 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
3504 .access
= PL3_RW
, .writefn
= vbar_write
,
3505 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
3507 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
3508 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
3509 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3510 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
3511 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
3512 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
3513 .access
= PL3_RW
, .resetvalue
= 0,
3514 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
3515 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
3516 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
3517 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
3519 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
3520 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
3521 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
3523 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
3524 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
3525 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
3527 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
3528 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
3529 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3530 .writefn
= tlbi_aa64_alle3is_write
},
3531 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
3532 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
3533 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3534 .writefn
= tlbi_aa64_vae3is_write
},
3535 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
3536 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
3537 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3538 .writefn
= tlbi_aa64_vae3is_write
},
3539 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
3540 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
3541 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3542 .writefn
= tlbi_aa64_alle3_write
},
3543 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
3544 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
3545 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3546 .writefn
= tlbi_aa64_vae3_write
},
3547 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
3548 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
3549 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3550 .writefn
= tlbi_aa64_vae3_write
},
3554 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3556 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3557 * but the AArch32 CTR has its own reginfo struct)
3559 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
3560 return CP_ACCESS_TRAP
;
3562 return CP_ACCESS_OK
;
3565 static const ARMCPRegInfo debug_cp_reginfo
[] = {
3566 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3567 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3568 * unlike DBGDRAR it is never accessible from EL0.
3569 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3572 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
3573 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3574 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
3575 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
3576 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3577 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3578 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3579 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3580 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
3581 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
3583 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
3585 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3586 * We don't implement the configurable EL0 access.
3588 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
3589 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
3590 .type
= ARM_CP_ALIAS
,
3592 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
3593 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
3594 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
3595 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
3596 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3597 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3598 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
3599 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
3600 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3601 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3602 * implement vector catch debug events yet.
3605 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
3606 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3610 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
3611 /* 64 bit access versions of the (dummy) debug registers */
3612 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
3613 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
3614 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
3615 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
3619 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
3621 CPUARMState
*env
= &cpu
->env
;
3623 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
3624 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
3626 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
3628 if (env
->cpu_watchpoint
[n
]) {
3629 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
3630 env
->cpu_watchpoint
[n
] = NULL
;
3633 if (!extract64(wcr
, 0, 1)) {
3634 /* E bit clear : watchpoint disabled */
3638 switch (extract64(wcr
, 3, 2)) {
3640 /* LSC 00 is reserved and must behave as if the wp is disabled */
3643 flags
|= BP_MEM_READ
;
3646 flags
|= BP_MEM_WRITE
;
3649 flags
|= BP_MEM_ACCESS
;
3653 /* Attempts to use both MASK and BAS fields simultaneously are
3654 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3655 * thus generating a watchpoint for every byte in the masked region.
3657 mask
= extract64(wcr
, 24, 4);
3658 if (mask
== 1 || mask
== 2) {
3659 /* Reserved values of MASK; we must act as if the mask value was
3660 * some non-reserved value, or as if the watchpoint were disabled.
3661 * We choose the latter.
3665 /* Watchpoint covers an aligned area up to 2GB in size */
3667 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3668 * whether the watchpoint fires when the unmasked bits match; we opt
3669 * to generate the exceptions.
3673 /* Watchpoint covers bytes defined by the byte address select bits */
3674 int bas
= extract64(wcr
, 5, 8);
3678 /* This must act as if the watchpoint is disabled */
3682 if (extract64(wvr
, 2, 1)) {
3683 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3684 * ignored, and BAS[3:0] define which bytes to watch.
3688 /* The BAS bits are supposed to be programmed to indicate a contiguous
3689 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3690 * we fire for each byte in the word/doubleword addressed by the WVR.
3691 * We choose to ignore any non-zero bits after the first range of 1s.
3693 basstart
= ctz32(bas
);
3694 len
= cto32(bas
>> basstart
);
3698 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
3699 &env
->cpu_watchpoint
[n
]);
3702 void hw_watchpoint_update_all(ARMCPU
*cpu
)
3705 CPUARMState
*env
= &cpu
->env
;
3707 /* Completely clear out existing QEMU watchpoints and our array, to
3708 * avoid possible stale entries following migration load.
3710 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
3711 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
3713 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
3714 hw_watchpoint_update(cpu
, i
);
3718 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3721 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3724 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3725 * register reads and behaves as if values written are sign extended.
3726 * Bits [1:0] are RES0.
3728 value
= sextract64(value
, 0, 49) & ~3ULL;
3730 raw_write(env
, ri
, value
);
3731 hw_watchpoint_update(cpu
, i
);
3734 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3737 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3740 raw_write(env
, ri
, value
);
3741 hw_watchpoint_update(cpu
, i
);
3744 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
3746 CPUARMState
*env
= &cpu
->env
;
3747 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
3748 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
3753 if (env
->cpu_breakpoint
[n
]) {
3754 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
3755 env
->cpu_breakpoint
[n
] = NULL
;
3758 if (!extract64(bcr
, 0, 1)) {
3759 /* E bit clear : watchpoint disabled */
3763 bt
= extract64(bcr
, 20, 4);
3766 case 4: /* unlinked address mismatch (reserved if AArch64) */
3767 case 5: /* linked address mismatch (reserved if AArch64) */
3768 qemu_log_mask(LOG_UNIMP
,
3769 "arm: address mismatch breakpoint types not implemented");
3771 case 0: /* unlinked address match */
3772 case 1: /* linked address match */
3774 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3775 * we behave as if the register was sign extended. Bits [1:0] are
3776 * RES0. The BAS field is used to allow setting breakpoints on 16
3777 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3778 * a bp will fire if the addresses covered by the bp and the addresses
3779 * covered by the insn overlap but the insn doesn't start at the
3780 * start of the bp address range. We choose to require the insn and
3781 * the bp to have the same address. The constraints on writing to
3782 * BAS enforced in dbgbcr_write mean we have only four cases:
3783 * 0b0000 => no breakpoint
3784 * 0b0011 => breakpoint on addr
3785 * 0b1100 => breakpoint on addr + 2
3786 * 0b1111 => breakpoint on addr
3787 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3789 int bas
= extract64(bcr
, 5, 4);
3790 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
3799 case 2: /* unlinked context ID match */
3800 case 8: /* unlinked VMID match (reserved if no EL2) */
3801 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3802 qemu_log_mask(LOG_UNIMP
,
3803 "arm: unlinked context breakpoint types not implemented");
3805 case 9: /* linked VMID match (reserved if no EL2) */
3806 case 11: /* linked context ID and VMID match (reserved if no EL2) */
3807 case 3: /* linked context ID match */
3809 /* We must generate no events for Linked context matches (unless
3810 * they are linked to by some other bp/wp, which is handled in
3811 * updates for the linking bp/wp). We choose to also generate no events
3812 * for reserved values.
3817 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
3820 void hw_breakpoint_update_all(ARMCPU
*cpu
)
3823 CPUARMState
*env
= &cpu
->env
;
3825 /* Completely clear out existing QEMU breakpoints and our array, to
3826 * avoid possible stale entries following migration load.
3828 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
3829 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
3831 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
3832 hw_breakpoint_update(cpu
, i
);
3836 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3839 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3842 raw_write(env
, ri
, value
);
3843 hw_breakpoint_update(cpu
, i
);
3846 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3849 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3852 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3855 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
3856 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
3858 raw_write(env
, ri
, value
);
3859 hw_breakpoint_update(cpu
, i
);
3862 static void define_debug_regs(ARMCPU
*cpu
)
3864 /* Define v7 and v8 architectural debug registers.
3865 * These are just dummy implementations for now.
3868 int wrps
, brps
, ctx_cmps
;
3869 ARMCPRegInfo dbgdidr
= {
3870 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
3871 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
3874 /* Note that all these register fields hold "number of Xs minus 1". */
3875 brps
= extract32(cpu
->dbgdidr
, 24, 4);
3876 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
3877 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
3879 assert(ctx_cmps
<= brps
);
3881 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3882 * of the debug registers such as number of breakpoints;
3883 * check that if they both exist then they agree.
3885 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
3886 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
3887 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
3888 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
3891 define_one_arm_cp_reg(cpu
, &dbgdidr
);
3892 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
3894 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
3895 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
3898 for (i
= 0; i
< brps
+ 1; i
++) {
3899 ARMCPRegInfo dbgregs
[] = {
3900 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
3901 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
3903 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
3904 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
3906 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
3907 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
3909 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
3910 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
3914 define_arm_cp_regs(cpu
, dbgregs
);
3917 for (i
= 0; i
< wrps
+ 1; i
++) {
3918 ARMCPRegInfo dbgregs
[] = {
3919 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
3920 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
3922 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
3923 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
3925 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
3926 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
3928 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
3929 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
3933 define_arm_cp_regs(cpu
, dbgregs
);
3937 void register_cp_regs_for_features(ARMCPU
*cpu
)
3939 /* Register all the coprocessor registers based on feature bits */
3940 CPUARMState
*env
= &cpu
->env
;
3941 if (arm_feature(env
, ARM_FEATURE_M
)) {
3942 /* M profile has no coprocessor registers */
3946 define_arm_cp_regs(cpu
, cp_reginfo
);
3947 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3948 /* Must go early as it is full of wildcards that may be
3949 * overridden by later definitions.
3951 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
3954 if (arm_feature(env
, ARM_FEATURE_V6
)) {
3955 /* The ID registers all have impdef reset values */
3956 ARMCPRegInfo v6_idregs
[] = {
3957 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
3958 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
3959 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3960 .resetvalue
= cpu
->id_pfr0
},
3961 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
3962 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
3963 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3964 .resetvalue
= cpu
->id_pfr1
},
3965 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
3966 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
3967 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3968 .resetvalue
= cpu
->id_dfr0
},
3969 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
3970 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
3971 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3972 .resetvalue
= cpu
->id_afr0
},
3973 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
3974 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
3975 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3976 .resetvalue
= cpu
->id_mmfr0
},
3977 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
3978 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
3979 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3980 .resetvalue
= cpu
->id_mmfr1
},
3981 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
3982 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
3983 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3984 .resetvalue
= cpu
->id_mmfr2
},
3985 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
3986 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
3987 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3988 .resetvalue
= cpu
->id_mmfr3
},
3989 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
3990 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
3991 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3992 .resetvalue
= cpu
->id_isar0
},
3993 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
3994 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
3995 .access
= PL1_R
, .type
= ARM_CP_CONST
,
3996 .resetvalue
= cpu
->id_isar1
},
3997 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
3998 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
3999 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4000 .resetvalue
= cpu
->id_isar2
},
4001 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4002 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4003 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4004 .resetvalue
= cpu
->id_isar3
},
4005 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4006 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4007 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4008 .resetvalue
= cpu
->id_isar4
},
4009 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4010 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4011 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4012 .resetvalue
= cpu
->id_isar5
},
4013 /* 6..7 are as yet unallocated and must RAZ */
4014 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
4015 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
4017 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
4018 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
4022 define_arm_cp_regs(cpu
, v6_idregs
);
4023 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4025 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4027 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4028 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4030 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4031 !arm_feature(env
, ARM_FEATURE_MPU
)) {
4032 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4034 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4035 /* v7 performance monitor control register: same implementor
4036 * field as main ID register, and we implement only the cycle
4039 #ifndef CONFIG_USER_ONLY
4040 ARMCPRegInfo pmcr
= {
4041 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4043 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4044 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4045 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4046 .raw_writefn
= raw_write
,
4048 ARMCPRegInfo pmcr64
= {
4049 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4050 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4051 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4053 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4054 .resetvalue
= cpu
->midr
& 0xff000000,
4055 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4057 define_one_arm_cp_reg(cpu
, &pmcr
);
4058 define_one_arm_cp_reg(cpu
, &pmcr64
);
4060 ARMCPRegInfo clidr
= {
4061 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4062 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4063 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4065 define_one_arm_cp_reg(cpu
, &clidr
);
4066 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4067 define_debug_regs(cpu
);
4069 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4071 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4072 /* AArch64 ID registers, which all have impdef reset values */
4073 ARMCPRegInfo v8_idregs
[] = {
4074 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4075 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4076 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4077 .resetvalue
= cpu
->id_aa64pfr0
},
4078 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4079 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4080 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4081 .resetvalue
= cpu
->id_aa64pfr1
},
4082 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4083 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4084 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4085 /* We mask out the PMUVer field, because we don't currently
4086 * implement the PMU. Not advertising it prevents the guest
4087 * from trying to use it and getting UNDEFs on registers we
4090 .resetvalue
= cpu
->id_aa64dfr0
& ~0xf00 },
4091 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4092 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4093 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4094 .resetvalue
= cpu
->id_aa64dfr1
},
4095 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4096 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4097 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4098 .resetvalue
= cpu
->id_aa64afr0
},
4099 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4100 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4101 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4102 .resetvalue
= cpu
->id_aa64afr1
},
4103 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
4104 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
4105 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4106 .resetvalue
= cpu
->id_aa64isar0
},
4107 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
4108 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
4109 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4110 .resetvalue
= cpu
->id_aa64isar1
},
4111 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4112 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4113 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4114 .resetvalue
= cpu
->id_aa64mmfr0
},
4115 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4116 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
4117 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4118 .resetvalue
= cpu
->id_aa64mmfr1
},
4119 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4120 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
4121 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4122 .resetvalue
= cpu
->mvfr0
},
4123 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4124 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
4125 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4126 .resetvalue
= cpu
->mvfr1
},
4127 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
4128 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
4129 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4130 .resetvalue
= cpu
->mvfr2
},
4133 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4134 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
4135 !arm_feature(env
, ARM_FEATURE_EL2
)) {
4136 ARMCPRegInfo rvbar
= {
4137 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4138 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4139 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
4141 define_one_arm_cp_reg(cpu
, &rvbar
);
4143 define_arm_cp_regs(cpu
, v8_idregs
);
4144 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
4146 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4147 uint64_t vmpidr_def
= mpidr_read_val(env
);
4148 ARMCPRegInfo vpidr_regs
[] = {
4149 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
4150 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4151 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4152 .resetvalue
= cpu
->midr
,
4153 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4154 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4155 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4156 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
4157 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4158 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
4159 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4160 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4161 .resetvalue
= vmpidr_def
,
4162 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4163 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4164 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4166 .resetvalue
= vmpidr_def
,
4167 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4170 define_arm_cp_regs(cpu
, vpidr_regs
);
4171 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
4172 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4173 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
4174 ARMCPRegInfo rvbar
= {
4175 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
4176 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
4177 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
4179 define_one_arm_cp_reg(cpu
, &rvbar
);
4182 /* If EL2 is missing but higher ELs are enabled, we need to
4183 * register the no_el2 reginfos.
4185 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4186 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4187 * of MIDR_EL1 and MPIDR_EL1.
4189 ARMCPRegInfo vpidr_regs
[] = {
4190 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4191 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4192 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4193 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
4194 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4195 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4196 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4197 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4198 .type
= ARM_CP_NO_RAW
,
4199 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
4202 define_arm_cp_regs(cpu
, vpidr_regs
);
4203 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
4206 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4207 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
4208 ARMCPRegInfo rvbar
= {
4209 .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4210 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
4211 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
4213 define_one_arm_cp_reg(cpu
, &rvbar
);
4215 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
4216 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4217 /* PMSAv6 not implemented */
4218 assert(arm_feature(env
, ARM_FEATURE_V7
));
4219 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4220 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
4222 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
4225 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4226 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
4228 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
4229 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
4231 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
4232 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
4234 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
4235 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
4237 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
4238 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
4240 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
4241 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
4243 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
4244 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
4246 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
4247 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
4249 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
4250 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
4252 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
4253 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
4255 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
4256 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
4258 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4259 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
4261 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4262 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4263 * be read-only (ie write causes UNDEF exception).
4266 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
4267 /* Pre-v8 MIDR space.
4268 * Note that the MIDR isn't a simple constant register because
4269 * of the TI925 behaviour where writes to another register can
4270 * cause the MIDR value to change.
4272 * Unimplemented registers in the c15 0 0 0 space default to
4273 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4274 * and friends override accordingly.
4277 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
4278 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
4279 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
4280 .readfn
= midr_read
,
4281 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
4282 .type
= ARM_CP_OVERRIDE
},
4283 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4285 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
4286 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4288 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
4289 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4291 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
4292 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4294 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
4295 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4297 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
4298 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4301 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
4302 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
4303 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
4304 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
4305 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
4306 .readfn
= midr_read
},
4307 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4308 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
4309 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
4310 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
4311 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
4312 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
4313 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
4314 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
4315 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
4316 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
4319 ARMCPRegInfo id_cp_reginfo
[] = {
4320 /* These are common to v8 and pre-v8 */
4322 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
4323 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
4324 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
4325 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
4326 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
4327 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
4328 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4330 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
4331 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4334 /* TLBTR is specific to VMSA */
4335 ARMCPRegInfo id_tlbtr_reginfo
= {
4337 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
4338 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
4340 /* MPUIR is specific to PMSA V6+ */
4341 ARMCPRegInfo id_mpuir_reginfo
= {
4343 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
4344 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4345 .resetvalue
= cpu
->pmsav7_dregion
<< 8
4347 ARMCPRegInfo crn0_wi_reginfo
= {
4348 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
4349 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
4350 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
4352 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
4353 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
4355 /* Register the blanket "writes ignored" value first to cover the
4356 * whole space. Then update the specific ID registers to allow write
4357 * access, so that they ignore writes rather than causing them to
4360 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
4361 for (r
= id_pre_v8_midr_cp_reginfo
;
4362 r
->type
!= ARM_CP_SENTINEL
; r
++) {
4365 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
4368 id_tlbtr_reginfo
.access
= PL1_RW
;
4369 id_tlbtr_reginfo
.access
= PL1_RW
;
4371 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4372 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
4374 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
4376 define_arm_cp_regs(cpu
, id_cp_reginfo
);
4377 if (!arm_feature(env
, ARM_FEATURE_MPU
)) {
4378 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
4379 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
4380 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
4384 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
4385 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
4388 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
4389 ARMCPRegInfo auxcr_reginfo
[] = {
4390 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4391 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
4392 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
4393 .resetvalue
= cpu
->reset_auxcr
},
4394 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4395 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
4396 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4398 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
4399 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
4400 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4404 define_arm_cp_regs(cpu
, auxcr_reginfo
);
4407 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
4408 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
4409 /* 32 bit view is [31:18] 0...0 [43:32]. */
4410 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
4411 | extract64(cpu
->reset_cbar
, 32, 12);
4412 ARMCPRegInfo cbar_reginfo
[] = {
4414 .type
= ARM_CP_CONST
,
4415 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
4416 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
4417 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4418 .type
= ARM_CP_CONST
,
4419 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
4420 .access
= PL1_R
, .resetvalue
= cbar32
},
4423 /* We don't implement a r/w 64 bit CBAR currently */
4424 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
4425 define_arm_cp_regs(cpu
, cbar_reginfo
);
4427 ARMCPRegInfo cbar
= {
4429 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
4430 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
4431 .fieldoffset
= offsetof(CPUARMState
,
4432 cp15
.c15_config_base_address
)
4434 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
4435 cbar
.access
= PL1_R
;
4436 cbar
.fieldoffset
= 0;
4437 cbar
.type
= ARM_CP_CONST
;
4439 define_one_arm_cp_reg(cpu
, &cbar
);
4443 /* Generic registers whose values depend on the implementation */
4445 ARMCPRegInfo sctlr
= {
4446 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
4447 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4449 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
4450 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
4451 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
4452 .raw_writefn
= raw_write
,
4454 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
4455 /* Normally we would always end the TB on an SCTLR write, but Linux
4456 * arch/arm/mach-pxa/sleep.S expects two instructions following
4457 * an MMU enable to execute from cache. Imitate this behaviour.
4459 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
4461 define_one_arm_cp_reg(cpu
, &sctlr
);
4465 ARMCPU
*cpu_arm_init(const char *cpu_model
)
4467 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
4470 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
4472 CPUState
*cs
= CPU(cpu
);
4473 CPUARMState
*env
= &cpu
->env
;
4475 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
4476 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
4477 aarch64_fpu_gdb_set_reg
,
4478 34, "aarch64-fpu.xml", 0);
4479 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
4480 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
4481 51, "arm-neon.xml", 0);
4482 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
4483 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
4484 35, "arm-vfp3.xml", 0);
4485 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
4486 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
4487 19, "arm-vfp.xml", 0);
4491 /* Sort alphabetically by type name, except for "any". */
4492 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
4494 ObjectClass
*class_a
= (ObjectClass
*)a
;
4495 ObjectClass
*class_b
= (ObjectClass
*)b
;
4496 const char *name_a
, *name_b
;
4498 name_a
= object_class_get_name(class_a
);
4499 name_b
= object_class_get_name(class_b
);
4500 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
4502 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
4505 return strcmp(name_a
, name_b
);
4509 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
4511 ObjectClass
*oc
= data
;
4512 CPUListState
*s
= user_data
;
4513 const char *typename
;
4516 typename
= object_class_get_name(oc
);
4517 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
4518 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
4523 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
4527 .cpu_fprintf
= cpu_fprintf
,
4531 list
= object_class_get_list(TYPE_ARM_CPU
, false);
4532 list
= g_slist_sort(list
, arm_cpu_list_compare
);
4533 (*cpu_fprintf
)(f
, "Available CPUs:\n");
4534 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
4537 /* The 'host' CPU type is dynamically registered only if KVM is
4538 * enabled, so we have to special-case it here:
4540 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
4544 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
4546 ObjectClass
*oc
= data
;
4547 CpuDefinitionInfoList
**cpu_list
= user_data
;
4548 CpuDefinitionInfoList
*entry
;
4549 CpuDefinitionInfo
*info
;
4550 const char *typename
;
4552 typename
= object_class_get_name(oc
);
4553 info
= g_malloc0(sizeof(*info
));
4554 info
->name
= g_strndup(typename
,
4555 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
4557 entry
= g_malloc0(sizeof(*entry
));
4558 entry
->value
= info
;
4559 entry
->next
= *cpu_list
;
4563 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
4565 CpuDefinitionInfoList
*cpu_list
= NULL
;
4568 list
= object_class_get_list(TYPE_ARM_CPU
, false);
4569 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
4575 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
4576 void *opaque
, int state
, int secstate
,
4577 int crm
, int opc1
, int opc2
)
4579 /* Private utility function for define_one_arm_cp_reg_with_opaque():
4580 * add a single reginfo struct to the hash table.
4582 uint32_t *key
= g_new(uint32_t, 1);
4583 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
4584 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
4585 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
4587 /* Reset the secure state to the specific incoming state. This is
4588 * necessary as the register may have been defined with both states.
4590 r2
->secure
= secstate
;
4592 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
4593 /* Register is banked (using both entries in array).
4594 * Overwriting fieldoffset as the array is only used to define
4595 * banked registers but later only fieldoffset is used.
4597 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
4600 if (state
== ARM_CP_STATE_AA32
) {
4601 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
4602 /* If the register is banked then we don't need to migrate or
4603 * reset the 32-bit instance in certain cases:
4605 * 1) If the register has both 32-bit and 64-bit instances then we
4606 * can count on the 64-bit instance taking care of the
4608 * 2) If ARMv8 is enabled then we can count on a 64-bit version
4609 * taking care of the secure bank. This requires that separate
4610 * 32 and 64-bit definitions are provided.
4612 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
4613 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
4614 r2
->type
|= ARM_CP_ALIAS
;
4616 } else if ((secstate
!= r
->secure
) && !ns
) {
4617 /* The register is not banked so we only want to allow migration of
4618 * the non-secure instance.
4620 r2
->type
|= ARM_CP_ALIAS
;
4623 if (r
->state
== ARM_CP_STATE_BOTH
) {
4624 /* We assume it is a cp15 register if the .cp field is left unset.
4630 #ifdef HOST_WORDS_BIGENDIAN
4631 if (r2
->fieldoffset
) {
4632 r2
->fieldoffset
+= sizeof(uint32_t);
4637 if (state
== ARM_CP_STATE_AA64
) {
4638 /* To allow abbreviation of ARMCPRegInfo
4639 * definitions, we treat cp == 0 as equivalent to
4640 * the value for "standard guest-visible sysreg".
4641 * STATE_BOTH definitions are also always "standard
4642 * sysreg" in their AArch64 view (the .cp value may
4643 * be non-zero for the benefit of the AArch32 view).
4645 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
4646 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
4648 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
4649 r2
->opc0
, opc1
, opc2
);
4651 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
4654 r2
->opaque
= opaque
;
4656 /* reginfo passed to helpers is correct for the actual access,
4657 * and is never ARM_CP_STATE_BOTH:
4660 /* Make sure reginfo passed to helpers for wildcarded regs
4661 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4666 /* By convention, for wildcarded registers only the first
4667 * entry is used for migration; the others are marked as
4668 * ALIAS so we don't try to transfer the register
4669 * multiple times. Special registers (ie NOP/WFI) are
4670 * never migratable and not even raw-accessible.
4672 if ((r
->type
& ARM_CP_SPECIAL
)) {
4673 r2
->type
|= ARM_CP_NO_RAW
;
4675 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
4676 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
4677 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
4678 r2
->type
|= ARM_CP_ALIAS
;
4681 /* Check that raw accesses are either forbidden or handled. Note that
4682 * we can't assert this earlier because the setup of fieldoffset for
4683 * banked registers has to be done first.
4685 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
4686 assert(!raw_accessors_invalid(r2
));
4689 /* Overriding of an existing definition must be explicitly
4692 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
4693 ARMCPRegInfo
*oldreg
;
4694 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
4695 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
4696 fprintf(stderr
, "Register redefined: cp=%d %d bit "
4697 "crn=%d crm=%d opc1=%d opc2=%d, "
4698 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
4699 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
4700 oldreg
->name
, r2
->name
);
4701 g_assert_not_reached();
4704 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
4708 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
4709 const ARMCPRegInfo
*r
, void *opaque
)
4711 /* Define implementations of coprocessor registers.
4712 * We store these in a hashtable because typically
4713 * there are less than 150 registers in a space which
4714 * is 16*16*16*8*8 = 262144 in size.
4715 * Wildcarding is supported for the crm, opc1 and opc2 fields.
4716 * If a register is defined twice then the second definition is
4717 * used, so this can be used to define some generic registers and
4718 * then override them with implementation specific variations.
4719 * At least one of the original and the second definition should
4720 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4721 * against accidental use.
4723 * The state field defines whether the register is to be
4724 * visible in the AArch32 or AArch64 execution state. If the
4725 * state is set to ARM_CP_STATE_BOTH then we synthesise a
4726 * reginfo structure for the AArch32 view, which sees the lower
4727 * 32 bits of the 64 bit register.
4729 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4730 * be wildcarded. AArch64 registers are always considered to be 64
4731 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4732 * the register, if any.
4734 int crm
, opc1
, opc2
, state
;
4735 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
4736 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
4737 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
4738 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
4739 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
4740 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
4741 /* 64 bit registers have only CRm and Opc1 fields */
4742 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
4743 /* op0 only exists in the AArch64 encodings */
4744 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
4745 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4746 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
4747 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4748 * encodes a minimum access level for the register. We roll this
4749 * runtime check into our general permission check code, so check
4750 * here that the reginfo's specified permissions are strict enough
4751 * to encompass the generic architectural permission check.
4753 if (r
->state
!= ARM_CP_STATE_AA32
) {
4756 case 0: case 1: case 2:
4769 /* unallocated encoding, so not possible */
4777 /* min_EL EL1, secure mode only (we don't check the latter) */
4781 /* broken reginfo with out-of-range opc1 */
4785 /* assert our permissions are not too lax (stricter is fine) */
4786 assert((r
->access
& ~mask
) == 0);
4789 /* Check that the register definition has enough info to handle
4790 * reads and writes if they are permitted.
4792 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
4793 if (r
->access
& PL3_R
) {
4794 assert((r
->fieldoffset
||
4795 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
4798 if (r
->access
& PL3_W
) {
4799 assert((r
->fieldoffset
||
4800 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
4804 /* Bad type field probably means missing sentinel at end of reg list */
4805 assert(cptype_valid(r
->type
));
4806 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
4807 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
4808 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
4809 for (state
= ARM_CP_STATE_AA32
;
4810 state
<= ARM_CP_STATE_AA64
; state
++) {
4811 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
4814 if (state
== ARM_CP_STATE_AA32
) {
4815 /* Under AArch32 CP registers can be common
4816 * (same for secure and non-secure world) or banked.
4818 switch (r
->secure
) {
4819 case ARM_CP_SECSTATE_S
:
4820 case ARM_CP_SECSTATE_NS
:
4821 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4822 r
->secure
, crm
, opc1
, opc2
);
4825 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4828 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4834 /* AArch64 registers get mapped to non-secure instance
4836 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4846 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
4847 const ARMCPRegInfo
*regs
, void *opaque
)
4849 /* Define a whole list of registers */
4850 const ARMCPRegInfo
*r
;
4851 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
4852 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
4856 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
4858 return g_hash_table_lookup(cpregs
, &encoded_cp
);
4861 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4864 /* Helper coprocessor write function for write-ignore registers */
4867 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4869 /* Helper coprocessor write function for read-as-zero registers */
4873 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
4875 /* Helper coprocessor reset function for do-nothing-on-reset registers */
4878 static int bad_mode_switch(CPUARMState
*env
, int mode
)
4880 /* Return true if it is not valid for us to switch to
4881 * this CPU mode (ie all the UNPREDICTABLE cases in
4882 * the ARM ARM CPSRWriteByInstr pseudocode).
4885 case ARM_CPU_MODE_USR
:
4886 case ARM_CPU_MODE_SYS
:
4887 case ARM_CPU_MODE_SVC
:
4888 case ARM_CPU_MODE_ABT
:
4889 case ARM_CPU_MODE_UND
:
4890 case ARM_CPU_MODE_IRQ
:
4891 case ARM_CPU_MODE_FIQ
:
4893 case ARM_CPU_MODE_MON
:
4894 return !arm_is_secure(env
);
4900 uint32_t cpsr_read(CPUARMState
*env
)
4903 ZF
= (env
->ZF
== 0);
4904 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
4905 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
4906 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
4907 | ((env
->condexec_bits
& 0xfc) << 8)
4908 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
4911 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
4913 uint32_t changed_daif
;
4915 if (mask
& CPSR_NZCV
) {
4916 env
->ZF
= (~val
) & CPSR_Z
;
4918 env
->CF
= (val
>> 29) & 1;
4919 env
->VF
= (val
<< 3) & 0x80000000;
4922 env
->QF
= ((val
& CPSR_Q
) != 0);
4924 env
->thumb
= ((val
& CPSR_T
) != 0);
4925 if (mask
& CPSR_IT_0_1
) {
4926 env
->condexec_bits
&= ~3;
4927 env
->condexec_bits
|= (val
>> 25) & 3;
4929 if (mask
& CPSR_IT_2_7
) {
4930 env
->condexec_bits
&= 3;
4931 env
->condexec_bits
|= (val
>> 8) & 0xfc;
4933 if (mask
& CPSR_GE
) {
4934 env
->GE
= (val
>> 16) & 0xf;
4937 /* In a V7 implementation that includes the security extensions but does
4938 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
4939 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
4940 * bits respectively.
4942 * In a V8 implementation, it is permitted for privileged software to
4943 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
4945 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
4946 arm_feature(env
, ARM_FEATURE_EL3
) &&
4947 !arm_feature(env
, ARM_FEATURE_EL2
) &&
4948 !arm_is_secure(env
)) {
4950 changed_daif
= (env
->daif
^ val
) & mask
;
4952 if (changed_daif
& CPSR_A
) {
4953 /* Check to see if we are allowed to change the masking of async
4954 * abort exceptions from a non-secure state.
4956 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
4957 qemu_log_mask(LOG_GUEST_ERROR
,
4958 "Ignoring attempt to switch CPSR_A flag from "
4959 "non-secure world with SCR.AW bit clear\n");
4964 if (changed_daif
& CPSR_F
) {
4965 /* Check to see if we are allowed to change the masking of FIQ
4966 * exceptions from a non-secure state.
4968 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
4969 qemu_log_mask(LOG_GUEST_ERROR
,
4970 "Ignoring attempt to switch CPSR_F flag from "
4971 "non-secure world with SCR.FW bit clear\n");
4975 /* Check whether non-maskable FIQ (NMFI) support is enabled.
4976 * If this bit is set software is not allowed to mask
4977 * FIQs, but is allowed to set CPSR_F to 0.
4979 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
4981 qemu_log_mask(LOG_GUEST_ERROR
,
4982 "Ignoring attempt to enable CPSR_F flag "
4983 "(non-maskable FIQ [NMFI] support enabled)\n");
4989 env
->daif
&= ~(CPSR_AIF
& mask
);
4990 env
->daif
|= val
& CPSR_AIF
& mask
;
4992 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
4993 if (bad_mode_switch(env
, val
& CPSR_M
)) {
4994 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
4995 * We choose to ignore the attempt and leave the CPSR M field
5000 switch_mode(env
, val
& CPSR_M
);
5003 mask
&= ~CACHED_CPSR_BITS
;
5004 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
5007 /* Sign/zero extend */
5008 uint32_t HELPER(sxtb16
)(uint32_t x
)
5011 res
= (uint16_t)(int8_t)x
;
5012 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
5016 uint32_t HELPER(uxtb16
)(uint32_t x
)
5019 res
= (uint16_t)(uint8_t)x
;
5020 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
5024 uint32_t HELPER(clz
)(uint32_t x
)
5029 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
5033 if (num
== INT_MIN
&& den
== -1)
5038 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
5045 uint32_t HELPER(rbit
)(uint32_t x
)
5050 #if defined(CONFIG_USER_ONLY)
5052 /* These should probably raise undefined insn exceptions. */
5053 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
5055 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5057 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
5060 uint32_t QEMU_NORETURN
HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
5062 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5064 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
5067 void switch_mode(CPUARMState
*env
, int mode
)
5069 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5071 if (mode
!= ARM_CPU_MODE_USR
) {
5072 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
5076 void QEMU_NORETURN
HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
5078 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5080 cpu_abort(CPU(cpu
), "banked r13 write\n");
5083 uint32_t QEMU_NORETURN
HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
5085 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5087 cpu_abort(CPU(cpu
), "banked r13 read\n");
5090 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5091 uint32_t cur_el
, bool secure
)
5096 void aarch64_sync_64_to_32(CPUARMState
*env
)
5098 g_assert_not_reached();
5103 /* Map CPU modes onto saved register banks. */
5104 int bank_number(int mode
)
5107 case ARM_CPU_MODE_USR
:
5108 case ARM_CPU_MODE_SYS
:
5110 case ARM_CPU_MODE_SVC
:
5112 case ARM_CPU_MODE_ABT
:
5114 case ARM_CPU_MODE_UND
:
5116 case ARM_CPU_MODE_IRQ
:
5118 case ARM_CPU_MODE_FIQ
:
5120 case ARM_CPU_MODE_HYP
:
5122 case ARM_CPU_MODE_MON
:
5125 g_assert_not_reached();
5128 void switch_mode(CPUARMState
*env
, int mode
)
5133 old_mode
= env
->uncached_cpsr
& CPSR_M
;
5134 if (mode
== old_mode
)
5137 if (old_mode
== ARM_CPU_MODE_FIQ
) {
5138 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5139 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
5140 } else if (mode
== ARM_CPU_MODE_FIQ
) {
5141 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5142 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
5145 i
= bank_number(old_mode
);
5146 env
->banked_r13
[i
] = env
->regs
[13];
5147 env
->banked_r14
[i
] = env
->regs
[14];
5148 env
->banked_spsr
[i
] = env
->spsr
;
5150 i
= bank_number(mode
);
5151 env
->regs
[13] = env
->banked_r13
[i
];
5152 env
->regs
[14] = env
->banked_r14
[i
];
5153 env
->spsr
= env
->banked_spsr
[i
];
5156 /* Physical Interrupt Target EL Lookup Table
5158 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5160 * The below multi-dimensional table is used for looking up the target
5161 * exception level given numerous condition criteria. Specifically, the
5162 * target EL is based on SCR and HCR routing controls as well as the
5163 * currently executing EL and secure state.
5166 * target_el_table[2][2][2][2][2][4]
5167 * | | | | | +--- Current EL
5168 * | | | | +------ Non-secure(0)/Secure(1)
5169 * | | | +--------- HCR mask override
5170 * | | +------------ SCR exec state control
5171 * | +--------------- SCR mask override
5172 * +------------------ 32-bit(0)/64-bit(1) EL3
5174 * The table values are as such:
5178 * The ARM ARM target EL table includes entries indicating that an "exception
5179 * is not taken". The two cases where this is applicable are:
5180 * 1) An exception is taken from EL3 but the SCR does not have the exception
5182 * 2) An exception is taken from EL2 but the HCR does not have the exception
5184 * In these two cases, the below table contain a target of EL1. This value is
5185 * returned as it is expected that the consumer of the table data will check
5186 * for "target EL >= current EL" to ensure the exception is not taken.
5190 * BIT IRQ IMO Non-secure Secure
5191 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
5193 const int8_t target_el_table
[2][2][2][2][2][4] = {
5194 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5195 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
5196 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5197 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
5198 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5199 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
5200 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5201 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
5202 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
5203 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
5204 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
5205 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
5206 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5207 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
5208 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5209 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
5213 * Determine the target EL for physical exceptions
5215 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5216 uint32_t cur_el
, bool secure
)
5218 CPUARMState
*env
= cs
->env_ptr
;
5219 int rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
5223 int is64
= arm_el_is_aa64(env
, 3);
5227 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
5228 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
5231 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
5232 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
5235 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
5236 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
5240 /* If HCR.TGE is set then HCR is treated as being 1 */
5241 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
5243 /* Perform a table-lookup for the target EL given the current state */
5244 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
5246 assert(target_el
> 0);
5251 static void v7m_push(CPUARMState
*env
, uint32_t val
)
5253 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5256 stl_phys(cs
->as
, env
->regs
[13], val
);
5259 static uint32_t v7m_pop(CPUARMState
*env
)
5261 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5264 val
= ldl_phys(cs
->as
, env
->regs
[13]);
5269 /* Switch to V7M main or process stack pointer. */
5270 static void switch_v7m_sp(CPUARMState
*env
, int process
)
5273 if (env
->v7m
.current_sp
!= process
) {
5274 tmp
= env
->v7m
.other_sp
;
5275 env
->v7m
.other_sp
= env
->regs
[13];
5276 env
->regs
[13] = tmp
;
5277 env
->v7m
.current_sp
= process
;
5281 static void do_v7m_exception_exit(CPUARMState
*env
)
5286 type
= env
->regs
[15];
5287 if (env
->v7m
.exception
!= 0)
5288 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
5290 /* Switch to the target stack. */
5291 switch_v7m_sp(env
, (type
& 4) != 0);
5292 /* Pop registers. */
5293 env
->regs
[0] = v7m_pop(env
);
5294 env
->regs
[1] = v7m_pop(env
);
5295 env
->regs
[2] = v7m_pop(env
);
5296 env
->regs
[3] = v7m_pop(env
);
5297 env
->regs
[12] = v7m_pop(env
);
5298 env
->regs
[14] = v7m_pop(env
);
5299 env
->regs
[15] = v7m_pop(env
);
5300 if (env
->regs
[15] & 1) {
5301 qemu_log_mask(LOG_GUEST_ERROR
,
5302 "M profile return from interrupt with misaligned "
5303 "PC is UNPREDICTABLE\n");
5304 /* Actual hardware seems to ignore the lsbit, and there are several
5305 * RTOSes out there which incorrectly assume the r15 in the stack
5306 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5308 env
->regs
[15] &= ~1U;
5310 xpsr
= v7m_pop(env
);
5311 xpsr_write(env
, xpsr
, 0xfffffdff);
5312 /* Undo stack alignment. */
5315 /* ??? The exception return type specifies Thread/Handler mode. However
5316 this is also implied by the xPSR value. Not sure what to do
5317 if there is a mismatch. */
5318 /* ??? Likewise for mismatches between the CONTROL register and the stack
5322 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
5324 ARMCPU
*cpu
= ARM_CPU(cs
);
5325 CPUARMState
*env
= &cpu
->env
;
5326 uint32_t xpsr
= xpsr_read(env
);
5330 arm_log_exception(cs
->exception_index
);
5333 if (env
->v7m
.current_sp
)
5335 if (env
->v7m
.exception
== 0)
5338 /* For exceptions we just mark as pending on the NVIC, and let that
5340 /* TODO: Need to escalate if the current priority is higher than the
5341 one we're raising. */
5342 switch (cs
->exception_index
) {
5344 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
5347 /* The PC already points to the next instruction. */
5348 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
5350 case EXCP_PREFETCH_ABORT
:
5351 case EXCP_DATA_ABORT
:
5352 /* TODO: if we implemented the MPU registers, this is where we
5353 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5355 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
5358 if (semihosting_enabled()) {
5360 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
5363 qemu_log_mask(CPU_LOG_INT
,
5364 "...handling as semihosting call 0x%x\n",
5366 env
->regs
[0] = do_arm_semihosting(env
);
5370 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
5373 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
5375 case EXCP_EXCEPTION_EXIT
:
5376 do_v7m_exception_exit(env
);
5379 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
5380 return; /* Never happens. Keep compiler happy. */
5383 /* Align stack pointer. */
5384 /* ??? Should only do this if Configuration Control Register
5385 STACKALIGN bit is set. */
5386 if (env
->regs
[13] & 4) {
5390 /* Switch to the handler mode. */
5391 v7m_push(env
, xpsr
);
5392 v7m_push(env
, env
->regs
[15]);
5393 v7m_push(env
, env
->regs
[14]);
5394 v7m_push(env
, env
->regs
[12]);
5395 v7m_push(env
, env
->regs
[3]);
5396 v7m_push(env
, env
->regs
[2]);
5397 v7m_push(env
, env
->regs
[1]);
5398 v7m_push(env
, env
->regs
[0]);
5399 switch_v7m_sp(env
, 0);
5401 env
->condexec_bits
= 0;
5403 addr
= ldl_phys(cs
->as
, env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
5404 env
->regs
[15] = addr
& 0xfffffffe;
5405 env
->thumb
= addr
& 1;
5408 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5409 * register set. This is necessary when switching between AArch32 and AArch64
5412 void aarch64_sync_32_to_64(CPUARMState
*env
)
5415 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
5417 /* We can blanket copy R[0:7] to X[0:7] */
5418 for (i
= 0; i
< 8; i
++) {
5419 env
->xregs
[i
] = env
->regs
[i
];
5422 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5423 * Otherwise, they come from the banked user regs.
5425 if (mode
== ARM_CPU_MODE_FIQ
) {
5426 for (i
= 8; i
< 13; i
++) {
5427 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
5430 for (i
= 8; i
< 13; i
++) {
5431 env
->xregs
[i
] = env
->regs
[i
];
5435 /* Registers x13-x23 are the various mode SP and FP registers. Registers
5436 * r13 and r14 are only copied if we are in that mode, otherwise we copy
5437 * from the mode banked register.
5439 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
5440 env
->xregs
[13] = env
->regs
[13];
5441 env
->xregs
[14] = env
->regs
[14];
5443 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
5444 /* HYP is an exception in that it is copied from r14 */
5445 if (mode
== ARM_CPU_MODE_HYP
) {
5446 env
->xregs
[14] = env
->regs
[14];
5448 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
5452 if (mode
== ARM_CPU_MODE_HYP
) {
5453 env
->xregs
[15] = env
->regs
[13];
5455 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
5458 if (mode
== ARM_CPU_MODE_IRQ
) {
5459 env
->xregs
[16] = env
->regs
[14];
5460 env
->xregs
[17] = env
->regs
[13];
5462 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
5463 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
5466 if (mode
== ARM_CPU_MODE_SVC
) {
5467 env
->xregs
[18] = env
->regs
[14];
5468 env
->xregs
[19] = env
->regs
[13];
5470 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
5471 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
5474 if (mode
== ARM_CPU_MODE_ABT
) {
5475 env
->xregs
[20] = env
->regs
[14];
5476 env
->xregs
[21] = env
->regs
[13];
5478 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
5479 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
5482 if (mode
== ARM_CPU_MODE_UND
) {
5483 env
->xregs
[22] = env
->regs
[14];
5484 env
->xregs
[23] = env
->regs
[13];
5486 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
5487 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
5490 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
5491 * mode, then we can copy from r8-r14. Otherwise, we copy from the
5492 * FIQ bank for r8-r14.
5494 if (mode
== ARM_CPU_MODE_FIQ
) {
5495 for (i
= 24; i
< 31; i
++) {
5496 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
5499 for (i
= 24; i
< 29; i
++) {
5500 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
5502 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
5503 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
5506 env
->pc
= env
->regs
[15];
5509 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5510 * register set. This is necessary when switching between AArch32 and AArch64
5513 void aarch64_sync_64_to_32(CPUARMState
*env
)
5516 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
5518 /* We can blanket copy X[0:7] to R[0:7] */
5519 for (i
= 0; i
< 8; i
++) {
5520 env
->regs
[i
] = env
->xregs
[i
];
5523 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5524 * Otherwise, we copy x8-x12 into the banked user regs.
5526 if (mode
== ARM_CPU_MODE_FIQ
) {
5527 for (i
= 8; i
< 13; i
++) {
5528 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
5531 for (i
= 8; i
< 13; i
++) {
5532 env
->regs
[i
] = env
->xregs
[i
];
5536 /* Registers r13 & r14 depend on the current mode.
5537 * If we are in a given mode, we copy the corresponding x registers to r13
5538 * and r14. Otherwise, we copy the x register to the banked r13 and r14
5541 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
5542 env
->regs
[13] = env
->xregs
[13];
5543 env
->regs
[14] = env
->xregs
[14];
5545 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
5547 /* HYP is an exception in that it does not have its own banked r14 but
5548 * shares the USR r14
5550 if (mode
== ARM_CPU_MODE_HYP
) {
5551 env
->regs
[14] = env
->xregs
[14];
5553 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
5557 if (mode
== ARM_CPU_MODE_HYP
) {
5558 env
->regs
[13] = env
->xregs
[15];
5560 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
5563 if (mode
== ARM_CPU_MODE_IRQ
) {
5564 env
->regs
[14] = env
->xregs
[16];
5565 env
->regs
[13] = env
->xregs
[17];
5567 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
5568 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
5571 if (mode
== ARM_CPU_MODE_SVC
) {
5572 env
->regs
[14] = env
->xregs
[18];
5573 env
->regs
[13] = env
->xregs
[19];
5575 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
5576 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
5579 if (mode
== ARM_CPU_MODE_ABT
) {
5580 env
->regs
[14] = env
->xregs
[20];
5581 env
->regs
[13] = env
->xregs
[21];
5583 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
5584 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
5587 if (mode
== ARM_CPU_MODE_UND
) {
5588 env
->regs
[14] = env
->xregs
[22];
5589 env
->regs
[13] = env
->xregs
[23];
5591 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
5592 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
5595 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
5596 * mode, then we can copy to r8-r14. Otherwise, we copy to the
5597 * FIQ bank for r8-r14.
5599 if (mode
== ARM_CPU_MODE_FIQ
) {
5600 for (i
= 24; i
< 31; i
++) {
5601 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
5604 for (i
= 24; i
< 29; i
++) {
5605 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
5607 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
5608 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
5611 env
->regs
[15] = env
->pc
;
5614 /* Handle a CPU exception. */
5615 void arm_cpu_do_interrupt(CPUState
*cs
)
5617 ARMCPU
*cpu
= ARM_CPU(cs
);
5618 CPUARMState
*env
= &cpu
->env
;
5627 arm_log_exception(cs
->exception_index
);
5629 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
5630 arm_handle_psci_call(cpu
);
5631 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
5635 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5636 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
5638 case EC_BREAKPOINT_SAME_EL
:
5642 case EC_WATCHPOINT_SAME_EL
:
5648 case EC_VECTORCATCH
:
5657 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
5660 /* TODO: Vectored interrupt controller. */
5661 switch (cs
->exception_index
) {
5663 new_mode
= ARM_CPU_MODE_UND
;
5672 if (semihosting_enabled()) {
5673 /* Check for semihosting interrupt. */
5675 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
5678 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
5681 /* Only intercept calls from privileged modes, to provide some
5682 semblance of security. */
5683 if (((mask
== 0x123456 && !env
->thumb
)
5684 || (mask
== 0xab && env
->thumb
))
5685 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
5686 qemu_log_mask(CPU_LOG_INT
,
5687 "...handling as semihosting call 0x%x\n",
5689 env
->regs
[0] = do_arm_semihosting(env
);
5693 new_mode
= ARM_CPU_MODE_SVC
;
5696 /* The PC already points to the next instruction. */
5700 /* See if this is a semihosting syscall. */
5701 if (env
->thumb
&& semihosting_enabled()) {
5702 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
5704 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
5706 qemu_log_mask(CPU_LOG_INT
,
5707 "...handling as semihosting call 0x%x\n",
5709 env
->regs
[0] = do_arm_semihosting(env
);
5713 env
->exception
.fsr
= 2;
5714 /* Fall through to prefetch abort. */
5715 case EXCP_PREFETCH_ABORT
:
5716 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
5717 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
5718 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
5719 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
5720 new_mode
= ARM_CPU_MODE_ABT
;
5722 mask
= CPSR_A
| CPSR_I
;
5725 case EXCP_DATA_ABORT
:
5726 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
5727 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
5728 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
5730 (uint32_t)env
->exception
.vaddress
);
5731 new_mode
= ARM_CPU_MODE_ABT
;
5733 mask
= CPSR_A
| CPSR_I
;
5737 new_mode
= ARM_CPU_MODE_IRQ
;
5739 /* Disable IRQ and imprecise data aborts. */
5740 mask
= CPSR_A
| CPSR_I
;
5742 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
5743 /* IRQ routed to monitor mode */
5744 new_mode
= ARM_CPU_MODE_MON
;
5749 new_mode
= ARM_CPU_MODE_FIQ
;
5751 /* Disable FIQ, IRQ and imprecise data aborts. */
5752 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
5753 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
5754 /* FIQ routed to monitor mode */
5755 new_mode
= ARM_CPU_MODE_MON
;
5760 new_mode
= ARM_CPU_MODE_MON
;
5762 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
5766 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
5767 return; /* Never happens. Keep compiler happy. */
5770 if (new_mode
== ARM_CPU_MODE_MON
) {
5771 addr
+= env
->cp15
.mvbar
;
5772 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
5773 /* High vectors. When enabled, base address cannot be remapped. */
5776 /* ARM v7 architectures provide a vector base address register to remap
5777 * the interrupt vector table.
5778 * This register is only followed in non-monitor mode, and is banked.
5779 * Note: only bits 31:5 are valid.
5781 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
5784 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
5785 env
->cp15
.scr_el3
&= ~SCR_NS
;
5788 switch_mode (env
, new_mode
);
5789 /* For exceptions taken to AArch32 we must clear the SS bit in both
5790 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5792 env
->uncached_cpsr
&= ~PSTATE_SS
;
5793 env
->spsr
= cpsr_read(env
);
5794 /* Clear IT bits. */
5795 env
->condexec_bits
= 0;
5796 /* Switch to the new mode, and to the correct instruction set. */
5797 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
5799 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5800 * and we should just guard the thumb mode on V4 */
5801 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
5802 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
5804 env
->regs
[14] = env
->regs
[15] + offset
;
5805 env
->regs
[15] = addr
;
5806 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
5810 /* Return the exception level which controls this address translation regime */
5811 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5814 case ARMMMUIdx_S2NS
:
5815 case ARMMMUIdx_S1E2
:
5817 case ARMMMUIdx_S1E3
:
5819 case ARMMMUIdx_S1SE0
:
5820 return arm_el_is_aa64(env
, 3) ? 1 : 3;
5821 case ARMMMUIdx_S1SE1
:
5822 case ARMMMUIdx_S1NSE0
:
5823 case ARMMMUIdx_S1NSE1
:
5826 g_assert_not_reached();
5830 /* Return true if this address translation regime is secure */
5831 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5834 case ARMMMUIdx_S12NSE0
:
5835 case ARMMMUIdx_S12NSE1
:
5836 case ARMMMUIdx_S1NSE0
:
5837 case ARMMMUIdx_S1NSE1
:
5838 case ARMMMUIdx_S1E2
:
5839 case ARMMMUIdx_S2NS
:
5841 case ARMMMUIdx_S1E3
:
5842 case ARMMMUIdx_S1SE0
:
5843 case ARMMMUIdx_S1SE1
:
5846 g_assert_not_reached();
5850 /* Return the SCTLR value which controls this address translation regime */
5851 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5853 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
5856 /* Return true if the specified stage of address translation is disabled */
5857 static inline bool regime_translation_disabled(CPUARMState
*env
,
5860 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5861 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
5863 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
5866 /* Return the TCR controlling this translation regime */
5867 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5869 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5870 return &env
->cp15
.vtcr_el2
;
5872 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
5875 /* Return the TTBR associated with this translation regime */
5876 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5879 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5880 return env
->cp15
.vttbr_el2
;
5883 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
5885 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
5889 /* Return true if the translation regime is using LPAE format page tables */
5890 static inline bool regime_using_lpae_format(CPUARMState
*env
,
5893 int el
= regime_el(env
, mmu_idx
);
5894 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
5897 if (arm_feature(env
, ARM_FEATURE_LPAE
)
5898 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
5904 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5907 case ARMMMUIdx_S1SE0
:
5908 case ARMMMUIdx_S1NSE0
:
5912 case ARMMMUIdx_S12NSE0
:
5913 case ARMMMUIdx_S12NSE1
:
5914 g_assert_not_reached();
5918 /* Translate section/page access permissions to page
5919 * R/W protection flags
5922 * @mmu_idx: MMU index indicating required translation regime
5923 * @ap: The 3-bit access permissions (AP[2:0])
5924 * @domain_prot: The 2-bit domain access permissions
5926 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5927 int ap
, int domain_prot
)
5929 bool is_user
= regime_is_user(env
, mmu_idx
);
5931 if (domain_prot
== 3) {
5932 return PAGE_READ
| PAGE_WRITE
;
5937 if (arm_feature(env
, ARM_FEATURE_V7
)) {
5940 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
5942 return is_user
? 0 : PAGE_READ
;
5949 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
5954 return PAGE_READ
| PAGE_WRITE
;
5957 return PAGE_READ
| PAGE_WRITE
;
5958 case 4: /* Reserved. */
5961 return is_user
? 0 : PAGE_READ
;
5965 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
5970 g_assert_not_reached();
5974 /* Translate section/page access permissions to page
5975 * R/W protection flags.
5977 * @ap: The 2-bit simple AP (AP[2:1])
5978 * @is_user: TRUE if accessing from PL0
5980 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
5984 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
5986 return PAGE_READ
| PAGE_WRITE
;
5988 return is_user
? 0 : PAGE_READ
;
5992 g_assert_not_reached();
5997 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
5999 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
6002 /* Translate section/page access permissions to protection flags
6005 * @mmu_idx: MMU index indicating required translation regime
6006 * @is_aa64: TRUE if AArch64
6007 * @ap: The 2-bit simple AP (AP[2:1])
6008 * @ns: NS (non-secure) bit
6009 * @xn: XN (execute-never) bit
6010 * @pxn: PXN (privileged execute-never) bit
6012 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
6013 int ap
, int ns
, int xn
, int pxn
)
6015 bool is_user
= regime_is_user(env
, mmu_idx
);
6016 int prot_rw
, user_rw
;
6020 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
6022 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
6026 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
6029 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
6033 /* TODO have_wxn should be replaced with
6034 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6035 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6036 * compatible processors have EL2, which is required for [U]WXN.
6038 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
6041 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
6045 switch (regime_el(env
, mmu_idx
)) {
6048 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
6055 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
6056 switch (regime_el(env
, mmu_idx
)) {
6060 xn
= xn
|| !(user_rw
& PAGE_READ
);
6064 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
6066 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
6067 (uwxn
&& (user_rw
& PAGE_WRITE
));
6077 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
6080 return prot_rw
| PAGE_EXEC
;
6083 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
6084 uint32_t *table
, uint32_t address
)
6086 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6087 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
6089 if (address
& tcr
->mask
) {
6090 if (tcr
->raw_tcr
& TTBCR_PD1
) {
6091 /* Translation table walk disabled for TTBR1 */
6094 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
6096 if (tcr
->raw_tcr
& TTBCR_PD0
) {
6097 /* Translation table walk disabled for TTBR0 */
6100 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
6102 *table
|= (address
>> 18) & 0x3ffc;
6106 /* All loads done in the course of a page table walk go through here.
6107 * TODO: rather than ignoring errors from physical memory reads (which
6108 * are external aborts in ARM terminology) we should propagate this
6109 * error out so that we can turn it into a Data Abort if this walk
6110 * was being done for a CPU load/store or an address translation instruction
6111 * (but not if it was for a debug access).
6113 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
)
6115 MemTxAttrs attrs
= {};
6117 attrs
.secure
= is_secure
;
6118 return address_space_ldl(cs
->as
, addr
, attrs
, NULL
);
6121 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
)
6123 MemTxAttrs attrs
= {};
6125 attrs
.secure
= is_secure
;
6126 return address_space_ldq(cs
->as
, addr
, attrs
, NULL
);
6129 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
6130 int access_type
, ARMMMUIdx mmu_idx
,
6131 hwaddr
*phys_ptr
, int *prot
,
6132 target_ulong
*page_size
, uint32_t *fsr
)
6134 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6145 /* Pagetable walk. */
6146 /* Lookup l1 descriptor. */
6147 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
6148 /* Section translation fault if page walk is disabled by PD0 or PD1 */
6152 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
6154 domain
= (desc
>> 5) & 0x0f;
6155 if (regime_el(env
, mmu_idx
) == 1) {
6156 dacr
= env
->cp15
.dacr_ns
;
6158 dacr
= env
->cp15
.dacr_s
;
6160 domain_prot
= (dacr
>> (domain
* 2)) & 3;
6162 /* Section translation fault. */
6166 if (domain_prot
== 0 || domain_prot
== 2) {
6168 code
= 9; /* Section domain fault. */
6170 code
= 11; /* Page domain fault. */
6175 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
6176 ap
= (desc
>> 10) & 3;
6178 *page_size
= 1024 * 1024;
6180 /* Lookup l2 entry. */
6182 /* Coarse pagetable. */
6183 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
6185 /* Fine pagetable. */
6186 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
6188 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
6190 case 0: /* Page translation fault. */
6193 case 1: /* 64k page. */
6194 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
6195 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
6196 *page_size
= 0x10000;
6198 case 2: /* 4k page. */
6199 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
6200 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
6201 *page_size
= 0x1000;
6203 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6205 /* ARMv6/XScale extended small page format */
6206 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
6207 || arm_feature(env
, ARM_FEATURE_V6
)) {
6208 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
6209 *page_size
= 0x1000;
6211 /* UNPREDICTABLE in ARMv5; we choose to take a
6212 * page translation fault.
6218 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
6221 ap
= (desc
>> 4) & 3;
6224 /* Never happens, but compiler isn't smart enough to tell. */
6229 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
6230 *prot
|= *prot
? PAGE_EXEC
: 0;
6231 if (!(*prot
& (1 << access_type
))) {
6232 /* Access permission fault. */
6235 *phys_ptr
= phys_addr
;
6238 *fsr
= code
| (domain
<< 4);
6242 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
6243 int access_type
, ARMMMUIdx mmu_idx
,
6244 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
6245 target_ulong
*page_size
, uint32_t *fsr
)
6247 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6261 /* Pagetable walk. */
6262 /* Lookup l1 descriptor. */
6263 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
6264 /* Section translation fault if page walk is disabled by PD0 or PD1 */
6268 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
6270 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
6271 /* Section translation fault, or attempt to use the encoding
6272 * which is Reserved on implementations without PXN.
6277 if ((type
== 1) || !(desc
& (1 << 18))) {
6278 /* Page or Section. */
6279 domain
= (desc
>> 5) & 0x0f;
6281 if (regime_el(env
, mmu_idx
) == 1) {
6282 dacr
= env
->cp15
.dacr_ns
;
6284 dacr
= env
->cp15
.dacr_s
;
6286 domain_prot
= (dacr
>> (domain
* 2)) & 3;
6287 if (domain_prot
== 0 || domain_prot
== 2) {
6289 code
= 9; /* Section domain fault. */
6291 code
= 11; /* Page domain fault. */
6296 if (desc
& (1 << 18)) {
6298 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
6299 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
6300 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
6301 *page_size
= 0x1000000;
6304 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
6305 *page_size
= 0x100000;
6307 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
6308 xn
= desc
& (1 << 4);
6311 ns
= extract32(desc
, 19, 1);
6313 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
6314 pxn
= (desc
>> 2) & 1;
6316 ns
= extract32(desc
, 3, 1);
6317 /* Lookup l2 entry. */
6318 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
6319 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
));
6320 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
6322 case 0: /* Page translation fault. */
6325 case 1: /* 64k page. */
6326 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
6327 xn
= desc
& (1 << 15);
6328 *page_size
= 0x10000;
6330 case 2: case 3: /* 4k page. */
6331 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
6333 *page_size
= 0x1000;
6336 /* Never happens, but compiler isn't smart enough to tell. */
6341 if (domain_prot
== 3) {
6342 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
6344 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
6347 if (xn
&& access_type
== 2)
6350 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
6351 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
6352 /* The simplified model uses AP[0] as an access control bit. */
6353 if ((ap
& 1) == 0) {
6354 /* Access flag fault. */
6355 code
= (code
== 15) ? 6 : 3;
6358 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
6360 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
6365 if (!(*prot
& (1 << access_type
))) {
6366 /* Access permission fault. */
6371 /* The NS bit will (as required by the architecture) have no effect if
6372 * the CPU doesn't support TZ or this is a non-secure translation
6373 * regime, because the attribute will already be non-secure.
6375 attrs
->secure
= false;
6377 *phys_ptr
= phys_addr
;
6380 *fsr
= code
| (domain
<< 4);
6384 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6385 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6388 translation_fault
= 1,
6390 permission_fault
= 3,
6393 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
6394 int access_type
, ARMMMUIdx mmu_idx
,
6395 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
6396 target_ulong
*page_size_ptr
, uint32_t *fsr
)
6398 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6399 /* Read an LPAE long-descriptor translation table. */
6400 MMUFaultType fault_type
= translation_fault
;
6407 hwaddr descaddr
, descmask
;
6408 uint32_t tableattrs
;
6409 target_ulong page_size
;
6411 int32_t granule_sz
= 9;
6412 int32_t va_size
= 32;
6414 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
6415 int ap
, ns
, xn
, pxn
;
6416 uint32_t el
= regime_el(env
, mmu_idx
);
6417 bool ttbr1_valid
= true;
6420 * This code does not handle the different format TCR for VTCR_EL2.
6421 * This code also does not support shareability levels.
6422 * Attribute and permission bit handling should also be checked when adding
6423 * support for those page table walks.
6425 if (arm_el_is_aa64(env
, el
)) {
6428 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
6429 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
6432 if (extract64(address
, 55, 1)) {
6433 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
6435 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
6440 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6444 ttbr1_valid
= false;
6447 /* There is no TTBR1 for EL2 */
6449 ttbr1_valid
= false;
6453 /* Determine whether this address is in the region controlled by
6454 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6455 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6456 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6458 uint32_t t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
6459 if (va_size
== 64) {
6460 t0sz
= MIN(t0sz
, 39);
6461 t0sz
= MAX(t0sz
, 16);
6463 uint32_t t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
6464 if (va_size
== 64) {
6465 t1sz
= MIN(t1sz
, 39);
6466 t1sz
= MAX(t1sz
, 16);
6468 if (t0sz
&& !extract64(address
, va_size
- t0sz
, t0sz
- tbi
)) {
6469 /* there is a ttbr0 region and we are in it (high bits all zero) */
6471 } else if (ttbr1_valid
&& t1sz
&&
6472 !extract64(~address
, va_size
- t1sz
, t1sz
- tbi
)) {
6473 /* there is a ttbr1 region and we are in it (high bits all one) */
6476 /* ttbr0 region is "everything not in the ttbr1 region" */
6478 } else if (!t1sz
&& ttbr1_valid
) {
6479 /* ttbr1 region is "everything not in the ttbr0 region" */
6482 /* in the gap between the two regions, this is a Translation fault */
6483 fault_type
= translation_fault
;
6487 /* Note that QEMU ignores shareability and cacheability attributes,
6488 * so we don't need to do anything with the SH, ORGN, IRGN fields
6489 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
6490 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6491 * implement any ASID-like capability so we can ignore it (instead
6492 * we will always flush the TLB any time the ASID is changed).
6494 if (ttbr_select
== 0) {
6495 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
6497 epd
= extract32(tcr
->raw_tcr
, 7, 1);
6501 tg
= extract32(tcr
->raw_tcr
, 14, 2);
6502 if (tg
== 1) { /* 64KB pages */
6505 if (tg
== 2) { /* 16KB pages */
6509 /* We should only be here if TTBR1 is valid */
6510 assert(ttbr1_valid
);
6512 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
6513 epd
= extract32(tcr
->raw_tcr
, 23, 1);
6516 tg
= extract32(tcr
->raw_tcr
, 30, 2);
6517 if (tg
== 3) { /* 64KB pages */
6520 if (tg
== 1) { /* 16KB pages */
6525 /* Here we should have set up all the parameters for the translation:
6526 * va_size, ttbr, epd, tsz, granule_sz, tbi
6530 /* Translation table walk disabled => Translation fault on TLB miss
6531 * Note: This is always 0 on 64-bit EL2 and EL3.
6536 /* The starting level depends on the virtual address size (which can be
6537 * up to 48 bits) and the translation granule size. It indicates the number
6538 * of strides (granule_sz bits at a time) needed to consume the bits
6539 * of the input address. In the pseudocode this is:
6540 * level = 4 - RoundUp((inputsize - grainsize) / stride)
6541 * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
6542 * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
6543 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6544 * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
6545 * = 4 - (va_size - tsz - 4) / granule_sz;
6547 level
= 4 - (va_size
- tsz
- 4) / granule_sz
;
6549 /* Clear the vaddr bits which aren't part of the within-region address,
6550 * so that we don't have to special case things when calculating the
6551 * first descriptor address.
6554 address
&= (1ULL << (va_size
- tsz
)) - 1;
6557 descmask
= (1ULL << (granule_sz
+ 3)) - 1;
6559 /* Now we can extract the actual base address from the TTBR */
6560 descaddr
= extract64(ttbr
, 0, 48);
6561 descaddr
&= ~((1ULL << (va_size
- tsz
- (granule_sz
* (4 - level
)))) - 1);
6563 /* Secure accesses start with the page table in secure memory and
6564 * can be downgraded to non-secure at any step. Non-secure accesses
6565 * remain non-secure. We implement this by just ORing in the NSTable/NS
6566 * bits at each step.
6568 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
6570 uint64_t descriptor
;
6573 descaddr
|= (address
>> (granule_sz
* (4 - level
))) & descmask
;
6575 nstable
= extract32(tableattrs
, 4, 1);
6576 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
);
6577 if (!(descriptor
& 1) ||
6578 (!(descriptor
& 2) && (level
== 3))) {
6579 /* Invalid, or the Reserved level 3 encoding */
6582 descaddr
= descriptor
& 0xfffffff000ULL
;
6584 if ((descriptor
& 2) && (level
< 3)) {
6585 /* Table entry. The top five bits are attributes which may
6586 * propagate down through lower levels of the table (and
6587 * which are all arranged so that 0 means "no effect", so
6588 * we can gather them up by ORing in the bits at each level).
6590 tableattrs
|= extract64(descriptor
, 59, 5);
6594 /* Block entry at level 1 or 2, or page entry at level 3.
6595 * These are basically the same thing, although the number
6596 * of bits we pull in from the vaddr varies.
6598 page_size
= (1ULL << ((granule_sz
* (4 - level
)) + 3));
6599 descaddr
|= (address
& (page_size
- 1));
6600 /* Extract attributes from the descriptor and merge with table attrs */
6601 attrs
= extract64(descriptor
, 2, 10)
6602 | (extract64(descriptor
, 52, 12) << 10);
6603 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
6604 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
6605 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
6606 * means "force PL1 access only", which means forcing AP[1] to 0.
6608 if (extract32(tableattrs
, 2, 1)) {
6611 attrs
|= nstable
<< 3; /* NS */
6614 /* Here descaddr is the final physical address, and attributes
6617 fault_type
= access_fault
;
6618 if ((attrs
& (1 << 8)) == 0) {
6623 ap
= extract32(attrs
, 4, 2);
6624 ns
= extract32(attrs
, 3, 1);
6625 xn
= extract32(attrs
, 12, 1);
6626 pxn
= extract32(attrs
, 11, 1);
6628 *prot
= get_S1prot(env
, mmu_idx
, va_size
== 64, ap
, ns
, xn
, pxn
);
6630 fault_type
= permission_fault
;
6631 if (!(*prot
& (1 << access_type
))) {
6636 /* The NS bit will (as required by the architecture) have no effect if
6637 * the CPU doesn't support TZ or this is a non-secure translation
6638 * regime, because the attribute will already be non-secure.
6640 txattrs
->secure
= false;
6642 *phys_ptr
= descaddr
;
6643 *page_size_ptr
= page_size
;
6647 /* Long-descriptor format IFSR/DFSR value */
6648 *fsr
= (1 << 9) | (fault_type
<< 2) | level
;
6652 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
6654 int32_t address
, int *prot
)
6656 *prot
= PAGE_READ
| PAGE_WRITE
;
6658 case 0xF0000000 ... 0xFFFFFFFF:
6659 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) { /* hivecs execing is ok */
6663 case 0x00000000 ... 0x7FFFFFFF:
6670 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
6671 int access_type
, ARMMMUIdx mmu_idx
,
6672 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
6674 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6676 bool is_user
= regime_is_user(env
, mmu_idx
);
6678 *phys_ptr
= address
;
6681 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
6682 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
6683 } else { /* MPU enabled */
6684 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
6686 uint32_t base
= env
->pmsav7
.drbar
[n
];
6687 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
6691 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
6696 qemu_log_mask(LOG_GUEST_ERROR
, "DRSR.Rsize field can not be 0");
6700 rmask
= (1ull << rsize
) - 1;
6703 qemu_log_mask(LOG_GUEST_ERROR
, "DRBAR %" PRIx32
" misaligned "
6704 "to DRSR region size, mask = %" PRIx32
,
6709 if (address
< base
|| address
> base
+ rmask
) {
6713 /* Region matched */
6715 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
6717 uint32_t srdis_mask
;
6719 rsize
-= 3; /* sub region size (power of 2) */
6720 snd
= ((address
- base
) >> rsize
) & 0x7;
6721 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
6723 srdis_mask
= srdis
? 0x3 : 0x0;
6724 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
6725 /* This will check in groups of 2, 4 and then 8, whether
6726 * the subregion bits are consistent. rsize is incremented
6727 * back up to give the region size, considering consistent
6728 * adjacent subregions as one region. Stop testing if rsize
6729 * is already big enough for an entire QEMU page.
6731 int snd_rounded
= snd
& ~(i
- 1);
6732 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
6733 snd_rounded
+ 8, i
);
6734 if (srdis_mask
^ srdis_multi
) {
6737 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
6741 if (rsize
< TARGET_PAGE_BITS
) {
6742 qemu_log_mask(LOG_UNIMP
, "No support for MPU (sub)region"
6743 "alignment of %" PRIu32
" bits. Minimum is %d\n",
6744 rsize
, TARGET_PAGE_BITS
);
6753 if (n
== -1) { /* no hits */
6754 if (cpu
->pmsav7_dregion
&&
6755 (is_user
|| !(regime_sctlr(env
, mmu_idx
) & SCTLR_BR
))) {
6756 /* background fault */
6760 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
6761 } else { /* a MPU hit! */
6762 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
6764 if (is_user
) { /* User mode AP bit decoding */
6769 break; /* no access */
6771 *prot
|= PAGE_WRITE
;
6775 *prot
|= PAGE_READ
| PAGE_EXEC
;
6778 qemu_log_mask(LOG_GUEST_ERROR
,
6779 "Bad value for AP bits in DRACR %"
6782 } else { /* Priv. mode AP bits decoding */
6785 break; /* no access */
6789 *prot
|= PAGE_WRITE
;
6793 *prot
|= PAGE_READ
| PAGE_EXEC
;
6796 qemu_log_mask(LOG_GUEST_ERROR
,
6797 "Bad value for AP bits in DRACR %"
6803 if (env
->pmsav7
.dracr
[n
] & (1 << 12)) {
6804 *prot
&= ~PAGE_EXEC
;
6809 *fsr
= 0x00d; /* Permission fault */
6810 return !(*prot
& (1 << access_type
));
6813 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
6814 int access_type
, ARMMMUIdx mmu_idx
,
6815 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
6820 bool is_user
= regime_is_user(env
, mmu_idx
);
6822 *phys_ptr
= address
;
6823 for (n
= 7; n
>= 0; n
--) {
6824 base
= env
->cp15
.c6_region
[n
];
6825 if ((base
& 1) == 0) {
6828 mask
= 1 << ((base
>> 1) & 0x1f);
6829 /* Keep this shift separate from the above to avoid an
6830 (undefined) << 32. */
6831 mask
= (mask
<< 1) - 1;
6832 if (((base
^ address
) & ~mask
) == 0) {
6841 if (access_type
== 2) {
6842 mask
= env
->cp15
.pmsav5_insn_ap
;
6844 mask
= env
->cp15
.pmsav5_data_ap
;
6846 mask
= (mask
>> (n
* 4)) & 0xf;
6856 *prot
= PAGE_READ
| PAGE_WRITE
;
6861 *prot
|= PAGE_WRITE
;
6865 *prot
= PAGE_READ
| PAGE_WRITE
;
6878 /* Bad permission. */
6886 /* get_phys_addr - get the physical address for this virtual address
6888 * Find the physical address corresponding to the given virtual address,
6889 * by doing a translation table walk on MMU based systems or using the
6890 * MPU state on MPU based systems.
6892 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
6893 * prot and page_size may not be filled in, and the populated fsr value provides
6894 * information on why the translation aborted, in the format of a
6895 * DFSR/IFSR fault register, with the following caveats:
6896 * * we honour the short vs long DFSR format differences.
6897 * * the WnR bit is never set (the caller must do this).
6898 * * for PSMAv5 based systems we don't bother to return a full FSR format
6902 * @address: virtual address to get physical address for
6903 * @access_type: 0 for read, 1 for write, 2 for execute
6904 * @mmu_idx: MMU index indicating required translation regime
6905 * @phys_ptr: set to the physical address corresponding to the virtual address
6906 * @attrs: set to the memory transaction attributes to use
6907 * @prot: set to the permissions for the page containing phys_ptr
6908 * @page_size: set to the size of the page containing phys_ptr
6909 * @fsr: set to the DFSR/IFSR value on failure
6911 static inline bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
6912 int access_type
, ARMMMUIdx mmu_idx
,
6913 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
6914 target_ulong
*page_size
, uint32_t *fsr
)
6916 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
6917 /* TODO: when we support EL2 we should here call ourselves recursively
6918 * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
6919 * functions will also need changing to perform ARMMMUIdx_S2NS loads
6920 * rather than direct physical memory loads when appropriate.
6921 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
6923 assert(!arm_feature(env
, ARM_FEATURE_EL2
));
6924 mmu_idx
+= ARMMMUIdx_S1NSE0
;
6927 /* The page table entries may downgrade secure to non-secure, but
6928 * cannot upgrade an non-secure translation regime's attributes
6931 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
6932 attrs
->user
= regime_is_user(env
, mmu_idx
);
6934 /* Fast Context Switch Extension. This doesn't exist at all in v8.
6935 * In v7 and earlier it affects all stage 1 translations.
6937 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
6938 && !arm_feature(env
, ARM_FEATURE_V8
)) {
6939 if (regime_el(env
, mmu_idx
) == 3) {
6940 address
+= env
->cp15
.fcseidr_s
;
6942 address
+= env
->cp15
.fcseidr_ns
;
6946 /* pmsav7 has special handling for when MPU is disabled so call it before
6947 * the common MMU/MPU disabled check below.
6949 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
6950 arm_feature(env
, ARM_FEATURE_V7
)) {
6951 *page_size
= TARGET_PAGE_SIZE
;
6952 return get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
6953 phys_ptr
, prot
, fsr
);
6956 if (regime_translation_disabled(env
, mmu_idx
)) {
6957 /* MMU/MPU disabled. */
6958 *phys_ptr
= address
;
6959 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
6960 *page_size
= TARGET_PAGE_SIZE
;
6964 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
6966 *page_size
= TARGET_PAGE_SIZE
;
6967 return get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
6968 phys_ptr
, prot
, fsr
);
6971 if (regime_using_lpae_format(env
, mmu_idx
)) {
6972 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, phys_ptr
,
6973 attrs
, prot
, page_size
, fsr
);
6974 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
6975 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
, phys_ptr
,
6976 attrs
, prot
, page_size
, fsr
);
6978 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
, phys_ptr
,
6979 prot
, page_size
, fsr
);
6983 /* Walk the page table and (if the mapping exists) add the page
6984 * to the TLB. Return false on success, or true on failure. Populate
6985 * fsr with ARM DFSR/IFSR fault register format value on failure.
6987 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
6988 int access_type
, int mmu_idx
, uint32_t *fsr
)
6990 ARMCPU
*cpu
= ARM_CPU(cs
);
6991 CPUARMState
*env
= &cpu
->env
;
6993 target_ulong page_size
;
6996 MemTxAttrs attrs
= {};
6998 ret
= get_phys_addr(env
, address
, access_type
, mmu_idx
, &phys_addr
,
6999 &attrs
, &prot
, &page_size
, fsr
);
7001 /* Map a single [sub]page. */
7002 phys_addr
&= TARGET_PAGE_MASK
;
7003 address
&= TARGET_PAGE_MASK
;
7004 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
7005 prot
, mmu_idx
, page_size
);
7012 hwaddr
arm_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
7014 ARMCPU
*cpu
= ARM_CPU(cs
);
7015 CPUARMState
*env
= &cpu
->env
;
7017 target_ulong page_size
;
7021 MemTxAttrs attrs
= {};
7023 ret
= get_phys_addr(env
, addr
, 0, cpu_mmu_index(env
, false), &phys_addr
,
7024 &attrs
, &prot
, &page_size
, &fsr
);
7033 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
7035 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
7036 env
->regs
[13] = val
;
7038 env
->banked_r13
[bank_number(mode
)] = val
;
7042 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
7044 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
7045 return env
->regs
[13];
7047 return env
->banked_r13
[bank_number(mode
)];
7051 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
7053 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7057 return xpsr_read(env
) & 0xf8000000;
7059 return xpsr_read(env
) & 0xf80001ff;
7061 return xpsr_read(env
) & 0xff00fc00;
7063 return xpsr_read(env
) & 0xff00fdff;
7065 return xpsr_read(env
) & 0x000001ff;
7067 return xpsr_read(env
) & 0x0700fc00;
7069 return xpsr_read(env
) & 0x0700edff;
7071 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
7073 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
7074 case 16: /* PRIMASK */
7075 return (env
->daif
& PSTATE_I
) != 0;
7076 case 17: /* BASEPRI */
7077 case 18: /* BASEPRI_MAX */
7078 return env
->v7m
.basepri
;
7079 case 19: /* FAULTMASK */
7080 return (env
->daif
& PSTATE_F
) != 0;
7081 case 20: /* CONTROL */
7082 return env
->v7m
.control
;
7084 /* ??? For debugging only. */
7085 cpu_abort(CPU(cpu
), "Unimplemented system register read (%d)\n", reg
);
7090 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
7092 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7096 xpsr_write(env
, val
, 0xf8000000);
7099 xpsr_write(env
, val
, 0xf8000000);
7102 xpsr_write(env
, val
, 0xfe00fc00);
7105 xpsr_write(env
, val
, 0xfe00fc00);
7108 /* IPSR bits are readonly. */
7111 xpsr_write(env
, val
, 0x0600fc00);
7114 xpsr_write(env
, val
, 0x0600fc00);
7117 if (env
->v7m
.current_sp
)
7118 env
->v7m
.other_sp
= val
;
7120 env
->regs
[13] = val
;
7123 if (env
->v7m
.current_sp
)
7124 env
->regs
[13] = val
;
7126 env
->v7m
.other_sp
= val
;
7128 case 16: /* PRIMASK */
7130 env
->daif
|= PSTATE_I
;
7132 env
->daif
&= ~PSTATE_I
;
7135 case 17: /* BASEPRI */
7136 env
->v7m
.basepri
= val
& 0xff;
7138 case 18: /* BASEPRI_MAX */
7140 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
7141 env
->v7m
.basepri
= val
;
7143 case 19: /* FAULTMASK */
7145 env
->daif
|= PSTATE_F
;
7147 env
->daif
&= ~PSTATE_F
;
7150 case 20: /* CONTROL */
7151 env
->v7m
.control
= val
& 3;
7152 switch_v7m_sp(env
, (val
& 2) != 0);
7155 /* ??? For debugging only. */
7156 cpu_abort(CPU(cpu
), "Unimplemented system register write (%d)\n", reg
);
7163 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
7165 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7166 * Note that we do not implement the (architecturally mandated)
7167 * alignment fault for attempts to use this on Device memory
7168 * (which matches the usual QEMU behaviour of not implementing either
7169 * alignment faults or any memory attribute handling).
7172 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7173 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
7174 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
7176 #ifndef CONFIG_USER_ONLY
7178 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7179 * the block size so we might have to do more than one TLB lookup.
7180 * We know that in fact for any v8 CPU the page size is at least 4K
7181 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7182 * 1K as an artefact of legacy v5 subpage support being present in the
7183 * same QEMU executable.
7185 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
7186 void *hostaddr
[maxidx
];
7188 unsigned mmu_idx
= cpu_mmu_index(env
, false);
7189 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
7191 for (try = 0; try < 2; try++) {
7193 for (i
= 0; i
< maxidx
; i
++) {
7194 hostaddr
[i
] = tlb_vaddr_to_host(env
,
7195 vaddr
+ TARGET_PAGE_SIZE
* i
,
7202 /* If it's all in the TLB it's fair game for just writing to;
7203 * we know we don't need to update dirty status, etc.
7205 for (i
= 0; i
< maxidx
- 1; i
++) {
7206 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
7208 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
7211 /* OK, try a store and see if we can populate the tlb. This
7212 * might cause an exception if the memory isn't writable,
7213 * in which case we will longjmp out of here. We must for
7214 * this purpose use the actual register value passed to us
7215 * so that we get the fault address right.
7217 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETRA());
7218 /* Now we can populate the other TLB entries, if any */
7219 for (i
= 0; i
< maxidx
; i
++) {
7220 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
7221 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
7222 helper_ret_stb_mmu(env
, va
, 0, oi
, GETRA());
7227 /* Slow path (probably attempt to do this to an I/O device or
7228 * similar, or clearing of a block of code we have translations
7229 * cached for). Just do a series of byte writes as the architecture
7230 * demands. It's not worth trying to use a cpu_physical_memory_map(),
7231 * memset(), unmap() sequence here because:
7232 * + we'd need to account for the blocksize being larger than a page
7233 * + the direct-RAM access case is almost always going to be dealt
7234 * with in the fastpath code above, so there's no speed benefit
7235 * + we would have to deal with the map returning NULL because the
7236 * bounce buffer was in use
7238 for (i
= 0; i
< blocklen
; i
++) {
7239 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETRA());
7243 memset(g2h(vaddr
), 0, blocklen
);
7247 /* Note that signed overflow is undefined in C. The following routines are
7248 careful to use unsigned types where modulo arithmetic is required.
7249 Failure to do so _will_ break on newer gcc. */
7251 /* Signed saturating arithmetic. */
7253 /* Perform 16-bit signed saturating addition. */
7254 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
7259 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
7268 /* Perform 8-bit signed saturating addition. */
7269 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
7274 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
7283 /* Perform 16-bit signed saturating subtraction. */
7284 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
7289 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
7298 /* Perform 8-bit signed saturating subtraction. */
7299 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
7304 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
7313 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7314 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7315 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
7316 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
7319 #include "op_addsub.h"
7321 /* Unsigned saturating arithmetic. */
7322 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
7331 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
7339 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
7348 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
7356 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7357 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7358 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
7359 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
7362 #include "op_addsub.h"
7364 /* Signed modulo arithmetic. */
7365 #define SARITH16(a, b, n, op) do { \
7367 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7368 RESULT(sum, n, 16); \
7370 ge |= 3 << (n * 2); \
7373 #define SARITH8(a, b, n, op) do { \
7375 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7376 RESULT(sum, n, 8); \
7382 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7383 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7384 #define ADD8(a, b, n) SARITH8(a, b, n, +)
7385 #define SUB8(a, b, n) SARITH8(a, b, n, -)
7389 #include "op_addsub.h"
7391 /* Unsigned modulo arithmetic. */
7392 #define ADD16(a, b, n) do { \
7394 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7395 RESULT(sum, n, 16); \
7396 if ((sum >> 16) == 1) \
7397 ge |= 3 << (n * 2); \
7400 #define ADD8(a, b, n) do { \
7402 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7403 RESULT(sum, n, 8); \
7404 if ((sum >> 8) == 1) \
7408 #define SUB16(a, b, n) do { \
7410 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7411 RESULT(sum, n, 16); \
7412 if ((sum >> 16) == 0) \
7413 ge |= 3 << (n * 2); \
7416 #define SUB8(a, b, n) do { \
7418 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7419 RESULT(sum, n, 8); \
7420 if ((sum >> 8) == 0) \
7427 #include "op_addsub.h"
7429 /* Halved signed arithmetic. */
7430 #define ADD16(a, b, n) \
7431 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7432 #define SUB16(a, b, n) \
7433 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7434 #define ADD8(a, b, n) \
7435 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7436 #define SUB8(a, b, n) \
7437 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7440 #include "op_addsub.h"
7442 /* Halved unsigned arithmetic. */
7443 #define ADD16(a, b, n) \
7444 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7445 #define SUB16(a, b, n) \
7446 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7447 #define ADD8(a, b, n) \
7448 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7449 #define SUB8(a, b, n) \
7450 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7453 #include "op_addsub.h"
7455 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
7463 /* Unsigned sum of absolute byte differences. */
7464 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
7467 sum
= do_usad(a
, b
);
7468 sum
+= do_usad(a
>> 8, b
>> 8);
7469 sum
+= do_usad(a
>> 16, b
>>16);
7470 sum
+= do_usad(a
>> 24, b
>> 24);
7474 /* For ARMv6 SEL instruction. */
7475 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
7488 return (a
& mask
) | (b
& ~mask
);
7491 /* VFP support. We follow the convention used for VFP instructions:
7492 Single precision routines have a "s" suffix, double precision a
7495 /* Convert host exception flags to vfp form. */
7496 static inline int vfp_exceptbits_from_host(int host_bits
)
7498 int target_bits
= 0;
7500 if (host_bits
& float_flag_invalid
)
7502 if (host_bits
& float_flag_divbyzero
)
7504 if (host_bits
& float_flag_overflow
)
7506 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
7508 if (host_bits
& float_flag_inexact
)
7509 target_bits
|= 0x10;
7510 if (host_bits
& float_flag_input_denormal
)
7511 target_bits
|= 0x80;
7515 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
7520 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
7521 | (env
->vfp
.vec_len
<< 16)
7522 | (env
->vfp
.vec_stride
<< 20);
7523 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
7524 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
7525 fpscr
|= vfp_exceptbits_from_host(i
);
7529 uint32_t vfp_get_fpscr(CPUARMState
*env
)
7531 return HELPER(vfp_get_fpscr
)(env
);
7534 /* Convert vfp exception flags to target form. */
7535 static inline int vfp_exceptbits_to_host(int target_bits
)
7539 if (target_bits
& 1)
7540 host_bits
|= float_flag_invalid
;
7541 if (target_bits
& 2)
7542 host_bits
|= float_flag_divbyzero
;
7543 if (target_bits
& 4)
7544 host_bits
|= float_flag_overflow
;
7545 if (target_bits
& 8)
7546 host_bits
|= float_flag_underflow
;
7547 if (target_bits
& 0x10)
7548 host_bits
|= float_flag_inexact
;
7549 if (target_bits
& 0x80)
7550 host_bits
|= float_flag_input_denormal
;
7554 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
7559 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
7560 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
7561 env
->vfp
.vec_len
= (val
>> 16) & 7;
7562 env
->vfp
.vec_stride
= (val
>> 20) & 3;
7565 if (changed
& (3 << 22)) {
7566 i
= (val
>> 22) & 3;
7568 case FPROUNDING_TIEEVEN
:
7569 i
= float_round_nearest_even
;
7571 case FPROUNDING_POSINF
:
7574 case FPROUNDING_NEGINF
:
7575 i
= float_round_down
;
7577 case FPROUNDING_ZERO
:
7578 i
= float_round_to_zero
;
7581 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
7583 if (changed
& (1 << 24)) {
7584 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
7585 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
7587 if (changed
& (1 << 25))
7588 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
7590 i
= vfp_exceptbits_to_host(val
);
7591 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
7592 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
7595 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
7597 HELPER(vfp_set_fpscr
)(env
, val
);
7600 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
7602 #define VFP_BINOP(name) \
7603 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
7605 float_status *fpst = fpstp; \
7606 return float32_ ## name(a, b, fpst); \
7608 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
7610 float_status *fpst = fpstp; \
7611 return float64_ ## name(a, b, fpst); \
7623 float32
VFP_HELPER(neg
, s
)(float32 a
)
7625 return float32_chs(a
);
7628 float64
VFP_HELPER(neg
, d
)(float64 a
)
7630 return float64_chs(a
);
7633 float32
VFP_HELPER(abs
, s
)(float32 a
)
7635 return float32_abs(a
);
7638 float64
VFP_HELPER(abs
, d
)(float64 a
)
7640 return float64_abs(a
);
7643 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
7645 return float32_sqrt(a
, &env
->vfp
.fp_status
);
7648 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
7650 return float64_sqrt(a
, &env
->vfp
.fp_status
);
7653 /* XXX: check quiet/signaling case */
7654 #define DO_VFP_cmp(p, type) \
7655 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
7658 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
7659 case 0: flags = 0x6; break; \
7660 case -1: flags = 0x8; break; \
7661 case 1: flags = 0x2; break; \
7662 default: case 2: flags = 0x3; break; \
7664 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7665 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7667 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
7670 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
7671 case 0: flags = 0x6; break; \
7672 case -1: flags = 0x8; break; \
7673 case 1: flags = 0x2; break; \
7674 default: case 2: flags = 0x3; break; \
7676 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
7677 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
7679 DO_VFP_cmp(s
, float32
)
7680 DO_VFP_cmp(d
, float64
)
7683 /* Integer to float and float to integer conversions */
7685 #define CONV_ITOF(name, fsz, sign) \
7686 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
7688 float_status *fpst = fpstp; \
7689 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
7692 #define CONV_FTOI(name, fsz, sign, round) \
7693 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
7695 float_status *fpst = fpstp; \
7696 if (float##fsz##_is_any_nan(x)) { \
7697 float_raise(float_flag_invalid, fpst); \
7700 return float##fsz##_to_##sign##int32##round(x, fpst); \
7703 #define FLOAT_CONVS(name, p, fsz, sign) \
7704 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
7705 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
7706 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
7708 FLOAT_CONVS(si
, s
, 32, )
7709 FLOAT_CONVS(si
, d
, 64, )
7710 FLOAT_CONVS(ui
, s
, 32, u
)
7711 FLOAT_CONVS(ui
, d
, 64, u
)
7717 /* floating point conversion */
7718 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
7720 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
7721 /* ARM requires that S<->D conversion of any kind of NaN generates
7722 * a quiet NaN by forcing the most significant frac bit to 1.
7724 return float64_maybe_silence_nan(r
);
7727 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
7729 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
7730 /* ARM requires that S<->D conversion of any kind of NaN generates
7731 * a quiet NaN by forcing the most significant frac bit to 1.
7733 return float32_maybe_silence_nan(r
);
7736 /* VFP3 fixed point conversion. */
7737 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
7738 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
7741 float_status *fpst = fpstp; \
7743 tmp = itype##_to_##float##fsz(x, fpst); \
7744 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
7747 /* Notice that we want only input-denormal exception flags from the
7748 * scalbn operation: the other possible flags (overflow+inexact if
7749 * we overflow to infinity, output-denormal) aren't correct for the
7750 * complete scale-and-convert operation.
7752 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
7753 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
7757 float_status *fpst = fpstp; \
7758 int old_exc_flags = get_float_exception_flags(fpst); \
7760 if (float##fsz##_is_any_nan(x)) { \
7761 float_raise(float_flag_invalid, fpst); \
7764 tmp = float##fsz##_scalbn(x, shift, fpst); \
7765 old_exc_flags |= get_float_exception_flags(fpst) \
7766 & float_flag_input_denormal; \
7767 set_float_exception_flags(old_exc_flags, fpst); \
7768 return float##fsz##_to_##itype##round(tmp, fpst); \
7771 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
7772 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
7773 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
7774 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
7776 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
7777 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
7778 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
7780 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
7781 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
7782 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
7783 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
7784 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
7785 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
7786 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
7787 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
7788 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
7789 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
7790 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
7791 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
7793 #undef VFP_CONV_FIX_FLOAT
7794 #undef VFP_CONV_FLOAT_FIX_ROUND
7796 /* Set the current fp rounding mode and return the old one.
7797 * The argument is a softfloat float_round_ value.
7799 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
7801 float_status
*fp_status
= &env
->vfp
.fp_status
;
7803 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
7804 set_float_rounding_mode(rmode
, fp_status
);
7809 /* Set the current fp rounding mode in the standard fp status and return
7810 * the old one. This is for NEON instructions that need to change the
7811 * rounding mode but wish to use the standard FPSCR values for everything
7812 * else. Always set the rounding mode back to the correct value after
7814 * The argument is a softfloat float_round_ value.
7816 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
7818 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
7820 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
7821 set_float_rounding_mode(rmode
, fp_status
);
7826 /* Half precision conversions. */
7827 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
7829 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7830 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
7832 return float32_maybe_silence_nan(r
);
7837 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
7839 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7840 float16 r
= float32_to_float16(a
, ieee
, s
);
7842 r
= float16_maybe_silence_nan(r
);
7844 return float16_val(r
);
7847 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
7849 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
7852 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
7854 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
7857 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
7859 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
7862 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
7864 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
7867 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
7869 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7870 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
7872 return float64_maybe_silence_nan(r
);
7877 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
7879 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
7880 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
7882 r
= float16_maybe_silence_nan(r
);
7884 return float16_val(r
);
7887 #define float32_two make_float32(0x40000000)
7888 #define float32_three make_float32(0x40400000)
7889 #define float32_one_point_five make_float32(0x3fc00000)
7891 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
7893 float_status
*s
= &env
->vfp
.standard_fp_status
;
7894 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
7895 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
7896 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
7897 float_raise(float_flag_input_denormal
, s
);
7901 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
7904 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
7906 float_status
*s
= &env
->vfp
.standard_fp_status
;
7908 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
7909 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
7910 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
7911 float_raise(float_flag_input_denormal
, s
);
7913 return float32_one_point_five
;
7915 product
= float32_mul(a
, b
, s
);
7916 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
7921 /* Constants 256 and 512 are used in some helpers; we avoid relying on
7922 * int->float conversions at run-time. */
7923 #define float64_256 make_float64(0x4070000000000000LL)
7924 #define float64_512 make_float64(0x4080000000000000LL)
7925 #define float32_maxnorm make_float32(0x7f7fffff)
7926 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
7928 /* Reciprocal functions
7930 * The algorithm that must be used to calculate the estimate
7931 * is specified by the ARM ARM, see FPRecipEstimate()
7934 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
7936 /* These calculations mustn't set any fp exception flags,
7937 * so we use a local copy of the fp_status.
7939 float_status dummy_status
= *real_fp_status
;
7940 float_status
*s
= &dummy_status
;
7941 /* q = (int)(a * 512.0) */
7942 float64 q
= float64_mul(float64_512
, a
, s
);
7943 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
7945 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
7946 q
= int64_to_float64(q_int
, s
);
7947 q
= float64_add(q
, float64_half
, s
);
7948 q
= float64_div(q
, float64_512
, s
);
7949 q
= float64_div(float64_one
, q
, s
);
7951 /* s = (int)(256.0 * r + 0.5) */
7952 q
= float64_mul(q
, float64_256
, s
);
7953 q
= float64_add(q
, float64_half
, s
);
7954 q_int
= float64_to_int64_round_to_zero(q
, s
);
7956 /* return (double)s / 256.0 */
7957 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
7960 /* Common wrapper to call recip_estimate */
7961 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
7963 uint64_t val64
= float64_val(num
);
7964 uint64_t frac
= extract64(val64
, 0, 52);
7965 int64_t exp
= extract64(val64
, 52, 11);
7967 float64 scaled
, estimate
;
7969 /* Generate the scaled number for the estimate function */
7971 if (extract64(frac
, 51, 1) == 0) {
7973 frac
= extract64(frac
, 0, 50) << 2;
7975 frac
= extract64(frac
, 0, 51) << 1;
7979 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
7980 scaled
= make_float64((0x3feULL
<< 52)
7981 | extract64(frac
, 44, 8) << 44);
7983 estimate
= recip_estimate(scaled
, fpst
);
7985 /* Build new result */
7986 val64
= float64_val(estimate
);
7987 sbit
= 0x8000000000000000ULL
& val64
;
7989 frac
= extract64(val64
, 0, 52);
7992 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
7993 } else if (exp
== -1) {
7994 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
7998 return make_float64(sbit
| (exp
<< 52) | frac
);
8001 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
8003 switch (fpst
->float_rounding_mode
) {
8004 case float_round_nearest_even
: /* Round to Nearest */
8006 case float_round_up
: /* Round to +Inf */
8008 case float_round_down
: /* Round to -Inf */
8010 case float_round_to_zero
: /* Round to Zero */
8014 g_assert_not_reached();
8017 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
8019 float_status
*fpst
= fpstp
;
8020 float32 f32
= float32_squash_input_denormal(input
, fpst
);
8021 uint32_t f32_val
= float32_val(f32
);
8022 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
8023 int32_t f32_exp
= extract32(f32_val
, 23, 8);
8024 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
8030 if (float32_is_any_nan(f32
)) {
8032 if (float32_is_signaling_nan(f32
)) {
8033 float_raise(float_flag_invalid
, fpst
);
8034 nan
= float32_maybe_silence_nan(f32
);
8036 if (fpst
->default_nan_mode
) {
8037 nan
= float32_default_nan
;
8040 } else if (float32_is_infinity(f32
)) {
8041 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
8042 } else if (float32_is_zero(f32
)) {
8043 float_raise(float_flag_divbyzero
, fpst
);
8044 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
8045 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
8046 /* Abs(value) < 2.0^-128 */
8047 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
8048 if (round_to_inf(fpst
, f32_sbit
)) {
8049 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
8051 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
8053 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
8054 float_raise(float_flag_underflow
, fpst
);
8055 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
8059 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
8060 r64
= call_recip_estimate(f64
, 253, fpst
);
8061 r64_val
= float64_val(r64
);
8062 r64_exp
= extract64(r64_val
, 52, 11);
8063 r64_frac
= extract64(r64_val
, 0, 52);
8065 /* result = sign : result_exp<7:0> : fraction<51:29>; */
8066 return make_float32(f32_sbit
|
8067 (r64_exp
& 0xff) << 23 |
8068 extract64(r64_frac
, 29, 24));
8071 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
8073 float_status
*fpst
= fpstp
;
8074 float64 f64
= float64_squash_input_denormal(input
, fpst
);
8075 uint64_t f64_val
= float64_val(f64
);
8076 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
8077 int64_t f64_exp
= extract64(f64_val
, 52, 11);
8083 /* Deal with any special cases */
8084 if (float64_is_any_nan(f64
)) {
8086 if (float64_is_signaling_nan(f64
)) {
8087 float_raise(float_flag_invalid
, fpst
);
8088 nan
= float64_maybe_silence_nan(f64
);
8090 if (fpst
->default_nan_mode
) {
8091 nan
= float64_default_nan
;
8094 } else if (float64_is_infinity(f64
)) {
8095 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
8096 } else if (float64_is_zero(f64
)) {
8097 float_raise(float_flag_divbyzero
, fpst
);
8098 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
8099 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
8100 /* Abs(value) < 2.0^-1024 */
8101 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
8102 if (round_to_inf(fpst
, f64_sbit
)) {
8103 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
8105 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
8107 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
8108 float_raise(float_flag_underflow
, fpst
);
8109 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
8112 r64
= call_recip_estimate(f64
, 2045, fpst
);
8113 r64_val
= float64_val(r64
);
8114 r64_exp
= extract64(r64_val
, 52, 11);
8115 r64_frac
= extract64(r64_val
, 0, 52);
8117 /* result = sign : result_exp<10:0> : fraction<51:0> */
8118 return make_float64(f64_sbit
|
8119 ((r64_exp
& 0x7ff) << 52) |
8123 /* The algorithm that must be used to calculate the estimate
8124 * is specified by the ARM ARM.
8126 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
8128 /* These calculations mustn't set any fp exception flags,
8129 * so we use a local copy of the fp_status.
8131 float_status dummy_status
= *real_fp_status
;
8132 float_status
*s
= &dummy_status
;
8136 if (float64_lt(a
, float64_half
, s
)) {
8137 /* range 0.25 <= a < 0.5 */
8139 /* a in units of 1/512 rounded down */
8140 /* q0 = (int)(a * 512.0); */
8141 q
= float64_mul(float64_512
, a
, s
);
8142 q_int
= float64_to_int64_round_to_zero(q
, s
);
8144 /* reciprocal root r */
8145 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
8146 q
= int64_to_float64(q_int
, s
);
8147 q
= float64_add(q
, float64_half
, s
);
8148 q
= float64_div(q
, float64_512
, s
);
8149 q
= float64_sqrt(q
, s
);
8150 q
= float64_div(float64_one
, q
, s
);
8152 /* range 0.5 <= a < 1.0 */
8154 /* a in units of 1/256 rounded down */
8155 /* q1 = (int)(a * 256.0); */
8156 q
= float64_mul(float64_256
, a
, s
);
8157 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
8159 /* reciprocal root r */
8160 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8161 q
= int64_to_float64(q_int
, s
);
8162 q
= float64_add(q
, float64_half
, s
);
8163 q
= float64_div(q
, float64_256
, s
);
8164 q
= float64_sqrt(q
, s
);
8165 q
= float64_div(float64_one
, q
, s
);
8167 /* r in units of 1/256 rounded to nearest */
8168 /* s = (int)(256.0 * r + 0.5); */
8170 q
= float64_mul(q
, float64_256
,s
);
8171 q
= float64_add(q
, float64_half
, s
);
8172 q_int
= float64_to_int64_round_to_zero(q
, s
);
8174 /* return (double)s / 256.0;*/
8175 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
8178 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
8180 float_status
*s
= fpstp
;
8181 float32 f32
= float32_squash_input_denormal(input
, s
);
8182 uint32_t val
= float32_val(f32
);
8183 uint32_t f32_sbit
= 0x80000000 & val
;
8184 int32_t f32_exp
= extract32(val
, 23, 8);
8185 uint32_t f32_frac
= extract32(val
, 0, 23);
8191 if (float32_is_any_nan(f32
)) {
8193 if (float32_is_signaling_nan(f32
)) {
8194 float_raise(float_flag_invalid
, s
);
8195 nan
= float32_maybe_silence_nan(f32
);
8197 if (s
->default_nan_mode
) {
8198 nan
= float32_default_nan
;
8201 } else if (float32_is_zero(f32
)) {
8202 float_raise(float_flag_divbyzero
, s
);
8203 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
8204 } else if (float32_is_neg(f32
)) {
8205 float_raise(float_flag_invalid
, s
);
8206 return float32_default_nan
;
8207 } else if (float32_is_infinity(f32
)) {
8208 return float32_zero
;
8211 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8212 * preserving the parity of the exponent. */
8214 f64_frac
= ((uint64_t) f32_frac
) << 29;
8216 while (extract64(f64_frac
, 51, 1) == 0) {
8217 f64_frac
= f64_frac
<< 1;
8218 f32_exp
= f32_exp
-1;
8220 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
8223 if (extract64(f32_exp
, 0, 1) == 0) {
8224 f64
= make_float64(((uint64_t) f32_sbit
) << 32
8228 f64
= make_float64(((uint64_t) f32_sbit
) << 32
8233 result_exp
= (380 - f32_exp
) / 2;
8235 f64
= recip_sqrt_estimate(f64
, s
);
8237 val64
= float64_val(f64
);
8239 val
= ((result_exp
& 0xff) << 23)
8240 | ((val64
>> 29) & 0x7fffff);
8241 return make_float32(val
);
8244 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
8246 float_status
*s
= fpstp
;
8247 float64 f64
= float64_squash_input_denormal(input
, s
);
8248 uint64_t val
= float64_val(f64
);
8249 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
8250 int64_t f64_exp
= extract64(val
, 52, 11);
8251 uint64_t f64_frac
= extract64(val
, 0, 52);
8253 uint64_t result_frac
;
8255 if (float64_is_any_nan(f64
)) {
8257 if (float64_is_signaling_nan(f64
)) {
8258 float_raise(float_flag_invalid
, s
);
8259 nan
= float64_maybe_silence_nan(f64
);
8261 if (s
->default_nan_mode
) {
8262 nan
= float64_default_nan
;
8265 } else if (float64_is_zero(f64
)) {
8266 float_raise(float_flag_divbyzero
, s
);
8267 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
8268 } else if (float64_is_neg(f64
)) {
8269 float_raise(float_flag_invalid
, s
);
8270 return float64_default_nan
;
8271 } else if (float64_is_infinity(f64
)) {
8272 return float64_zero
;
8275 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8276 * preserving the parity of the exponent. */
8279 while (extract64(f64_frac
, 51, 1) == 0) {
8280 f64_frac
= f64_frac
<< 1;
8281 f64_exp
= f64_exp
- 1;
8283 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
8286 if (extract64(f64_exp
, 0, 1) == 0) {
8287 f64
= make_float64(f64_sbit
8291 f64
= make_float64(f64_sbit
8296 result_exp
= (3068 - f64_exp
) / 2;
8298 f64
= recip_sqrt_estimate(f64
, s
);
8300 result_frac
= extract64(float64_val(f64
), 0, 52);
8302 return make_float64(f64_sbit
|
8303 ((result_exp
& 0x7ff) << 52) |
8307 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
8309 float_status
*s
= fpstp
;
8312 if ((a
& 0x80000000) == 0) {
8316 f64
= make_float64((0x3feULL
<< 52)
8317 | ((int64_t)(a
& 0x7fffffff) << 21));
8319 f64
= recip_estimate(f64
, s
);
8321 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
8324 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
8326 float_status
*fpst
= fpstp
;
8329 if ((a
& 0xc0000000) == 0) {
8333 if (a
& 0x80000000) {
8334 f64
= make_float64((0x3feULL
<< 52)
8335 | ((uint64_t)(a
& 0x7fffffff) << 21));
8336 } else { /* bits 31-30 == '01' */
8337 f64
= make_float64((0x3fdULL
<< 52)
8338 | ((uint64_t)(a
& 0x3fffffff) << 22));
8341 f64
= recip_sqrt_estimate(f64
, fpst
);
8343 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
8346 /* VFPv4 fused multiply-accumulate */
8347 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
8349 float_status
*fpst
= fpstp
;
8350 return float32_muladd(a
, b
, c
, 0, fpst
);
8353 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
8355 float_status
*fpst
= fpstp
;
8356 return float64_muladd(a
, b
, c
, 0, fpst
);
8359 /* ARMv8 round to integral */
8360 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
8362 return float32_round_to_int(x
, fp_status
);
8365 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
8367 return float64_round_to_int(x
, fp_status
);
8370 float32
HELPER(rints
)(float32 x
, void *fp_status
)
8372 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
8375 ret
= float32_round_to_int(x
, fp_status
);
8377 /* Suppress any inexact exceptions the conversion produced */
8378 if (!(old_flags
& float_flag_inexact
)) {
8379 new_flags
= get_float_exception_flags(fp_status
);
8380 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
8386 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
8388 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
8391 ret
= float64_round_to_int(x
, fp_status
);
8393 new_flags
= get_float_exception_flags(fp_status
);
8395 /* Suppress any inexact exceptions the conversion produced */
8396 if (!(old_flags
& float_flag_inexact
)) {
8397 new_flags
= get_float_exception_flags(fp_status
);
8398 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
8404 /* Convert ARM rounding mode to softfloat */
8405 int arm_rmode_to_sf(int rmode
)
8408 case FPROUNDING_TIEAWAY
:
8409 rmode
= float_round_ties_away
;
8411 case FPROUNDING_ODD
:
8412 /* FIXME: add support for TIEAWAY and ODD */
8413 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
8415 case FPROUNDING_TIEEVEN
:
8417 rmode
= float_round_nearest_even
;
8419 case FPROUNDING_POSINF
:
8420 rmode
= float_round_up
;
8422 case FPROUNDING_NEGINF
:
8423 rmode
= float_round_down
;
8425 case FPROUNDING_ZERO
:
8426 rmode
= float_round_to_zero
;
8433 * The upper bytes of val (above the number specified by 'bytes') must have
8434 * been zeroed out by the caller.
8436 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
8442 /* zlib crc32 converts the accumulator and output to one's complement. */
8443 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
8446 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
8452 /* Linux crc32c converts the output to one's complement. */
8453 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;