2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
28 /* Page tracking code uses ram addresses in system mode, and virtual
29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
31 #if defined(CONFIG_USER_ONLY)
32 typedef abi_ulong tb_page_addr_t
;
34 typedef ram_addr_t tb_page_addr_t
;
37 /* is_jmp field values */
38 #define DISAS_NEXT 0 /* next instruction can be analyzed */
39 #define DISAS_JUMP 1 /* only pc was modified dynamically */
40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
43 struct TranslationBlock
;
44 typedef struct TranslationBlock TranslationBlock
;
46 /* XXX: make safe guess about sizes */
47 #define MAX_OP_PER_INSTR 266
49 #if HOST_LONG_BITS == 32
50 #define MAX_OPC_PARAM_PER_ARG 2
52 #define MAX_OPC_PARAM_PER_ARG 1
54 #define MAX_OPC_PARAM_IARGS 5
55 #define MAX_OPC_PARAM_OARGS 1
56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
59 * and up to 4 + N parameters on 64-bit archs
60 * (N = number of input arguments + output arguments). */
61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
62 #define OPC_BUF_SIZE 640
63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
65 /* Maximum size a TCG op can expand to. This is complicated because a
66 single op may require several host instructions and register reloads.
67 For now take a wild guess at 192 bytes, which should allow at least
68 a couple of fixup instructions per argument. */
69 #define TCG_MAX_OP_SIZE 192
71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
75 void gen_intermediate_code(CPUArchState
*env
, struct TranslationBlock
*tb
);
76 void gen_intermediate_code_pc(CPUArchState
*env
, struct TranslationBlock
*tb
);
77 void restore_state_to_opc(CPUArchState
*env
, struct TranslationBlock
*tb
,
80 /* Get a backtrace for the guest code. */
81 const char *qemu_sprint_backtrace(char *buffer
, size_t length
);
83 void cpu_gen_init(void);
84 int cpu_gen_code(CPUArchState
*env
, struct TranslationBlock
*tb
,
85 int *gen_code_size_ptr
);
86 bool cpu_restore_state(CPUState
*cpu
, uintptr_t searched_pc
);
87 void page_size_init(void);
89 void QEMU_NORETURN
cpu_resume_from_signal(CPUState
*cpu
, void *puc
);
90 void QEMU_NORETURN
cpu_io_recompile(CPUState
*cpu
, uintptr_t retaddr
);
91 TranslationBlock
*tb_gen_code(CPUState
*cpu
,
92 target_ulong pc
, target_ulong cs_base
, int flags
,
94 void cpu_exec_init(CPUState
*cpu
, Error
**errp
);
95 void QEMU_NORETURN
cpu_loop_exit(CPUState
*cpu
);
96 void QEMU_NORETURN
cpu_loop_exit_restore(CPUState
*cpu
, uintptr_t pc
);
98 #if !defined(CONFIG_USER_ONLY)
99 bool qemu_in_vcpu_thread(void);
100 void cpu_reload_memory_map(CPUState
*cpu
);
101 void tcg_cpu_address_space_init(CPUState
*cpu
, AddressSpace
*as
);
105 * @cpu: CPU whose TLB should be flushed
106 * @addr: virtual address of page to be flushed
108 * Flush one page from the TLB of the specified CPU, for all
111 void tlb_flush_page(CPUState
*cpu
, target_ulong addr
);
114 * @cpu: CPU whose TLB should be flushed
115 * @flush_global: ignored
117 * Flush the entire TLB for the specified CPU.
118 * The flush_global flag is in theory an indicator of whether the whole
119 * TLB should be flushed, or only those entries not marked global.
120 * In practice QEMU does not implement any global/not global flag for
121 * TLB entries, and the argument is ignored.
123 void tlb_flush(CPUState
*cpu
, int flush_global
);
125 * tlb_flush_page_by_mmuidx:
126 * @cpu: CPU whose TLB should be flushed
127 * @addr: virtual address of page to be flushed
128 * @...: list of MMU indexes to flush, terminated by a negative value
130 * Flush one page from the TLB of the specified CPU, for the specified
133 void tlb_flush_page_by_mmuidx(CPUState
*cpu
, target_ulong addr
, ...);
135 * tlb_flush_by_mmuidx:
136 * @cpu: CPU whose TLB should be flushed
137 * @...: list of MMU indexes to flush, terminated by a negative value
139 * Flush all entries from the TLB of the specified CPU, for the specified
142 void tlb_flush_by_mmuidx(CPUState
*cpu
, ...);
143 void tlb_set_page(CPUState
*cpu
, target_ulong vaddr
,
144 hwaddr paddr
, int prot
,
145 int mmu_idx
, target_ulong size
);
146 void tlb_set_page_with_attrs(CPUState
*cpu
, target_ulong vaddr
,
147 hwaddr paddr
, MemTxAttrs attrs
,
148 int prot
, int mmu_idx
, target_ulong size
);
149 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
);
150 void probe_write(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
153 static inline void tlb_flush_page(CPUState
*cpu
, target_ulong addr
)
157 static inline void tlb_flush(CPUState
*cpu
, int flush_global
)
161 static inline void tlb_flush_page_by_mmuidx(CPUState
*cpu
,
162 target_ulong addr
, ...)
166 static inline void tlb_flush_by_mmuidx(CPUState
*cpu
, ...)
171 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
173 #define CODE_GEN_PHYS_HASH_BITS 15
174 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
176 /* estimated block size for TB allocation */
177 /* XXX: use a per code average code fragment size and modulate it
178 according to the host CPU */
179 #if defined(CONFIG_SOFTMMU)
180 #define CODE_GEN_AVG_BLOCK_SIZE 128
182 #define CODE_GEN_AVG_BLOCK_SIZE 64
185 #if defined(__arm__) || defined(_ARCH_PPC) \
186 || defined(__x86_64__) || defined(__i386__) \
187 || defined(__sparc__) || defined(__aarch64__) \
188 || defined(__s390x__) || defined(__mips__) \
189 || defined(CONFIG_TCG_INTERPRETER)
190 #define USE_DIRECT_JUMP
193 struct TranslationBlock
{
194 target_ulong pc
; /* simulated PC corresponding to this block (EIP + CS base) */
195 target_ulong cs_base
; /* CS base for this block */
196 uint64_t flags
; /* flags defining in which context the code was generated */
197 uint16_t size
; /* size of target code for this block (1 <=
198 size <= TARGET_PAGE_SIZE) */
200 uint32_t cflags
; /* compile flags */
201 #define CF_COUNT_MASK 0x7fff
202 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
203 #define CF_NOCACHE 0x10000 /* To be freed after execution */
204 #define CF_USE_ICOUNT 0x20000
206 void *tc_ptr
; /* pointer to the translated code */
207 /* next matching tb for physical address. */
208 struct TranslationBlock
*phys_hash_next
;
209 /* original tb when cflags has CF_NOCACHE */
210 struct TranslationBlock
*orig_tb
;
211 /* first and second physical page containing code. The lower bit
212 of the pointer tells the index in page_next[] */
213 struct TranslationBlock
*page_next
[2];
214 tb_page_addr_t page_addr
[2];
216 /* the following data are used to directly call another TB from
217 the code of this one. */
218 uint16_t tb_next_offset
[2]; /* offset of original jump target */
219 #ifdef USE_DIRECT_JUMP
220 uint16_t tb_jmp_offset
[2]; /* offset of jump instruction */
222 uintptr_t tb_next
[2]; /* address of jump generated code */
224 /* list of TBs jumping to this one. This is a circular list using
225 the two least significant bits of the pointers to tell what is
226 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
228 struct TranslationBlock
*jmp_next
[2];
229 struct TranslationBlock
*jmp_first
;
232 #include "qemu/thread.h"
234 typedef struct TBContext TBContext
;
238 TranslationBlock
*tbs
;
239 TranslationBlock
*tb_phys_hash
[CODE_GEN_PHYS_HASH_SIZE
];
241 /* any access to the tbs or the page table must use this lock */
246 int tb_phys_invalidate_count
;
248 int tb_invalidated_flag
;
251 void tb_free(TranslationBlock
*tb
);
252 void tb_flush(CPUState
*cpu
);
253 void tb_phys_invalidate(TranslationBlock
*tb
, tb_page_addr_t page_addr
);
255 #if defined(USE_DIRECT_JUMP)
257 #if defined(CONFIG_TCG_INTERPRETER)
258 static inline void tb_set_jmp_target1(uintptr_t jmp_addr
, uintptr_t addr
)
260 /* patch the branch destination */
261 *(uint32_t *)jmp_addr
= addr
- (jmp_addr
+ 4);
262 /* no need to flush icache explicitly */
264 #elif defined(_ARCH_PPC)
265 void ppc_tb_set_jmp_target(uintptr_t jmp_addr
, uintptr_t addr
);
266 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
267 #elif defined(__i386__) || defined(__x86_64__)
268 static inline void tb_set_jmp_target1(uintptr_t jmp_addr
, uintptr_t addr
)
270 /* patch the branch destination */
271 stl_le_p((void*)jmp_addr
, addr
- (jmp_addr
+ 4));
272 /* no need to flush icache explicitly */
274 #elif defined(__s390x__)
275 static inline void tb_set_jmp_target1(uintptr_t jmp_addr
, uintptr_t addr
)
277 /* patch the branch destination */
278 intptr_t disp
= addr
- (jmp_addr
- 2);
279 stl_be_p((void*)jmp_addr
, disp
/ 2);
280 /* no need to flush icache explicitly */
282 #elif defined(__aarch64__)
283 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr
, uintptr_t addr
);
284 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
285 #elif defined(__arm__)
286 static inline void tb_set_jmp_target1(uintptr_t jmp_addr
, uintptr_t addr
)
288 #if !QEMU_GNUC_PREREQ(4, 1)
289 register unsigned long _beg
__asm ("a1");
290 register unsigned long _end
__asm ("a2");
291 register unsigned long _flg
__asm ("a3");
294 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
295 *(uint32_t *)jmp_addr
=
296 (*(uint32_t *)jmp_addr
& ~0xffffff)
297 | (((addr
- (jmp_addr
+ 8)) >> 2) & 0xffffff);
299 #if QEMU_GNUC_PREREQ(4, 1)
300 __builtin___clear_cache((char *) jmp_addr
, (char *) jmp_addr
+ 4);
306 __asm
__volatile__ ("swi 0x9f0002" : : "r" (_beg
), "r" (_end
), "r" (_flg
));
309 #elif defined(__sparc__) || defined(__mips__)
310 void tb_set_jmp_target1(uintptr_t jmp_addr
, uintptr_t addr
);
312 #error tb_set_jmp_target1 is missing
315 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
316 int n
, uintptr_t addr
)
318 uint16_t offset
= tb
->tb_jmp_offset
[n
];
319 tb_set_jmp_target1((uintptr_t)(tb
->tc_ptr
+ offset
), addr
);
324 /* set the jump target */
325 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
326 int n
, uintptr_t addr
)
328 tb
->tb_next
[n
] = addr
;
333 static inline void tb_add_jump(TranslationBlock
*tb
, int n
,
334 TranslationBlock
*tb_next
)
336 /* NOTE: this test is only needed for thread safety */
337 if (!tb
->jmp_next
[n
]) {
338 /* patch the native jump address */
339 tb_set_jmp_target(tb
, n
, (uintptr_t)tb_next
->tc_ptr
);
341 /* add in TB jmp circular list */
342 tb
->jmp_next
[n
] = tb_next
->jmp_first
;
343 tb_next
->jmp_first
= (TranslationBlock
*)((uintptr_t)(tb
) | (n
));
347 /* GETRA is the true target of the return instruction that we'll execute,
348 defined here for simplicity of defining the follow-up macros. */
349 #if defined(CONFIG_TCG_INTERPRETER)
350 extern uintptr_t tci_tb_ptr
;
351 # define GETRA() tci_tb_ptr
354 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
357 /* The true return address will often point to a host insn that is part of
358 the next translated guest insn. Adjust the address backward to point to
359 the middle of the call insn. Subtracting one would do the job except for
360 several compressed mode architectures (arm, mips) which set the low bit
361 to indicate the compressed mode; subtracting two works around that. It
362 is also the case that there are no host isas that contain a call insn
363 smaller than 4 bytes, so we don't worry about special-casing this. */
366 #define GETPC() (GETRA() - GETPC_ADJ)
368 #if !defined(CONFIG_USER_ONLY)
370 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
));
372 struct MemoryRegion
*iotlb_to_region(CPUState
*cpu
,
375 void tlb_fill(CPUState
*cpu
, target_ulong addr
, int is_write
, int mmu_idx
,
380 #if defined(CONFIG_USER_ONLY)
381 void mmap_lock(void);
382 void mmap_unlock(void);
384 static inline tb_page_addr_t
get_page_addr_code(CPUArchState
*env1
, target_ulong addr
)
389 static inline void mmap_lock(void) {}
390 static inline void mmap_unlock(void) {}
393 tb_page_addr_t
get_page_addr_code(CPUArchState
*env1
, target_ulong addr
);
395 void tlb_reset_dirty(CPUState
*cpu
, ram_addr_t start1
, ram_addr_t length
);
396 void tlb_set_dirty(CPUState
*cpu
, target_ulong vaddr
);
399 void tb_flush_jmp_cache(CPUState
*cpu
, target_ulong addr
);
401 MemoryRegionSection
*
402 address_space_translate_for_iotlb(CPUState
*cpu
, hwaddr addr
, hwaddr
*xlat
,
404 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
405 MemoryRegionSection
*section
,
407 hwaddr paddr
, hwaddr xlat
,
409 target_ulong
*address
);
410 bool memory_region_is_unassigned(MemoryRegion
*mr
);
415 extern int singlestep
;
417 /* cpu-exec.c, accessed with atomic_mb_read/atomic_mb_set */
418 extern CPUState
*tcg_current_cpu
;
419 extern bool exit_request
;
421 #if !defined(CONFIG_USER_ONLY)
422 void migration_bitmap_extend(ram_addr_t old
, ram_addr_t
new);