hw/mips/cputimer.c

   1 /*
   2  * QEMU MIPS timer support
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include "hw/hw.h"
  24 #include "hw/mips/cpudevs.h"
  25 #include "qemu/timer.h"
  26 #include "sysemu/kvm.h"
  27
  28 //~ #define TIMER_FREQ  100 * 1000 * 1000
  29
  30 /* Timer on Sinus 154 DSL Basic SE (Openwrt) needs a lower frequency. */
  31 #define TIMER_FREQ      10 * 1000 * 1000
  32
  33 static void mips_timer_cb(void *opaque);
  34
  35 #if 0
  36 /* Workaround to satisfy Linux c0_compare_int_usable. */
  37 static int cpu_mips_timer_triggered;
  38 #endif
  39
  40 /* XXX: do not use a global */
  41 uint32_t cpu_mips_get_random (CPUMIPSState *env)
  42 {
  43     static uint32_t seed = 1;
  44     static uint32_t prev_idx = 0;
  45     uint32_t idx;
  46     uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
  47
  48     if (nb_rand_tlb == 1) {
  49         return env->tlb->nb_tlb - 1;
  50     }
  51
  52     /* Don't return same value twice, so get another value */
  53     do {
  54         /* Use a simple algorithm of Linear Congruential Generator
  55          * from ISO/IEC 9899 standard. */
  56         seed = 1103515245 * seed + 12345;
  57         idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
  58     } while (idx == prev_idx);
  59     prev_idx = idx;
  60     return idx;
  61 }
  62
  63 /* MIPS R4K timer */
  64
  65 static int cpu_mips_timer_disabled(CPUMIPSState *env)
  66 {
  67   return env->CP0_Cause & (1 << CP0Ca_DC);
  68 }
  69
  70 #if 0
  71 uint32_t cpu_mips_get_count (CPUMIPSState *env)
  72 {
  73     uint32_t value = env->CP0_Count;
  74     if (!cpu_mips_timer_disabled(env)) {
  75         int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  76         value += (uint32_t)muldiv64(current_time, TIMER_FREQ, get_ticks_per_sec());
  77         /* If count passed compare value, a timer interrupt should occur.
  78            But this will happen only in the main loop, so we check here. */
  79         int delta = value - env->CP0_Compare;
  80         if (delta > 0 && !cpu_mips_timer_triggered) {
  81             mips_timer_cb(env);
  82         }
  83     }
  84     return value;
  85 }
  86 #endif
  87
  88 static void cpu_mips_timer_update(CPUMIPSState *env)
  89 {
  90     uint64_t now, next;
  91     uint32_t wait;
  92
  93     now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  94     wait = env->CP0_Compare - env->CP0_Count -
  95             (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
  96     next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
  97     timer_mod(env->timer, next);
  98 }
  99
 100 /* Expire the timer.  */
 101 static void cpu_mips_timer_expire(CPUMIPSState *env)
 102 {
 103     cpu_mips_timer_update(env);
 104     if (env->insn_flags & ISA_MIPS32R2) {
 105         env->CP0_Cause |= 1 << CP0Ca_TI;
 106     }
 107     qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 108 }
 109
 110 uint32_t cpu_mips_get_count (CPUMIPSState *env)
 111 {
 112     uint32_t value = env->CP0_Count;
 113     if (!cpu_mips_timer_disabled(env)) {
 114         int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 115         value += (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
 116         if (timer_pending(env->timer)
 117             && timer_expired(env->timer, now)) {
 118             /* The timer has already expired. */
 119             cpu_mips_timer_expire(env);
 120         }
 121     }
 122     return value;
 123 }
 124
 125 void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
 126 {
 127     /*
 128      * This gets called from cpu_state_reset(), potentially before timer init.
 129      * So env->timer may be NULL, which is also the case with KVM enabled so
 130      * treat timer as disabled in that case.
 131      */
 132     if (cpu_mips_timer_disabled(env) || !env->timer) {
 133         env->CP0_Count = count;
 134     } else {
 135         /* Store new count register */
 136         env->CP0_Count =
 137             count - (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 138                                        TIMER_FREQ, get_ticks_per_sec());
 139         /* Update timer timer */
 140         cpu_mips_timer_update(env);
 141 #if 0
 142         cpu_mips_timer_triggered = 1;
 143 #endif
 144     }
 145 }
 146
 147 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
 148 {
 149     env->CP0_Compare = value;
 150     if (!cpu_mips_timer_disabled(env)) {
 151         cpu_mips_timer_update(env);
 152     }
 153     if (env->insn_flags & ISA_MIPS32R2)
 154         env->CP0_Cause &= ~(1 << CP0Ca_TI);
 155     qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 156 #if 0
 157     cpu_mips_timer_triggered = 0;
 158 #endif
 159 }
 160
 161 void cpu_mips_start_count(CPUMIPSState *env)
 162 {
 163     cpu_mips_store_count(env, env->CP0_Count);
 164 }
 165
 166 void cpu_mips_stop_count(CPUMIPSState *env)
 167 {
 168     /* Store the current value */
 169     env->CP0_Count += (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 170                                          TIMER_FREQ, get_ticks_per_sec());
 171 }
 172
 173 static void mips_timer_cb(void *opaque)
 174 {
 175     CPUMIPSState *env;
 176
 177     env = opaque;
 178 #if 0
 179     qemu_log("%s\n", __func__);
 180 #endif
 181
 182     if (cpu_mips_timer_disabled(env)) {
 183         return;
 184     }
 185
 186     /* ??? This callback should occur when the counter is exactly equal to
 187        the comparator value.  Offset the count by one to avoid immediately
 188        retriggering the callback before any virtual time has passed.  */
 189     env->CP0_Count++;
 190     cpu_mips_timer_expire(env);
 191     env->CP0_Count--;
 192 #if 0
 193     if (env->insn_flags & ISA_MIPS32R2)
 194         env->CP0_Cause |= 1 << CP0Ca_TI;
 195     qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 196     cpu_mips_timer_triggered = 1;
 197 #endif
 198 }
 199
 200 void cpu_mips_clock_init (CPUMIPSState *env)
 201 {
 202     /*
 203      * If we're in KVM mode, don't create the periodic timer, that is handled in
 204      * kernel.
 205      */
 206     if (!kvm_enabled()) {
 207         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
 208     }
 209 }