hw/arm/exynos4210.c

   1 /*
   2  *  Samsung exynos4210 SoC emulation
   3  *
   4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5  *    Maksim Kozlov <m.kozlov@samsung.com>
   6  *    Evgeny Voevodin <e.voevodin@samsung.com>
   7  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License as published by the
  11  *  Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include "hw/boards.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/arm/arm.h"
  28 #include "hw/loader.h"
  29 #include "hw/arm/exynos4210.h"
  30 #include "hw/usb/hcd-ehci.h"
  31
  32 #define EXYNOS4210_CHIPID_ADDR         0x10000000
  33
  34 /* PWM */
  35 #define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  36
  37 /* RTC */
  38 #define EXYNOS4210_RTC_BASE_ADDR       0x10070000
  39
  40 /* MCT */
  41 #define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  42
  43 /* I2C */
  44 #define EXYNOS4210_I2C_SHIFT           0x00010000
  45 #define EXYNOS4210_I2C_BASE_ADDR       0x13860000
  46 /* Interrupt Group of External Interrupt Combiner for I2C */
  47 #define EXYNOS4210_I2C_INTG            27
  48 #define EXYNOS4210_HDMI_INTG           16
  49
  50 /* UART's definitions */
  51 #define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  52 #define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  53 #define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  54 #define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  55 #define EXYNOS4210_UART0_FIFO_SIZE     256
  56 #define EXYNOS4210_UART1_FIFO_SIZE     64
  57 #define EXYNOS4210_UART2_FIFO_SIZE     16
  58 #define EXYNOS4210_UART3_FIFO_SIZE     16
  59 /* Interrupt Group of External Interrupt Combiner for UART */
  60 #define EXYNOS4210_UART_INT_GRP        26
  61
  62 /* External GIC */
  63 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  64 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  65
  66 /* Combiner */
  67 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  68 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  69
  70 /* SD/MMC host controllers SFR base addresses */
  71 #define EXYNOS4210_SDHC0_BASE_ADDR          0x12510000
  72 #define EXYNOS4210_SDHC1_BASE_ADDR          0x12520000
  73 #define EXYNOS4210_SDHC2_BASE_ADDR          0x12530000
  74 #define EXYNOS4210_SDHC3_BASE_ADDR          0x12540000
  75
  76 /* PMU SFR base address */
  77 #define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  78
  79 /* Display controllers (FIMD) */
  80 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  81
  82 /* EHCI */
  83 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
  84
  85 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
  86                                     0x09, 0x00, 0x00, 0x00 };
  87
  88 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
  89                                                unsigned size)
  90 {
  91     assert(offset < sizeof(chipid_and_omr));
  92     return chipid_and_omr[offset];
  93 }
  94
  95 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
  96                                             uint64_t value, unsigned size)
  97 {
  98     return;
  99 }
 100
 101 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
 102     .read = exynos4210_chipid_and_omr_read,
 103     .write = exynos4210_chipid_and_omr_write,
 104     .endianness = DEVICE_NATIVE_ENDIAN,
 105     .impl = {
 106         .max_access_size = 1,
 107     }
 108 };
 109
 110 void exynos4210_write_secondary(ARMCPU *cpu,
 111         const struct arm_boot_info *info)
 112 {
 113     int n;
 114     uint32_t smpboot[] = {
 115         0xe59f3034, /* ldr r3, External gic_cpu_if */
 116         0xe59f2034, /* ldr r2, Internal gic_cpu_if */
 117         0xe59f0034, /* ldr r0, startaddr */
 118         0xe3a01001, /* mov r1, #1 */
 119         0xe5821000, /* str r1, [r2] */
 120         0xe5831000, /* str r1, [r3] */
 121         0xe3a010ff, /* mov r1, #0xff */
 122         0xe5821004, /* str r1, [r2, #4] */
 123         0xe5831004, /* str r1, [r3, #4] */
 124         0xf57ff04f, /* dsb */
 125         0xe320f003, /* wfi */
 126         0xe5901000, /* ldr     r1, [r0] */
 127         0xe1110001, /* tst     r1, r1 */
 128         0x0afffffb, /* beq     <wfi> */
 129         0xe12fff11, /* bx      r1 */
 130         EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
 131         0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
 132         0           /* bootreg: Boot register address is held here */
 133     };
 134     smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
 135     smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
 136     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
 137         smpboot[n] = tswap32(smpboot[n]);
 138     }
 139     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
 140                        info->smp_loader_start);
 141 }
 142
 143 Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
 144         unsigned long ram_size)
 145 {
 146     int i, n;
 147     Exynos4210State *s = g_new(Exynos4210State, 1);
 148     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
 149     unsigned long mem_size;
 150     DeviceState *dev;
 151     SysBusDevice *busdev;
 152     ObjectClass *cpu_oc;
 153
 154     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
 155     assert(cpu_oc);
 156
 157     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 158         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 159         Error *err = NULL;
 160
 161         /* By default A9 CPUs have EL3 enabled.  This board does not currently
 162          * support EL3 so the CPU EL3 property is disabled before realization.
 163          */
 164         if (object_property_find(cpuobj, "has_el3", NULL)) {
 165             object_property_set_bool(cpuobj, false, "has_el3", &err);
 166             if (err) {
 167                 error_report_err(err);
 168                 exit(1);
 169             }
 170         }
 171
 172         s->cpu[n] = ARM_CPU(cpuobj);
 173         object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
 174                                 "reset-cbar", &error_abort);
 175         object_property_set_bool(cpuobj, true, "realized", &err);
 176         if (err) {
 177             error_report_err(err);
 178             exit(1);
 179         }
 180     }
 181
 182     /*** IRQs ***/
 183
 184     s->irq_table = exynos4210_init_irq(&s->irqs);
 185
 186     /* IRQ Gate */
 187     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
 188         dev = qdev_create(NULL, "exynos4210.irq_gate");
 189         qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
 190         qdev_init_nofail(dev);
 191         /* Get IRQ Gate input in gate_irq */
 192         for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
 193             gate_irq[i][n] = qdev_get_gpio_in(dev, n);
 194         }
 195         busdev = SYS_BUS_DEVICE(dev);
 196
 197         /* Connect IRQ Gate output to CPU's IRQ line */
 198         sysbus_connect_irq(busdev, 0,
 199                            qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
 200     }
 201
 202     /* Private memory region and Internal GIC */
 203     dev = qdev_create(NULL, "a9mpcore_priv");
 204     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 205     qdev_init_nofail(dev);
 206     busdev = SYS_BUS_DEVICE(dev);
 207     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 208     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 209         sysbus_connect_irq(busdev, n, gate_irq[n][0]);
 210     }
 211     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 212         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 213     }
 214
 215     /* Cache controller */
 216     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 217
 218     /* External GIC */
 219     dev = qdev_create(NULL, "exynos4210.gic");
 220     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 221     qdev_init_nofail(dev);
 222     busdev = SYS_BUS_DEVICE(dev);
 223     /* Map CPU interface */
 224     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 225     /* Map Distributer interface */
 226     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 227     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 228         sysbus_connect_irq(busdev, n, gate_irq[n][1]);
 229     }
 230     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 231         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 232     }
 233
 234     /* Internal Interrupt Combiner */
 235     dev = qdev_create(NULL, "exynos4210.combiner");
 236     qdev_init_nofail(dev);
 237     busdev = SYS_BUS_DEVICE(dev);
 238     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 239         sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
 240     }
 241     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 242     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 243
 244     /* External Interrupt Combiner */
 245     dev = qdev_create(NULL, "exynos4210.combiner");
 246     qdev_prop_set_uint32(dev, "external", 1);
 247     qdev_init_nofail(dev);
 248     busdev = SYS_BUS_DEVICE(dev);
 249     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 250         sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 251     }
 252     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 253     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 254
 255     /* Initialize board IRQs. */
 256     exynos4210_init_board_irqs(&s->irqs);
 257
 258     /*** Memory ***/
 259
 260     /* Chip-ID and OMR */
 261     memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
 262         NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
 263     memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 264                                 &s->chipid_mem);
 265
 266     /* Internal ROM */
 267     memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
 268                            EXYNOS4210_IROM_SIZE, &error_fatal);
 269     vmstate_register_ram_global(&s->irom_mem);
 270     memory_region_set_readonly(&s->irom_mem, true);
 271     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 272                                 &s->irom_mem);
 273     /* mirror of iROM */
 274     memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
 275                              &s->irom_mem,
 276                              0,
 277                              EXYNOS4210_IROM_SIZE);
 278     memory_region_set_readonly(&s->irom_alias_mem, true);
 279     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 280                                 &s->irom_alias_mem);
 281
 282     /* Internal RAM */
 283     memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
 284                            EXYNOS4210_IRAM_SIZE, &error_fatal);
 285     vmstate_register_ram_global(&s->iram_mem);
 286     memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 287                                 &s->iram_mem);
 288
 289     /* DRAM */
 290     mem_size = ram_size;
 291     if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
 292         memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
 293                 mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal);
 294         vmstate_register_ram_global(&s->dram1_mem);
 295         memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
 296                 &s->dram1_mem);
 297         mem_size = EXYNOS4210_DRAM_MAX_SIZE;
 298     }
 299     memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
 300                            &error_fatal);
 301     vmstate_register_ram_global(&s->dram0_mem);
 302     memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
 303             &s->dram0_mem);
 304
 305    /* PMU.
 306     * The only reason of existence at the moment is that secondary CPU boot
 307     * loader uses PMU INFORM5 register as a holding pen.
 308     */
 309     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 310
 311     /* PWM */
 312     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 313                           s->irq_table[exynos4210_get_irq(22, 0)],
 314                           s->irq_table[exynos4210_get_irq(22, 1)],
 315                           s->irq_table[exynos4210_get_irq(22, 2)],
 316                           s->irq_table[exynos4210_get_irq(22, 3)],
 317                           s->irq_table[exynos4210_get_irq(22, 4)],
 318                           NULL);
 319     /* RTC */
 320     sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
 321                           s->irq_table[exynos4210_get_irq(23, 0)],
 322                           s->irq_table[exynos4210_get_irq(23, 1)],
 323                           NULL);
 324
 325     /* Multi Core Timer */
 326     dev = qdev_create(NULL, "exynos4210.mct");
 327     qdev_init_nofail(dev);
 328     busdev = SYS_BUS_DEVICE(dev);
 329     for (n = 0; n < 4; n++) {
 330         /* Connect global timer interrupts to Combiner gpio_in */
 331         sysbus_connect_irq(busdev, n,
 332                 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 333     }
 334     /* Connect local timer interrupts to Combiner gpio_in */
 335     sysbus_connect_irq(busdev, 4,
 336             s->irq_table[exynos4210_get_irq(51, 0)]);
 337     sysbus_connect_irq(busdev, 5,
 338             s->irq_table[exynos4210_get_irq(35, 3)]);
 339     sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 340
 341     /*** I2C ***/
 342     for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
 343         uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
 344         qemu_irq i2c_irq;
 345
 346         if (n < 8) {
 347             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
 348         } else {
 349             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
 350         }
 351
 352         dev = qdev_create(NULL, "exynos4210.i2c");
 353         qdev_init_nofail(dev);
 354         busdev = SYS_BUS_DEVICE(dev);
 355         sysbus_connect_irq(busdev, 0, i2c_irq);
 356         sysbus_mmio_map(busdev, 0, addr);
 357         s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 358     }
 359
 360
 361     /*** UARTs ***/
 362     exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 363                            EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
 364                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 365
 366     exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 367                            EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
 368                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 369
 370     exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 371                            EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
 372                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 373
 374     exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 375                            EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
 376                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 377
 378     /*** SD/MMC host controllers ***/
 379
 380     sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC0_BASE_ADDR,
 381             s->irq_table[exynos4210_get_irq(29, 0)]);
 382
 383     sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC1_BASE_ADDR,
 384             s->irq_table[exynos4210_get_irq(29, 1)]);
 385
 386     sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC2_BASE_ADDR,
 387             s->irq_table[exynos4210_get_irq(29, 2)]);
 388
 389     sysbus_create_simple("exynos4210.sdhci", EXYNOS4210_SDHC3_BASE_ADDR,
 390             s->irq_table[exynos4210_get_irq(29, 3)]);
 391
 392     /*** Display controller (FIMD) ***/
 393     sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 394             s->irq_table[exynos4210_get_irq(11, 0)],
 395             s->irq_table[exynos4210_get_irq(11, 1)],
 396             s->irq_table[exynos4210_get_irq(11, 2)],
 397             NULL);
 398
 399     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
 400             s->irq_table[exynos4210_get_irq(28, 3)]);
 401
 402     return s;
 403 }