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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into...
[qemu/ar7.git] / target / i386 / kvm.c
blobbfd09bd4417dcde8b68bc7b0df088aeac98025b1
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "cpu.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/kvm_int.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/runstate.h"
29 #include "kvm_i386.h"
30 #include "hyperv.h"
31 #include "hyperv-proto.h"
32
33 #include "exec/gdbstub.h"
34 #include "qemu/host-utils.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #include "hw/i386/pc.h"
39 #include "hw/i386/apic.h"
40 #include "hw/i386/apic_internal.h"
41 #include "hw/i386/apic-msidef.h"
42 #include "hw/i386/intel_iommu.h"
43 #include "hw/i386/x86-iommu.h"
44 #include "hw/i386/e820_memory_layout.h"
45
46 #include "hw/pci/pci.h"
47 #include "hw/pci/msi.h"
48 #include "hw/pci/msix.h"
49 #include "migration/blocker.h"
50 #include "exec/memattrs.h"
51 #include "trace.h"
52
53 //#define DEBUG_KVM
54
55 #ifdef DEBUG_KVM
56 #define DPRINTF(fmt, ...) \
57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
58 #else
59 #define DPRINTF(fmt, ...) \
60 do { } while (0)
61 #endif
62
63 #define MSR_KVM_WALL_CLOCK 0x11
64 #define MSR_KVM_SYSTEM_TIME 0x12
65
66 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
67 * 255 kvm_msr_entry structs */
68 #define MSR_BUF_SIZE 4096
69
70 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75 };
76
77 static bool has_msr_star;
78 static bool has_msr_hsave_pa;
79 static bool has_msr_tsc_aux;
80 static bool has_msr_tsc_adjust;
81 static bool has_msr_tsc_deadline;
82 static bool has_msr_feature_control;
83 static bool has_msr_misc_enable;
84 static bool has_msr_smbase;
85 static bool has_msr_bndcfgs;
86 static int lm_capable_kernel;
87 static bool has_msr_hv_hypercall;
88 static bool has_msr_hv_crash;
89 static bool has_msr_hv_reset;
90 static bool has_msr_hv_vpindex;
91 static bool hv_vpindex_settable;
92 static bool has_msr_hv_runtime;
93 static bool has_msr_hv_synic;
94 static bool has_msr_hv_stimer;
95 static bool has_msr_hv_frequencies;
96 static bool has_msr_hv_reenlightenment;
97 static bool has_msr_xss;
98 static bool has_msr_umwait;
99 static bool has_msr_spec_ctrl;
100 static bool has_msr_virt_ssbd;
101 static bool has_msr_smi_count;
102 static bool has_msr_arch_capabs;
103 static bool has_msr_core_capabs;
104 static bool has_msr_vmx_vmfunc;
105
106 static uint32_t has_architectural_pmu_version;
107 static uint32_t num_architectural_pmu_gp_counters;
108 static uint32_t num_architectural_pmu_fixed_counters;
109
110 static int has_xsave;
111 static int has_xcrs;
112 static int has_pit_state2;
113 static int has_exception_payload;
114
115 static bool has_msr_mcg_ext_ctl;
116
117 static struct kvm_cpuid2 *cpuid_cache;
118 static struct kvm_msr_list *kvm_feature_msrs;
119
120 int kvm_has_pit_state2(void)
121 {
122 return has_pit_state2;
123 }
124
125 bool kvm_has_smm(void)
126 {
127 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
128 }
129
130 bool kvm_has_adjust_clock_stable(void)
131 {
132 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
133
134 return (ret == KVM_CLOCK_TSC_STABLE);
135 }
136
137 bool kvm_has_exception_payload(void)
138 {
139 return has_exception_payload;
140 }
141
142 bool kvm_allows_irq0_override(void)
143 {
144 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
145 }
146
147 static bool kvm_x2apic_api_set_flags(uint64_t flags)
148 {
149 KVMState *s = KVM_STATE(current_machine->accelerator);
150
151 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
152 }
153
154 #define MEMORIZE(fn, _result) \
155 ({ \
156 static bool _memorized; \
157 \
158 if (_memorized) { \
159 return _result; \
160 } \
161 _memorized = true; \
162 _result = fn; \
163 })
164
165 static bool has_x2apic_api;
166
167 bool kvm_has_x2apic_api(void)
168 {
169 return has_x2apic_api;
170 }
171
172 bool kvm_enable_x2apic(void)
173 {
174 return MEMORIZE(
175 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
176 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
177 has_x2apic_api);
178 }
179
180 bool kvm_hv_vpindex_settable(void)
181 {
182 return hv_vpindex_settable;
183 }
184
185 static int kvm_get_tsc(CPUState *cs)
186 {
187 X86CPU *cpu = X86_CPU(cs);
188 CPUX86State *env = &cpu->env;
189 struct {
190 struct kvm_msrs info;
191 struct kvm_msr_entry entries[1];
192 } msr_data = {};
193 int ret;
194
195 if (env->tsc_valid) {
196 return 0;
197 }
198
199 memset(&msr_data, 0, sizeof(msr_data));
200 msr_data.info.nmsrs = 1;
201 msr_data.entries[0].index = MSR_IA32_TSC;
202 env->tsc_valid = !runstate_is_running();
203
204 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
205 if (ret < 0) {
206 return ret;
207 }
208
209 assert(ret == 1);
210 env->tsc = msr_data.entries[0].data;
211 return 0;
212 }
213
214 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
215 {
216 kvm_get_tsc(cpu);
217 }
218
219 void kvm_synchronize_all_tsc(void)
220 {
221 CPUState *cpu;
222
223 if (kvm_enabled()) {
224 CPU_FOREACH(cpu) {
225 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
226 }
227 }
228 }
229
230 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
231 {
232 struct kvm_cpuid2 *cpuid;
233 int r, size;
234
235 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
236 cpuid = g_malloc0(size);
237 cpuid->nent = max;
238 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
239 if (r == 0 && cpuid->nent >= max) {
240 r = -E2BIG;
241 }
242 if (r < 0) {
243 if (r == -E2BIG) {
244 g_free(cpuid);
245 return NULL;
246 } else {
247 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
248 strerror(-r));
249 exit(1);
250 }
251 }
252 return cpuid;
253 }
254
255 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
256 * for all entries.
257 */
258 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
259 {
260 struct kvm_cpuid2 *cpuid;
261 int max = 1;
262
263 if (cpuid_cache != NULL) {
264 return cpuid_cache;
265 }
266 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
267 max *= 2;
268 }
269 cpuid_cache = cpuid;
270 return cpuid;
271 }
272
273 static const struct kvm_para_features {
274 int cap;
275 int feature;
276 } para_features[] = {
277 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
278 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
279 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
280 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
281 };
282
283 static int get_para_features(KVMState *s)
284 {
285 int i, features = 0;
286
287 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
288 if (kvm_check_extension(s, para_features[i].cap)) {
289 features |= (1 << para_features[i].feature);
290 }
291 }
292
293 return features;
294 }
295
296 static bool host_tsx_blacklisted(void)
297 {
298 int family, model, stepping;\
299 char vendor[CPUID_VENDOR_SZ + 1];
300
301 host_vendor_fms(vendor, &family, &model, &stepping);
302
303 /* Check if we are running on a Haswell host known to have broken TSX */
304 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
305 (family == 6) &&
306 ((model == 63 && stepping < 4) ||
307 model == 60 || model == 69 || model == 70);
308 }
309
310 /* Returns the value for a specific register on the cpuid entry
311 */
312 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
313 {
314 uint32_t ret = 0;
315 switch (reg) {
316 case R_EAX:
317 ret = entry->eax;
318 break;
319 case R_EBX:
320 ret = entry->ebx;
321 break;
322 case R_ECX:
323 ret = entry->ecx;
324 break;
325 case R_EDX:
326 ret = entry->edx;
327 break;
328 }
329 return ret;
330 }
331
332 /* Find matching entry for function/index on kvm_cpuid2 struct
333 */
334 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
335 uint32_t function,
336 uint32_t index)
337 {
338 int i;
339 for (i = 0; i < cpuid->nent; ++i) {
340 if (cpuid->entries[i].function == function &&
341 cpuid->entries[i].index == index) {
342 return &cpuid->entries[i];
343 }
344 }
345 /* not found: */
346 return NULL;
347 }
348
349 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
350 uint32_t index, int reg)
351 {
352 struct kvm_cpuid2 *cpuid;
353 uint32_t ret = 0;
354 uint32_t cpuid_1_edx;
355 bool found = false;
356
357 cpuid = get_supported_cpuid(s);
358
359 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
360 if (entry) {
361 found = true;
362 ret = cpuid_entry_get_reg(entry, reg);
363 }
364
365 /* Fixups for the data returned by KVM, below */
366
367 if (function == 1 && reg == R_EDX) {
368 /* KVM before 2.6.30 misreports the following features */
369 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
370 } else if (function == 1 && reg == R_ECX) {
371 /* We can set the hypervisor flag, even if KVM does not return it on
372 * GET_SUPPORTED_CPUID
373 */
374 ret |= CPUID_EXT_HYPERVISOR;
375 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
376 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
377 * and the irqchip is in the kernel.
378 */
379 if (kvm_irqchip_in_kernel() &&
380 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
381 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
382 }
383
384 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
385 * without the in-kernel irqchip
386 */
387 if (!kvm_irqchip_in_kernel()) {
388 ret &= ~CPUID_EXT_X2APIC;
389 }
390
391 if (enable_cpu_pm) {
392 int disable_exits = kvm_check_extension(s,
393 KVM_CAP_X86_DISABLE_EXITS);
394
395 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
396 ret |= CPUID_EXT_MONITOR;
397 }
398 }
399 } else if (function == 6 && reg == R_EAX) {
400 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
401 } else if (function == 7 && index == 0 && reg == R_EBX) {
402 if (host_tsx_blacklisted()) {
403 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
404 }
405 } else if (function == 7 && index == 0 && reg == R_ECX) {
406 if (enable_cpu_pm) {
407 ret |= CPUID_7_0_ECX_WAITPKG;
408 } else {
409 ret &= ~CPUID_7_0_ECX_WAITPKG;
410 }
411 } else if (function == 7 && index == 0 && reg == R_EDX) {
412 /*
413 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
414 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
415 * returned by KVM_GET_MSR_INDEX_LIST.
416 */
417 if (!has_msr_arch_capabs) {
418 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
419 }
420 } else if (function == 0x80000001 && reg == R_ECX) {
421 /*
422 * It's safe to enable TOPOEXT even if it's not returned by
423 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
424 * us to keep CPU models including TOPOEXT runnable on older kernels.
425 */
426 ret |= CPUID_EXT3_TOPOEXT;
427 } else if (function == 0x80000001 && reg == R_EDX) {
428 /* On Intel, kvm returns cpuid according to the Intel spec,
429 * so add missing bits according to the AMD spec:
430 */
431 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
432 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
433 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
434 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
435 * be enabled without the in-kernel irqchip
436 */
437 if (!kvm_irqchip_in_kernel()) {
438 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
439 }
440 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
441 ret |= 1U << KVM_HINTS_REALTIME;
442 found = 1;
443 }
444
445 /* fallback for older kernels */
446 if ((function == KVM_CPUID_FEATURES) && !found) {
447 ret = get_para_features(s);
448 }
449
450 return ret;
451 }
452
453 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
454 {
455 struct {
456 struct kvm_msrs info;
457 struct kvm_msr_entry entries[1];
458 } msr_data = {};
459 uint64_t value;
460 uint32_t ret, can_be_one, must_be_one;
461
462 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
463 return 0;
464 }
465
466 /* Check if requested MSR is supported feature MSR */
467 int i;
468 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
469 if (kvm_feature_msrs->indices[i] == index) {
470 break;
471 }
472 if (i == kvm_feature_msrs->nmsrs) {
473 return 0; /* if the feature MSR is not supported, simply return 0 */
474 }
475
476 msr_data.info.nmsrs = 1;
477 msr_data.entries[0].index = index;
478
479 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
480 if (ret != 1) {
481 error_report("KVM get MSR (index=0x%x) feature failed, %s",
482 index, strerror(-ret));
483 exit(1);
484 }
485
486 value = msr_data.entries[0].data;
487 switch (index) {
488 case MSR_IA32_VMX_PROCBASED_CTLS2:
489 /* KVM forgot to add these bits for some time, do this ourselves. */
490 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) & CPUID_XSAVE_XSAVES) {
491 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
492 }
493 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) & CPUID_EXT_RDRAND) {
494 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
495 }
496 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & CPUID_7_0_EBX_INVPCID) {
497 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
498 }
499 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & CPUID_7_0_EBX_RDSEED) {
500 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
501 }
502 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) {
503 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
504 }
505 /* fall through */
506 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
507 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
508 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
509 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
510 /*
511 * Return true for bits that can be one, but do not have to be one.
512 * The SDM tells us which bits could have a "must be one" setting,
513 * so we can do the opposite transformation in make_vmx_msr_value.
514 */
515 must_be_one = (uint32_t)value;
516 can_be_one = (uint32_t)(value >> 32);
517 return can_be_one & ~must_be_one;
518
519 default:
520 return value;
521 }
522 }
523
524
525 typedef struct HWPoisonPage {
526 ram_addr_t ram_addr;
527 QLIST_ENTRY(HWPoisonPage) list;
528 } HWPoisonPage;
529
530 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
531 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
532
533 static void kvm_unpoison_all(void *param)
534 {
535 HWPoisonPage *page, *next_page;
536
537 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
538 QLIST_REMOVE(page, list);
539 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
540 g_free(page);
541 }
542 }
543
544 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
545 {
546 HWPoisonPage *page;
547
548 QLIST_FOREACH(page, &hwpoison_page_list, list) {
549 if (page->ram_addr == ram_addr) {
550 return;
551 }
552 }
553 page = g_new(HWPoisonPage, 1);
554 page->ram_addr = ram_addr;
555 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
556 }
557
558 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
559 int *max_banks)
560 {
561 int r;
562
563 r = kvm_check_extension(s, KVM_CAP_MCE);
564 if (r > 0) {
565 *max_banks = r;
566 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
567 }
568 return -ENOSYS;
569 }
570
571 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
572 {
573 CPUState *cs = CPU(cpu);
574 CPUX86State *env = &cpu->env;
575 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
576 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
577 uint64_t mcg_status = MCG_STATUS_MCIP;
578 int flags = 0;
579
580 if (code == BUS_MCEERR_AR) {
581 status |= MCI_STATUS_AR | 0x134;
582 mcg_status |= MCG_STATUS_EIPV;
583 } else {
584 status |= 0xc0;
585 mcg_status |= MCG_STATUS_RIPV;
586 }
587
588 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
589 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
590 * guest kernel back into env->mcg_ext_ctl.
591 */
592 cpu_synchronize_state(cs);
593 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
594 mcg_status |= MCG_STATUS_LMCE;
595 flags = 0;
596 }
597
598 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
599 (MCM_ADDR_PHYS << 6) | 0xc, flags);
600 }
601
602 static void hardware_memory_error(void *host_addr)
603 {
604 error_report("QEMU got Hardware memory error at addr %p", host_addr);
605 exit(1);
606 }
607
608 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
609 {
610 X86CPU *cpu = X86_CPU(c);
611 CPUX86State *env = &cpu->env;
612 ram_addr_t ram_addr;
613 hwaddr paddr;
614
615 /* If we get an action required MCE, it has been injected by KVM
616 * while the VM was running. An action optional MCE instead should
617 * be coming from the main thread, which qemu_init_sigbus identifies
618 * as the "early kill" thread.
619 */
620 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
621
622 if ((env->mcg_cap & MCG_SER_P) && addr) {
623 ram_addr = qemu_ram_addr_from_host(addr);
624 if (ram_addr != RAM_ADDR_INVALID &&
625 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
626 kvm_hwpoison_page_add(ram_addr);
627 kvm_mce_inject(cpu, paddr, code);
628
629 /*
630 * Use different logging severity based on error type.
631 * If there is additional MCE reporting on the hypervisor, QEMU VA
632 * could be another source to identify the PA and MCE details.
633 */
634 if (code == BUS_MCEERR_AR) {
635 error_report("Guest MCE Memory Error at QEMU addr %p and "
636 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
637 addr, paddr, "BUS_MCEERR_AR");
638 } else {
639 warn_report("Guest MCE Memory Error at QEMU addr %p and "
640 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
641 addr, paddr, "BUS_MCEERR_AO");
642 }
643
644 return;
645 }
646
647 if (code == BUS_MCEERR_AO) {
648 warn_report("Hardware memory error at addr %p of type %s "
649 "for memory used by QEMU itself instead of guest system!",
650 addr, "BUS_MCEERR_AO");
651 }
652 }
653
654 if (code == BUS_MCEERR_AR) {
655 hardware_memory_error(addr);
656 }
657
658 /* Hope we are lucky for AO MCE */
659 }
660
661 static void kvm_reset_exception(CPUX86State *env)
662 {
663 env->exception_nr = -1;
664 env->exception_pending = 0;
665 env->exception_injected = 0;
666 env->exception_has_payload = false;
667 env->exception_payload = 0;
668 }
669
670 static void kvm_queue_exception(CPUX86State *env,
671 int32_t exception_nr,
672 uint8_t exception_has_payload,
673 uint64_t exception_payload)
674 {
675 assert(env->exception_nr == -1);
676 assert(!env->exception_pending);
677 assert(!env->exception_injected);
678 assert(!env->exception_has_payload);
679
680 env->exception_nr = exception_nr;
681
682 if (has_exception_payload) {
683 env->exception_pending = 1;
684
685 env->exception_has_payload = exception_has_payload;
686 env->exception_payload = exception_payload;
687 } else {
688 env->exception_injected = 1;
689
690 if (exception_nr == EXCP01_DB) {
691 assert(exception_has_payload);
692 env->dr[6] = exception_payload;
693 } else if (exception_nr == EXCP0E_PAGE) {
694 assert(exception_has_payload);
695 env->cr[2] = exception_payload;
696 } else {
697 assert(!exception_has_payload);
698 }
699 }
700 }
701
702 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
703 {
704 CPUX86State *env = &cpu->env;
705
706 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
707 unsigned int bank, bank_num = env->mcg_cap & 0xff;
708 struct kvm_x86_mce mce;
709
710 kvm_reset_exception(env);
711
712 /*
713 * There must be at least one bank in use if an MCE is pending.
714 * Find it and use its values for the event injection.
715 */
716 for (bank = 0; bank < bank_num; bank++) {
717 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
718 break;
719 }
720 }
721 assert(bank < bank_num);
722
723 mce.bank = bank;
724 mce.status = env->mce_banks[bank * 4 + 1];
725 mce.mcg_status = env->mcg_status;
726 mce.addr = env->mce_banks[bank * 4 + 2];
727 mce.misc = env->mce_banks[bank * 4 + 3];
728
729 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
730 }
731 return 0;
732 }
733
734 static void cpu_update_state(void *opaque, int running, RunState state)
735 {
736 CPUX86State *env = opaque;
737
738 if (running) {
739 env->tsc_valid = false;
740 }
741 }
742
743 unsigned long kvm_arch_vcpu_id(CPUState *cs)
744 {
745 X86CPU *cpu = X86_CPU(cs);
746 return cpu->apic_id;
747 }
748
749 #ifndef KVM_CPUID_SIGNATURE_NEXT
750 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
751 #endif
752
753 static bool hyperv_enabled(X86CPU *cpu)
754 {
755 CPUState *cs = CPU(cpu);
756 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
757 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
758 cpu->hyperv_features || cpu->hyperv_passthrough);
759 }
760
761 static int kvm_arch_set_tsc_khz(CPUState *cs)
762 {
763 X86CPU *cpu = X86_CPU(cs);
764 CPUX86State *env = &cpu->env;
765 int r;
766
767 if (!env->tsc_khz) {
768 return 0;
769 }
770
771 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
772 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
773 -ENOTSUP;
774 if (r < 0) {
775 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
776 * TSC frequency doesn't match the one we want.
777 */
778 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
779 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
780 -ENOTSUP;
781 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
782 warn_report("TSC frequency mismatch between "
783 "VM (%" PRId64 " kHz) and host (%d kHz), "
784 "and TSC scaling unavailable",
785 env->tsc_khz, cur_freq);
786 return r;
787 }
788 }
789
790 return 0;
791 }
792
793 static bool tsc_is_stable_and_known(CPUX86State *env)
794 {
795 if (!env->tsc_khz) {
796 return false;
797 }
798 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
799 || env->user_tsc_khz;
800 }
801
802 static struct {
803 const char *desc;
804 struct {
805 uint32_t fw;
806 uint32_t bits;
807 } flags[2];
808 uint64_t dependencies;
809 } kvm_hyperv_properties[] = {
810 [HYPERV_FEAT_RELAXED] = {
811 .desc = "relaxed timing (hv-relaxed)",
812 .flags = {
813 {.fw = FEAT_HYPERV_EAX,
814 .bits = HV_HYPERCALL_AVAILABLE},
815 {.fw = FEAT_HV_RECOMM_EAX,
816 .bits = HV_RELAXED_TIMING_RECOMMENDED}
817 }
818 },
819 [HYPERV_FEAT_VAPIC] = {
820 .desc = "virtual APIC (hv-vapic)",
821 .flags = {
822 {.fw = FEAT_HYPERV_EAX,
823 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
824 {.fw = FEAT_HV_RECOMM_EAX,
825 .bits = HV_APIC_ACCESS_RECOMMENDED}
826 }
827 },
828 [HYPERV_FEAT_TIME] = {
829 .desc = "clocksources (hv-time)",
830 .flags = {
831 {.fw = FEAT_HYPERV_EAX,
832 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
833 HV_REFERENCE_TSC_AVAILABLE}
834 }
835 },
836 [HYPERV_FEAT_CRASH] = {
837 .desc = "crash MSRs (hv-crash)",
838 .flags = {
839 {.fw = FEAT_HYPERV_EDX,
840 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
841 }
842 },
843 [HYPERV_FEAT_RESET] = {
844 .desc = "reset MSR (hv-reset)",
845 .flags = {
846 {.fw = FEAT_HYPERV_EAX,
847 .bits = HV_RESET_AVAILABLE}
848 }
849 },
850 [HYPERV_FEAT_VPINDEX] = {
851 .desc = "VP_INDEX MSR (hv-vpindex)",
852 .flags = {
853 {.fw = FEAT_HYPERV_EAX,
854 .bits = HV_VP_INDEX_AVAILABLE}
855 }
856 },
857 [HYPERV_FEAT_RUNTIME] = {
858 .desc = "VP_RUNTIME MSR (hv-runtime)",
859 .flags = {
860 {.fw = FEAT_HYPERV_EAX,
861 .bits = HV_VP_RUNTIME_AVAILABLE}
862 }
863 },
864 [HYPERV_FEAT_SYNIC] = {
865 .desc = "synthetic interrupt controller (hv-synic)",
866 .flags = {
867 {.fw = FEAT_HYPERV_EAX,
868 .bits = HV_SYNIC_AVAILABLE}
869 }
870 },
871 [HYPERV_FEAT_STIMER] = {
872 .desc = "synthetic timers (hv-stimer)",
873 .flags = {
874 {.fw = FEAT_HYPERV_EAX,
875 .bits = HV_SYNTIMERS_AVAILABLE}
876 },
877 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
878 },
879 [HYPERV_FEAT_FREQUENCIES] = {
880 .desc = "frequency MSRs (hv-frequencies)",
881 .flags = {
882 {.fw = FEAT_HYPERV_EAX,
883 .bits = HV_ACCESS_FREQUENCY_MSRS},
884 {.fw = FEAT_HYPERV_EDX,
885 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
886 }
887 },
888 [HYPERV_FEAT_REENLIGHTENMENT] = {
889 .desc = "reenlightenment MSRs (hv-reenlightenment)",
890 .flags = {
891 {.fw = FEAT_HYPERV_EAX,
892 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
893 }
894 },
895 [HYPERV_FEAT_TLBFLUSH] = {
896 .desc = "paravirtualized TLB flush (hv-tlbflush)",
897 .flags = {
898 {.fw = FEAT_HV_RECOMM_EAX,
899 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
900 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
901 },
902 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
903 },
904 [HYPERV_FEAT_EVMCS] = {
905 .desc = "enlightened VMCS (hv-evmcs)",
906 .flags = {
907 {.fw = FEAT_HV_RECOMM_EAX,
908 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
909 },
910 .dependencies = BIT(HYPERV_FEAT_VAPIC)
911 },
912 [HYPERV_FEAT_IPI] = {
913 .desc = "paravirtualized IPI (hv-ipi)",
914 .flags = {
915 {.fw = FEAT_HV_RECOMM_EAX,
916 .bits = HV_CLUSTER_IPI_RECOMMENDED |
917 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
918 },
919 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
920 },
921 [HYPERV_FEAT_STIMER_DIRECT] = {
922 .desc = "direct mode synthetic timers (hv-stimer-direct)",
923 .flags = {
924 {.fw = FEAT_HYPERV_EDX,
925 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
926 },
927 .dependencies = BIT(HYPERV_FEAT_STIMER)
928 },
929 };
930
931 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
932 {
933 struct kvm_cpuid2 *cpuid;
934 int r, size;
935
936 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
937 cpuid = g_malloc0(size);
938 cpuid->nent = max;
939
940 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
941 if (r == 0 && cpuid->nent >= max) {
942 r = -E2BIG;
943 }
944 if (r < 0) {
945 if (r == -E2BIG) {
946 g_free(cpuid);
947 return NULL;
948 } else {
949 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
950 strerror(-r));
951 exit(1);
952 }
953 }
954 return cpuid;
955 }
956
957 /*
958 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
959 * for all entries.
960 */
961 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
962 {
963 struct kvm_cpuid2 *cpuid;
964 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
965
966 /*
967 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
968 * -E2BIG, however, it doesn't report back the right size. Keep increasing
969 * it and re-trying until we succeed.
970 */
971 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
972 max++;
973 }
974 return cpuid;
975 }
976
977 /*
978 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
979 * leaves from KVM_CAP_HYPERV* and present MSRs data.
980 */
981 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
982 {
983 X86CPU *cpu = X86_CPU(cs);
984 struct kvm_cpuid2 *cpuid;
985 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
986
987 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
988 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
989 cpuid->nent = 2;
990
991 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
992 entry_feat = &cpuid->entries[0];
993 entry_feat->function = HV_CPUID_FEATURES;
994
995 entry_recomm = &cpuid->entries[1];
996 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
997 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
998
999 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1000 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1001 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1002 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1003 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1004 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1005 }
1006
1007 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1008 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1009 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1010 }
1011
1012 if (has_msr_hv_frequencies) {
1013 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1014 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1015 }
1016
1017 if (has_msr_hv_crash) {
1018 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1019 }
1020
1021 if (has_msr_hv_reenlightenment) {
1022 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1023 }
1024
1025 if (has_msr_hv_reset) {
1026 entry_feat->eax |= HV_RESET_AVAILABLE;
1027 }
1028
1029 if (has_msr_hv_vpindex) {
1030 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1031 }
1032
1033 if (has_msr_hv_runtime) {
1034 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1035 }
1036
1037 if (has_msr_hv_synic) {
1038 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1039 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1040
1041 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1042 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1043 }
1044 }
1045
1046 if (has_msr_hv_stimer) {
1047 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1048 }
1049
1050 if (kvm_check_extension(cs->kvm_state,
1051 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1052 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1053 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1054 }
1055
1056 if (kvm_check_extension(cs->kvm_state,
1057 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1058 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1059 }
1060
1061 if (kvm_check_extension(cs->kvm_state,
1062 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1063 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1064 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1065 }
1066
1067 return cpuid;
1068 }
1069
1070 static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
1071 {
1072 struct kvm_cpuid_entry2 *entry;
1073 uint32_t func;
1074 int reg;
1075
1076 switch (fw) {
1077 case FEAT_HYPERV_EAX:
1078 reg = R_EAX;
1079 func = HV_CPUID_FEATURES;
1080 break;
1081 case FEAT_HYPERV_EDX:
1082 reg = R_EDX;
1083 func = HV_CPUID_FEATURES;
1084 break;
1085 case FEAT_HV_RECOMM_EAX:
1086 reg = R_EAX;
1087 func = HV_CPUID_ENLIGHTMENT_INFO;
1088 break;
1089 default:
1090 return -EINVAL;
1091 }
1092
1093 entry = cpuid_find_entry(cpuid, func, 0);
1094 if (!entry) {
1095 return -ENOENT;
1096 }
1097
1098 switch (reg) {
1099 case R_EAX:
1100 *r = entry->eax;
1101 break;
1102 case R_EDX:
1103 *r = entry->edx;
1104 break;
1105 default:
1106 return -EINVAL;
1107 }
1108
1109 return 0;
1110 }
1111
1112 static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1113 int feature)
1114 {
1115 X86CPU *cpu = X86_CPU(cs);
1116 CPUX86State *env = &cpu->env;
1117 uint32_t r, fw, bits;
1118 uint64_t deps;
1119 int i, dep_feat;
1120
1121 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
1122 return 0;
1123 }
1124
1125 deps = kvm_hyperv_properties[feature].dependencies;
1126 while (deps) {
1127 dep_feat = ctz64(deps);
1128 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1129 fprintf(stderr,
1130 "Hyper-V %s requires Hyper-V %s\n",
1131 kvm_hyperv_properties[feature].desc,
1132 kvm_hyperv_properties[dep_feat].desc);
1133 return 1;
1134 }
1135 deps &= ~(1ull << dep_feat);
1136 }
1137
1138 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1139 fw = kvm_hyperv_properties[feature].flags[i].fw;
1140 bits = kvm_hyperv_properties[feature].flags[i].bits;
1141
1142 if (!fw) {
1143 continue;
1144 }
1145
1146 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
1147 if (hyperv_feat_enabled(cpu, feature)) {
1148 fprintf(stderr,
1149 "Hyper-V %s is not supported by kernel\n",
1150 kvm_hyperv_properties[feature].desc);
1151 return 1;
1152 } else {
1153 return 0;
1154 }
1155 }
1156
1157 env->features[fw] |= bits;
1158 }
1159
1160 if (cpu->hyperv_passthrough) {
1161 cpu->hyperv_features |= BIT(feature);
1162 }
1163
1164 return 0;
1165 }
1166
1167 /*
1168 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1169 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1170 * extentions are enabled.
1171 */
1172 static int hyperv_handle_properties(CPUState *cs,
1173 struct kvm_cpuid_entry2 *cpuid_ent)
1174 {
1175 X86CPU *cpu = X86_CPU(cs);
1176 CPUX86State *env = &cpu->env;
1177 struct kvm_cpuid2 *cpuid;
1178 struct kvm_cpuid_entry2 *c;
1179 uint32_t signature[3];
1180 uint32_t cpuid_i = 0;
1181 int r;
1182
1183 if (!hyperv_enabled(cpu))
1184 return 0;
1185
1186 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1187 cpu->hyperv_passthrough) {
1188 uint16_t evmcs_version;
1189
1190 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1191 (uintptr_t)&evmcs_version);
1192
1193 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
1194 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1195 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1196 return -ENOSYS;
1197 }
1198
1199 if (!r) {
1200 env->features[FEAT_HV_RECOMM_EAX] |=
1201 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1202 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1203 }
1204 }
1205
1206 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1207 cpuid = get_supported_hv_cpuid(cs);
1208 } else {
1209 cpuid = get_supported_hv_cpuid_legacy(cs);
1210 }
1211
1212 if (cpu->hyperv_passthrough) {
1213 memcpy(cpuid_ent, &cpuid->entries[0],
1214 cpuid->nent * sizeof(cpuid->entries[0]));
1215
1216 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1217 if (c) {
1218 env->features[FEAT_HYPERV_EAX] = c->eax;
1219 env->features[FEAT_HYPERV_EBX] = c->ebx;
1220 env->features[FEAT_HYPERV_EDX] = c->eax;
1221 }
1222 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1223 if (c) {
1224 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1225
1226 /* hv-spinlocks may have been overriden */
1227 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1228 c->ebx = cpu->hyperv_spinlock_attempts;
1229 }
1230 }
1231 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1232 if (c) {
1233 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1234 }
1235 }
1236
1237 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1238 env->features[FEAT_HV_RECOMM_EAX] |= HV_NO_NONARCH_CORESHARING;
1239 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1240 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1241 if (c) {
1242 env->features[FEAT_HV_RECOMM_EAX] |=
1243 c->eax & HV_NO_NONARCH_CORESHARING;
1244 }
1245 }
1246
1247 /* Features */
1248 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
1249 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1250 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1251 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1252 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1253 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1254 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1255 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1256 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1257 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1258 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1259 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1260 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1261 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
1262 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
1263
1264 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1265 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1266 !cpu->hyperv_synic_kvm_only &&
1267 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1268 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
1269 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1270 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1271 r |= 1;
1272 }
1273
1274 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1275 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1276
1277 if (r) {
1278 r = -ENOSYS;
1279 goto free;
1280 }
1281
1282 if (cpu->hyperv_passthrough) {
1283 /* We already copied all feature words from KVM as is */
1284 r = cpuid->nent;
1285 goto free;
1286 }
1287
1288 c = &cpuid_ent[cpuid_i++];
1289 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1290 if (!cpu->hyperv_vendor_id) {
1291 memcpy(signature, "Microsoft Hv", 12);
1292 } else {
1293 size_t len = strlen(cpu->hyperv_vendor_id);
1294
1295 if (len > 12) {
1296 error_report("hv-vendor-id truncated to 12 characters");
1297 len = 12;
1298 }
1299 memset(signature, 0, 12);
1300 memcpy(signature, cpu->hyperv_vendor_id, len);
1301 }
1302 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1303 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1304 c->ebx = signature[0];
1305 c->ecx = signature[1];
1306 c->edx = signature[2];
1307
1308 c = &cpuid_ent[cpuid_i++];
1309 c->function = HV_CPUID_INTERFACE;
1310 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1311 c->eax = signature[0];
1312 c->ebx = 0;
1313 c->ecx = 0;
1314 c->edx = 0;
1315
1316 c = &cpuid_ent[cpuid_i++];
1317 c->function = HV_CPUID_VERSION;
1318 c->eax = 0x00001bbc;
1319 c->ebx = 0x00060001;
1320
1321 c = &cpuid_ent[cpuid_i++];
1322 c->function = HV_CPUID_FEATURES;
1323 c->eax = env->features[FEAT_HYPERV_EAX];
1324 c->ebx = env->features[FEAT_HYPERV_EBX];
1325 c->edx = env->features[FEAT_HYPERV_EDX];
1326
1327 c = &cpuid_ent[cpuid_i++];
1328 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1329 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1330 c->ebx = cpu->hyperv_spinlock_attempts;
1331
1332 c = &cpuid_ent[cpuid_i++];
1333 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1334 c->eax = cpu->hv_max_vps;
1335 c->ebx = 0x40;
1336
1337 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1338 __u32 function;
1339
1340 /* Create zeroed 0x40000006..0x40000009 leaves */
1341 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1342 function < HV_CPUID_NESTED_FEATURES; function++) {
1343 c = &cpuid_ent[cpuid_i++];
1344 c->function = function;
1345 }
1346
1347 c = &cpuid_ent[cpuid_i++];
1348 c->function = HV_CPUID_NESTED_FEATURES;
1349 c->eax = env->features[FEAT_HV_NESTED_EAX];
1350 }
1351 r = cpuid_i;
1352
1353 free:
1354 g_free(cpuid);
1355
1356 return r;
1357 }
1358
1359 static Error *hv_passthrough_mig_blocker;
1360 static Error *hv_no_nonarch_cs_mig_blocker;
1361
1362 static int hyperv_init_vcpu(X86CPU *cpu)
1363 {
1364 CPUState *cs = CPU(cpu);
1365 Error *local_err = NULL;
1366 int ret;
1367
1368 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1369 error_setg(&hv_passthrough_mig_blocker,
1370 "'hv-passthrough' CPU flag prevents migration, use explicit"
1371 " set of hv-* flags instead");
1372 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1373 if (local_err) {
1374 error_report_err(local_err);
1375 error_free(hv_passthrough_mig_blocker);
1376 return ret;
1377 }
1378 }
1379
1380 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1381 hv_no_nonarch_cs_mig_blocker == NULL) {
1382 error_setg(&hv_no_nonarch_cs_mig_blocker,
1383 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1384 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1385 " make sure SMT is disabled and/or that vCPUs are properly"
1386 " pinned)");
1387 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1388 if (local_err) {
1389 error_report_err(local_err);
1390 error_free(hv_no_nonarch_cs_mig_blocker);
1391 return ret;
1392 }
1393 }
1394
1395 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1396 /*
1397 * the kernel doesn't support setting vp_index; assert that its value
1398 * is in sync
1399 */
1400 struct {
1401 struct kvm_msrs info;
1402 struct kvm_msr_entry entries[1];
1403 } msr_data = {
1404 .info.nmsrs = 1,
1405 .entries[0].index = HV_X64_MSR_VP_INDEX,
1406 };
1407
1408 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
1409 if (ret < 0) {
1410 return ret;
1411 }
1412 assert(ret == 1);
1413
1414 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
1415 error_report("kernel's vp_index != QEMU's vp_index");
1416 return -ENXIO;
1417 }
1418 }
1419
1420 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1421 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1422 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1423 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1424 if (ret < 0) {
1425 error_report("failed to turn on HyperV SynIC in KVM: %s",
1426 strerror(-ret));
1427 return ret;
1428 }
1429
1430 if (!cpu->hyperv_synic_kvm_only) {
1431 ret = hyperv_x86_synic_add(cpu);
1432 if (ret < 0) {
1433 error_report("failed to create HyperV SynIC: %s",
1434 strerror(-ret));
1435 return ret;
1436 }
1437 }
1438 }
1439
1440 return 0;
1441 }
1442
1443 static Error *invtsc_mig_blocker;
1444
1445 #define KVM_MAX_CPUID_ENTRIES 100
1446
1447 int kvm_arch_init_vcpu(CPUState *cs)
1448 {
1449 struct {
1450 struct kvm_cpuid2 cpuid;
1451 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1452 } cpuid_data;
1453 /*
1454 * The kernel defines these structs with padding fields so there
1455 * should be no extra padding in our cpuid_data struct.
1456 */
1457 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1458 sizeof(struct kvm_cpuid2) +
1459 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1460
1461 X86CPU *cpu = X86_CPU(cs);
1462 CPUX86State *env = &cpu->env;
1463 uint32_t limit, i, j, cpuid_i;
1464 uint32_t unused;
1465 struct kvm_cpuid_entry2 *c;
1466 uint32_t signature[3];
1467 int kvm_base = KVM_CPUID_SIGNATURE;
1468 int max_nested_state_len;
1469 int r;
1470 Error *local_err = NULL;
1471
1472 memset(&cpuid_data, 0, sizeof(cpuid_data));
1473
1474 cpuid_i = 0;
1475
1476 r = kvm_arch_set_tsc_khz(cs);
1477 if (r < 0) {
1478 return r;
1479 }
1480
1481 /* vcpu's TSC frequency is either specified by user, or following
1482 * the value used by KVM if the former is not present. In the
1483 * latter case, we query it from KVM and record in env->tsc_khz,
1484 * so that vcpu's TSC frequency can be migrated later via this field.
1485 */
1486 if (!env->tsc_khz) {
1487 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1488 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1489 -ENOTSUP;
1490 if (r > 0) {
1491 env->tsc_khz = r;
1492 }
1493 }
1494
1495 /* Paravirtualization CPUIDs */
1496 r = hyperv_handle_properties(cs, cpuid_data.entries);
1497 if (r < 0) {
1498 return r;
1499 } else if (r > 0) {
1500 cpuid_i = r;
1501 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1502 has_msr_hv_hypercall = true;
1503 }
1504
1505 if (cpu->expose_kvm) {
1506 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1507 c = &cpuid_data.entries[cpuid_i++];
1508 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1509 c->eax = KVM_CPUID_FEATURES | kvm_base;
1510 c->ebx = signature[0];
1511 c->ecx = signature[1];
1512 c->edx = signature[2];
1513
1514 c = &cpuid_data.entries[cpuid_i++];
1515 c->function = KVM_CPUID_FEATURES | kvm_base;
1516 c->eax = env->features[FEAT_KVM];
1517 c->edx = env->features[FEAT_KVM_HINTS];
1518 }
1519
1520 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1521
1522 for (i = 0; i <= limit; i++) {
1523 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1524 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1525 abort();
1526 }
1527 c = &cpuid_data.entries[cpuid_i++];
1528
1529 switch (i) {
1530 case 2: {
1531 /* Keep reading function 2 till all the input is received */
1532 int times;
1533
1534 c->function = i;
1535 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1536 KVM_CPUID_FLAG_STATE_READ_NEXT;
1537 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1538 times = c->eax & 0xff;
1539
1540 for (j = 1; j < times; ++j) {
1541 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1542 fprintf(stderr, "cpuid_data is full, no space for "
1543 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1544 abort();
1545 }
1546 c = &cpuid_data.entries[cpuid_i++];
1547 c->function = i;
1548 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1549 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1550 }
1551 break;
1552 }
1553 case 0x1f:
1554 if (env->nr_dies < 2) {
1555 break;
1556 }
1557 case 4:
1558 case 0xb:
1559 case 0xd:
1560 for (j = 0; ; j++) {
1561 if (i == 0xd && j == 64) {
1562 break;
1563 }
1564
1565 if (i == 0x1f && j == 64) {
1566 break;
1567 }
1568
1569 c->function = i;
1570 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1571 c->index = j;
1572 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1573
1574 if (i == 4 && c->eax == 0) {
1575 break;
1576 }
1577 if (i == 0xb && !(c->ecx & 0xff00)) {
1578 break;
1579 }
1580 if (i == 0x1f && !(c->ecx & 0xff00)) {
1581 break;
1582 }
1583 if (i == 0xd && c->eax == 0) {
1584 continue;
1585 }
1586 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1587 fprintf(stderr, "cpuid_data is full, no space for "
1588 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1589 abort();
1590 }
1591 c = &cpuid_data.entries[cpuid_i++];
1592 }
1593 break;
1594 case 0x7:
1595 case 0x14: {
1596 uint32_t times;
1597
1598 c->function = i;
1599 c->index = 0;
1600 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1601 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1602 times = c->eax;
1603
1604 for (j = 1; j <= times; ++j) {
1605 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1606 fprintf(stderr, "cpuid_data is full, no space for "
1607 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1608 abort();
1609 }
1610 c = &cpuid_data.entries[cpuid_i++];
1611 c->function = i;
1612 c->index = j;
1613 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1614 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1615 }
1616 break;
1617 }
1618 default:
1619 c->function = i;
1620 c->flags = 0;
1621 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1622 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1623 /*
1624 * KVM already returns all zeroes if a CPUID entry is missing,
1625 * so we can omit it and avoid hitting KVM's 80-entry limit.
1626 */
1627 cpuid_i--;
1628 }
1629 break;
1630 }
1631 }
1632
1633 if (limit >= 0x0a) {
1634 uint32_t eax, edx;
1635
1636 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1637
1638 has_architectural_pmu_version = eax & 0xff;
1639 if (has_architectural_pmu_version > 0) {
1640 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1641
1642 /* Shouldn't be more than 32, since that's the number of bits
1643 * available in EBX to tell us _which_ counters are available.
1644 * Play it safe.
1645 */
1646 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1647 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1648 }
1649
1650 if (has_architectural_pmu_version > 1) {
1651 num_architectural_pmu_fixed_counters = edx & 0x1f;
1652
1653 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1654 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1655 }
1656 }
1657 }
1658 }
1659
1660 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1661
1662 for (i = 0x80000000; i <= limit; i++) {
1663 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1664 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1665 abort();
1666 }
1667 c = &cpuid_data.entries[cpuid_i++];
1668
1669 switch (i) {
1670 case 0x8000001d:
1671 /* Query for all AMD cache information leaves */
1672 for (j = 0; ; j++) {
1673 c->function = i;
1674 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1675 c->index = j;
1676 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1677
1678 if (c->eax == 0) {
1679 break;
1680 }
1681 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1682 fprintf(stderr, "cpuid_data is full, no space for "
1683 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1684 abort();
1685 }
1686 c = &cpuid_data.entries[cpuid_i++];
1687 }
1688 break;
1689 default:
1690 c->function = i;
1691 c->flags = 0;
1692 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1693 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1694 /*
1695 * KVM already returns all zeroes if a CPUID entry is missing,
1696 * so we can omit it and avoid hitting KVM's 80-entry limit.
1697 */
1698 cpuid_i--;
1699 }
1700 break;
1701 }
1702 }
1703
1704 /* Call Centaur's CPUID instructions they are supported. */
1705 if (env->cpuid_xlevel2 > 0) {
1706 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1707
1708 for (i = 0xC0000000; i <= limit; i++) {
1709 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1710 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1711 abort();
1712 }
1713 c = &cpuid_data.entries[cpuid_i++];
1714
1715 c->function = i;
1716 c->flags = 0;
1717 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1718 }
1719 }
1720
1721 cpuid_data.cpuid.nent = cpuid_i;
1722
1723 if (((env->cpuid_version >> 8)&0xF) >= 6
1724 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1725 (CPUID_MCE | CPUID_MCA)
1726 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1727 uint64_t mcg_cap, unsupported_caps;
1728 int banks;
1729 int ret;
1730
1731 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1732 if (ret < 0) {
1733 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1734 return ret;
1735 }
1736
1737 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1738 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1739 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1740 return -ENOTSUP;
1741 }
1742
1743 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1744 if (unsupported_caps) {
1745 if (unsupported_caps & MCG_LMCE_P) {
1746 error_report("kvm: LMCE not supported");
1747 return -ENOTSUP;
1748 }
1749 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1750 unsupported_caps);
1751 }
1752
1753 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1754 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1755 if (ret < 0) {
1756 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1757 return ret;
1758 }
1759 }
1760
1761 qemu_add_vm_change_state_handler(cpu_update_state, env);
1762
1763 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1764 if (c) {
1765 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1766 !!(c->ecx & CPUID_EXT_SMX);
1767 }
1768
1769 if (env->mcg_cap & MCG_LMCE_P) {
1770 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1771 }
1772
1773 if (!env->user_tsc_khz) {
1774 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1775 invtsc_mig_blocker == NULL) {
1776 error_setg(&invtsc_mig_blocker,
1777 "State blocked by non-migratable CPU device"
1778 " (invtsc flag)");
1779 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1780 if (local_err) {
1781 error_report_err(local_err);
1782 error_free(invtsc_mig_blocker);
1783 return r;
1784 }
1785 }
1786 }
1787
1788 if (cpu->vmware_cpuid_freq
1789 /* Guests depend on 0x40000000 to detect this feature, so only expose
1790 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1791 && cpu->expose_kvm
1792 && kvm_base == KVM_CPUID_SIGNATURE
1793 /* TSC clock must be stable and known for this feature. */
1794 && tsc_is_stable_and_known(env)) {
1795
1796 c = &cpuid_data.entries[cpuid_i++];
1797 c->function = KVM_CPUID_SIGNATURE | 0x10;
1798 c->eax = env->tsc_khz;
1799 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1800 * APIC_BUS_CYCLE_NS */
1801 c->ebx = 1000000;
1802 c->ecx = c->edx = 0;
1803
1804 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1805 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1806 }
1807
1808 cpuid_data.cpuid.nent = cpuid_i;
1809
1810 cpuid_data.cpuid.padding = 0;
1811 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1812 if (r) {
1813 goto fail;
1814 }
1815
1816 if (has_xsave) {
1817 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1818 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
1819 }
1820
1821 max_nested_state_len = kvm_max_nested_state_length();
1822 if (max_nested_state_len > 0) {
1823 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1824
1825 if (cpu_has_vmx(env)) {
1826 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1827
1828 env->nested_state = g_malloc0(max_nested_state_len);
1829 env->nested_state->size = max_nested_state_len;
1830 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1831
1832 vmx_hdr = &env->nested_state->hdr.vmx;
1833 vmx_hdr->vmxon_pa = -1ull;
1834 vmx_hdr->vmcs12_pa = -1ull;
1835 }
1836 }
1837
1838 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1839
1840 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1841 has_msr_tsc_aux = false;
1842 }
1843
1844 r = hyperv_init_vcpu(cpu);
1845 if (r) {
1846 goto fail;
1847 }
1848
1849 return 0;
1850
1851 fail:
1852 migrate_del_blocker(invtsc_mig_blocker);
1853
1854 return r;
1855 }
1856
1857 int kvm_arch_destroy_vcpu(CPUState *cs)
1858 {
1859 X86CPU *cpu = X86_CPU(cs);
1860 CPUX86State *env = &cpu->env;
1861
1862 if (cpu->kvm_msr_buf) {
1863 g_free(cpu->kvm_msr_buf);
1864 cpu->kvm_msr_buf = NULL;
1865 }
1866
1867 if (env->nested_state) {
1868 g_free(env->nested_state);
1869 env->nested_state = NULL;
1870 }
1871
1872 return 0;
1873 }
1874
1875 void kvm_arch_reset_vcpu(X86CPU *cpu)
1876 {
1877 CPUX86State *env = &cpu->env;
1878
1879 env->xcr0 = 1;
1880 if (kvm_irqchip_in_kernel()) {
1881 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1882 KVM_MP_STATE_UNINITIALIZED;
1883 } else {
1884 env->mp_state = KVM_MP_STATE_RUNNABLE;
1885 }
1886
1887 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1888 int i;
1889 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1890 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1891 }
1892
1893 hyperv_x86_synic_reset(cpu);
1894 }
1895 /* enabled by default */
1896 env->poll_control_msr = 1;
1897 }
1898
1899 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1900 {
1901 CPUX86State *env = &cpu->env;
1902
1903 /* APs get directly into wait-for-SIPI state. */
1904 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1905 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1906 }
1907 }
1908
1909 static int kvm_get_supported_feature_msrs(KVMState *s)
1910 {
1911 int ret = 0;
1912
1913 if (kvm_feature_msrs != NULL) {
1914 return 0;
1915 }
1916
1917 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1918 return 0;
1919 }
1920
1921 struct kvm_msr_list msr_list;
1922
1923 msr_list.nmsrs = 0;
1924 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1925 if (ret < 0 && ret != -E2BIG) {
1926 error_report("Fetch KVM feature MSR list failed: %s",
1927 strerror(-ret));
1928 return ret;
1929 }
1930
1931 assert(msr_list.nmsrs > 0);
1932 kvm_feature_msrs = (struct kvm_msr_list *) \
1933 g_malloc0(sizeof(msr_list) +
1934 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1935
1936 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1937 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1938
1939 if (ret < 0) {
1940 error_report("Fetch KVM feature MSR list failed: %s",
1941 strerror(-ret));
1942 g_free(kvm_feature_msrs);
1943 kvm_feature_msrs = NULL;
1944 return ret;
1945 }
1946
1947 return 0;
1948 }
1949
1950 static int kvm_get_supported_msrs(KVMState *s)
1951 {
1952 int ret = 0;
1953 struct kvm_msr_list msr_list, *kvm_msr_list;
1954
1955 /*
1956 * Obtain MSR list from KVM. These are the MSRs that we must
1957 * save/restore.
1958 */
1959 msr_list.nmsrs = 0;
1960 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1961 if (ret < 0 && ret != -E2BIG) {
1962 return ret;
1963 }
1964 /*
1965 * Old kernel modules had a bug and could write beyond the provided
1966 * memory. Allocate at least a safe amount of 1K.
1967 */
1968 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1969 msr_list.nmsrs *
1970 sizeof(msr_list.indices[0])));
1971
1972 kvm_msr_list->nmsrs = msr_list.nmsrs;
1973 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1974 if (ret >= 0) {
1975 int i;
1976
1977 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1978 switch (kvm_msr_list->indices[i]) {
1979 case MSR_STAR:
1980 has_msr_star = true;
1981 break;
1982 case MSR_VM_HSAVE_PA:
1983 has_msr_hsave_pa = true;
1984 break;
1985 case MSR_TSC_AUX:
1986 has_msr_tsc_aux = true;
1987 break;
1988 case MSR_TSC_ADJUST:
1989 has_msr_tsc_adjust = true;
1990 break;
1991 case MSR_IA32_TSCDEADLINE:
1992 has_msr_tsc_deadline = true;
1993 break;
1994 case MSR_IA32_SMBASE:
1995 has_msr_smbase = true;
1996 break;
1997 case MSR_SMI_COUNT:
1998 has_msr_smi_count = true;
1999 break;
2000 case MSR_IA32_MISC_ENABLE:
2001 has_msr_misc_enable = true;
2002 break;
2003 case MSR_IA32_BNDCFGS:
2004 has_msr_bndcfgs = true;
2005 break;
2006 case MSR_IA32_XSS:
2007 has_msr_xss = true;
2008 break;
2009 case MSR_IA32_UMWAIT_CONTROL:
2010 has_msr_umwait = true;
2011 break;
2012 case HV_X64_MSR_CRASH_CTL:
2013 has_msr_hv_crash = true;
2014 break;
2015 case HV_X64_MSR_RESET:
2016 has_msr_hv_reset = true;
2017 break;
2018 case HV_X64_MSR_VP_INDEX:
2019 has_msr_hv_vpindex = true;
2020 break;
2021 case HV_X64_MSR_VP_RUNTIME:
2022 has_msr_hv_runtime = true;
2023 break;
2024 case HV_X64_MSR_SCONTROL:
2025 has_msr_hv_synic = true;
2026 break;
2027 case HV_X64_MSR_STIMER0_CONFIG:
2028 has_msr_hv_stimer = true;
2029 break;
2030 case HV_X64_MSR_TSC_FREQUENCY:
2031 has_msr_hv_frequencies = true;
2032 break;
2033 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2034 has_msr_hv_reenlightenment = true;
2035 break;
2036 case MSR_IA32_SPEC_CTRL:
2037 has_msr_spec_ctrl = true;
2038 break;
2039 case MSR_VIRT_SSBD:
2040 has_msr_virt_ssbd = true;
2041 break;
2042 case MSR_IA32_ARCH_CAPABILITIES:
2043 has_msr_arch_capabs = true;
2044 break;
2045 case MSR_IA32_CORE_CAPABILITY:
2046 has_msr_core_capabs = true;
2047 break;
2048 case MSR_IA32_VMX_VMFUNC:
2049 has_msr_vmx_vmfunc = true;
2050 break;
2051 }
2052 }
2053 }
2054
2055 g_free(kvm_msr_list);
2056
2057 return ret;
2058 }
2059
2060 static Notifier smram_machine_done;
2061 static KVMMemoryListener smram_listener;
2062 static AddressSpace smram_address_space;
2063 static MemoryRegion smram_as_root;
2064 static MemoryRegion smram_as_mem;
2065
2066 static void register_smram_listener(Notifier *n, void *unused)
2067 {
2068 MemoryRegion *smram =
2069 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2070
2071 /* Outer container... */
2072 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2073 memory_region_set_enabled(&smram_as_root, true);
2074
2075 /* ... with two regions inside: normal system memory with low
2076 * priority, and...
2077 */
2078 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2079 get_system_memory(), 0, ~0ull);
2080 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2081 memory_region_set_enabled(&smram_as_mem, true);
2082
2083 if (smram) {
2084 /* ... SMRAM with higher priority */
2085 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2086 memory_region_set_enabled(smram, true);
2087 }
2088
2089 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2090 kvm_memory_listener_register(kvm_state, &smram_listener,
2091 &smram_address_space, 1);
2092 }
2093
2094 int kvm_arch_init(MachineState *ms, KVMState *s)
2095 {
2096 uint64_t identity_base = 0xfffbc000;
2097 uint64_t shadow_mem;
2098 int ret;
2099 struct utsname utsname;
2100
2101 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
2102 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
2103 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
2104
2105 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2106
2107 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2108 if (has_exception_payload) {
2109 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2110 if (ret < 0) {
2111 error_report("kvm: Failed to enable exception payload cap: %s",
2112 strerror(-ret));
2113 return ret;
2114 }
2115 }
2116
2117 ret = kvm_get_supported_msrs(s);
2118 if (ret < 0) {
2119 return ret;
2120 }
2121
2122 kvm_get_supported_feature_msrs(s);
2123
2124 uname(&utsname);
2125 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2126
2127 /*
2128 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2129 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2130 * Since these must be part of guest physical memory, we need to allocate
2131 * them, both by setting their start addresses in the kernel and by
2132 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2133 *
2134 * Older KVM versions may not support setting the identity map base. In
2135 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2136 * size.
2137 */
2138 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2139 /* Allows up to 16M BIOSes. */
2140 identity_base = 0xfeffc000;
2141
2142 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2143 if (ret < 0) {
2144 return ret;
2145 }
2146 }
2147
2148 /* Set TSS base one page after EPT identity map. */
2149 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2150 if (ret < 0) {
2151 return ret;
2152 }
2153
2154 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2155 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2156 if (ret < 0) {
2157 fprintf(stderr, "e820_add_entry() table is full\n");
2158 return ret;
2159 }
2160 qemu_register_reset(kvm_unpoison_all, NULL);
2161
2162 shadow_mem = machine_kvm_shadow_mem(ms);
2163 if (shadow_mem != -1) {
2164 shadow_mem /= 4096;
2165 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2166 if (ret < 0) {
2167 return ret;
2168 }
2169 }
2170
2171 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2172 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
2173 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
2174 smram_machine_done.notify = register_smram_listener;
2175 qemu_add_machine_init_done_notifier(&smram_machine_done);
2176 }
2177
2178 if (enable_cpu_pm) {
2179 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2180 int ret;
2181
2182 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2183 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2184 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2185 #endif
2186 if (disable_exits) {
2187 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2188 KVM_X86_DISABLE_EXITS_HLT |
2189 KVM_X86_DISABLE_EXITS_PAUSE |
2190 KVM_X86_DISABLE_EXITS_CSTATE);
2191 }
2192
2193 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2194 disable_exits);
2195 if (ret < 0) {
2196 error_report("kvm: guest stopping CPU not supported: %s",
2197 strerror(-ret));
2198 }
2199 }
2200
2201 return 0;
2202 }
2203
2204 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2205 {
2206 lhs->selector = rhs->selector;
2207 lhs->base = rhs->base;
2208 lhs->limit = rhs->limit;
2209 lhs->type = 3;
2210 lhs->present = 1;
2211 lhs->dpl = 3;
2212 lhs->db = 0;
2213 lhs->s = 1;
2214 lhs->l = 0;
2215 lhs->g = 0;
2216 lhs->avl = 0;
2217 lhs->unusable = 0;
2218 }
2219
2220 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2221 {
2222 unsigned flags = rhs->flags;
2223 lhs->selector = rhs->selector;
2224 lhs->base = rhs->base;
2225 lhs->limit = rhs->limit;
2226 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2227 lhs->present = (flags & DESC_P_MASK) != 0;
2228 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2229 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2230 lhs->s = (flags & DESC_S_MASK) != 0;
2231 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2232 lhs->g = (flags & DESC_G_MASK) != 0;
2233 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2234 lhs->unusable = !lhs->present;
2235 lhs->padding = 0;
2236 }
2237
2238 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2239 {
2240 lhs->selector = rhs->selector;
2241 lhs->base = rhs->base;
2242 lhs->limit = rhs->limit;
2243 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2244 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2245 (rhs->dpl << DESC_DPL_SHIFT) |
2246 (rhs->db << DESC_B_SHIFT) |
2247 (rhs->s * DESC_S_MASK) |
2248 (rhs->l << DESC_L_SHIFT) |
2249 (rhs->g * DESC_G_MASK) |
2250 (rhs->avl * DESC_AVL_MASK);
2251 }
2252
2253 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2254 {
2255 if (set) {
2256 *kvm_reg = *qemu_reg;
2257 } else {
2258 *qemu_reg = *kvm_reg;
2259 }
2260 }
2261
2262 static int kvm_getput_regs(X86CPU *cpu, int set)
2263 {
2264 CPUX86State *env = &cpu->env;
2265 struct kvm_regs regs;
2266 int ret = 0;
2267
2268 if (!set) {
2269 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2270 if (ret < 0) {
2271 return ret;
2272 }
2273 }
2274
2275 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2276 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2277 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2278 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2279 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2280 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2281 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2282 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2283 #ifdef TARGET_X86_64
2284 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2285 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2286 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2287 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2288 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2289 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2290 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2291 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2292 #endif
2293
2294 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2295 kvm_getput_reg(&regs.rip, &env->eip, set);
2296
2297 if (set) {
2298 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2299 }
2300
2301 return ret;
2302 }
2303
2304 static int kvm_put_fpu(X86CPU *cpu)
2305 {
2306 CPUX86State *env = &cpu->env;
2307 struct kvm_fpu fpu;
2308 int i;
2309
2310 memset(&fpu, 0, sizeof fpu);
2311 fpu.fsw = env->fpus & ~(7 << 11);
2312 fpu.fsw |= (env->fpstt & 7) << 11;
2313 fpu.fcw = env->fpuc;
2314 fpu.last_opcode = env->fpop;
2315 fpu.last_ip = env->fpip;
2316 fpu.last_dp = env->fpdp;
2317 for (i = 0; i < 8; ++i) {
2318 fpu.ftwx |= (!env->fptags[i]) << i;
2319 }
2320 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
2321 for (i = 0; i < CPU_NB_REGS; i++) {
2322 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2323 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
2324 }
2325 fpu.mxcsr = env->mxcsr;
2326
2327 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
2328 }
2329
2330 #define XSAVE_FCW_FSW 0
2331 #define XSAVE_FTW_FOP 1
2332 #define XSAVE_CWD_RIP 2
2333 #define XSAVE_CWD_RDP 4
2334 #define XSAVE_MXCSR 6
2335 #define XSAVE_ST_SPACE 8
2336 #define XSAVE_XMM_SPACE 40
2337 #define XSAVE_XSTATE_BV 128
2338 #define XSAVE_YMMH_SPACE 144
2339 #define XSAVE_BNDREGS 240
2340 #define XSAVE_BNDCSR 256
2341 #define XSAVE_OPMASK 272
2342 #define XSAVE_ZMM_Hi256 288
2343 #define XSAVE_Hi16_ZMM 416
2344 #define XSAVE_PKRU 672
2345
2346 #define XSAVE_BYTE_OFFSET(word_offset) \
2347 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2348
2349 #define ASSERT_OFFSET(word_offset, field) \
2350 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2351 offsetof(X86XSaveArea, field))
2352
2353 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2354 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2355 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2356 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2357 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2358 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2359 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2360 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2361 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2362 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2363 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2364 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2365 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2366 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2367 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2368
2369 static int kvm_put_xsave(X86CPU *cpu)
2370 {
2371 CPUX86State *env = &cpu->env;
2372 X86XSaveArea *xsave = env->xsave_buf;
2373
2374 if (!has_xsave) {
2375 return kvm_put_fpu(cpu);
2376 }
2377 x86_cpu_xsave_all_areas(cpu, xsave);
2378
2379 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2380 }
2381
2382 static int kvm_put_xcrs(X86CPU *cpu)
2383 {
2384 CPUX86State *env = &cpu->env;
2385 struct kvm_xcrs xcrs = {};
2386
2387 if (!has_xcrs) {
2388 return 0;
2389 }
2390
2391 xcrs.nr_xcrs = 1;
2392 xcrs.flags = 0;
2393 xcrs.xcrs[0].xcr = 0;
2394 xcrs.xcrs[0].value = env->xcr0;
2395 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2396 }
2397
2398 static int kvm_put_sregs(X86CPU *cpu)
2399 {
2400 CPUX86State *env = &cpu->env;
2401 struct kvm_sregs sregs;
2402
2403 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2404 if (env->interrupt_injected >= 0) {
2405 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2406 (uint64_t)1 << (env->interrupt_injected % 64);
2407 }
2408
2409 if ((env->eflags & VM_MASK)) {
2410 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2411 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2412 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2413 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2414 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2415 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2416 } else {
2417 set_seg(&sregs.cs, &env->segs[R_CS]);
2418 set_seg(&sregs.ds, &env->segs[R_DS]);
2419 set_seg(&sregs.es, &env->segs[R_ES]);
2420 set_seg(&sregs.fs, &env->segs[R_FS]);
2421 set_seg(&sregs.gs, &env->segs[R_GS]);
2422 set_seg(&sregs.ss, &env->segs[R_SS]);
2423 }
2424
2425 set_seg(&sregs.tr, &env->tr);
2426 set_seg(&sregs.ldt, &env->ldt);
2427
2428 sregs.idt.limit = env->idt.limit;
2429 sregs.idt.base = env->idt.base;
2430 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2431 sregs.gdt.limit = env->gdt.limit;
2432 sregs.gdt.base = env->gdt.base;
2433 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2434
2435 sregs.cr0 = env->cr[0];
2436 sregs.cr2 = env->cr[2];
2437 sregs.cr3 = env->cr[3];
2438 sregs.cr4 = env->cr[4];
2439
2440 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2441 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2442
2443 sregs.efer = env->efer;
2444
2445 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2446 }
2447
2448 static void kvm_msr_buf_reset(X86CPU *cpu)
2449 {
2450 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2451 }
2452
2453 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2454 {
2455 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2456 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2457 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2458
2459 assert((void *)(entry + 1) <= limit);
2460
2461 entry->index = index;
2462 entry->reserved = 0;
2463 entry->data = value;
2464 msrs->nmsrs++;
2465 }
2466
2467 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2468 {
2469 kvm_msr_buf_reset(cpu);
2470 kvm_msr_entry_add(cpu, index, value);
2471
2472 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2473 }
2474
2475 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2476 {
2477 int ret;
2478
2479 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2480 assert(ret == 1);
2481 }
2482
2483 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2484 {
2485 CPUX86State *env = &cpu->env;
2486 int ret;
2487
2488 if (!has_msr_tsc_deadline) {
2489 return 0;
2490 }
2491
2492 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
2493 if (ret < 0) {
2494 return ret;
2495 }
2496
2497 assert(ret == 1);
2498 return 0;
2499 }
2500
2501 /*
2502 * Provide a separate write service for the feature control MSR in order to
2503 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2504 * before writing any other state because forcibly leaving nested mode
2505 * invalidates the VCPU state.
2506 */
2507 static int kvm_put_msr_feature_control(X86CPU *cpu)
2508 {
2509 int ret;
2510
2511 if (!has_msr_feature_control) {
2512 return 0;
2513 }
2514
2515 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2516 cpu->env.msr_ia32_feature_control);
2517 if (ret < 0) {
2518 return ret;
2519 }
2520
2521 assert(ret == 1);
2522 return 0;
2523 }
2524
2525 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2526 {
2527 uint32_t default1, can_be_one, can_be_zero;
2528 uint32_t must_be_one;
2529
2530 switch (index) {
2531 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2532 default1 = 0x00000016;
2533 break;
2534 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2535 default1 = 0x0401e172;
2536 break;
2537 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2538 default1 = 0x000011ff;
2539 break;
2540 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2541 default1 = 0x00036dff;
2542 break;
2543 case MSR_IA32_VMX_PROCBASED_CTLS2:
2544 default1 = 0;
2545 break;
2546 default:
2547 abort();
2548 }
2549
2550 /* If a feature bit is set, the control can be either set or clear.
2551 * Otherwise the value is limited to either 0 or 1 by default1.
2552 */
2553 can_be_one = features | default1;
2554 can_be_zero = features | ~default1;
2555 must_be_one = ~can_be_zero;
2556
2557 /*
2558 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2559 * Bit 32:63 -> 1 if the control bit can be one.
2560 */
2561 return must_be_one | (((uint64_t)can_be_one) << 32);
2562 }
2563
2564 #define VMCS12_MAX_FIELD_INDEX (0x17)
2565
2566 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2567 {
2568 uint64_t kvm_vmx_basic =
2569 kvm_arch_get_supported_msr_feature(kvm_state,
2570 MSR_IA32_VMX_BASIC);
2571 uint64_t kvm_vmx_misc =
2572 kvm_arch_get_supported_msr_feature(kvm_state,
2573 MSR_IA32_VMX_MISC);
2574 uint64_t kvm_vmx_ept_vpid =
2575 kvm_arch_get_supported_msr_feature(kvm_state,
2576 MSR_IA32_VMX_EPT_VPID_CAP);
2577
2578 /*
2579 * If the guest is 64-bit, a value of 1 is allowed for the host address
2580 * space size vmexit control.
2581 */
2582 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2583 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2584
2585 /*
2586 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2587 * not change them for backwards compatibility.
2588 */
2589 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2590 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2591 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2592 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2593
2594 /*
2595 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2596 * change in the future but are always zero for now, clear them to be
2597 * future proof. Bits 32-63 in theory could change, though KVM does
2598 * not support dual-monitor treatment and probably never will; mask
2599 * them out as well.
2600 */
2601 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2602 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2603 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2604
2605 /*
2606 * EPT memory types should not change either, so we do not bother
2607 * adding features for them.
2608 */
2609 uint64_t fixed_vmx_ept_mask =
2610 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2611 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2612 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2613
2614 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2615 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2616 f[FEAT_VMX_PROCBASED_CTLS]));
2617 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2618 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2619 f[FEAT_VMX_PINBASED_CTLS]));
2620 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2621 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2622 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2623 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2624 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2625 f[FEAT_VMX_ENTRY_CTLS]));
2626 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2627 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2628 f[FEAT_VMX_SECONDARY_CTLS]));
2629 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2630 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2631 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2632 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2633 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2634 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2635 if (has_msr_vmx_vmfunc) {
2636 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2637 }
2638
2639 /*
2640 * Just to be safe, write these with constant values. The CRn_FIXED1
2641 * MSRs are generated by KVM based on the vCPU's CPUID.
2642 */
2643 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2644 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2645 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2646 CR4_VMXE_MASK);
2647 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM,
2648 VMCS12_MAX_FIELD_INDEX << 1);
2649 }
2650
2651 static int kvm_put_msrs(X86CPU *cpu, int level)
2652 {
2653 CPUX86State *env = &cpu->env;
2654 int i;
2655 int ret;
2656
2657 kvm_msr_buf_reset(cpu);
2658
2659 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2660 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2661 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2662 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
2663 if (has_msr_star) {
2664 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
2665 }
2666 if (has_msr_hsave_pa) {
2667 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
2668 }
2669 if (has_msr_tsc_aux) {
2670 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
2671 }
2672 if (has_msr_tsc_adjust) {
2673 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
2674 }
2675 if (has_msr_misc_enable) {
2676 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2677 env->msr_ia32_misc_enable);
2678 }
2679 if (has_msr_smbase) {
2680 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2681 }
2682 if (has_msr_smi_count) {
2683 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2684 }
2685 if (has_msr_bndcfgs) {
2686 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2687 }
2688 if (has_msr_xss) {
2689 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2690 }
2691 if (has_msr_umwait) {
2692 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2693 }
2694 if (has_msr_spec_ctrl) {
2695 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2696 }
2697 if (has_msr_virt_ssbd) {
2698 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2699 }
2700
2701 #ifdef TARGET_X86_64
2702 if (lm_capable_kernel) {
2703 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2704 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2705 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2706 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2707 }
2708 #endif
2709
2710 /* If host supports feature MSR, write down. */
2711 if (has_msr_arch_capabs) {
2712 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2713 env->features[FEAT_ARCH_CAPABILITIES]);
2714 }
2715
2716 if (has_msr_core_capabs) {
2717 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2718 env->features[FEAT_CORE_CAPABILITY]);
2719 }
2720
2721 /*
2722 * The following MSRs have side effects on the guest or are too heavy
2723 * for normal writeback. Limit them to reset or full state updates.
2724 */
2725 if (level >= KVM_PUT_RESET_STATE) {
2726 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2727 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2728 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2729 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2730 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2731 }
2732 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2733 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2734 }
2735 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2736 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2737 }
2738
2739 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2740 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2741 }
2742
2743 if (has_architectural_pmu_version > 0) {
2744 if (has_architectural_pmu_version > 1) {
2745 /* Stop the counter. */
2746 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2747 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2748 }
2749
2750 /* Set the counter values. */
2751 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2752 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2753 env->msr_fixed_counters[i]);
2754 }
2755 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2756 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2757 env->msr_gp_counters[i]);
2758 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2759 env->msr_gp_evtsel[i]);
2760 }
2761 if (has_architectural_pmu_version > 1) {
2762 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2763 env->msr_global_status);
2764 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2765 env->msr_global_ovf_ctrl);
2766
2767 /* Now start the PMU. */
2768 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2769 env->msr_fixed_ctr_ctrl);
2770 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2771 env->msr_global_ctrl);
2772 }
2773 }
2774 /*
2775 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2776 * only sync them to KVM on the first cpu
2777 */
2778 if (current_cpu == first_cpu) {
2779 if (has_msr_hv_hypercall) {
2780 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2781 env->msr_hv_guest_os_id);
2782 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2783 env->msr_hv_hypercall);
2784 }
2785 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2786 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2787 env->msr_hv_tsc);
2788 }
2789 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2790 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2791 env->msr_hv_reenlightenment_control);
2792 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2793 env->msr_hv_tsc_emulation_control);
2794 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2795 env->msr_hv_tsc_emulation_status);
2796 }
2797 }
2798 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2799 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2800 env->msr_hv_vapic);
2801 }
2802 if (has_msr_hv_crash) {
2803 int j;
2804
2805 for (j = 0; j < HV_CRASH_PARAMS; j++)
2806 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2807 env->msr_hv_crash_params[j]);
2808
2809 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2810 }
2811 if (has_msr_hv_runtime) {
2812 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2813 }
2814 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2815 && hv_vpindex_settable) {
2816 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2817 hyperv_vp_index(CPU(cpu)));
2818 }
2819 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2820 int j;
2821
2822 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2823
2824 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2825 env->msr_hv_synic_control);
2826 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2827 env->msr_hv_synic_evt_page);
2828 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2829 env->msr_hv_synic_msg_page);
2830
2831 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2832 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2833 env->msr_hv_synic_sint[j]);
2834 }
2835 }
2836 if (has_msr_hv_stimer) {
2837 int j;
2838
2839 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2840 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2841 env->msr_hv_stimer_config[j]);
2842 }
2843
2844 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2845 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2846 env->msr_hv_stimer_count[j]);
2847 }
2848 }
2849 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2850 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2851
2852 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2853 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2854 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2855 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2856 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2857 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2858 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2859 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2860 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2861 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2862 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2863 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2864 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2865 /* The CPU GPs if we write to a bit above the physical limit of
2866 * the host CPU (and KVM emulates that)
2867 */
2868 uint64_t mask = env->mtrr_var[i].mask;
2869 mask &= phys_mask;
2870
2871 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2872 env->mtrr_var[i].base);
2873 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2874 }
2875 }
2876 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2877 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2878 0x14, 1, R_EAX) & 0x7;
2879
2880 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2881 env->msr_rtit_ctrl);
2882 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2883 env->msr_rtit_status);
2884 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2885 env->msr_rtit_output_base);
2886 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2887 env->msr_rtit_output_mask);
2888 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2889 env->msr_rtit_cr3_match);
2890 for (i = 0; i < addr_num; i++) {
2891 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2892 env->msr_rtit_addrs[i]);
2893 }
2894 }
2895
2896 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2897 * kvm_put_msr_feature_control. */
2898
2899 /*
2900 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2901 * all kernels with MSR features should have them.
2902 */
2903 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2904 kvm_msr_entry_add_vmx(cpu, env->features);
2905 }
2906 }
2907
2908 if (env->mcg_cap) {
2909 int i;
2910
2911 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2912 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2913 if (has_msr_mcg_ext_ctl) {
2914 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2915 }
2916 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2917 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2918 }
2919 }
2920
2921 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2922 if (ret < 0) {
2923 return ret;
2924 }
2925
2926 if (ret < cpu->kvm_msr_buf->nmsrs) {
2927 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2928 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2929 (uint32_t)e->index, (uint64_t)e->data);
2930 }
2931
2932 assert(ret == cpu->kvm_msr_buf->nmsrs);
2933 return 0;
2934 }
2935
2936
2937 static int kvm_get_fpu(X86CPU *cpu)
2938 {
2939 CPUX86State *env = &cpu->env;
2940 struct kvm_fpu fpu;
2941 int i, ret;
2942
2943 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2944 if (ret < 0) {
2945 return ret;
2946 }
2947
2948 env->fpstt = (fpu.fsw >> 11) & 7;
2949 env->fpus = fpu.fsw;
2950 env->fpuc = fpu.fcw;
2951 env->fpop = fpu.last_opcode;
2952 env->fpip = fpu.last_ip;
2953 env->fpdp = fpu.last_dp;
2954 for (i = 0; i < 8; ++i) {
2955 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2956 }
2957 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2958 for (i = 0; i < CPU_NB_REGS; i++) {
2959 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2960 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2961 }
2962 env->mxcsr = fpu.mxcsr;
2963
2964 return 0;
2965 }
2966
2967 static int kvm_get_xsave(X86CPU *cpu)
2968 {
2969 CPUX86State *env = &cpu->env;
2970 X86XSaveArea *xsave = env->xsave_buf;
2971 int ret;
2972
2973 if (!has_xsave) {
2974 return kvm_get_fpu(cpu);
2975 }
2976
2977 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2978 if (ret < 0) {
2979 return ret;
2980 }
2981 x86_cpu_xrstor_all_areas(cpu, xsave);
2982
2983 return 0;
2984 }
2985
2986 static int kvm_get_xcrs(X86CPU *cpu)
2987 {
2988 CPUX86State *env = &cpu->env;
2989 int i, ret;
2990 struct kvm_xcrs xcrs;
2991
2992 if (!has_xcrs) {
2993 return 0;
2994 }
2995
2996 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2997 if (ret < 0) {
2998 return ret;
2999 }
3000
3001 for (i = 0; i < xcrs.nr_xcrs; i++) {
3002 /* Only support xcr0 now */
3003 if (xcrs.xcrs[i].xcr == 0) {
3004 env->xcr0 = xcrs.xcrs[i].value;
3005 break;
3006 }
3007 }
3008 return 0;
3009 }
3010
3011 static int kvm_get_sregs(X86CPU *cpu)
3012 {
3013 CPUX86State *env = &cpu->env;
3014 struct kvm_sregs sregs;
3015 int bit, i, ret;
3016
3017 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
3018 if (ret < 0) {
3019 return ret;
3020 }
3021
3022 /* There can only be one pending IRQ set in the bitmap at a time, so try
3023 to find it and save its number instead (-1 for none). */
3024 env->interrupt_injected = -1;
3025 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3026 if (sregs.interrupt_bitmap[i]) {
3027 bit = ctz64(sregs.interrupt_bitmap[i]);
3028 env->interrupt_injected = i * 64 + bit;
3029 break;
3030 }
3031 }
3032
3033 get_seg(&env->segs[R_CS], &sregs.cs);
3034 get_seg(&env->segs[R_DS], &sregs.ds);
3035 get_seg(&env->segs[R_ES], &sregs.es);
3036 get_seg(&env->segs[R_FS], &sregs.fs);
3037 get_seg(&env->segs[R_GS], &sregs.gs);
3038 get_seg(&env->segs[R_SS], &sregs.ss);
3039
3040 get_seg(&env->tr, &sregs.tr);
3041 get_seg(&env->ldt, &sregs.ldt);
3042
3043 env->idt.limit = sregs.idt.limit;
3044 env->idt.base = sregs.idt.base;
3045 env->gdt.limit = sregs.gdt.limit;
3046 env->gdt.base = sregs.gdt.base;
3047
3048 env->cr[0] = sregs.cr0;
3049 env->cr[2] = sregs.cr2;
3050 env->cr[3] = sregs.cr3;
3051 env->cr[4] = sregs.cr4;
3052
3053 env->efer = sregs.efer;
3054
3055 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3056 x86_update_hflags(env);
3057
3058 return 0;
3059 }
3060
3061 static int kvm_get_msrs(X86CPU *cpu)
3062 {
3063 CPUX86State *env = &cpu->env;
3064 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
3065 int ret, i;
3066 uint64_t mtrr_top_bits;
3067
3068 kvm_msr_buf_reset(cpu);
3069
3070 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3071 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3072 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3073 kvm_msr_entry_add(cpu, MSR_PAT, 0);
3074 if (has_msr_star) {
3075 kvm_msr_entry_add(cpu, MSR_STAR, 0);
3076 }
3077 if (has_msr_hsave_pa) {
3078 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
3079 }
3080 if (has_msr_tsc_aux) {
3081 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
3082 }
3083 if (has_msr_tsc_adjust) {
3084 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
3085 }
3086 if (has_msr_tsc_deadline) {
3087 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
3088 }
3089 if (has_msr_misc_enable) {
3090 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
3091 }
3092 if (has_msr_smbase) {
3093 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
3094 }
3095 if (has_msr_smi_count) {
3096 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3097 }
3098 if (has_msr_feature_control) {
3099 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
3100 }
3101 if (has_msr_bndcfgs) {
3102 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
3103 }
3104 if (has_msr_xss) {
3105 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
3106 }
3107 if (has_msr_umwait) {
3108 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3109 }
3110 if (has_msr_spec_ctrl) {
3111 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3112 }
3113 if (has_msr_virt_ssbd) {
3114 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3115 }
3116 if (!env->tsc_valid) {
3117 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
3118 env->tsc_valid = !runstate_is_running();
3119 }
3120
3121 #ifdef TARGET_X86_64
3122 if (lm_capable_kernel) {
3123 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3124 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3125 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3126 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
3127 }
3128 #endif
3129 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3130 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
3131 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3132 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3133 }
3134 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3135 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
3136 }
3137 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3138 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
3139 }
3140 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3141 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3142 }
3143 if (has_architectural_pmu_version > 0) {
3144 if (has_architectural_pmu_version > 1) {
3145 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3146 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3147 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3148 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3149 }
3150 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
3151 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
3152 }
3153 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
3154 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3155 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
3156 }
3157 }
3158
3159 if (env->mcg_cap) {
3160 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3161 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
3162 if (has_msr_mcg_ext_ctl) {
3163 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3164 }
3165 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3166 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
3167 }
3168 }
3169
3170 if (has_msr_hv_hypercall) {
3171 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3172 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
3173 }
3174 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
3175 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
3176 }
3177 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
3178 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
3179 }
3180 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
3181 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3182 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3183 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3184 }
3185 if (has_msr_hv_crash) {
3186 int j;
3187
3188 for (j = 0; j < HV_CRASH_PARAMS; j++) {
3189 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
3190 }
3191 }
3192 if (has_msr_hv_runtime) {
3193 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
3194 }
3195 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
3196 uint32_t msr;
3197
3198 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
3199 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3200 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
3201 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
3202 kvm_msr_entry_add(cpu, msr, 0);
3203 }
3204 }
3205 if (has_msr_hv_stimer) {
3206 uint32_t msr;
3207
3208 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3209 msr++) {
3210 kvm_msr_entry_add(cpu, msr, 0);
3211 }
3212 }
3213 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3214 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3215 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3216 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3217 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3218 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3219 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3220 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3221 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3222 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3223 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3224 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3225 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
3226 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3227 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3228 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
3229 }
3230 }
3231
3232 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3233 int addr_num =
3234 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3235
3236 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3237 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3238 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3239 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3240 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3241 for (i = 0; i < addr_num; i++) {
3242 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3243 }
3244 }
3245
3246 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
3247 if (ret < 0) {
3248 return ret;
3249 }
3250
3251 if (ret < cpu->kvm_msr_buf->nmsrs) {
3252 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3253 error_report("error: failed to get MSR 0x%" PRIx32,
3254 (uint32_t)e->index);
3255 }
3256
3257 assert(ret == cpu->kvm_msr_buf->nmsrs);
3258 /*
3259 * MTRR masks: Each mask consists of 5 parts
3260 * a 10..0: must be zero
3261 * b 11 : valid bit
3262 * c n-1.12: actual mask bits
3263 * d 51..n: reserved must be zero
3264 * e 63.52: reserved must be zero
3265 *
3266 * 'n' is the number of physical bits supported by the CPU and is
3267 * apparently always <= 52. We know our 'n' but don't know what
3268 * the destinations 'n' is; it might be smaller, in which case
3269 * it masks (c) on loading. It might be larger, in which case
3270 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3271 * we're migrating to.
3272 */
3273
3274 if (cpu->fill_mtrr_mask) {
3275 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3276 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3277 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3278 } else {
3279 mtrr_top_bits = 0;
3280 }
3281
3282 for (i = 0; i < ret; i++) {
3283 uint32_t index = msrs[i].index;
3284 switch (index) {
3285 case MSR_IA32_SYSENTER_CS:
3286 env->sysenter_cs = msrs[i].data;
3287 break;
3288 case MSR_IA32_SYSENTER_ESP:
3289 env->sysenter_esp = msrs[i].data;
3290 break;
3291 case MSR_IA32_SYSENTER_EIP:
3292 env->sysenter_eip = msrs[i].data;
3293 break;
3294 case MSR_PAT:
3295 env->pat = msrs[i].data;
3296 break;
3297 case MSR_STAR:
3298 env->star = msrs[i].data;
3299 break;
3300 #ifdef TARGET_X86_64
3301 case MSR_CSTAR:
3302 env->cstar = msrs[i].data;
3303 break;
3304 case MSR_KERNELGSBASE:
3305 env->kernelgsbase = msrs[i].data;
3306 break;
3307 case MSR_FMASK:
3308 env->fmask = msrs[i].data;
3309 break;
3310 case MSR_LSTAR:
3311 env->lstar = msrs[i].data;
3312 break;
3313 #endif
3314 case MSR_IA32_TSC:
3315 env->tsc = msrs[i].data;
3316 break;
3317 case MSR_TSC_AUX:
3318 env->tsc_aux = msrs[i].data;
3319 break;
3320 case MSR_TSC_ADJUST:
3321 env->tsc_adjust = msrs[i].data;
3322 break;
3323 case MSR_IA32_TSCDEADLINE:
3324 env->tsc_deadline = msrs[i].data;
3325 break;
3326 case MSR_VM_HSAVE_PA:
3327 env->vm_hsave = msrs[i].data;
3328 break;
3329 case MSR_KVM_SYSTEM_TIME:
3330 env->system_time_msr = msrs[i].data;
3331 break;
3332 case MSR_KVM_WALL_CLOCK:
3333 env->wall_clock_msr = msrs[i].data;
3334 break;
3335 case MSR_MCG_STATUS:
3336 env->mcg_status = msrs[i].data;
3337 break;
3338 case MSR_MCG_CTL:
3339 env->mcg_ctl = msrs[i].data;
3340 break;
3341 case MSR_MCG_EXT_CTL:
3342 env->mcg_ext_ctl = msrs[i].data;
3343 break;
3344 case MSR_IA32_MISC_ENABLE:
3345 env->msr_ia32_misc_enable = msrs[i].data;
3346 break;
3347 case MSR_IA32_SMBASE:
3348 env->smbase = msrs[i].data;
3349 break;
3350 case MSR_SMI_COUNT:
3351 env->msr_smi_count = msrs[i].data;
3352 break;
3353 case MSR_IA32_FEATURE_CONTROL:
3354 env->msr_ia32_feature_control = msrs[i].data;
3355 break;
3356 case MSR_IA32_BNDCFGS:
3357 env->msr_bndcfgs = msrs[i].data;
3358 break;
3359 case MSR_IA32_XSS:
3360 env->xss = msrs[i].data;
3361 break;
3362 case MSR_IA32_UMWAIT_CONTROL:
3363 env->umwait = msrs[i].data;
3364 break;
3365 default:
3366 if (msrs[i].index >= MSR_MC0_CTL &&
3367 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3368 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
3369 }
3370 break;
3371 case MSR_KVM_ASYNC_PF_EN:
3372 env->async_pf_en_msr = msrs[i].data;
3373 break;
3374 case MSR_KVM_PV_EOI_EN:
3375 env->pv_eoi_en_msr = msrs[i].data;
3376 break;
3377 case MSR_KVM_STEAL_TIME:
3378 env->steal_time_msr = msrs[i].data;
3379 break;
3380 case MSR_KVM_POLL_CONTROL: {
3381 env->poll_control_msr = msrs[i].data;
3382 break;
3383 }
3384 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3385 env->msr_fixed_ctr_ctrl = msrs[i].data;
3386 break;
3387 case MSR_CORE_PERF_GLOBAL_CTRL:
3388 env->msr_global_ctrl = msrs[i].data;
3389 break;
3390 case MSR_CORE_PERF_GLOBAL_STATUS:
3391 env->msr_global_status = msrs[i].data;
3392 break;
3393 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3394 env->msr_global_ovf_ctrl = msrs[i].data;
3395 break;
3396 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3397 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3398 break;
3399 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3400 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3401 break;
3402 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3403 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3404 break;
3405 case HV_X64_MSR_HYPERCALL:
3406 env->msr_hv_hypercall = msrs[i].data;
3407 break;
3408 case HV_X64_MSR_GUEST_OS_ID:
3409 env->msr_hv_guest_os_id = msrs[i].data;
3410 break;
3411 case HV_X64_MSR_APIC_ASSIST_PAGE:
3412 env->msr_hv_vapic = msrs[i].data;
3413 break;
3414 case HV_X64_MSR_REFERENCE_TSC:
3415 env->msr_hv_tsc = msrs[i].data;
3416 break;
3417 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3418 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3419 break;
3420 case HV_X64_MSR_VP_RUNTIME:
3421 env->msr_hv_runtime = msrs[i].data;
3422 break;
3423 case HV_X64_MSR_SCONTROL:
3424 env->msr_hv_synic_control = msrs[i].data;
3425 break;
3426 case HV_X64_MSR_SIEFP:
3427 env->msr_hv_synic_evt_page = msrs[i].data;
3428 break;
3429 case HV_X64_MSR_SIMP:
3430 env->msr_hv_synic_msg_page = msrs[i].data;
3431 break;
3432 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3433 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
3434 break;
3435 case HV_X64_MSR_STIMER0_CONFIG:
3436 case HV_X64_MSR_STIMER1_CONFIG:
3437 case HV_X64_MSR_STIMER2_CONFIG:
3438 case HV_X64_MSR_STIMER3_CONFIG:
3439 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3440 msrs[i].data;
3441 break;
3442 case HV_X64_MSR_STIMER0_COUNT:
3443 case HV_X64_MSR_STIMER1_COUNT:
3444 case HV_X64_MSR_STIMER2_COUNT:
3445 case HV_X64_MSR_STIMER3_COUNT:
3446 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3447 msrs[i].data;
3448 break;
3449 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3450 env->msr_hv_reenlightenment_control = msrs[i].data;
3451 break;
3452 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3453 env->msr_hv_tsc_emulation_control = msrs[i].data;
3454 break;
3455 case HV_X64_MSR_TSC_EMULATION_STATUS:
3456 env->msr_hv_tsc_emulation_status = msrs[i].data;
3457 break;
3458 case MSR_MTRRdefType:
3459 env->mtrr_deftype = msrs[i].data;
3460 break;
3461 case MSR_MTRRfix64K_00000:
3462 env->mtrr_fixed[0] = msrs[i].data;
3463 break;
3464 case MSR_MTRRfix16K_80000:
3465 env->mtrr_fixed[1] = msrs[i].data;
3466 break;
3467 case MSR_MTRRfix16K_A0000:
3468 env->mtrr_fixed[2] = msrs[i].data;
3469 break;
3470 case MSR_MTRRfix4K_C0000:
3471 env->mtrr_fixed[3] = msrs[i].data;
3472 break;
3473 case MSR_MTRRfix4K_C8000:
3474 env->mtrr_fixed[4] = msrs[i].data;
3475 break;
3476 case MSR_MTRRfix4K_D0000:
3477 env->mtrr_fixed[5] = msrs[i].data;
3478 break;
3479 case MSR_MTRRfix4K_D8000:
3480 env->mtrr_fixed[6] = msrs[i].data;
3481 break;
3482 case MSR_MTRRfix4K_E0000:
3483 env->mtrr_fixed[7] = msrs[i].data;
3484 break;
3485 case MSR_MTRRfix4K_E8000:
3486 env->mtrr_fixed[8] = msrs[i].data;
3487 break;
3488 case MSR_MTRRfix4K_F0000:
3489 env->mtrr_fixed[9] = msrs[i].data;
3490 break;
3491 case MSR_MTRRfix4K_F8000:
3492 env->mtrr_fixed[10] = msrs[i].data;
3493 break;
3494 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3495 if (index & 1) {
3496 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3497 mtrr_top_bits;
3498 } else {
3499 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3500 }
3501 break;
3502 case MSR_IA32_SPEC_CTRL:
3503 env->spec_ctrl = msrs[i].data;
3504 break;
3505 case MSR_VIRT_SSBD:
3506 env->virt_ssbd = msrs[i].data;
3507 break;
3508 case MSR_IA32_RTIT_CTL:
3509 env->msr_rtit_ctrl = msrs[i].data;
3510 break;
3511 case MSR_IA32_RTIT_STATUS:
3512 env->msr_rtit_status = msrs[i].data;
3513 break;
3514 case MSR_IA32_RTIT_OUTPUT_BASE:
3515 env->msr_rtit_output_base = msrs[i].data;
3516 break;
3517 case MSR_IA32_RTIT_OUTPUT_MASK:
3518 env->msr_rtit_output_mask = msrs[i].data;
3519 break;
3520 case MSR_IA32_RTIT_CR3_MATCH:
3521 env->msr_rtit_cr3_match = msrs[i].data;
3522 break;
3523 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3524 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3525 break;
3526 }
3527 }
3528
3529 return 0;
3530 }
3531
3532 static int kvm_put_mp_state(X86CPU *cpu)
3533 {
3534 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
3535
3536 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
3537 }
3538
3539 static int kvm_get_mp_state(X86CPU *cpu)
3540 {
3541 CPUState *cs = CPU(cpu);
3542 CPUX86State *env = &cpu->env;
3543 struct kvm_mp_state mp_state;
3544 int ret;
3545
3546 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
3547 if (ret < 0) {
3548 return ret;
3549 }
3550 env->mp_state = mp_state.mp_state;
3551 if (kvm_irqchip_in_kernel()) {
3552 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
3553 }
3554 return 0;
3555 }
3556
3557 static int kvm_get_apic(X86CPU *cpu)
3558 {
3559 DeviceState *apic = cpu->apic_state;
3560 struct kvm_lapic_state kapic;
3561 int ret;
3562
3563 if (apic && kvm_irqchip_in_kernel()) {
3564 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
3565 if (ret < 0) {
3566 return ret;
3567 }
3568
3569 kvm_get_apic_state(apic, &kapic);
3570 }
3571 return 0;
3572 }
3573
3574 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
3575 {
3576 CPUState *cs = CPU(cpu);
3577 CPUX86State *env = &cpu->env;
3578 struct kvm_vcpu_events events = {};
3579
3580 if (!kvm_has_vcpu_events()) {
3581 return 0;
3582 }
3583
3584 events.flags = 0;
3585
3586 if (has_exception_payload) {
3587 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3588 events.exception.pending = env->exception_pending;
3589 events.exception_has_payload = env->exception_has_payload;
3590 events.exception_payload = env->exception_payload;
3591 }
3592 events.exception.nr = env->exception_nr;
3593 events.exception.injected = env->exception_injected;
3594 events.exception.has_error_code = env->has_error_code;
3595 events.exception.error_code = env->error_code;
3596
3597 events.interrupt.injected = (env->interrupt_injected >= 0);
3598 events.interrupt.nr = env->interrupt_injected;
3599 events.interrupt.soft = env->soft_interrupt;
3600
3601 events.nmi.injected = env->nmi_injected;
3602 events.nmi.pending = env->nmi_pending;
3603 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3604
3605 events.sipi_vector = env->sipi_vector;
3606
3607 if (has_msr_smbase) {
3608 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3609 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3610 if (kvm_irqchip_in_kernel()) {
3611 /* As soon as these are moved to the kernel, remove them
3612 * from cs->interrupt_request.
3613 */
3614 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3615 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3616 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3617 } else {
3618 /* Keep these in cs->interrupt_request. */
3619 events.smi.pending = 0;
3620 events.smi.latched_init = 0;
3621 }
3622 /* Stop SMI delivery on old machine types to avoid a reboot
3623 * on an inward migration of an old VM.
3624 */
3625 if (!cpu->kvm_no_smi_migration) {
3626 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3627 }
3628 }
3629
3630 if (level >= KVM_PUT_RESET_STATE) {
3631 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3632 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3633 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3634 }
3635 }
3636
3637 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
3638 }
3639
3640 static int kvm_get_vcpu_events(X86CPU *cpu)
3641 {
3642 CPUX86State *env = &cpu->env;
3643 struct kvm_vcpu_events events;
3644 int ret;
3645
3646 if (!kvm_has_vcpu_events()) {
3647 return 0;
3648 }
3649
3650 memset(&events, 0, sizeof(events));
3651 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
3652 if (ret < 0) {
3653 return ret;
3654 }
3655
3656 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3657 env->exception_pending = events.exception.pending;
3658 env->exception_has_payload = events.exception_has_payload;
3659 env->exception_payload = events.exception_payload;
3660 } else {
3661 env->exception_pending = 0;
3662 env->exception_has_payload = false;
3663 }
3664 env->exception_injected = events.exception.injected;
3665 env->exception_nr =
3666 (env->exception_pending || env->exception_injected) ?
3667 events.exception.nr : -1;
3668 env->has_error_code = events.exception.has_error_code;
3669 env->error_code = events.exception.error_code;
3670
3671 env->interrupt_injected =
3672 events.interrupt.injected ? events.interrupt.nr : -1;
3673 env->soft_interrupt = events.interrupt.soft;
3674
3675 env->nmi_injected = events.nmi.injected;
3676 env->nmi_pending = events.nmi.pending;
3677 if (events.nmi.masked) {
3678 env->hflags2 |= HF2_NMI_MASK;
3679 } else {
3680 env->hflags2 &= ~HF2_NMI_MASK;
3681 }
3682
3683 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3684 if (events.smi.smm) {
3685 env->hflags |= HF_SMM_MASK;
3686 } else {
3687 env->hflags &= ~HF_SMM_MASK;
3688 }
3689 if (events.smi.pending) {
3690 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3691 } else {
3692 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3693 }
3694 if (events.smi.smm_inside_nmi) {
3695 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3696 } else {
3697 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3698 }
3699 if (events.smi.latched_init) {
3700 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3701 } else {
3702 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3703 }
3704 }
3705
3706 env->sipi_vector = events.sipi_vector;
3707
3708 return 0;
3709 }
3710
3711 static int kvm_guest_debug_workarounds(X86CPU *cpu)
3712 {
3713 CPUState *cs = CPU(cpu);
3714 CPUX86State *env = &cpu->env;
3715 int ret = 0;
3716 unsigned long reinject_trap = 0;
3717
3718 if (!kvm_has_vcpu_events()) {
3719 if (env->exception_nr == EXCP01_DB) {
3720 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3721 } else if (env->exception_injected == EXCP03_INT3) {
3722 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3723 }
3724 kvm_reset_exception(env);
3725 }
3726
3727 /*
3728 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3729 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3730 * by updating the debug state once again if single-stepping is on.
3731 * Another reason to call kvm_update_guest_debug here is a pending debug
3732 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3733 * reinject them via SET_GUEST_DEBUG.
3734 */
3735 if (reinject_trap ||
3736 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3737 ret = kvm_update_guest_debug(cs, reinject_trap);
3738 }
3739 return ret;
3740 }
3741
3742 static int kvm_put_debugregs(X86CPU *cpu)
3743 {
3744 CPUX86State *env = &cpu->env;
3745 struct kvm_debugregs dbgregs;
3746 int i;
3747
3748 if (!kvm_has_debugregs()) {
3749 return 0;
3750 }
3751
3752 memset(&dbgregs, 0, sizeof(dbgregs));
3753 for (i = 0; i < 4; i++) {
3754 dbgregs.db[i] = env->dr[i];
3755 }
3756 dbgregs.dr6 = env->dr[6];
3757 dbgregs.dr7 = env->dr[7];
3758 dbgregs.flags = 0;
3759
3760 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3761 }
3762
3763 static int kvm_get_debugregs(X86CPU *cpu)
3764 {
3765 CPUX86State *env = &cpu->env;
3766 struct kvm_debugregs dbgregs;
3767 int i, ret;
3768
3769 if (!kvm_has_debugregs()) {
3770 return 0;
3771 }
3772
3773 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3774 if (ret < 0) {
3775 return ret;
3776 }
3777 for (i = 0; i < 4; i++) {
3778 env->dr[i] = dbgregs.db[i];
3779 }
3780 env->dr[4] = env->dr[6] = dbgregs.dr6;
3781 env->dr[5] = env->dr[7] = dbgregs.dr7;
3782
3783 return 0;
3784 }
3785
3786 static int kvm_put_nested_state(X86CPU *cpu)
3787 {
3788 CPUX86State *env = &cpu->env;
3789 int max_nested_state_len = kvm_max_nested_state_length();
3790
3791 if (!env->nested_state) {
3792 return 0;
3793 }
3794
3795 assert(env->nested_state->size <= max_nested_state_len);
3796 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3797 }
3798
3799 static int kvm_get_nested_state(X86CPU *cpu)
3800 {
3801 CPUX86State *env = &cpu->env;
3802 int max_nested_state_len = kvm_max_nested_state_length();
3803 int ret;
3804
3805 if (!env->nested_state) {
3806 return 0;
3807 }
3808
3809 /*
3810 * It is possible that migration restored a smaller size into
3811 * nested_state->hdr.size than what our kernel support.
3812 * We preserve migration origin nested_state->hdr.size for
3813 * call to KVM_SET_NESTED_STATE but wish that our next call
3814 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3815 */
3816 env->nested_state->size = max_nested_state_len;
3817
3818 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3819 if (ret < 0) {
3820 return ret;
3821 }
3822
3823 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3824 env->hflags |= HF_GUEST_MASK;
3825 } else {
3826 env->hflags &= ~HF_GUEST_MASK;
3827 }
3828
3829 return ret;
3830 }
3831
3832 int kvm_arch_put_registers(CPUState *cpu, int level)
3833 {
3834 X86CPU *x86_cpu = X86_CPU(cpu);
3835 int ret;
3836
3837 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3838
3839 if (level >= KVM_PUT_RESET_STATE) {
3840 ret = kvm_put_nested_state(x86_cpu);
3841 if (ret < 0) {
3842 return ret;
3843 }
3844
3845 ret = kvm_put_msr_feature_control(x86_cpu);
3846 if (ret < 0) {
3847 return ret;
3848 }
3849 }
3850
3851 if (level == KVM_PUT_FULL_STATE) {
3852 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3853 * because TSC frequency mismatch shouldn't abort migration,
3854 * unless the user explicitly asked for a more strict TSC
3855 * setting (e.g. using an explicit "tsc-freq" option).
3856 */
3857 kvm_arch_set_tsc_khz(cpu);
3858 }
3859
3860 ret = kvm_getput_regs(x86_cpu, 1);
3861 if (ret < 0) {
3862 return ret;
3863 }
3864 ret = kvm_put_xsave(x86_cpu);
3865 if (ret < 0) {
3866 return ret;
3867 }
3868 ret = kvm_put_xcrs(x86_cpu);
3869 if (ret < 0) {
3870 return ret;
3871 }
3872 ret = kvm_put_sregs(x86_cpu);
3873 if (ret < 0) {
3874 return ret;
3875 }
3876 /* must be before kvm_put_msrs */
3877 ret = kvm_inject_mce_oldstyle(x86_cpu);
3878 if (ret < 0) {
3879 return ret;
3880 }
3881 ret = kvm_put_msrs(x86_cpu, level);
3882 if (ret < 0) {
3883 return ret;
3884 }
3885 ret = kvm_put_vcpu_events(x86_cpu, level);
3886 if (ret < 0) {
3887 return ret;
3888 }
3889 if (level >= KVM_PUT_RESET_STATE) {
3890 ret = kvm_put_mp_state(x86_cpu);
3891 if (ret < 0) {
3892 return ret;
3893 }
3894 }
3895
3896 ret = kvm_put_tscdeadline_msr(x86_cpu);
3897 if (ret < 0) {
3898 return ret;
3899 }
3900 ret = kvm_put_debugregs(x86_cpu);
3901 if (ret < 0) {
3902 return ret;
3903 }
3904 /* must be last */
3905 ret = kvm_guest_debug_workarounds(x86_cpu);
3906 if (ret < 0) {
3907 return ret;
3908 }
3909 return 0;
3910 }
3911
3912 int kvm_arch_get_registers(CPUState *cs)
3913 {
3914 X86CPU *cpu = X86_CPU(cs);
3915 int ret;
3916
3917 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3918
3919 ret = kvm_get_vcpu_events(cpu);
3920 if (ret < 0) {
3921 goto out;
3922 }
3923 /*
3924 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3925 * KVM_GET_REGS and KVM_GET_SREGS.
3926 */
3927 ret = kvm_get_mp_state(cpu);
3928 if (ret < 0) {
3929 goto out;
3930 }
3931 ret = kvm_getput_regs(cpu, 0);
3932 if (ret < 0) {
3933 goto out;
3934 }
3935 ret = kvm_get_xsave(cpu);
3936 if (ret < 0) {
3937 goto out;
3938 }
3939 ret = kvm_get_xcrs(cpu);
3940 if (ret < 0) {
3941 goto out;
3942 }
3943 ret = kvm_get_sregs(cpu);
3944 if (ret < 0) {
3945 goto out;
3946 }
3947 ret = kvm_get_msrs(cpu);
3948 if (ret < 0) {
3949 goto out;
3950 }
3951 ret = kvm_get_apic(cpu);
3952 if (ret < 0) {
3953 goto out;
3954 }
3955 ret = kvm_get_debugregs(cpu);
3956 if (ret < 0) {
3957 goto out;
3958 }
3959 ret = kvm_get_nested_state(cpu);
3960 if (ret < 0) {
3961 goto out;
3962 }
3963 ret = 0;
3964 out:
3965 cpu_sync_bndcs_hflags(&cpu->env);
3966 return ret;
3967 }
3968
3969 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3970 {
3971 X86CPU *x86_cpu = X86_CPU(cpu);
3972 CPUX86State *env = &x86_cpu->env;
3973 int ret;
3974
3975 /* Inject NMI */
3976 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3977 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3978 qemu_mutex_lock_iothread();
3979 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3980 qemu_mutex_unlock_iothread();
3981 DPRINTF("injected NMI\n");
3982 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3983 if (ret < 0) {
3984 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3985 strerror(-ret));
3986 }
3987 }
3988 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3989 qemu_mutex_lock_iothread();
3990 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3991 qemu_mutex_unlock_iothread();
3992 DPRINTF("injected SMI\n");
3993 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3994 if (ret < 0) {
3995 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3996 strerror(-ret));
3997 }
3998 }
3999 }
4000
4001 if (!kvm_pic_in_kernel()) {
4002 qemu_mutex_lock_iothread();
4003 }
4004
4005 /* Force the VCPU out of its inner loop to process any INIT requests
4006 * or (for userspace APIC, but it is cheap to combine the checks here)
4007 * pending TPR access reports.
4008 */
4009 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
4010 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4011 !(env->hflags & HF_SMM_MASK)) {
4012 cpu->exit_request = 1;
4013 }
4014 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4015 cpu->exit_request = 1;
4016 }
4017 }
4018
4019 if (!kvm_pic_in_kernel()) {
4020 /* Try to inject an interrupt if the guest can accept it */
4021 if (run->ready_for_interrupt_injection &&
4022 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
4023 (env->eflags & IF_MASK)) {
4024 int irq;
4025
4026 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
4027 irq = cpu_get_pic_interrupt(env);
4028 if (irq >= 0) {
4029 struct kvm_interrupt intr;
4030
4031 intr.irq = irq;
4032 DPRINTF("injected interrupt %d\n", irq);
4033 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
4034 if (ret < 0) {
4035 fprintf(stderr,
4036 "KVM: injection failed, interrupt lost (%s)\n",
4037 strerror(-ret));
4038 }
4039 }
4040 }
4041
4042 /* If we have an interrupt but the guest is not ready to receive an
4043 * interrupt, request an interrupt window exit. This will
4044 * cause a return to userspace as soon as the guest is ready to
4045 * receive interrupts. */
4046 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
4047 run->request_interrupt_window = 1;
4048 } else {
4049 run->request_interrupt_window = 0;
4050 }
4051
4052 DPRINTF("setting tpr\n");
4053 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4054
4055 qemu_mutex_unlock_iothread();
4056 }
4057 }
4058
4059 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
4060 {
4061 X86CPU *x86_cpu = X86_CPU(cpu);
4062 CPUX86State *env = &x86_cpu->env;
4063
4064 if (run->flags & KVM_RUN_X86_SMM) {
4065 env->hflags |= HF_SMM_MASK;
4066 } else {
4067 env->hflags &= ~HF_SMM_MASK;
4068 }
4069 if (run->if_flag) {
4070 env->eflags |= IF_MASK;
4071 } else {
4072 env->eflags &= ~IF_MASK;
4073 }
4074
4075 /* We need to protect the apic state against concurrent accesses from
4076 * different threads in case the userspace irqchip is used. */
4077 if (!kvm_irqchip_in_kernel()) {
4078 qemu_mutex_lock_iothread();
4079 }
4080 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4081 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4082 if (!kvm_irqchip_in_kernel()) {
4083 qemu_mutex_unlock_iothread();
4084 }
4085 return cpu_get_mem_attrs(env);
4086 }
4087
4088 int kvm_arch_process_async_events(CPUState *cs)
4089 {
4090 X86CPU *cpu = X86_CPU(cs);
4091 CPUX86State *env = &cpu->env;
4092
4093 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
4094 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4095 assert(env->mcg_cap);
4096
4097 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
4098
4099 kvm_cpu_synchronize_state(cs);
4100
4101 if (env->exception_nr == EXCP08_DBLE) {
4102 /* this means triple fault */
4103 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4104 cs->exit_request = 1;
4105 return 0;
4106 }
4107 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
4108 env->has_error_code = 0;
4109
4110 cs->halted = 0;
4111 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4112 env->mp_state = KVM_MP_STATE_RUNNABLE;
4113 }
4114 }
4115
4116 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4117 !(env->hflags & HF_SMM_MASK)) {
4118 kvm_cpu_synchronize_state(cs);
4119 do_cpu_init(cpu);
4120 }
4121
4122 if (kvm_irqchip_in_kernel()) {
4123 return 0;
4124 }
4125
4126 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4127 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
4128 apic_poll_irq(cpu->apic_state);
4129 }
4130 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4131 (env->eflags & IF_MASK)) ||
4132 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4133 cs->halted = 0;
4134 }
4135 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
4136 kvm_cpu_synchronize_state(cs);
4137 do_cpu_sipi(cpu);
4138 }
4139 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4140 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
4141 kvm_cpu_synchronize_state(cs);
4142 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
4143 env->tpr_access_type);
4144 }
4145
4146 return cs->halted;
4147 }
4148
4149 static int kvm_handle_halt(X86CPU *cpu)
4150 {
4151 CPUState *cs = CPU(cpu);
4152 CPUX86State *env = &cpu->env;
4153
4154 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4155 (env->eflags & IF_MASK)) &&
4156 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4157 cs->halted = 1;
4158 return EXCP_HLT;
4159 }
4160
4161 return 0;
4162 }
4163
4164 static int kvm_handle_tpr_access(X86CPU *cpu)
4165 {
4166 CPUState *cs = CPU(cpu);
4167 struct kvm_run *run = cs->kvm_run;
4168
4169 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
4170 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4171 : TPR_ACCESS_READ);
4172 return 1;
4173 }
4174
4175 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4176 {
4177 static const uint8_t int3 = 0xcc;
4178
4179 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4180 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
4181 return -EINVAL;
4182 }
4183 return 0;
4184 }
4185
4186 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4187 {
4188 uint8_t int3;
4189
4190 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
4191 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
4192 return -EINVAL;
4193 }
4194 return 0;
4195 }
4196
4197 static struct {
4198 target_ulong addr;
4199 int len;
4200 int type;
4201 } hw_breakpoint[4];
4202
4203 static int nb_hw_breakpoint;
4204
4205 static int find_hw_breakpoint(target_ulong addr, int len, int type)
4206 {
4207 int n;
4208
4209 for (n = 0; n < nb_hw_breakpoint; n++) {
4210 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
4211 (hw_breakpoint[n].len == len || len == -1)) {
4212 return n;
4213 }
4214 }
4215 return -1;
4216 }
4217
4218 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4219 target_ulong len, int type)
4220 {
4221 switch (type) {
4222 case GDB_BREAKPOINT_HW:
4223 len = 1;
4224 break;
4225 case GDB_WATCHPOINT_WRITE:
4226 case GDB_WATCHPOINT_ACCESS:
4227 switch (len) {
4228 case 1:
4229 break;
4230 case 2:
4231 case 4:
4232 case 8:
4233 if (addr & (len - 1)) {
4234 return -EINVAL;
4235 }
4236 break;
4237 default:
4238 return -EINVAL;
4239 }
4240 break;
4241 default:
4242 return -ENOSYS;
4243 }
4244
4245 if (nb_hw_breakpoint == 4) {
4246 return -ENOBUFS;
4247 }
4248 if (find_hw_breakpoint(addr, len, type) >= 0) {
4249 return -EEXIST;
4250 }
4251 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4252 hw_breakpoint[nb_hw_breakpoint].len = len;
4253 hw_breakpoint[nb_hw_breakpoint].type = type;
4254 nb_hw_breakpoint++;
4255
4256 return 0;
4257 }
4258
4259 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4260 target_ulong len, int type)
4261 {
4262 int n;
4263
4264 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
4265 if (n < 0) {
4266 return -ENOENT;
4267 }
4268 nb_hw_breakpoint--;
4269 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4270
4271 return 0;
4272 }
4273
4274 void kvm_arch_remove_all_hw_breakpoints(void)
4275 {
4276 nb_hw_breakpoint = 0;
4277 }
4278
4279 static CPUWatchpoint hw_watchpoint;
4280
4281 static int kvm_handle_debug(X86CPU *cpu,
4282 struct kvm_debug_exit_arch *arch_info)
4283 {
4284 CPUState *cs = CPU(cpu);
4285 CPUX86State *env = &cpu->env;
4286 int ret = 0;
4287 int n;
4288
4289 if (arch_info->exception == EXCP01_DB) {
4290 if (arch_info->dr6 & DR6_BS) {
4291 if (cs->singlestep_enabled) {
4292 ret = EXCP_DEBUG;
4293 }
4294 } else {
4295 for (n = 0; n < 4; n++) {
4296 if (arch_info->dr6 & (1 << n)) {
4297 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4298 case 0x0:
4299 ret = EXCP_DEBUG;
4300 break;
4301 case 0x1:
4302 ret = EXCP_DEBUG;
4303 cs->watchpoint_hit = &hw_watchpoint;
4304 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4305 hw_watchpoint.flags = BP_MEM_WRITE;
4306 break;
4307 case 0x3:
4308 ret = EXCP_DEBUG;
4309 cs->watchpoint_hit = &hw_watchpoint;
4310 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4311 hw_watchpoint.flags = BP_MEM_ACCESS;
4312 break;
4313 }
4314 }
4315 }
4316 }
4317 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
4318 ret = EXCP_DEBUG;
4319 }
4320 if (ret == 0) {
4321 cpu_synchronize_state(cs);
4322 assert(env->exception_nr == -1);
4323
4324 /* pass to guest */
4325 kvm_queue_exception(env, arch_info->exception,
4326 arch_info->exception == EXCP01_DB,
4327 arch_info->dr6);
4328 env->has_error_code = 0;
4329 }
4330
4331 return ret;
4332 }
4333
4334 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
4335 {
4336 const uint8_t type_code[] = {
4337 [GDB_BREAKPOINT_HW] = 0x0,
4338 [GDB_WATCHPOINT_WRITE] = 0x1,
4339 [GDB_WATCHPOINT_ACCESS] = 0x3
4340 };
4341 const uint8_t len_code[] = {
4342 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4343 };
4344 int n;
4345
4346 if (kvm_sw_breakpoints_active(cpu)) {
4347 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
4348 }
4349 if (nb_hw_breakpoint > 0) {
4350 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4351 dbg->arch.debugreg[7] = 0x0600;
4352 for (n = 0; n < nb_hw_breakpoint; n++) {
4353 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4354 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4355 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
4356 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
4357 }
4358 }
4359 }
4360
4361 static bool host_supports_vmx(void)
4362 {
4363 uint32_t ecx, unused;
4364
4365 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4366 return ecx & CPUID_EXT_VMX;
4367 }
4368
4369 #define VMX_INVALID_GUEST_STATE 0x80000021
4370
4371 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
4372 {
4373 X86CPU *cpu = X86_CPU(cs);
4374 uint64_t code;
4375 int ret;
4376
4377 switch (run->exit_reason) {
4378 case KVM_EXIT_HLT:
4379 DPRINTF("handle_hlt\n");
4380 qemu_mutex_lock_iothread();
4381 ret = kvm_handle_halt(cpu);
4382 qemu_mutex_unlock_iothread();
4383 break;
4384 case KVM_EXIT_SET_TPR:
4385 ret = 0;
4386 break;
4387 case KVM_EXIT_TPR_ACCESS:
4388 qemu_mutex_lock_iothread();
4389 ret = kvm_handle_tpr_access(cpu);
4390 qemu_mutex_unlock_iothread();
4391 break;
4392 case KVM_EXIT_FAIL_ENTRY:
4393 code = run->fail_entry.hardware_entry_failure_reason;
4394 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4395 code);
4396 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4397 fprintf(stderr,
4398 "\nIf you're running a guest on an Intel machine without "
4399 "unrestricted mode\n"
4400 "support, the failure can be most likely due to the guest "
4401 "entering an invalid\n"
4402 "state for Intel VT. For example, the guest maybe running "
4403 "in big real mode\n"
4404 "which is not supported on less recent Intel processors."
4405 "\n\n");
4406 }
4407 ret = -1;
4408 break;
4409 case KVM_EXIT_EXCEPTION:
4410 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4411 run->ex.exception, run->ex.error_code);
4412 ret = -1;
4413 break;
4414 case KVM_EXIT_DEBUG:
4415 DPRINTF("kvm_exit_debug\n");
4416 qemu_mutex_lock_iothread();
4417 ret = kvm_handle_debug(cpu, &run->debug.arch);
4418 qemu_mutex_unlock_iothread();
4419 break;
4420 case KVM_EXIT_HYPERV:
4421 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4422 break;
4423 case KVM_EXIT_IOAPIC_EOI:
4424 ioapic_eoi_broadcast(run->eoi.vector);
4425 ret = 0;
4426 break;
4427 default:
4428 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4429 ret = -1;
4430 break;
4431 }
4432
4433 return ret;
4434 }
4435
4436 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4437 {
4438 X86CPU *cpu = X86_CPU(cs);
4439 CPUX86State *env = &cpu->env;
4440
4441 kvm_cpu_synchronize_state(cs);
4442 return !(env->cr[0] & CR0_PE_MASK) ||
4443 ((env->segs[R_CS].selector & 3) != 3);
4444 }
4445
4446 void kvm_arch_init_irq_routing(KVMState *s)
4447 {
4448 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4449 /* If kernel can't do irq routing, interrupt source
4450 * override 0->2 cannot be set up as required by HPET.
4451 * So we have to disable it.
4452 */
4453 no_hpet = 1;
4454 }
4455 /* We know at this point that we're using the in-kernel
4456 * irqchip, so we can use irqfds, and on x86 we know
4457 * we can use msi via irqfd and GSI routing.
4458 */
4459 kvm_msi_via_irqfd_allowed = true;
4460 kvm_gsi_routing_allowed = true;
4461
4462 if (kvm_irqchip_is_split()) {
4463 int i;
4464
4465 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4466 MSI routes for signaling interrupts to the local apics. */
4467 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
4468 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
4469 error_report("Could not enable split IRQ mode.");
4470 exit(1);
4471 }
4472 }
4473 }
4474 }
4475
4476 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4477 {
4478 int ret;
4479 if (machine_kernel_irqchip_split(ms)) {
4480 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4481 if (ret) {
4482 error_report("Could not enable split irqchip mode: %s",
4483 strerror(-ret));
4484 exit(1);
4485 } else {
4486 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4487 kvm_split_irqchip = true;
4488 return 1;
4489 }
4490 } else {
4491 return 0;
4492 }
4493 }
4494
4495 /* Classic KVM device assignment interface. Will remain x86 only. */
4496 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4497 uint32_t flags, uint32_t *dev_id)
4498 {
4499 struct kvm_assigned_pci_dev dev_data = {
4500 .segnr = dev_addr->domain,
4501 .busnr = dev_addr->bus,
4502 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4503 .flags = flags,
4504 };
4505 int ret;
4506
4507 dev_data.assigned_dev_id =
4508 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4509
4510 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4511 if (ret < 0) {
4512 return ret;
4513 }
4514
4515 *dev_id = dev_data.assigned_dev_id;
4516
4517 return 0;
4518 }
4519
4520 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4521 {
4522 struct kvm_assigned_pci_dev dev_data = {
4523 .assigned_dev_id = dev_id,
4524 };
4525
4526 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4527 }
4528
4529 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4530 uint32_t irq_type, uint32_t guest_irq)
4531 {
4532 struct kvm_assigned_irq assigned_irq = {
4533 .assigned_dev_id = dev_id,
4534 .guest_irq = guest_irq,
4535 .flags = irq_type,
4536 };
4537
4538 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4539 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4540 } else {
4541 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4542 }
4543 }
4544
4545 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4546 uint32_t guest_irq)
4547 {
4548 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4549 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4550
4551 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4552 }
4553
4554 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4555 {
4556 struct kvm_assigned_pci_dev dev_data = {
4557 .assigned_dev_id = dev_id,
4558 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4559 };
4560
4561 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4562 }
4563
4564 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4565 uint32_t type)
4566 {
4567 struct kvm_assigned_irq assigned_irq = {
4568 .assigned_dev_id = dev_id,
4569 .flags = type,
4570 };
4571
4572 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4573 }
4574
4575 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4576 {
4577 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4578 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4579 }
4580
4581 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4582 {
4583 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4584 KVM_DEV_IRQ_GUEST_MSI, virq);
4585 }
4586
4587 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4588 {
4589 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4590 KVM_DEV_IRQ_HOST_MSI);
4591 }
4592
4593 bool kvm_device_msix_supported(KVMState *s)
4594 {
4595 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4596 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4597 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4598 }
4599
4600 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4601 uint32_t nr_vectors)
4602 {
4603 struct kvm_assigned_msix_nr msix_nr = {
4604 .assigned_dev_id = dev_id,
4605 .entry_nr = nr_vectors,
4606 };
4607
4608 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4609 }
4610
4611 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4612 int virq)
4613 {
4614 struct kvm_assigned_msix_entry msix_entry = {
4615 .assigned_dev_id = dev_id,
4616 .gsi = virq,
4617 .entry = vector,
4618 };
4619
4620 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4621 }
4622
4623 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4624 {
4625 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4626 KVM_DEV_IRQ_GUEST_MSIX, 0);
4627 }
4628
4629 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4630 {
4631 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4632 KVM_DEV_IRQ_HOST_MSIX);
4633 }
4634
4635 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
4636 uint64_t address, uint32_t data, PCIDevice *dev)
4637 {
4638 X86IOMMUState *iommu = x86_iommu_get_default();
4639
4640 if (iommu) {
4641 int ret;
4642 MSIMessage src, dst;
4643 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4644
4645 if (!class->int_remap) {
4646 return 0;
4647 }
4648
4649 src.address = route->u.msi.address_hi;
4650 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4651 src.address |= route->u.msi.address_lo;
4652 src.data = route->u.msi.data;
4653
4654 ret = class->int_remap(iommu, &src, &dst, dev ? \
4655 pci_requester_id(dev) : \
4656 X86_IOMMU_SID_INVALID);
4657 if (ret) {
4658 trace_kvm_x86_fixup_msi_error(route->gsi);
4659 return 1;
4660 }
4661
4662 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4663 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4664 route->u.msi.data = dst.data;
4665 }
4666
4667 return 0;
4668 }
4669
4670 typedef struct MSIRouteEntry MSIRouteEntry;
4671
4672 struct MSIRouteEntry {
4673 PCIDevice *dev; /* Device pointer */
4674 int vector; /* MSI/MSIX vector index */
4675 int virq; /* Virtual IRQ index */
4676 QLIST_ENTRY(MSIRouteEntry) list;
4677 };
4678
4679 /* List of used GSI routes */
4680 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4681 QLIST_HEAD_INITIALIZER(msi_route_list);
4682
4683 static void kvm_update_msi_routes_all(void *private, bool global,
4684 uint32_t index, uint32_t mask)
4685 {
4686 int cnt = 0, vector;
4687 MSIRouteEntry *entry;
4688 MSIMessage msg;
4689 PCIDevice *dev;
4690
4691 /* TODO: explicit route update */
4692 QLIST_FOREACH(entry, &msi_route_list, list) {
4693 cnt++;
4694 vector = entry->vector;
4695 dev = entry->dev;
4696 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4697 msg = msix_get_message(dev, vector);
4698 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4699 msg = msi_get_message(dev, vector);
4700 } else {
4701 /*
4702 * Either MSI/MSIX is disabled for the device, or the
4703 * specific message was masked out. Skip this one.
4704 */
4705 continue;
4706 }
4707 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
4708 }
4709 kvm_irqchip_commit_routes(kvm_state);
4710 trace_kvm_x86_update_msi_routes(cnt);
4711 }
4712
4713 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4714 int vector, PCIDevice *dev)
4715 {
4716 static bool notify_list_inited = false;
4717 MSIRouteEntry *entry;
4718
4719 if (!dev) {
4720 /* These are (possibly) IOAPIC routes only used for split
4721 * kernel irqchip mode, while what we are housekeeping are
4722 * PCI devices only. */
4723 return 0;
4724 }
4725
4726 entry = g_new0(MSIRouteEntry, 1);
4727 entry->dev = dev;
4728 entry->vector = vector;
4729 entry->virq = route->gsi;
4730 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4731
4732 trace_kvm_x86_add_msi_route(route->gsi);
4733
4734 if (!notify_list_inited) {
4735 /* For the first time we do add route, add ourselves into
4736 * IOMMU's IEC notify list if needed. */
4737 X86IOMMUState *iommu = x86_iommu_get_default();
4738 if (iommu) {
4739 x86_iommu_iec_register_notifier(iommu,
4740 kvm_update_msi_routes_all,
4741 NULL);
4742 }
4743 notify_list_inited = true;
4744 }
4745 return 0;
4746 }
4747
4748 int kvm_arch_release_virq_post(int virq)
4749 {
4750 MSIRouteEntry *entry, *next;
4751 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4752 if (entry->virq == virq) {
4753 trace_kvm_x86_remove_msi_route(virq);
4754 QLIST_REMOVE(entry, list);
4755 g_free(entry);
4756 break;
4757 }
4758 }
4759 return 0;
4760 }
4761
4762 int kvm_arch_msi_data_to_gsi(uint32_t data)
4763 {
4764 abort();
4765 }
AR7 emulation for QEMU