1 /* NOR flash devices */
2 typedef struct pflash_t pflash_t
;
5 pflash_t
*pflash_cfi01_register(target_phys_addr_t base
, ram_addr_t off
,
7 uint32_t sector_len
, int nb_blocs
, int width
,
8 uint16_t id0
, uint16_t id1
,
9 uint16_t id2
, uint16_t id3
, int be
);
12 pflash_t
*pflash_cfi02_register(target_phys_addr_t base
, ram_addr_t off
,
13 BlockDriverState
*bs
, uint32_t sector_len
,
14 int nb_blocs
, int nb_mappings
, int width
,
15 uint16_t id0
, uint16_t id1
,
16 uint16_t id2
, uint16_t id3
,
17 uint16_t unlock_addr0
, uint16_t unlock_addr1
,
21 DeviceState
*nand_init(BlockDriverState
*bdrv
, int manf_id
, int chip_id
);
22 void nand_setpins(DeviceState
*dev
, uint8_t cle
, uint8_t ale
,
23 uint8_t ce
, uint8_t wp
, uint8_t gnd
);
24 void nand_getpins(DeviceState
*dev
, int *rb
);
25 void nand_setio(DeviceState
*dev
, uint32_t value
);
26 uint32_t nand_getio(DeviceState
*dev
);
27 uint32_t nand_getbuswidth(DeviceState
*dev
);
29 #define NAND_MFR_TOSHIBA 0x98
30 #define NAND_MFR_SAMSUNG 0xec
31 #define NAND_MFR_FUJITSU 0x04
32 #define NAND_MFR_NATIONAL 0x8f
33 #define NAND_MFR_RENESAS 0x07
34 #define NAND_MFR_STMICRO 0x20
35 #define NAND_MFR_HYNIX 0xad
36 #define NAND_MFR_MICRON 0x2c
39 void *onenand_raw_otp(DeviceState
*onenand_device
);
43 uint8_t cp
; /* Column parity */
44 uint16_t lp
[2]; /* Line parity */
48 uint8_t ecc_digest(ECCState
*s
, uint8_t sample
);
49 void ecc_reset(ECCState
*s
);
50 extern VMStateDescription vmstate_ecc_state
;