hw/cuda.c

   1 /*
   2  * QEMU PowerMac CUDA device support
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc_mac.h"
  27 #include "qemu-timer.h"
  28 #include "sysemu.h"
  29
  30 /* XXX: implement all timer modes */
  31
  32 /* debug CUDA */
  33 //#define DEBUG_CUDA
  34
  35 /* debug CUDA packets */
  36 //#define DEBUG_CUDA_PACKET
  37
  38 #ifdef DEBUG_CUDA
  39 #define CUDA_DPRINTF(fmt, ...)                                  \
  40     do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
  41 #else
  42 #define CUDA_DPRINTF(fmt, ...)
  43 #endif
  44
  45 /* Bits in B data register: all active low */
  46 #define TREQ            0x08            /* Transfer request (input) */
  47 #define TACK            0x10            /* Transfer acknowledge (output) */
  48 #define TIP             0x20            /* Transfer in progress (output) */
  49
  50 /* Bits in ACR */
  51 #define SR_CTRL         0x1c            /* Shift register control bits */
  52 #define SR_EXT          0x0c            /* Shift on external clock */
  53 #define SR_OUT          0x10            /* Shift out if 1 */
  54
  55 /* Bits in IFR and IER */
  56 #define IER_SET         0x80            /* set bits in IER */
  57 #define IER_CLR         0               /* clear bits in IER */
  58 #define SR_INT          0x04            /* Shift register full/empty */
  59 #define T1_INT          0x40            /* Timer 1 interrupt */
  60 #define T2_INT          0x20            /* Timer 2 interrupt */
  61
  62 /* Bits in ACR */
  63 #define T1MODE          0xc0            /* Timer 1 mode */
  64 #define T1MODE_CONT     0x40            /*  continuous interrupts */
  65
  66 /* commands (1st byte) */
  67 #define ADB_PACKET      0
  68 #define CUDA_PACKET     1
  69 #define ERROR_PACKET    2
  70 #define TIMER_PACKET    3
  71 #define POWER_PACKET    4
  72 #define MACIIC_PACKET   5
  73 #define PMU_PACKET      6
  74
  75
  76 /* CUDA commands (2nd byte) */
  77 #define CUDA_WARM_START                 0x0
  78 #define CUDA_AUTOPOLL                   0x1
  79 #define CUDA_GET_6805_ADDR              0x2
  80 #define CUDA_GET_TIME                   0x3
  81 #define CUDA_GET_PRAM                   0x7
  82 #define CUDA_SET_6805_ADDR              0x8
  83 #define CUDA_SET_TIME                   0x9
  84 #define CUDA_POWERDOWN                  0xa
  85 #define CUDA_POWERUP_TIME               0xb
  86 #define CUDA_SET_PRAM                   0xc
  87 #define CUDA_MS_RESET                   0xd
  88 #define CUDA_SEND_DFAC                  0xe
  89 #define CUDA_BATTERY_SWAP_SENSE         0x10
  90 #define CUDA_RESET_SYSTEM               0x11
  91 #define CUDA_SET_IPL                    0x12
  92 #define CUDA_FILE_SERVER_FLAG           0x13
  93 #define CUDA_SET_AUTO_RATE              0x14
  94 #define CUDA_GET_AUTO_RATE              0x16
  95 #define CUDA_SET_DEVICE_LIST            0x19
  96 #define CUDA_GET_DEVICE_LIST            0x1a
  97 #define CUDA_SET_ONE_SECOND_MODE        0x1b
  98 #define CUDA_SET_POWER_MESSAGES         0x21
  99 #define CUDA_GET_SET_IIC                0x22
 100 #define CUDA_WAKEUP                     0x23
 101 #define CUDA_TIMER_TICKLE               0x24
 102 #define CUDA_COMBINED_FORMAT_IIC        0x25
 103
 104 #define CUDA_TIMER_FREQ (4700000 / 6)
 105 #define CUDA_ADB_POLL_FREQ 50
 106
 107 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
 108 #define RTC_OFFSET                      2082844800
 109
 110 typedef struct CUDATimer {
 111     int index;
 112     uint16_t latch;
 113     uint16_t counter_value; /* counter value at load time */
 114     int64_t load_time;
 115     int64_t next_irq_time;
 116     QEMUTimer *timer;
 117 } CUDATimer;
 118
 119 typedef struct CUDAState {
 120     MemoryRegion mem;
 121     /* cuda registers */
 122     uint8_t b;      /* B-side data */
 123     uint8_t a;      /* A-side data */
 124     uint8_t dirb;   /* B-side direction (1=output) */
 125     uint8_t dira;   /* A-side direction (1=output) */
 126     uint8_t sr;     /* Shift register */
 127     uint8_t acr;    /* Auxiliary control register */
 128     uint8_t pcr;    /* Peripheral control register */
 129     uint8_t ifr;    /* Interrupt flag register */
 130     uint8_t ier;    /* Interrupt enable register */
 131     uint8_t anh;    /* A-side data, no handshake */
 132
 133     CUDATimer timers[2];
 134
 135     uint32_t tick_offset;
 136
 137     uint8_t last_b; /* last value of B register */
 138     uint8_t last_acr; /* last value of B register */
 139
 140     int data_in_size;
 141     int data_in_index;
 142     int data_out_index;
 143
 144     qemu_irq irq;
 145     uint8_t autopoll;
 146     uint8_t data_in[128];
 147     uint8_t data_out[16];
 148     QEMUTimer *adb_poll_timer;
 149 } CUDAState;
 150
 151 static CUDAState cuda_state;
 152 ADBBusState adb_bus;
 153
 154 static void cuda_update(CUDAState *s);
 155 static void cuda_receive_packet_from_host(CUDAState *s,
 156                                           const uint8_t *data, int len);
 157 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 158                               int64_t current_time);
 159
 160 static void cuda_update_irq(CUDAState *s)
 161 {
 162     if (s->ifr & s->ier & (SR_INT | T1_INT)) {
 163         qemu_irq_raise(s->irq);
 164     } else {
 165         qemu_irq_lower(s->irq);
 166     }
 167 }
 168
 169 static unsigned int get_counter(CUDATimer *s)
 170 {
 171     int64_t d;
 172     unsigned int counter;
 173
 174     d = muldiv64(qemu_get_clock_ns(vm_clock) - s->load_time,
 175                  CUDA_TIMER_FREQ, get_ticks_per_sec());
 176     if (s->index == 0) {
 177         /* the timer goes down from latch to -1 (period of latch + 2) */
 178         if (d <= (s->counter_value + 1)) {
 179             counter = (s->counter_value - d) & 0xffff;
 180         } else {
 181             counter = (d - (s->counter_value + 1)) % (s->latch + 2);
 182             counter = (s->latch - counter) & 0xffff;
 183         }
 184     } else {
 185         counter = (s->counter_value - d) & 0xffff;
 186     }
 187     return counter;
 188 }
 189
 190 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
 191 {
 192     CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
 193     ti->load_time = qemu_get_clock_ns(vm_clock);
 194     ti->counter_value = val;
 195     cuda_timer_update(s, ti, ti->load_time);
 196 }
 197
 198 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
 199 {
 200     int64_t d, next_time;
 201     unsigned int counter;
 202
 203     /* current counter value */
 204     d = muldiv64(current_time - s->load_time,
 205                  CUDA_TIMER_FREQ, get_ticks_per_sec());
 206     /* the timer goes down from latch to -1 (period of latch + 2) */
 207     if (d <= (s->counter_value + 1)) {
 208         counter = (s->counter_value - d) & 0xffff;
 209     } else {
 210         counter = (d - (s->counter_value + 1)) % (s->latch + 2);
 211         counter = (s->latch - counter) & 0xffff;
 212     }
 213
 214     /* Note: we consider the irq is raised on 0 */
 215     if (counter == 0xffff) {
 216         next_time = d + s->latch + 1;
 217     } else if (counter == 0) {
 218         next_time = d + s->latch + 2;
 219     } else {
 220         next_time = d + counter;
 221     }
 222     CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
 223                  s->latch, d, next_time - d);
 224     next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) +
 225         s->load_time;
 226     if (next_time <= current_time)
 227         next_time = current_time + 1;
 228     return next_time;
 229 }
 230
 231 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 232                               int64_t current_time)
 233 {
 234     if (!ti->timer)
 235         return;
 236     if ((s->acr & T1MODE) != T1MODE_CONT) {
 237         qemu_del_timer(ti->timer);
 238     } else {
 239         ti->next_irq_time = get_next_irq_time(ti, current_time);
 240         qemu_mod_timer(ti->timer, ti->next_irq_time);
 241     }
 242 }
 243
 244 static void cuda_timer1(void *opaque)
 245 {
 246     CUDAState *s = opaque;
 247     CUDATimer *ti = &s->timers[0];
 248
 249     cuda_timer_update(s, ti, ti->next_irq_time);
 250     s->ifr |= T1_INT;
 251     cuda_update_irq(s);
 252 }
 253
 254 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
 255 {
 256     CUDAState *s = opaque;
 257     uint32_t val;
 258
 259     addr = (addr >> 9) & 0xf;
 260     switch(addr) {
 261     case 0:
 262         val = s->b;
 263         break;
 264     case 1:
 265         val = s->a;
 266         break;
 267     case 2:
 268         val = s->dirb;
 269         break;
 270     case 3:
 271         val = s->dira;
 272         break;
 273     case 4:
 274         val = get_counter(&s->timers[0]) & 0xff;
 275         s->ifr &= ~T1_INT;
 276         cuda_update_irq(s);
 277         break;
 278     case 5:
 279         val = get_counter(&s->timers[0]) >> 8;
 280         cuda_update_irq(s);
 281         break;
 282     case 6:
 283         val = s->timers[0].latch & 0xff;
 284         break;
 285     case 7:
 286         /* XXX: check this */
 287         val = (s->timers[0].latch >> 8) & 0xff;
 288         break;
 289     case 8:
 290         val = get_counter(&s->timers[1]) & 0xff;
 291         s->ifr &= ~T2_INT;
 292         break;
 293     case 9:
 294         val = get_counter(&s->timers[1]) >> 8;
 295         break;
 296     case 10:
 297         val = s->sr;
 298         s->ifr &= ~SR_INT;
 299         cuda_update_irq(s);
 300         break;
 301     case 11:
 302         val = s->acr;
 303         break;
 304     case 12:
 305         val = s->pcr;
 306         break;
 307     case 13:
 308         val = s->ifr;
 309         if (s->ifr & s->ier)
 310             val |= 0x80;
 311         break;
 312     case 14:
 313         val = s->ier | 0x80;
 314         break;
 315     default:
 316     case 15:
 317         val = s->anh;
 318         break;
 319     }
 320     if (addr != 13 || val != 0) {
 321         CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
 322     }
 323
 324     return val;
 325 }
 326
 327 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 328 {
 329     CUDAState *s = opaque;
 330
 331     addr = (addr >> 9) & 0xf;
 332     CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
 333
 334     switch(addr) {
 335     case 0:
 336         s->b = val;
 337         cuda_update(s);
 338         break;
 339     case 1:
 340         s->a = val;
 341         break;
 342     case 2:
 343         s->dirb = val;
 344         break;
 345     case 3:
 346         s->dira = val;
 347         break;
 348     case 4:
 349         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 350         cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
 351         break;
 352     case 5:
 353         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 354         s->ifr &= ~T1_INT;
 355         set_counter(s, &s->timers[0], s->timers[0].latch);
 356         break;
 357     case 6:
 358         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 359         cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
 360         break;
 361     case 7:
 362         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 363         s->ifr &= ~T1_INT;
 364         cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
 365         break;
 366     case 8:
 367         s->timers[1].latch = val;
 368         set_counter(s, &s->timers[1], val);
 369         break;
 370     case 9:
 371         set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
 372         break;
 373     case 10:
 374         s->sr = val;
 375         break;
 376     case 11:
 377         s->acr = val;
 378         cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
 379         cuda_update(s);
 380         break;
 381     case 12:
 382         s->pcr = val;
 383         break;
 384     case 13:
 385         /* reset bits */
 386         s->ifr &= ~val;
 387         cuda_update_irq(s);
 388         break;
 389     case 14:
 390         if (val & IER_SET) {
 391             /* set bits */
 392             s->ier |= val & 0x7f;
 393         } else {
 394             /* reset bits */
 395             s->ier &= ~val;
 396         }
 397         cuda_update_irq(s);
 398         break;
 399     default:
 400     case 15:
 401         s->anh = val;
 402         break;
 403     }
 404 }
 405
 406 /* NOTE: TIP and TREQ are negated */
 407 static void cuda_update(CUDAState *s)
 408 {
 409     int packet_received, len;
 410
 411     packet_received = 0;
 412     if (!(s->b & TIP)) {
 413         /* transfer requested from host */
 414
 415         if (s->acr & SR_OUT) {
 416             /* data output */
 417             if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 418                 if (s->data_out_index < sizeof(s->data_out)) {
 419                     CUDA_DPRINTF("send: %02x\n", s->sr);
 420                     s->data_out[s->data_out_index++] = s->sr;
 421                     s->ifr |= SR_INT;
 422                     cuda_update_irq(s);
 423                 }
 424             }
 425         } else {
 426             if (s->data_in_index < s->data_in_size) {
 427                 /* data input */
 428                 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 429                     s->sr = s->data_in[s->data_in_index++];
 430                     CUDA_DPRINTF("recv: %02x\n", s->sr);
 431                     /* indicate end of transfer */
 432                     if (s->data_in_index >= s->data_in_size) {
 433                         s->b = (s->b | TREQ);
 434                     }
 435                     s->ifr |= SR_INT;
 436                     cuda_update_irq(s);
 437                 }
 438             }
 439         }
 440     } else {
 441         /* no transfer requested: handle sync case */
 442         if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
 443             /* update TREQ state each time TACK change state */
 444             if (s->b & TACK)
 445                 s->b = (s->b | TREQ);
 446             else
 447                 s->b = (s->b & ~TREQ);
 448             s->ifr |= SR_INT;
 449             cuda_update_irq(s);
 450         } else {
 451             if (!(s->last_b & TIP)) {
 452                 /* handle end of host to cuda transfer */
 453                 packet_received = (s->data_out_index > 0);
 454                 /* always an IRQ at the end of transfer */
 455                 s->ifr |= SR_INT;
 456                 cuda_update_irq(s);
 457             }
 458             /* signal if there is data to read */
 459             if (s->data_in_index < s->data_in_size) {
 460                 s->b = (s->b & ~TREQ);
 461             }
 462         }
 463     }
 464
 465     s->last_acr = s->acr;
 466     s->last_b = s->b;
 467
 468     /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
 469        recursively */
 470     if (packet_received) {
 471         len = s->data_out_index;
 472         s->data_out_index = 0;
 473         cuda_receive_packet_from_host(s, s->data_out, len);
 474     }
 475 }
 476
 477 static void cuda_send_packet_to_host(CUDAState *s,
 478                                      const uint8_t *data, int len)
 479 {
 480 #ifdef DEBUG_CUDA_PACKET
 481     {
 482         int i;
 483         printf("cuda_send_packet_to_host:\n");
 484         for(i = 0; i < len; i++)
 485             printf(" %02x", data[i]);
 486         printf("\n");
 487     }
 488 #endif
 489     memcpy(s->data_in, data, len);
 490     s->data_in_size = len;
 491     s->data_in_index = 0;
 492     cuda_update(s);
 493     s->ifr |= SR_INT;
 494     cuda_update_irq(s);
 495 }
 496
 497 static void cuda_adb_poll(void *opaque)
 498 {
 499     CUDAState *s = opaque;
 500     uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 501     int olen;
 502
 503     olen = adb_poll(&adb_bus, obuf + 2);
 504     if (olen > 0) {
 505         obuf[0] = ADB_PACKET;
 506         obuf[1] = 0x40; /* polled data */
 507         cuda_send_packet_to_host(s, obuf, olen + 2);
 508     }
 509     qemu_mod_timer(s->adb_poll_timer,
 510                    qemu_get_clock_ns(vm_clock) +
 511                    (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
 512 }
 513
 514 static void cuda_receive_packet(CUDAState *s,
 515                                 const uint8_t *data, int len)
 516 {
 517     uint8_t obuf[16];
 518     int autopoll;
 519     uint32_t ti;
 520
 521     switch(data[0]) {
 522     case CUDA_AUTOPOLL:
 523         autopoll = (data[1] != 0);
 524         if (autopoll != s->autopoll) {
 525             s->autopoll = autopoll;
 526             if (autopoll) {
 527                 qemu_mod_timer(s->adb_poll_timer,
 528                                qemu_get_clock_ns(vm_clock) +
 529                                (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
 530             } else {
 531                 qemu_del_timer(s->adb_poll_timer);
 532             }
 533         }
 534         obuf[0] = CUDA_PACKET;
 535         obuf[1] = data[1];
 536         cuda_send_packet_to_host(s, obuf, 2);
 537         break;
 538     case CUDA_SET_TIME:
 539         ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];
 540         s->tick_offset = ti - (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
 541         obuf[0] = CUDA_PACKET;
 542         obuf[1] = 0;
 543         obuf[2] = 0;
 544         cuda_send_packet_to_host(s, obuf, 3);
 545         break;
 546     case CUDA_GET_TIME:
 547         ti = s->tick_offset + (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
 548         obuf[0] = CUDA_PACKET;
 549         obuf[1] = 0;
 550         obuf[2] = 0;
 551         obuf[3] = ti >> 24;
 552         obuf[4] = ti >> 16;
 553         obuf[5] = ti >> 8;
 554         obuf[6] = ti;
 555         cuda_send_packet_to_host(s, obuf, 7);
 556         break;
 557     case CUDA_FILE_SERVER_FLAG:
 558     case CUDA_SET_DEVICE_LIST:
 559     case CUDA_SET_AUTO_RATE:
 560     case CUDA_SET_POWER_MESSAGES:
 561         obuf[0] = CUDA_PACKET;
 562         obuf[1] = 0;
 563         cuda_send_packet_to_host(s, obuf, 2);
 564         break;
 565     case CUDA_POWERDOWN:
 566         obuf[0] = CUDA_PACKET;
 567         obuf[1] = 0;
 568         cuda_send_packet_to_host(s, obuf, 2);
 569         qemu_system_shutdown_request();
 570         break;
 571     case CUDA_RESET_SYSTEM:
 572         obuf[0] = CUDA_PACKET;
 573         obuf[1] = 0;
 574         cuda_send_packet_to_host(s, obuf, 2);
 575         qemu_system_reset_request();
 576         break;
 577     default:
 578         break;
 579     }
 580 }
 581
 582 static void cuda_receive_packet_from_host(CUDAState *s,
 583                                           const uint8_t *data, int len)
 584 {
 585 #ifdef DEBUG_CUDA_PACKET
 586     {
 587         int i;
 588         printf("cuda_receive_packet_from_host:\n");
 589         for(i = 0; i < len; i++)
 590             printf(" %02x", data[i]);
 591         printf("\n");
 592     }
 593 #endif
 594     switch(data[0]) {
 595     case ADB_PACKET:
 596         {
 597             uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 598             int olen;
 599             olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
 600             if (olen > 0) {
 601                 obuf[0] = ADB_PACKET;
 602                 obuf[1] = 0x00;
 603             } else {
 604                 /* error */
 605                 obuf[0] = ADB_PACKET;
 606                 obuf[1] = -olen;
 607                 olen = 0;
 608             }
 609             cuda_send_packet_to_host(s, obuf, olen + 2);
 610         }
 611         break;
 612     case CUDA_PACKET:
 613         cuda_receive_packet(s, data + 1, len - 1);
 614         break;
 615     }
 616 }
 617
 618 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 619 {
 620 }
 621
 622 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 623 {
 624 }
 625
 626 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
 627 {
 628     return 0;
 629 }
 630
 631 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
 632 {
 633     return 0;
 634 }
 635
 636 static CPUWriteMemoryFunc * const cuda_write[] = {
 637     &cuda_writeb,
 638     &cuda_writew,
 639     &cuda_writel,
 640 };
 641
 642 static CPUReadMemoryFunc * const cuda_read[] = {
 643     &cuda_readb,
 644     &cuda_readw,
 645     &cuda_readl,
 646 };
 647
 648 static bool cuda_timer_exist(void *opaque, int version_id)
 649 {
 650     CUDATimer *s = opaque;
 651
 652     return s->timer != NULL;
 653 }
 654
 655 static const VMStateDescription vmstate_cuda_timer = {
 656     .name = "cuda_timer",
 657     .version_id = 0,
 658     .minimum_version_id = 0,
 659     .minimum_version_id_old = 0,
 660     .fields      = (VMStateField[]) {
 661         VMSTATE_UINT16(latch, CUDATimer),
 662         VMSTATE_UINT16(counter_value, CUDATimer),
 663         VMSTATE_INT64(load_time, CUDATimer),
 664         VMSTATE_INT64(next_irq_time, CUDATimer),
 665         VMSTATE_TIMER_TEST(timer, CUDATimer, cuda_timer_exist),
 666         VMSTATE_END_OF_LIST()
 667     }
 668 };
 669
 670 static const VMStateDescription vmstate_cuda = {
 671     .name = "cuda",
 672     .version_id = 1,
 673     .minimum_version_id = 1,
 674     .minimum_version_id_old = 1,
 675     .fields      = (VMStateField[]) {
 676         VMSTATE_UINT8(a, CUDAState),
 677         VMSTATE_UINT8(b, CUDAState),
 678         VMSTATE_UINT8(dira, CUDAState),
 679         VMSTATE_UINT8(dirb, CUDAState),
 680         VMSTATE_UINT8(sr, CUDAState),
 681         VMSTATE_UINT8(acr, CUDAState),
 682         VMSTATE_UINT8(pcr, CUDAState),
 683         VMSTATE_UINT8(ifr, CUDAState),
 684         VMSTATE_UINT8(ier, CUDAState),
 685         VMSTATE_UINT8(anh, CUDAState),
 686         VMSTATE_INT32(data_in_size, CUDAState),
 687         VMSTATE_INT32(data_in_index, CUDAState),
 688         VMSTATE_INT32(data_out_index, CUDAState),
 689         VMSTATE_UINT8(autopoll, CUDAState),
 690         VMSTATE_BUFFER(data_in, CUDAState),
 691         VMSTATE_BUFFER(data_out, CUDAState),
 692         VMSTATE_UINT32(tick_offset, CUDAState),
 693         VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1,
 694                              vmstate_cuda_timer, CUDATimer),
 695         VMSTATE_END_OF_LIST()
 696     }
 697 };
 698
 699 static void cuda_reset(void *opaque)
 700 {
 701     CUDAState *s = opaque;
 702
 703     s->b = 0;
 704     s->a = 0;
 705     s->dirb = 0;
 706     s->dira = 0;
 707     s->sr = 0;
 708     s->acr = 0;
 709     s->pcr = 0;
 710     s->ifr = 0;
 711     s->ier = 0;
 712     //    s->ier = T1_INT | SR_INT;
 713     s->anh = 0;
 714     s->data_in_size = 0;
 715     s->data_in_index = 0;
 716     s->data_out_index = 0;
 717     s->autopoll = 0;
 718
 719     s->timers[0].latch = 0xffff;
 720     set_counter(s, &s->timers[0], 0xffff);
 721
 722     s->timers[1].latch = 0;
 723     set_counter(s, &s->timers[1], 0xffff);
 724 }
 725
 726 void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq)
 727 {
 728     struct tm tm;
 729     CUDAState *s = &cuda_state;
 730
 731     s->irq = irq;
 732
 733     s->timers[0].index = 0;
 734     s->timers[0].timer = qemu_new_timer_ns(vm_clock, cuda_timer1, s);
 735
 736     s->timers[1].index = 1;
 737
 738     qemu_get_timedate(&tm, 0);
 739     s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
 740
 741     s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
 742     cpu_register_io_memory(cuda_read, cuda_write, s,
 743                                              DEVICE_NATIVE_ENDIAN);
 744     *cuda_mem = &s->mem;
 745     vmstate_register(NULL, -1, &vmstate_cuda, s);
 746     qemu_register_reset(cuda_reset, s);
 747 }